20 Sep, 2016
1 commit
-
Install the callbacks via the state machine.
[ tglx: Reuse the MIPS_SOC_PREPARE state ]
Signed-off-by: Sebastian Andrzej Siewior
Acked-by: Ralf Baechle
Cc: linux-mips@linux-mips.org
Cc: Peter Zijlstra
Cc: rt@linutronix.de
Link: http://lkml.kernel.org/r/20160906170457.32393-17-bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner
06 Aug, 2016
1 commit
-
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS for 4.8. Also includes is a
minor SSB cleanup as SSB code traditionally is merged through the MIPS
tree:ATH25:
- MIPS: Add default configuration for ath25Boot:
- For zboot, copy appended dtb to the end of the kernel
- store the appended dtb address in a variableBPF:
- Fix off by one error in offset allocationCobalt code:
- Fix typosCore code:
- debugfs_create_file returns NULL on error, so don't use IS_ERR for
testing for errors.
- Fix double locking issue in RM7000 S-cache code. This would only
affect RM7000 ARC systems on reboot.
- Fix page table corruption on THP permission changes.
- Use compat_sys_keyctl for 32 bit userspace on 64 bit kernels.
David says, there are no compatibility issues raised by this fix.
- Move some signal code around.
- Rewrite r4k count/compare clockevent device registration such that
min_delta_ticks/max_delta_ticks files are guaranteed to be
initialized.
- Only register r4k count/compare as clockevent device if we can
assume the clock to be constant.
- Fix MSA asm warnings in control reg accessors
- uasm and tlbex fixes and tweaking.
- Print segment physical address when EU=1.
- Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO.
- CP: Allow booting by VP other than VP 0
- Cache handling fixes and optimizations for r4k class caches
- Add hotplug support for R6 processors
- Cleanup hotplug bits in kconfig
- traps: return correct si code for accessing nonmapped addresses
- Remove cpu_has_safe_index_cacheopsLantiq:
- Register IRQ handler for virtual IRQ number
- Fix EIU interrupt loading code
- Use the real EXIN count
- Fix build error.Loongson 3:
- Increase HPET_MIN_PROG_DELTA and decrease HPET_MIN_CYCLESOcteon:
- Delete built-in DTB pruning code for D-Link DSR-1000N.
- Clean up GPIO definitions in dlink_dsr-1000n.dts.
- Add more LEDs to the DSR-100n DTS
- Fix off by one in octeon_irq_gpio_map()
- Typo fixes
- Enable SATA by default in cavium_octeon_defconfig
- Support readq/writeq()
- Remove forced mappings of USB interrupts.
- Ensure DMA descriptors are always in the low 4GB
- Improve USB reset code for OCTEON II.Pistachio:
- Add maintainers entry for pistachio SoC Support
- Remove plat_setup_iocoherencyRalink:
- Fix pwm UART in spis group pinmux.SSB:
- Change bare unsigned to unsigned int to suit coding styleTools:
- Fix reloc tool compiler warnings.Other:
- Delete use of ARCH_WANT_OPTIONAL_GPIOLIB"* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (61 commits)
MIPS: mm: Fix definition of R6 cache instruction
MIPS: tools: Fix relocs tool compiler warnings
MIPS: Cobalt: Fix typo
MIPS: Octeon: Fix typo
MIPS: Lantiq: Fix build failure
MIPS: Use CPHYSADDR to implement mips32 __pa
MIPS: Octeon: Dlink_dsr-1000n.dts: add more leds.
MIPS: Octeon: Clean up GPIO definitions in dlink_dsr-1000n.dts.
MIPS: Octeon: Delete built-in DTB pruning code for D-Link DSR-1000N.
MIPS: store the appended dtb address in a variable
MIPS: ZBOOT: copy appended dtb to the end of the kernel
MIPS: ralink: fix spis group pinmux
MIPS: Factor o32 specific code into signal_o32.c
MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present
MIPS: Use per-mm page to execute branch delay slot instructions
MIPS: Modify error handling
MIPS: c-r4k: Use SMP calls for CM indexed cache ops
MIPS: c-r4k: Avoid small flush_icache_range SMP calls
MIPS: c-r4k: Local flush_icache_range cache op override
MIPS: c-r4k: Split r4k_flush_kernel_vmap_range()
...
04 Aug, 2016
1 commit
-
The dma-mapping core and the implementations do not change the DMA
attributes passed by pointer. Thus the pointer can point to const data.
However the attributes do not have to be a bitfield. Instead unsigned
long will do fine:1. This is just simpler. Both in terms of reading the code and setting
attributes. Instead of initializing local attributes on the stack
and passing pointer to it to dma_set_attr(), just set the bits.2. It brings safeness and checking for const correctness because the
attributes are passed by value.Semantic patches for this change (at least most of them):
virtual patch
virtual context@r@
identifier f, attrs;@@
f(...,
- struct dma_attrs *attrs
+ unsigned long attrs
, ...)
{
...
}@@
identifier r.f;
@@
f(...,
- NULL
+ 0
)and
// Options: --all-includes
virtual patch
virtual context@r@
identifier f, attrs;
type t;@@
t f(..., struct dma_attrs *attrs);@@
identifier r.f;
@@
f(...,
- NULL
+ 0
)Link: http://lkml.kernel.org/r/1468399300-5399-2-git-send-email-k.kozlowski@samsung.com
Signed-off-by: Krzysztof Kozlowski
Acked-by: Vineet Gupta
Acked-by: Robin Murphy
Acked-by: Hans-Christian Noren Egtvedt
Acked-by: Mark Salter [c6x]
Acked-by: Jesper Nilsson [cris]
Acked-by: Daniel Vetter [drm]
Reviewed-by: Bart Van Assche
Acked-by: Joerg Roedel [iommu]
Acked-by: Fabien Dessenne [bdisp]
Reviewed-by: Marek Szyprowski [vb2-core]
Acked-by: David Vrabel [xen]
Acked-by: Konrad Rzeszutek Wilk [xen swiotlb]
Acked-by: Joerg Roedel [iommu]
Acked-by: Richard Kuo [hexagon]
Acked-by: Geert Uytterhoeven [m68k]
Acked-by: Gerald Schaefer [s390]
Acked-by: Bjorn Andersson
Acked-by: Hans-Christian Noren Egtvedt [avr32]
Acked-by: Vineet Gupta [arc]
Acked-by: Robin Murphy [arm64 and dma-iommu]
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
03 Aug, 2016
1 commit
29 Jul, 2016
1 commit
-
When a CPU is disabled via CPU hotplug, cpu_foreign_map is not updated.
This could result in cache management SMP calls being sent to offline
CPUs instead of online siblings in the same core.Add a call to calculate_cpu_foreign_map() in the various MIPS cpu
disable callbacks after set_cpu_online(). All cases are updated for
consistency and to keep cpu_foreign_map strictly up to date, not just
those which may support hardware multithreading.Fixes: cccf34e9411c ("MIPS: c-r4k: Fix cache flushing for MT cores")
Signed-off-by: James Hogan
Cc: Paul Burton
Cc: David Daney
Cc: Kevin Cernekee
Cc: Florian Fainelli
Cc: Huacai Chen
Cc: Hongliang Tao
Cc: Hua Yan
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13799/
Signed-off-by: Ralf Baechle
24 Jul, 2016
1 commit
-
At first, we prefer to use mips clockevent device, so we decrease the
rating of hpet clockevent device.For hpet, if HPET_MIN_PROG_DELTA (minimum delta of hpet programming) is
too small and HPET_MIN_CYCLES (threshold of -ETIME checking) is too
large, then hpet_next_event() can easily return -ETIME. After commit
c6eb3f70d44828 ("hrtimer: Get rid of hrtimer softirq") this will cause
a RCU stall.So, HPET_MIN_PROG_DELTA must be sufficient that we don't re-trip the
-ETIME check -- if we do, we will return -ETIME, forward the next event
time, try to set it, return -ETIME again, and basically lock the system
up. Meanwhile, HPET_MIN_CYCLES doesn't need to be too large, 16 cycles
is enough.This solution is similar to commit f9eccf24615672 ("clocksource/drivers
/vt8500: Increase the minimum delta").By the way, this patch ensures hpet count/compare to be 32-bit long.
Signed-off-by: Huacai Chen
Cc: John Crispin
Cc: Steven J . Hill
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13819/
Signed-off-by: Ralf Baechle
28 May, 2016
1 commit
-
Signed-off-by: Andrea Gelmini
Cc: chenhc@lemote.com
Cc: viresh.kumar@linaro.org
Cc: linux-mips@linux-mips.org
Cc: trivial@kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13322/
Patchwork: https://patchwork.linux-mips.org/patch/13332/
Signed-off-by: Ralf Baechle
13 May, 2016
4 commits
-
Loongson-3 CPU family:
Code-name Brand-name PRId
Loongson-3A R1 Loongson-3A1000 0x6305
Loongson-3A R2 Loongson-3A2000 0x6308
Loongson-3B R1 Loongson-3B1000 0x6306
Loongson-3B R2 Loongson-3B1500 0x6307Features of R2 revision of Loongson-3A:
- Primary cache includes I-Cache, D-Cache and V-Cache (Victim Cache).
- I-Cache, D-Cache and V-Cache are 16-way set-associative, linesize is
64 bytes.
- 64 entries of VTLB (classic TLB), 1024 entries of FTLB (8-way
set-associative).
- Supports DSP/DSPv2 instructions, UserLocal register and Read-Inhibit/
Execute-Inhibit.[ralf@linux-mips.org: Resolved merge conflicts.]
Signed-off-by: Huacai Chen
Cc: Aurelien Jarno
Cc: Steven J . Hill
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12751/
Patchwork: https://patchwork.linux-mips.org/patch/13136/
Signed-off-by: Ralf Baechle -
This patch adjust the logic in mach_irq_dispatch(), allow multiple IPs
handled in the same dispatching. This can speedup interrupt processing.Signed-off-by: Huacai Chen
Cc: Aurelien Jarno
Cc: Steven J . Hill
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12891/
Signed-off-by: Ralf Baechle -
SB700/SB710/SB800 chipset ACPI code is mostly Loongson-3 specific
routines rather than a "platform driver".Signed-off-by: Huacai Chen
Cc: John Crispin
Cc: Steven J. Hill
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11273/
Signed-off-by: Ralf Baechle -
flush_cache_all() is a nop and loongson 3 is fully coherent.
Signed-off-by: Ralf Baechle
09 May, 2016
2 commits
-
Commit d5ece1cb074b2c ("Fix ld-version.sh to handle large 3rd version
part") modifies the ld version description. This causes a build error
on Loongson-3, so fix it.Signed-off-by: Huacai Chen
Cc: Aurelien Jarno
Cc: Steven J . Hill
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Cc: Huacai Chen
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12890/
Signed-off-by: Ralf Baechle -
Due to datasheet, reserving 0xff800000~0xffffffff (8MB below 4GB) is
not enough for RS780E integrated GPU's TOM (top of memory) registers
and MSI/MSI-x memory region, so we reserve 0xfe000000~0xffffffff (32MB
below 4GB).Signed-off-by: Huacai Chen
Cc: Aurelien Jarno
Cc: Steven J . Hill
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12889/
Signed-off-by: Ralf Baechle
22 Jan, 2016
3 commits
-
This patch is borrowed from x86 hpet driver and explaind below:
Due to the overly intelligent design of HPETs, we need to workaround
the problem that the compare value which we write is already behind
the actual counter value at the point where the value hits the real
compare register. This happens for two reasons:1) We read out the counter, add the delta and write the result to the
compare register. When a NMI hits between the read out and the write
then the counter can be ahead of the event already.2) The write to the compare register is delayed by up to two HPET
cycles in AMD chipsets.We can work around this by reading back the compare register to make
sure that the written value has hit the hardware. But that is bad
performance wise for the normal case where the event is far enough in
the future.As we already know that the write can be delayed by up to two cycles
we can avoid the read back of the compare register completely if we
make the decision whether the delta has elapsed already or not based
on the following calculation:cmp = event - actual_count;
If cmp is less than 64 HPET clock cycles, then we decide that the event
has happened already and return -ETIME. That covers the above #1 and #2
problems which would cause a wait for HPET wraparound (~306 seconds).Signed-off-by: Huacai Chen
Cc: Aurelien Jarno
Cc: Steven J. Hill
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Cc: Huacai Chen
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12162/
Signed-off-by: Ralf Baechle -
When Core-0 handle SMP_ASK_C0COUNT IPI, we should make other cores to
see the result as soon as possible (especially when Store-Fill-Buffer
is enabled). Otherwise, C0_Count syncronization makes no sense.BTW, array is more suitable than per-cpu variable for syncronization,
and there is a corner case should be avoid: C0_Count of Core-0 can be
really 0.Signed-off-by: Huacai Chen
Cc: Aurelien Jarno
Cc: Steven J. Hill
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Cc: Huacai Chen
Cc: linux-mips@linux-mips.org
Cc:
Patchwork: https://patchwork.linux-mips.org/patch/12160/
Signed-off-by: Ralf Baechle -
If GCC >= 4.9 and Binutils >=2.25, we use -march=loongson3a, otherwise
we use -march=mips64r2, this can slightly improve performance. Besides,
arch/mips/loongson64/Platform is a better location rather than arch/
mips/Makefile.Signed-off-by: Huacai Chen
Cc: Aurelien Jarno
Cc: Steven J. Hill
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12161/
Signed-off-by: Ralf Baechle
11 Nov, 2015
1 commit
-
Now LOONGSON_CHIPCFG register definition doesn't depend on CPUFREQ any
more, so CPU_SUPPORTS_CPUFREQ is no longer needed for suspend/resume.
Remove CONFIG_LOONGSON_SUSPEND and use CONFIG_SUSPEND instead.Signed-off-by: Huacai Chen
Cc: John Crispin
Cc: Steven J. Hill
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11274/
Signed-off-by: Ralf Baechle
22 Sep, 2015
1 commit
-
Commit 3adeb2566b9b ("MIPS: Loongson: Improve LEFI firmware interface")
made the number of UARTs dynamic if LEFI_FIRMWARE_INTERFACE is configured.
Unfortunately, it did not initialize the number of UARTs if
LEFI_FIRMWARE_INTERFACE is not configured. As a result, the Fulong2e
system has no console.Fixes: 3adeb2566b9b ("MIPS: Loongson: Improve LEFI firmware interface")
Acked-by: Huacai Chen
Signed-off-by: Guenter Roeck
Tested-by: Markos Chandras
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11076/
Signed-off-by: Ralf Baechle
11 Sep, 2015
2 commits
-
Almost everyone implements dma_set_mask the same way, although some time
that's hidden in ->set_dma_mask methods.This patch consolidates those into a common implementation that either
calls ->set_dma_mask if present or otherwise uses the default
implementation. Some architectures used to only call ->set_dma_mask
after the initial checks, and those instance have been fixed to do the
full work. h8300 implemented dma_set_mask bogusly as a no-ops and has
been fixed.Unfortunately some architectures overload unrelated semantics like changing
the dma_ops into it so we still need to allow for an architecture override
for now.[jcmvbkbc@gmail.com: fix xtensa]
Signed-off-by: Christoph Hellwig
Cc: Arnd Bergmann
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Yoshinori Sato
Cc: Michal Simek
Cc: Jonas Bonn
Cc: Chris Metcalf
Cc: Guan Xuetao
Cc: Ralf Baechle
Cc: Benjamin Herrenschmidt
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: "H. Peter Anvin"
Cc: Andy Shevchenko
Signed-off-by: Max Filippov
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
Since 2009 we have a nice asm-generic header implementing lots of DMA API
functions for architectures using struct dma_map_ops, but unfortunately
it's still missing a lot of APIs that all architectures still have to
duplicate.This series consolidates the remaining functions, although we still need
arch opt outs for two of them as a few architectures have very
non-standard implementations.This patch (of 5):
The coherent DMA allocator works the same over all architectures supporting
dma_map operations.This patch consolidates them and converges the minor differences:
- the debug_dma helpers are now called from all architectures, including
those that were previously missing them
- dma_alloc_from_coherent and dma_release_from_coherent are now always
called from the generic alloc/free routines instead of the ops
dma-mapping-common.h always includes dma-coherent.h to get the defintions
for them, or the stubs if the architecture doesn't support this feature
- checks for ->alloc / ->free presence are removed. There is only one
magic instead of dma_map_ops without them (mic_dma_ops) and that one
is x86 only anyway.Besides that only x86 needs special treatment to replace a default devices
if none is passed and tweak the gfp_flags. An optional arch hook is provided
for that.[linux@roeck-us.net: fix build]
[jcmvbkbc@gmail.com: fix xtensa]
Signed-off-by: Christoph Hellwig
Cc: Arnd Bergmann
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Yoshinori Sato
Cc: Michal Simek
Cc: Jonas Bonn
Cc: Chris Metcalf
Cc: Guan Xuetao
Cc: Ralf Baechle
Cc: Benjamin Herrenschmidt
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: "H. Peter Anvin"
Cc: Andy Shevchenko
Signed-off-by: Guenter Roeck
Signed-off-by: Max Filippov
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
03 Sep, 2015
1 commit
-
Migrate loongson driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.This also enables us to implement callbacks for new states of clockevent
devices, for example: ONESHOT_STOPPED.[ralf@linux-mips.org: Folded in Viresh's followon fix.]
Signed-off-by: Viresh Kumar
Cc: Huacai Chen
Cc: Michael Opdenacker
Cc: Hongliang Tao
Cc: Valentin Rothberg
Cc: Daniel Lezcano
Cc: linux-mips@linux-mips.org
Cc: linaro-kernel@lists.linaro.org
Cc: Thomas Gleixner
Cc: Viresh Kumar
Patchwork: https://patchwork.linux-mips.org/patch/10608/
Patchwork: https://patchwork.linux-mips.org/patch/10883/
Signed-off-by: Ralf Baechle
03 Aug, 2015
1 commit
-
The majority of SMP platforms handle their IPIs through do_IRQ()
which calls irq_{enter/exit}(). When a call function IPI is received,
smp_call_function_interrupt() is called which also calls
irq_{enter,exit}(), meaning irq_count is raised twice.When tick broadcasting is used (which is implemented via a call
function IPI), this incorrectly causes all CPU idle time on the core
receiving broadcast ticks to be accounted as time spent servicing
IRQs, as account_process_tick() will account as such if irq_count is
greater than 1. This results in 100% CPU usage being reported on a
core which receives its ticks via broadcast.This patch removes the SMP smp_call_function_interrupt() wrapper which
calls irq_{enter,exit}(). Platforms which handle their IPIs through
do_IRQ() now call generic_smp_call_function_interrupt() directly to
avoid incrementing irq_count a second time. Platforms which don't
(loongson, sgi-ip27, sibyte) call generic_smp_call_function_interrupt()
wrapped in irq_{enter,exit}().Signed-off-by: Alex Smith
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10770/
Signed-off-by: Ralf Baechle
08 Jul, 2015
2 commits
-
Signed-off-by: Ralf Baechle
-
CC arch/mips/loongson64/lemote-2f/clock.o
/home/ralf/src/linux/linux-mips/arch/mips/loongson64/lemote-2f/clock.c:18:40: fatal error: asm/mach-loongson/loongson.h: No such file or directory
#include
^
compilation terminated.Signed-off-by: Ralf Baechle
22 Jun, 2015
2 commits
-
The file looks as if it is non-modular, but it piggy-backs
off CONFIG_SERIAL_8250 which is tristate. If set to "=m"
we will get this after the init/module header cleanup:arch/mips/loongson/common/serial.c:76:1: error: data definition has no type or storage class [-Werror]
arch/mips/loongson/common/serial.c:76:1: error: type defaults to 'int' in declaration of 'device_initcall' [-Werror=implicit-int]
arch/mips/loongson/common/serial.c:76:1: error: parameter names (without types) in function declaration [-Werror]
arch/mips/loongson/common/serial.c:58:19: error: 'serial_init' defined but not used [-Werror=unused-function]
cc1: all warnings being treated as errors
make[3]: *** [arch/mips/loongson/common/serial.o] Error 1Make it clearly modular, and add a module_exit function,
so that we avoid the above breakage.Reported-by: kbuild test robot
Cc: Ralf Baechle
Cc: linux-mips@linux-mips.org
Signed-off-by: Paul Gortmaker
Signed-off-by: Ralf Baechle -
Currently, code of Loongson-2/3 is under loongson directory and code of
Loongson-1 is under loongson1 directory. Besides, there are Kconfig
options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is
very ugly and confusing. Since Loongson-2/3 are both 64-bit general-
purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names
and Kconfig symbols from loongson/loongson1 to loongson64/loongson32.[ralf@linux-mips.org: Resolve a number of simple conflicts.]
Signed-off-by: Huacai Chen
Cc: Steven J. Hill
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Cc: Kelvin Cheung
Patchwork: https://patchwork.linux-mips.org/patch/9790/
Signed-off-by: Ralf Baechle
