13 Aug, 2016
1 commit
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clk-divider uses clk_readl()/clk_writel() everywhere, except in
clk_divider_round_rate(), where plain readl() is used. Change this to
clk_readl(), as it makes a difference on powerpc.Fixes: e6d5e7d90be92cee ("clk-divider: Fix READ_ONLY when divider > 1")
Signed-off-by: Geert Uytterhoeven
Reviewed-by: James Hogan
Signed-off-by: Stephen Boyd
20 Apr, 2016
1 commit
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Add registration APIs in the clk divider code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.Signed-off-by: Stephen Boyd
30 Jan, 2016
3 commits
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Because _next_div() returns a valid divider, there is no need to
consult _is_valid_div() for the validity of the divider in every
iteration.Signed-off-by: Masahiro Yamada
Signed-off-by: Stephen Boyd -
to_clk_*(_hw) macros have been repeatedly defined in many places.
This patch moves all the to_clk_*(_hw) definitions in the common
clock framework to public header clk-provider.h, and drop the local
definitions.Signed-off-by: Geliang Tang
Signed-off-by: Stephen Boyd -
Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed
the special ops struct for read-only clocks and instead opted to handle
them inside the regular ops.On the rk3368 this results in breakage as aclkm now gets set a value.
While it is the same divider value, the A53 core still doesn't like it,
which can result in the cpu ending up in a hang.
The reason being that "ACLKENMasserts one clock cycle before the rising
edge of ACLKM" and the clock should only be touched when STANDBYWFIL2
is asserted.To fix this, reintroduce the read-only ops but do include the round_rate
callback. That way no writes that may be unsafe are done to the divider
register in any case.The Rockchip use of the clk_divider_ops is adapted to this split again,
as is the nxp, lpc18xx-ccu driver that was included since the original
commit. On lpc18xx-ccu the divider seems to always be read-only
so only uses the new ops now.Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1")
Reported-by: Zhang Qing
Signed-off-by: Heiko Stuebner
Signed-off-by: Stephen Boyd
01 Dec, 2015
1 commit
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When we use a clk divider with a divider table, we limit the
maximum divider value in divider_get_val() to the
div_mask(width), but when we calculate the divider in
divider_round_rate() we don't consider that the maximum divider
may be limited by the width. Pass the width along to
_get_table_maxdiv() so that we only return the maximum divider
that is valid. This is useful for clocks that want to share the
same divider table while limiting the available dividers to some
subset of the table depending on the width of the bitfield.Cc: Rajendra Nayak
Signed-off-by: Stephen Boyd
17 Sep, 2015
1 commit
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On 32-bit architectures, 'unsigned long' (the type used to hold clock
rates, in Hz) is often only 32 bits wide. DIV_ROUND_UP() (as used in,
e.g., commit b11d282dbea2 "clk: divider: fix rate calculation for
fractional rates") can yield an integer overflow on clock rates that are
not (by themselves) too large to fit in 32 bits, because it performs
addition before the division. See for example:DIV_ROUND_UP(3000000000, 1500000000) = (3.0G + 1.5G - 1) / 1.5G
= OVERFLOW / 1.5GThis patch fixes such cases by always promoting the dividend to 64-bits
(unsigned long long) before doing the division. While this patch does
not resolve the issue with large clock rates across the common clock
framework nor address the problems with doing full 64-bit arithmetic on
a 32-bit architecture, it does fix some issues seen when using clock
dividers on a 3GHz reference clock to produce a 1.5GHz CPU clock for an
ARMv7 Brahma B15 SoC.Signed-off-by: Brian Norris
Reference: http://lkml.kernel.org/g/20150413201433.GQ32500@ld-irv-0074
Signed-off-by: Stephen Boyd
25 Aug, 2015
2 commits
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We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.Signed-off-by: Stephen Boyd
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Mostly converted with the following snippet:
@@
struct clk_hw *E;
@@-__clk_get_flags(E->clk)
+clk_hw_get_flags(E)Acked-by: Tero Kristo
Cc: Maxime Ripard
Cc: Max Filippov
Acked-by: Sebastian Hesselbarth
Cc: Daniel Thompson
Cc: Coquelin
Signed-off-by: Stephen Boyd
29 Jul, 2015
2 commits
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The basic clock types use conditional locking for the register
accessor spinlocks. Add __acquire() and __release() markings in
the right locations so that sparse isn't tripped up on the
conditional locking.drivers/clk/clk-mux.c:68:12: warning: context imbalance in 'clk_mux_set_parent' - different lock contexts for basic block
drivers/clk/clk-divider.c:379:12: warning: context imbalance in 'clk_divider_set_rate' - different lock contexts for basic block
drivers/clk/clk-gate.c:71:9: warning: context imbalance in 'clk_gate_endisable' - different lock contexts for basic block
drivers/clk/clk-fractional-divider.c:36:9: warning: context imbalance in 'clk_fd_recalc_rate' - different lock contexts for basic block
drivers/clk/clk-fractional-divider.c:68:12: warning: context imbalance in 'clk_fd_set_rate' - different lock contexts for basic blockCc: Andy Shevchenko
Signed-off-by: Stephen Boyd -
This commit allows certain Broadcom STB clock dividers to be used with
clk-divider.c. It allows for a clock whose field value is the equal
to the divisor, execpt when the field value is zero, in which case the
divisor is 2^width. For example, consider a divisor clock with a two
bit field:value divisor
0 4
1 1
2 2
3 3Signed-off-by: Jim Quinlan
Signed-off-by: Michael Turquette
15 May, 2015
1 commit
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Printing an error on kmalloc() failures is unnecessary. Remove
the print and use *ptr in sizeof() for future-proof code.Signed-off-by: Stephen Boyd
10 Mar, 2015
3 commits
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Similar to the reasoning for the previous commit
DIV_ROUND_CLOSEST(parent_rate, rate)
might not be the best integer divisor to get a good approximation for
rate from parent_rate (given the metric for CLK_DIVIDER_ROUND_CLOSEST).For example assume a parent rate of 1000 Hz and a target rate of 700.
Using DIV_ROUND_CLOSEST the suggested divisor gets calculated to 1
resulting in a target rate of 1000 with a delta of 300 to the desired
rate. With choosing 2 as divisor however the resulting rate is 500 which
is nearer to 700.Signed-off-by: Uwe Kleine-König
Acked-by: Sascha Hauer
Acked-by: Maxime Coquelin
Signed-off-by: Michael Turquette -
It's an invalid approach to assume that among two divider values
the one nearer the exact divider is the better one.Assume a parent rate of 1000 Hz, a divider with CLK_DIVIDER_POWER_OF_TWO
and a target rate of 89 Hz. The exact divider is ~ 11.236 so 8 and 16
are the candidates to choose from yielding rates 125 Hz and 62.5 Hz
respectivly. While 8 is nearer to 11.236 than 16 is, the latter is still
the better divider as 62.5 is nearer to 89 than 125 is.Fixes: 774b514390b1 (clk: divider: Add round to closest divider)
Signed-off-by: Uwe Kleine-König
Acked-by: Sascha Hauer
Acked-by: Maxime Coquelin
Signed-off-by: Michael Turquette -
The rate provided at the output of a clk-divider is calculated as:
DIV_ROUND_UP(parent_rate, div)
since commit b11d282dbea2 (clk: divider: fix rate calculation for
fractional rates). So to yield a rate not bigger than r parent_rate
must be = its 2nd parameter. Also for dividers with
CLK_DIVIDER_ROUND_CLOSEST set the calculation is not accurate. But this
fixes the test case by Sascha Hauer that uses a chain of three dividers
under a fixed clock.Fixes: b11d282dbea2 (clk: divider: fix rate calculation for fractional rates)
Suggested-by: Sascha Hauer
Signed-off-by: Uwe Kleine-König
Acked-by: Sascha Hauer
Signed-off-by: Michael Turquette
07 Mar, 2015
1 commit
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Commit bca9690b9426 ("clk: divider: Make generic for usage elsewhere")
returned only the divider value for read-only dividers instead of the
actual rate.Fixes: bca9690b9426 ("clk: divider: Make generic for usage elsewhere")
Signed-off-by: Heiko Stuebner
Reviewed-by: James Hogan
Tested-by: James Hogan
Acked-by: Stephen Boyd
Signed-off-by: Michael Turquette
28 Jan, 2015
1 commit
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Some devices don't use mmio to interact with dividers. Split out the
logic from the register read/write parts so that we can reuse the
division logic elsewhere.Signed-off-by: Stephen Boyd
Tested-by: Kenneth Westfield
Signed-off-by: Michael Turquette
18 Jan, 2015
1 commit
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The common clk_register_{divider,gate,mux} functions allocated memory
for internal data which wasn't freed anywhere. Drivers using these
helpers could only unregister clocks but the memory would still leak.Add corresponding unregister functions which will release all resources.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Stephen Boyd
Signed-off-by: Michael Turquette
18 Nov, 2014
1 commit
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Commit 79c6ab509558 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in
v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the
recalc_rate() and round_rate() clock callbacks to be omitted.However using this flag has the unfortunate side effect of causing the
clock recalculation code when a clock rate change is attempted to always
treat it as a pass-through clock, i.e. with a fixed divide of 1, which
may not be the case. Child clock rates are then recalculated using the
wrong parent rate.Therefore instead of dropping the recalc_rate() and round_rate()
callbacks, alter clk_divider_bestdiv() to always report the current
divider as the best divider so that it is never altered.For me the read only clock was the system clock, which divided the PLL
rate by 2, from which both the UART and the SPI clocks were divided.
Initial setting of the UART rate set it correctly, but when the SPI
clock was set, the other child clocks were miscalculated. The UART clock
was recalculated using the PLL rate as the parent rate, resulting in a
UART new_rate of double what it should be, and a UART which spewed forth
garbage when the rate changes were propagated.Signed-off-by: James Hogan
Cc: Thomas Abraham
Cc: Tomasz Figa
Cc: Max Schwarz
Cc: # v3.16+
Acked-by: Haojian Zhuang
Signed-off-by: Michael Turquette
28 May, 2014
1 commit
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Commit c686078 ("clk: divider: Add round to closest divider") introduced
a helper function to check whether given divisor is the best one instead
of direct check. However due to int type used instead of unsigned long
for passing calculated rates to this function in certain cases an
overflow could occur, for example when trying to obtain maximum possible
clock rate by calling clk_round_rate(..., UINT_MAX).This patch fixes this issue by changing the type of rate, now and best
arguments of the function to unsigned long, which is the type that
should be used for clock rates.Signed-off-by: Tomasz Figa
Acked-by: Maxime Coquelin
Signed-off-by: Mike Turquette
24 May, 2014
3 commits
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Commit 1d9fe6b97 ("clk: divider: Fix best div calculation for power-of-two and
table dividers") introduces a regression in its _table_round_up function.When the divider passed to this function is greater than the max divider
available in the table, this function returns table's max divider.
Problem is that it causes an infinite loop in clk_divider_bestdiv() because
_next_div() will never return a value greater than maxdiv.Instead of returning table's max divider, this patch returns INT_MAX.
Reported-by: Fabio Estevam
Reported-by: Shawn Guo
Tested-by: Fabio Estevam
Tested-by: Shawn Guo
Signed-off-by: Maxime Coquelin
Signed-off-by: Mike Turquette -
From: Heiko Stuebner
Similar to muxes which already have a read-only flag there sometimes
exist dividers which should not be changed by the clock framework
but whose value still should be readable.Therefore add a READ_ONLY flag similar to the mux-one to clk-divider
Signed-off-by: Heiko Stuebner
[changed flag bit to BIT(5) as suggested by Tomasz Figa]
Signed-off-by: Thomas Abraham
Acked-by: Tomasz Figa
Acked-by: Max Schwarz
Tested-by: Max Schwarz
Signed-off-by: Mike Turquette
01 May, 2014
3 commits
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Currently, the for-loop used to try all the different dividers to find the
one that best fit tries all the values from 1 to max_div, incrementing by one.
In case of power-of-two, or table based divider, the loop isn't optimal.Instead of incrementing by one, this patch provides directly the next divider.
Signed-off-by: Maxime Coquelin
Signed-off-by: Mike Turquette -
In some cases, we want to be able to round the divider to the closest one,
instead than rounding up.This patch adds a new CLK_DIVIDER_ROUND_CLOSEST flag to specify the divider
has to round to closest div, keeping rounding up as de default behaviour.Signed-off-by: Maxime Coquelin
Signed-off-by: Mike Turquette -
The divider returned by clk_divider_bestdiv() is likely to be invalid in case
of power-of-two and table dividers when CLK_SET_RATE_PARENT flag isn't set.Fixes boot on STiH416 platform.
Signed-off-by: Maxime Coquelin
Signed-off-by: Mike Turquette
[mturquette@linaro.org: trivial merge conflict & updated changelog]
27 Feb, 2014
1 commit
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clk-divider.c does not calculate the rates consistently at the moment.
As an example, on OMAP3 we have a clock divider with a source clock of
864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are:6: 144000000
7: 123428571.428571...
8: 108000000Calling clk_round_rate() with the rate in the first column will give the
rate in the second column:144000000 -> 144000000
143999999 -> 123428571
123428572 -> 123428571
123428571 -> 108000000Note how clk_round_rate() returns 123428571 for rates from 123428572 to
143999999, which is mathematically correct, but when clk_round_rate() is
called with 123428571, the returned value is surprisingly 108000000.This means that the following code works a bit oddly:
rate = clk_round_rate(clk, 123428572);
clk_set_rate(clk, rate);As clk_set_rate() also does clock rate rounding, the result is that the
clock is set to the rate of 108000000, not 123428571 returned by the
clk_round_rate.This patch changes the clk-divider.c to use DIV_ROUND_UP when
calculating the rate. This gives the following behavior which fixes the
inconsistency:144000000 -> 144000000
143999999 -> 123428572
123428572 -> 123428572
123428571 -> 108000000Signed-off-by: Tomi Valkeinen
Signed-off-by: Mike Turquette
09 Jan, 2014
1 commit
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Commit 6d9252bd9a4bb (clk: Add support for power of two type dividers)
merged in v3.6 added the _get_val function to convert a divisor value to
a register field value depending on the flags. However it used the type
u8 for the div field, causing divisors larger than 255 to be masked
and the resultant clock rate to be too high.E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down
to 32.768KHz. The divisor was correctly calculated as 750 (0x2ee). This
was masked to 238 (0xee) resulting in a frequency of 103.26KHz.Signed-off-by: James Hogan
Cc: Rajendra Nayak
Cc: linux-arm-kernel@lists.infradead.org
Cc: stable@vger.kernel.org
Signed-off-by: Mike Turquette
28 Aug, 2013
1 commit
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the common clock drivers were motivated/initiated by ARM development
and apparently assume little endian peripheralswrap register/peripherals access in the common code (div, gate, mux)
in preparation of adding COMMON_CLK support for other platformsSigned-off-by: Gerhard Sittig
Signed-off-by: Mike Turquette
17 Aug, 2013
1 commit
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clk_register_divider() needs to be exported so that it could be used
in a module driver, otherwise we get the following error:ERROR: "clk_register_divider" [sound/soc/mxs/snd-soc-mxs.ko] undefined!
Signed-off-by: Fabio Estevam
Signed-off-by: Mike Turquette
[mturquette@linaro.org: also export clk_register_divider_table]
16 Jun, 2013
1 commit
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In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the
paradigm of reading-changing-writing the register contents.
Instead they use a hiword mask to indicate the changed bits.When b01 should be set as setting divider, it also needs to indicate
the change by setting hiword mask (b11 << 16).The patch adds divider flag for this usage.
Signed-off-by: Heiko Stuebner
Signed-off-by: Haojian Zhuang
Signed-off-by: Mike Turquette
11 Jun, 2013
1 commit
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If the current rate of parent clock is sufficient to provide child a
requested rate with a proper divider setting, the rate change request
should not be propagated. Instead, changing the divider setting is good
enough to get child clock run at the requested rate.On an imx6q clock configuration illustrated below,
ahb --> ipg --> ipg_per
132M 66M 66Mcalling clk_set_rate(ipg_per, 22M) with the current
clk_divider_bestdiv() implementation will result in the rate change up
to ahb level like the following, because of the unnecessary/incorrect
rate change propagation.ahb --> ipg --> ipg_per
66M 22M 22MFix the problem by trying to see if the requested rate can be achieved
by simply changing the divider value, and in that case return the
divider immediately from function clk_divider_bestdiv() as the best
one, so that all those unnecessary rate change propagation can be saved.Reported-by: Anson Huang
Signed-off-by: Shawn Guo
Signed-off-by: Mike Turquette
04 Apr, 2013
1 commit
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Dividers which have CLK_DIVIDER_ONE_BASED set have a redundant state,
being a divider value of zero. Some hardware implementations allow a
zero divider which simply doesn't alter the frequency. I.e. it acts like
a divide by one or bypassing the divider.
This flag is used to handle such HW in the clk-divider model.Signed-off-by: Soren Brinkmann
Signed-off-by: Mike Turquette
19 Jan, 2013
1 commit
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The macro is_power_of_two() in clk-divider.c was defined as !(i & ~i)
which is always true. Instead use is_power_of_2() from log2.h.Also add brackets around the macro arguments in div_mask to avoid any
future operator precedence problems.Signed-off-by: James Hogan
Cc: Joe Perches
Signed-off-by: Mike Turquette
[mturquette@linaro.org: use log2.h per Joe Perches; update changelog]
12 Jul, 2012
3 commits
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Most platforms end up using a mix of basic clock types and
some which use clk_hw_foo struct for filling in custom platform
information when the clocks don't fit into basic types supported.In platform code, its useful to know if a clock is using a basic
type or clk_hw_foo, which helps platforms know if they can
safely use to_clk_hw_foo to derive the clk_hw_foo pointer from
clk_hw.Mark all basic clocks with a CLK_IS_BASIC flag.
Signed-off-by: Rajendra Nayak
Signed-off-by: Mike Turquette -
Some divider clks do not have any obvious relationship
between the divider and the value programmed in the
register. For instance, say a value of 1 could signify divide
by 6 and a value of 2 could signify divide by 4 etc.
Also there are dividers where not all values possible
based on the bitfield width are valid. For instance
a 3 bit wide bitfield can be used to program a value
from 0 to 7. However its possible that only 0 to 4
are valid values.All these cases need the platform code to pass a simple
table of divider/value tuple, so the framework knows
the exact value to be written based on the divider
calculation and can also do better error checking.This patch adds support for such rate table based
dividers and as part of the support adds a new
registration function 'clk_register_divider_table()'
and a new macro for static definition
'DEFINE_CLK_DIVIDER_TABLE'.Signed-off-by: Rajendra Nayak
Signed-off-by: Mike Turquette -
Quite often dividers and the value programmed in the
register have a relation of 'power of two', something like
value div
0 1
1 2
2 4
3 8...Add support for such dividers as part of clk-divider.
The clk-divider flag 'CLK_DIVIDER_POWER_OF_TWO' should be used
to define such clocks.Signed-off-by: Rajendra Nayak
Signed-off-by: Mike Turquette
02 May, 2012
1 commit
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Create a struct clk_init_data to hold all data that needs to be passed from
the platfrom specific driver to the common clock framework during clock
registration. Add a pointer to this struct inside clk_hw.This has several advantages:
* Completely hides struct clk from many clock platform drivers and static
clock initialization code that don't care for static initialization of
the struct clks.
* For platforms that want to do complete static initialization, it removed
the need to directly mess with the struct clk's fields while still
allowing to statically allocate struct clk. This keeps the code more
future proof even if they include clk-private.h.
* Simplifies the generic clk_register() function and allows adding optional
fields in the future without modifying the function signature.
* Simplifies the static initialization of clocks on all platforms by
removing the need for forward delcarations or convoluted macros.Signed-off-by: Saravana Kannan
[mturquette@linaro.org: kept DEFINE_CLK_* macros and __clk_init]
Signed-off-by: Mike Turquette
Cc: Andrew Lunn
Cc: Rob Herring
Cc: Russell King
Cc: Jeremy Kerr
Cc: Thomas Gleixner
Cc: Arnd Bergman
Cc: Paul Walmsley
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Jamie Iles
Cc: Richard Zhao
Cc: Saravana Kannan
Cc: Magnus Damm
Cc: Mark Brown
Cc: Linus Walleij
Cc: Stephen Boyd
Cc: Amit Kucheria
Cc: Deepak Saxena
Cc: Grant Likely
25 Apr, 2012
2 commits
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For most of .set_rate implementation, parent_rate will be used, so just
like passing parent_rate into .recalc_rate, let's pass parent_rate into
.set_rate too.It also updates the kernel doc for .set_rate ops.
Signed-off-by: Shawn Guo
Signed-off-by: Mike Turquette -
The parent_rate will likely be used by most .round_rate implementation
no matter whether flag CLK_SET_RATE_PARENT is set or not, so let's
always pass parent_rate into .round_rate.Signed-off-by: Shawn Guo
Signed-off-by: Mike Turquette