27 Aug, 2015
4 commits
-
Current critical clock list for pistachio enables
only mips and sys clocks by default but there are
also other clocks that are not claimed by anyone and
needs to be enabled by default.This patch updates the critical clocks that need
to be enabled by default.Add a separate struct to distinguish the critical clocks
as listed:
1.) core clocks:
a.) mips clock
2.) peripheral system clocks:
a.) sys clock
b.) sys_bus clock
c.) DDR clock
d.) ROM clockFixes: b35d7c33419c("CLK: Pistachio: Register core clocks")
Cc: # 4.1
Reviewed-by: Andrew Bresticker
Signed-off-by: Ezequiel Garcia
Signed-off-by: Damien.Horsley
Signed-off-by: Govindraj Raja
Signed-off-by: Stephen Boyd -
.recalc_rate callback for the fractional PLL doesn't take operating
mode into account when calculating PLL rate. This results in
the incorrect PLL rates when PLL is operating in integer mode.Operating mode of fractional PLL is based on the value of the
fractional divider. Currently it assumes that the PLL will always
be configured in fractional mode which may not be
the case. This may result in the wrong output frequency.Also vco was calculated based on the current operating mode which
makes no sense because .set_rate is setting operating mode. Instead,
vco should be calculated using PLL settings that are about to be set.Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
Cc: # 4.1
Reviewed-by: Andrew Bresticker
Signed-off-by: Zdenko Pulitika
Signed-off-by: Govindraj Raja
Signed-off-by: Stephen Boyd -
PLL enable callbacks are overriding PLL mode (int/frac) and
Noise reduction (on/off) settings set by the boot loader which
results in the incorrect clock rate.PLL mode and noise reduction are defined by the DSMPD and DACPD bits
of the PLL control register. PLL .enable() callbacks enable PLL
by deasserting all power-down bits of the PLL control register,
including DSMPD and DACPD bits, which is not necessary since
these bits don't actually enable/disable PLL.This commit fixes the problem by removing DSMPD and DACPD bits
from the "PLL enable" mask.Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
Cc: # 4.1
Reviewed-by: Andrew Bresitcker
Signed-off-by: Zdenko Pulitika
Signed-off-by: Govindraj Raja
Signed-off-by: Stephen Boyd -
This commit fixes 32bit integer overflows throughout the pll driver
(i.e. wherever the result of integer multiplication may exceed the
range of u32).One of the functions affected by this problem is .recalc_rate. It
returns incorrect rate for some pll settings (not for all though)
which in turn results in the incorrect rate setup of pll's child
clocks.Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
Cc: # 4.1
Reviewed-by: Andrew Bresticker
Signed-off-by: Zdenko Pulitika
Signed-off-by: Govindraj Raja
Signed-off-by: Stephen Boyd
25 Aug, 2015
1 commit
-
Use the provider based method to get a clock's name so that we
can get rid of the clk member in struct clk_hw one day. Mostly
converted with the following coccinelle script.@@
struct clk_hw *E;
@@-__clk_get_name(E->clk)
+clk_hw_get_name(E)Acked-by: Heiko Stuebner
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Cc: Peter De Schrijver
Cc: Prashant Gaikwad
Cc: Stephen Warren
Acked-by: Thierry Reding
Cc: Thierry Reding
Cc: Alexandre Courbot
Cc: Tero Kristo
Cc: Ulf Hansson
Acked-by: Sebastian Hesselbarth
Acked-by: Andrew Bresticker
Cc: Ezequiel Garcia
Cc: Ralf Baechle
Cc: Kevin Cernekee
Acked-by: Geert Uytterhoeven
Cc: Ulrich Hecht
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: Stephen Boyd
21 Jul, 2015
1 commit
-
This clock provider uses the consumer API, so include clk.h
explicitly.Cc: Andrew Bresticker
Cc: Ralf Baechle
Signed-off-by: Stephen Boyd
05 Jun, 2015
3 commits
-
When setting the PLL rates, check that:
- VCO is within range
- PFD is within range
- PLL is disabled when postdiv is changed
- postdiv2
Signed-off-by: Kevin Cernekee
Signed-off-by: Ezequiel Garcia
Signed-off-by: Stephen Boyd -
Currently, when the rate is changed, the driver makes sure the
PLL is enabled before doing so. This is done because the PLL
cannot be locked while disabled. Once locked, the drivers
returns the PLL to its previous enable/disable state.This is a bit cumbersome, and can be simplified.
This commit reworks the .set_rate() functions for the integer
and fractional PLLs. Upon rate change, the PLL is now locked
only if it's already enabled.Also, the driver locks the PLL on .enable(). This makes sure
the PLL is locked when enabled, and not locked when disabled.Signed-off-by: Andrew Bresticker
Signed-off-by: Ezequiel Garcia
Signed-off-by: Stephen Boyd -
This commit adds a pll_lock() helper making the code more readable.
Cosmetic change only, no functionality changes.Signed-off-by: Andrew Bresticker
Signed-off-by: Ezequiel Garcia
Signed-off-by: Stephen Boyd
31 Mar, 2015
6 commits
-
Register the clock gates for the external audio and ethernet
reference clocks provided by the top-level general control block.Signed-off-by: Damien Horsley
Signed-off-by: Andrew Bresticker
Cc: Mike Turquette
Cc: Stephen Boyd
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia
Cc: James Hartley
Cc: James Hogan
Acked-by: Stephen Boyd
Patchwork: https://patchwork.linux-mips.org/patch/9321/
Signed-off-by: Ralf Baechle -
Register the system interface gate clocks provided by the peripheral
general control block. These clocks gate register access for various
peripherals.Signed-off-by: Damien Horsley
Signed-off-by: Andrew Bresticker
Cc: Mike Turquette
Cc: Stephen Boyd
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia
Cc: James Hartley
Cc: James Hogan
Acked-by: Stephen Boyd
Patchwork: https://patchwork.linux-mips.org/patch/9322/
Signed-off-by: Ralf Baechle -
Register the clocks generated by the peripheral clock controller.
This includes the clocks for several peripherals, including I2C,
PWM, watchdog, and timer.Signed-off-by: Damien Horsley
Signed-off-by: Andrew Bresticker
Cc: Mike Turquette
Cc: Stephen Boyd
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia
Cc: James Hartley
Cc: James Hogan
Acked-by: Stephen Boyd
Patchwork: https://patchwork.linux-mips.org/patch/9320/
Signed-off-by: Ralf Baechle -
Register the clocks generated by the core clock controller.
This includes the 7 PLLs and clocks for the CPU, RPU co-processor,
audio, WiFi, bluetooth, and several other peripherals.The MIPS and PERIPH_SYS clocks must remain enabled at all times.
Signed-off-by: Damien Horsley
Signed-off-by: Andrew Bresticker
Cc: Mike Turquette
Cc: Stephen Boyd
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia
Cc: James Hartley
Cc: James Hogan
Acked-by: Stephen Boyd
Patchwork: https://patchwork.linux-mips.org/patch/9317/
Signed-off-by: Ralf Baechle -
Add a driver for the integer (GF40LP_LAINT) and fractional (GF40LP_FRAC)
PLLs present on Pistachio.Signed-off-by: Andrew Bresticker
Cc: Mike Turquette
Cc: Stephen Boyd
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia
Cc: James Hartley
Cc: James Hogan
Acked-by: Stephen Boyd
Patchwork: https://patchwork.linux-mips.org/patch/9316/
Signed-off-by: Ralf Baechle -
Add helpers for registering clocks and clock providers on Pistachio.
Signed-off-by: Andrew Bresticker
Cc: Mike Turquette
Cc: Stephen Boyd
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia
Cc: James Hartley
Cc: James Hogan
Acked-by: Stephen Boyd
Patchwork: https://patchwork.linux-mips.org/patch/9318/
Signed-off-by: Ralf Baechle
