Eric Lee / smarc-fsl-linux-kernel

01 Dec, 2015

1 commit

  • 55213e1ac   clk: qcom: Add gfx3d ping-pong PLL frequency switching ... Browse Code »

    The GPU clocks on msm8996 have three dedicated PLLs, MMPLL2,
    MMPLL8, and MMPLL9. We leave MMPLL9 at the maximum speed (624
    MHz), and we use MMPLL2 and MMPLL8 for the other frequencies. To
    make switching frequencies faster, we ping-pong between MMPLL2
    and MMPLL8 when we're switching between frequencies that aren't
    the maximum. Implement custom rcg clk ops for this type of
    frequency switching.

    Signed-off-by: Stephen Boyd

    Stephen Boyd
     

17 Oct, 2015

1 commit

  • d8aa2beed   clk: qcom: clk-rcg: Add customized clk_ops for DSI RCGs ... Browse Code »

    DSI specific RCG clocks required customized clk_ops. There are
    a total of 4 RCGs per DSI block: DSI, BYTE, ESC and PIXEL.

    There are a total of 2 clocks coming from the DSI PLL, which serve as
    inputs to these RCGs. The BYTE and ESC RCGs are fed by one of the
    post dividers of DSI1 or DSI2 PLLs, and the DSI and PIXEL RCGs are fed by
    another divider of the PLL.

    In each of the 2 groups above, only one of the clocks sets its parent.
    These are BYTE RCG and DSI RCG for each of the groups respectively, as
    shown in the diagram below.

    The DSI and BYTE RCGs serve as bypass clocks. We create a new set of ops
    clk_rcg_bypass2_ops, which are like the regular bypass ops, but don't
    take in a freq table, since the DSI driver using these clocks is
    parent-able.

    The PIXEL RCG needs to derive the required pixel clock using dsixpll.
    It parses a m/n frac table to retrieve the correct clock.

    The ESC RCG doesn't have a frac M/N block, it can just apply a pre-
    divider. Its ops simply check if the required clock rate can be
    achieved by the pre-divider.

    +-------------------+
    | |---dsixpllbyte---o---> To byte RCG
    | | | (sets parent rate)
    | | |
    | | |
    | DSI 1/2 PLL | |
    | | o---> To esc RCG
    | | (doesn't set parent rate)
    | |
    | |----dsixpll-----o---> To dsi RCG
    +-------------------+ | (sets parent rate)
    ( x = 1, 2 ) |
    |
    o---> To pixel rcg
    (doesn't set parent rate)

    Signed-off-by: Archit Taneja
    Signed-off-by: Stephen Boyd

    Archit Taneja
     

18 Sep, 2015

1 commit

  • d042877aa   clk: qcom: Add support for RCGs with shared branches ... Browse Code »

    Some root clock generators may have child branches that are controlled
    by different CPUs. These RCGs require some special operations:
    - some enable bits have to be toggled when we set the rate;
    - if RCG is disabled we only cache the rate and set it later when enabled;
    - when the RCG is disabled, the mux is set to the safe source;

    Signed-off-by: Georgi Djakov
    [sboyd@codeaurora.org: Simplify recalc_rate implementation]
    Signed-off-by: Stephen Boyd

    Georgi Djakov
     

17 Sep, 2015

1 commit

  • 8ee9c7de0   clk: qcom: Allow clk_set_parent() to work on display clocks ... Browse Code »

    Sometimes the display driver may want to change the parent PLL of
    the display clocks (byte and pixel clocks) depending on the
    use-case. Currently the parent is fixed by means of having a
    frequency table with one entry that chooses a particular parent.
    Remove this restriction and use the parent the clock is
    configured for in the hardware during clk_set_rate(). This
    requires consumers to rely on the default parent or to configure
    the parent with clk_set_parent()/assigned-clock-parents on the
    clocks before calling clk_set_rate().

    Tested-by: Archit Taneja
    Cc: Hai Li
    Signed-off-by: Stephen Boyd

    Stephen Boyd
     

24 Mar, 2015

1 commit

  • 293d2e97b   clk: qcom: Introduce parent_map tables ... Browse Code »

    In the current parent mapping code, we can get duplicate or inconsistent
    indexes, which leads to discrepancy between the number of elements in the
    array and the number of parents. Until now, this was solved with some
    reordering but this is not always possible.

    This patch introduces index tables that are used to define the relations
    between the PLL source and the hardware mux configuration value.
    To accomplish this, here we do the following:
    - Define a parent_map struct to map the relations between PLL source index
    and register configuration value.
    - Add a qcom_find_src_index() function for finding the index of a clock
    matching the specific PLL configuration.
    - Update the {set,get}_parent RCG functions use the newly introduced
    parent_map struct.
    - Convert all existing drivers to the new parent_map tables.

    Signed-off-by: Georgi Djakov
    Signed-off-by: Stephen Boyd

    Georgi Djakov
     

13 Mar, 2015

1 commit

  • 9d3745d44   clk: qcom: Properly change rates for ahbix clock ... Browse Code »

    The ahbix clock can never be turned off in practice. To change the
    rates we need to switch the mux off the M/N counter to an always on
    source (XO), reprogram the M/N counter to get the rate we want and
    finally switch back to the M/N counter. Add a new ops structure
    for this type of clock so that we can set the rate properly.

    Fixes: c99e515a92e9 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver"
    Tested-by: Kenneth Westfield
    Signed-off-by: Stephen Boyd

    Stephen Boyd
     

23 Sep, 2014

1 commit

16 Jul, 2014

1 commit

  • 404c1ff67   clk: qcom: Support bypass RCG configuration ... Browse Code »

    In the case of HDMI clocks, we want to bypass the RCG's ability
    to divide the output clock and pass through the parent HDMI PLL
    rate. Add a simple set of clk_ops to configure the RCG to do
    this. This removes the need to keep adding more frequency entries
    to the tv_src clock whenever we want to support a new rate.

    Tested-by: Rob Clark
    Signed-off-by: Stephen Boyd

    Stephen Boyd
     

30 May, 2014

1 commit

17 Jan, 2014

1 commit