Eric Lee / smarc-fsl-linux-kernel

02 Jul, 2016

1 commit

  • cdbf85c1c   clk: qcom: add EBI2 clocks to the MSM8660 GCC ... Browse Code »

    This adds the EBI2 2X and EBI2 clocks to the MSM8660/APQ8060
    GCC. This is necessary to enable clocking of the external bus
    interface so that peripherals on it can be mounted. These two
    clocks are simple gated branch clocks.

    In the vendor tree clock-8x60, these clocks have some kind of
    dependency, the EBI2 clock has .depends = &ebi2_2x_clk.c,
    what this means is undocumented, it doesn't seem like there
    is a parent/child relationship, so the solution I chose was to
    just have the EBI2 driver get and enable both clocks.

    Cc: Stephen Boyd
    Cc: Bjorn Andersson
    Signed-off-by: Linus Walleij
    Signed-off-by: Stephen Boyd

    Linus Walleij
     

05 Mar, 2016

1 commit

13 Feb, 2016

1 commit

  • c430daf95   Revert "clk: qcom: Specify LE device endianness" ... Browse Code »

    This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87.

    The commit that caused us to specify LE device endianness here,
    29bb45f25ff3 (regmap-mmio: Use native endianness for read/write,
    2015-10-29), has been reverted in mainline so now when we specify
    LE it actively breaks big endian kernels because the byte
    swapping in regmap-mmio is incorrect. Let's revert this change
    because it will 1) fix the big endian kernels and 2) be redundant
    to specify LE because that will become the default soon.

    Cc: Kevin Hilman
    Tested-by: Kevin Hilman
    Cc: Mark Brown
    Signed-off-by: Stephen Boyd

    Stephen Boyd
     

21 Nov, 2015

1 commit

  • 329cabcec   clk: qcom: Specify LE device endianness ... Browse Code »

    All these clock controllers are little endian devices, but so far
    we've been relying on the regmap mmio bus handling this for us
    without explicitly stating that fact. After commit 4a98da2164cf
    (regmap-mmio: Use native endianness for read/write, 2015-10-29),
    the regmap mmio bus will read/write with the __raw_*() IO
    accessors, instead of using the readl/writel() APIs that do
    proper byte swapping for little endian devices.

    So if we're running on a big endian processor and haven't
    specified the endianness explicitly in the regmap config or in
    DT, we're going to switch from doing little endian byte swapping
    to big endian accesses without byte swapping, leading to some
    confusing results. On my apq8074 dragonboard, this causes the
    device to fail to boot as we access the clock controller with
    big endian IO accesses even though the device is little endian.

    Specify the endianness explicitly so that the regmap core
    properly byte swaps the accesses for us.

    Reported-by: Kevin Hilman
    Tested-by: Tyler Baker
    Tested-by: Kevin Hilman
    Cc: Simon Arlott
    Cc: Mark Brown
    Signed-off-by: Stephen Boyd

    Stephen Boyd
     

17 Nov, 2015

1 commit

  • a085f877a   clk: qcom: Move cxo/pxo/xo into dt files ... Browse Code »

    Put these clocks into the dt files instead of registering them
    from C code. This provides a few benefits. It allows us to
    specify the frequency of these clocks at the board level instead
    of hard-coding them in the driver. It allows us to insert an RPM
    clock in between the consumers of the crystals and the actual
    clock. And finally, it helps us transition the GCC driver to use
    RPM clocks when that configuration is enabled.

    Cc: Georgi Djakov
    Signed-off-by: Stephen Boyd

    Stephen Boyd
     

09 Oct, 2015

1 commit

07 Jul, 2015

1 commit

24 Mar, 2015

1 commit

  • 293d2e97b   clk: qcom: Introduce parent_map tables ... Browse Code »

    In the current parent mapping code, we can get duplicate or inconsistent
    indexes, which leads to discrepancy between the number of elements in the
    array and the number of parents. Until now, this was solved with some
    reordering but this is not always possible.

    This patch introduces index tables that are used to define the relations
    between the PLL source and the hardware mux configuration value.
    To accomplish this, here we do the following:
    - Define a parent_map struct to map the relations between PLL source index
    and register configuration value.
    - Add a qcom_find_src_index() function for finding the index of a clock
    matching the specific PLL configuration.
    - Update the {set,get}_parent RCG functions use the newly introduced
    parent_map struct.
    - Convert all existing drivers to the new parent_map tables.

    Signed-off-by: Georgi Djakov
    Signed-off-by: Stephen Boyd

    Georgi Djakov
     

20 Oct, 2014

1 commit

17 May, 2014

1 commit

  • d15998e09   clk: qcom: Fix msm8660 GCC probe ... Browse Code »

    When consolidating the msm8660 GCC probe code I forgot to keep
    around these temporary clock registrations. Put them back so the
    clock tree is not entirely orphaned.

    Fixes: 49fc825f0cc2 (clk: qcom: Consolidate common probe code)
    Signed-off-by: Stephen Boyd
    Signed-off-by: Mike Turquette

    Stephen Boyd
     

01 May, 2014

1 commit

  • 49fc825f0   clk: qcom: Consolidate common probe code ... Browse Code »

    Most of the probe code is the same between all the different
    clock controllers. Consolidate the code into a common.c file.
    This makes changes to the common probe parts easier and reduces
    chances for bugs.

    Signed-off-by: Stephen Boyd
    Signed-off-by: Mike Turquette

    Stephen Boyd
     

17 Jan, 2014

1 commit