Eric Lee / smarc-fsl-linux-kernel

13 Feb, 2016

1 commit

  • c430daf95   Revert "clk: qcom: Specify LE device endianness" ... Browse Code »

    This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87.

    The commit that caused us to specify LE device endianness here,
    29bb45f25ff3 (regmap-mmio: Use native endianness for read/write,
    2015-10-29), has been reverted in mainline so now when we specify
    LE it actively breaks big endian kernels because the byte
    swapping in regmap-mmio is incorrect. Let's revert this change
    because it will 1) fix the big endian kernels and 2) be redundant
    to specify LE because that will become the default soon.

    Cc: Kevin Hilman
    Tested-by: Kevin Hilman
    Cc: Mark Brown
    Signed-off-by: Stephen Boyd

    Stephen Boyd
     

21 Nov, 2015

1 commit

  • 329cabcec   clk: qcom: Specify LE device endianness ... Browse Code »

    All these clock controllers are little endian devices, but so far
    we've been relying on the regmap mmio bus handling this for us
    without explicitly stating that fact. After commit 4a98da2164cf
    (regmap-mmio: Use native endianness for read/write, 2015-10-29),
    the regmap mmio bus will read/write with the __raw_*() IO
    accessors, instead of using the readl/writel() APIs that do
    proper byte swapping for little endian devices.

    So if we're running on a big endian processor and haven't
    specified the endianness explicitly in the regmap config or in
    DT, we're going to switch from doing little endian byte swapping
    to big endian accesses without byte swapping, leading to some
    confusing results. On my apq8074 dragonboard, this causes the
    device to fail to boot as we access the clock controller with
    big endian IO accesses even though the device is little endian.

    Specify the endianness explicitly so that the regmap core
    properly byte swaps the accesses for us.

    Reported-by: Kevin Hilman
    Tested-by: Tyler Baker
    Tested-by: Kevin Hilman
    Cc: Simon Arlott
    Cc: Mark Brown
    Signed-off-by: Stephen Boyd

    Stephen Boyd
     

09 Oct, 2015

1 commit

17 Sep, 2015

2 commits

  • cb2eb7de3   clk: qcom: gdsc: Add GDSCs in apq8084 MMCC ... Browse Code »

    Add the GDSC instances that exist as part of apq8084 MMCC block.

    Signed-off-by: Stephane Viau
    Signed-off-by: Rajendra Nayak
    Signed-off-by: Stephen Boyd

    Stephane Viau
     
  • 8ee9c7de0   clk: qcom: Allow clk_set_parent() to work on display clocks ... Browse Code »

    Sometimes the display driver may want to change the parent PLL of
    the display clocks (byte and pixel clocks) depending on the
    use-case. Currently the parent is fixed by means of having a
    frequency table with one entry that chooses a particular parent.
    Remove this restriction and use the parent the clock is
    configured for in the hardware during clk_set_rate(). This
    requires consumers to rely on the default parent or to configure
    the parent with clk_set_parent()/assigned-clock-parents on the
    clocks before calling clk_set_rate().

    Tested-by: Archit Taneja
    Cc: Hai Li
    Signed-off-by: Stephen Boyd

    Stephen Boyd
     

07 Jul, 2015

1 commit

24 Mar, 2015

1 commit

  • 293d2e97b   clk: qcom: Introduce parent_map tables ... Browse Code »

    In the current parent mapping code, we can get duplicate or inconsistent
    indexes, which leads to discrepancy between the number of elements in the
    array and the number of parents. Until now, this was solved with some
    reordering but this is not always possible.

    This patch introduces index tables that are used to define the relations
    between the PLL source and the hardware mux configuration value.
    To accomplish this, here we do the following:
    - Define a parent_map struct to map the relations between PLL source index
    and register configuration value.
    - Add a qcom_find_src_index() function for finding the index of a clock
    matching the specific PLL configuration.
    - Update the {set,get}_parent RCG functions use the newly introduced
    parent_map struct.
    - Convert all existing drivers to the new parent_map tables.

    Signed-off-by: Georgi Djakov
    Signed-off-by: Stephen Boyd

    Georgi Djakov
     

18 Nov, 2014

1 commit

  • 9a6cb70f4   clk: qcom: Fix duplicate rbcpr clock name ... Browse Code »

    There is a duplication in a clock name for apq8084 platform that causes
    the following warning: "RBCPR_CLK_SRC" redefined

    Resolve this by adding a MMSS_ prefix to this clock and making its name
    coherent with msm8974 platform.

    Fixes: 2b46cd23a5a2 ("clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support")
    Signed-off-by: Georgi Djakov
    Reviewed-by: Stephen Boyd
    Signed-off-by: Michael Turquette

    Georgi Djakov
     

26 Sep, 2014

1 commit

  • 59c0621d4   clk: Remove .owner field for driver ... Browse Code »

    There is no need to init .owner field.

    Based on the patch from Peter Griffin
    "mmc: remove .owner field for drivers using module_platform_driver"

    This patch removes the superflous .owner field for drivers which
    use the module_platform_driver API, as this is overriden in
    platform_driver_register anyway."

    Signed-off-by: Kiran Padwal
    Signed-off-by: Mike Turquette

    Kiran Padwal
     

16 Jul, 2014

1 commit