10 Sep, 2016
1 commit
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Add a new macro to declare muxes based on a table and a gate.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
26 Aug, 2016
4 commits
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On sunxi we support cpufreq by changing the clock rate of PLL-CPU.
It's possible the clock output of the PLL goes out of the CPU's
operational limits when the PLL's multipliers / dividers are changed
and it hasn't stabilized yet. This would result in the CPU hanging.To circumvent this, we temporarily switch the CPU mux clock to another
stable clock before the rate change, and switch it back after the PLL
stabilizes. This is done with clk notifiers registered on the PLL.This patch adds common functions for notifiers to reparent mux clocks.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard -
Some clocks on the A31 have fixed pre-dividers on multiple parents.
Add support for them.Signed-off-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard -
Some clock muxes have holes, i.e. invalid or unconnected inputs,
between parent mux values.Add support for specifying a mux table to map clock parents to
mux values.Signed-off-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard -
Rename the internal mux macro to be consistent with the other internal
structure macros.Signed-off-by: Maxime Ripard
09 Aug, 2016
1 commit
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Some clocks have a predivider value that is larger than what u8 can
store. One such example is the OUT clk found on A20/A31, which has
a /750 pre-divider on one of the osc24M parents.Increase the size of the div field to u16.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
09 Jul, 2016
1 commit
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Some clocks in the Allwinner SoCs clocks unit are just muxes.
However, those muxes might also be found in some other complicated clocks
that would benefit from the code in there to deal with "advanced" features,
like pre-dividers.Introduce a set of helpers to reduce the code duplication in such cases.
Signed-off-by: Maxime Ripard
Signed-off-by: Michael Turquette
Link: lkml.kernel.org/r/20160629190535.11855-6-maxime.ripard@free-electrons.com