10 Sep, 2016

1 commit

• 87ba9e596   clk: sunxi-ng: div: Allow to set a maximum ... Browse Code »

  Some dividers might have a maximum value that is lower than the width of
  the register.

  Add a field to _ccu_div to handle those case properly. If the field is set
  to 0, the code will assume that the maximum value is the maximum one that
  can be used with the field register width.

  Otherwise, we'll use whatever value has been set.

  Signed-off-by: Maxime Ripard
  Acked-by: Chen-Yu Tsai

  Maxime Ripard

  2016-09-10 17:41:18 +0800  

09 Aug, 2016

1 commit

• a36583595   clk: sunxi-ng: nkm: Add mux to support multiple parents ... Browse Code »

  The MIPI mode of the MIPI-PLL on A31 is an NKM-style PLL with 2
  selectable parents.

  Add mux support to the NKM clock.

  Signed-off-by: Chen-Yu Tsai
  Signed-off-by: Maxime Ripard

  Chen-Yu Tsai

  2016-08-09 02:03:20 +0800  

09 Jul, 2016

1 commit

• df6561e60   clk: sunxi-ng: Add N-K-M Factor clock ... Browse Code »

  Introduce support for clocks that multiply and divide using two linear
  multipliers and one linear divider.

  Signed-off-by: Maxime Ripard
  Signed-off-by: Michael Turquette
  Link: lkml.kernel.org/r/20160629190535.11855-12-maxime.ripard@free-electrons.com

  Maxime Ripard

  2016-07-09 09:05:03 +0800