22 Apr, 2016

1 commit

• 8f0767611   clk: sunxi: mod1 clock should modify it's parent ... Browse Code »

  add CLK_SET_RATE_PARENT to modify the rate on clk upstream

  Signed-off-by: Marcus Cooper
  Signed-off-by: Maxime Ripard

  Andrea Venturi

  2016-04-22 06:29:21 +0800  

22 Oct, 2015

1 commit

• 9b038bc58   clk: sunxi: mod1 clock support ... Browse Code »

  The module 1 type of clocks consist of a gate and a mux and are used on
  the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or
  SPDIF. This commit adds support for them on the sunxi clock driver.

  Signed-off-by: Emilio López
  Signed-off-by: Hans de Goede
  Signed-off-by: Maxime Ripard
  Reviewed-by: Chen-Yu Tsai

  Emilio López

  2015-10-22 03:51:29 +0800