30 Jun, 2016
1 commit
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Move the UTMI PLL initialization code form clk-tegra.c files into
clk-pll.c. UTMI PLL was being configured and set in HW control right
after registration. However, when the clock init_table is processed and
child clks of PLLU are enabled, it will call in and enable PLLU as
well, and initiate SW enabling sequence even though PLLU is already in
HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status.Doing the initialization once during pllu_enable means we configure it
properly into HW control.A side effect of the commonization/localization of the UTMI PLL init
code, is that it corrects some errors that were present for earlier
generations. For instance, in clk-tegra124.c, it used to have:#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
when the correct shift to use is present in the new version:
#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
which matches the Tegra124 TRM register definition.
Signed-off-by: Andrew Bresticker
[rklein: Merged in some later fixes for potential deadlocks]
Signed-off-by: Rhyland Klein
[treding: coding style bike-shedding, remove unused variable]
Signed-off-by: Thierry Reding
28 Apr, 2016
1 commit
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The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.Signed-off-by: Thierry Reding
21 Nov, 2015
3 commits
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This removes the conversion from pdiv to hw, which is already taken
care of by _get_table_rate before this code is run. This avoids
incorrectly converting pdiv to hw twice and getting the wrong hw value.Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while
setting all the other fields.In order to prevent regressions on earlier SoC generations, all of the
frequency tables need to be updated so that they contain the actual
divider values. If they contain hardware values these would be converted
to hardware values again, yielding the wrong value.Signed-off-by: Rhyland Klein
[treding@nvidia.com: fix regressions on earlier SoC generations]
Signed-off-by: Thierry Reding -
SoC specific drivers should define the appropriate flags for each
PLL rather than relying on the registration functions to automatically
set flags on their behalf. This will properly allow for changes between
SoC generations where flags might be different and allow sharing the
same logic functions.Reviewed-by: Benson Leung
Signed-off-by: Rhyland Klein
Signed-off-by: Thierry Reding -
This is static data that is never modified, so make it const.
Signed-off-by: Thierry Reding
18 Nov, 2015
3 commits
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Use spaces around { and } and pad values so that the cells are properly
aligned.Signed-off-by: Thierry Reding
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Use unsigned int for loop variables that can never become negative and
remove a couple of gratuitous blank lines. Also use single spaces around
operators and use a single space instead of a tab to separate comments
from code.Signed-off-by: Thierry Reding
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The OSC_FREQ field of the OSC_CTRL register uses the value 12 for an
oscillator frequency of 26 MHz, not 260 MHz. This isn't really critical
because I don't think boards with such an oscillator have ever existed,
much less been supported upstream.Signed-off-by: Thierry Reding
20 Oct, 2015
1 commit
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tegra_audio_clk_init was written expecting a single PLL to be
passed in directly. Change this to accept an array which will
allow for supporting multiple plls and specifying specific data
about them, like their parent, which may change over time.Reviewed-by: Benson Leung
Signed-off-by: Rhyland Klein
Signed-off-by: Thierry Reding
26 Aug, 2015
2 commits
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The latest Tegra clk pull had some problems. Fix them.
drivers/clk/tegra/clk-tegra124.c:1450:6: warning: symbol 'tegra124_clock_assert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1466:6: warning: symbol 'tegra124_clock_deassert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1476:5: warning: symbol 'tegra124_reset_assert' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1486:5: warning: symbol 'tegra124_reset_deassert' was not declared. Should it be static?
drivers/clk/tegra/clk-dfll.c:590 dfll_load_i2c_lut() warn: inconsistent indenting
drivers/clk/tegra/clk-dfll.c:1448 dfll_build_i2c_lut() warn: unsigned 'td->i2c_lut[0]' is never less than zero.Signed-off-by: Stephen Boyd
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…egra/linux into clk-next
clk: tegra: Changes for v4.3-rc1
This contains the DFLL driver needed to implement CPU frequency scaling
on Tegra.
21 Jul, 2015
1 commit
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Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are using
it. Also add in a clkdev.h include that was missing in a file
using clkdev APIs.Cc: Peter De Schrijver
Cc: Thierry Reding
Signed-off-by: Stephen Boyd
16 Jul, 2015
2 commits
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Save and restore this register since the LP1 restore assembly routines
fiddle with it. Otherwise the CPU would keep running on PLLX after
resume from suspend even when DFLL was the original clocksource.Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
Acked-by: Peter De Schrijver
Acked-by: Michael Turquette
Signed-off-by: Thierry Reding -
The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block. This reset line is asserted upon SoC
reset. Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP block will complete.Thanks to Aleksandr Frid for identifying this and
saving hours of debugging time.Signed-off-by: Paul Walmsley
[ttynkkynen: ported to tegra124 from tegra114]
Signed-off-by: Tuomas Tynkkynen
[mikko.perttunen: ported to special reset callback]
Signed-off-by: Mikko Perttunen
Acked-by: Michael Turquette
Signed-off-by: Thierry Reding
13 May, 2015
3 commits
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On Tegra124, as we now have a proper driver for the EMC.
Signed-off-by: Tomeu Vizoso
Signed-off-by: Thierry Reding -
The driver is currently only tested on Tegra124 Jetson TK1, but should
work with other Tegra124 boards, provided that correct EMC tables are
provided through the device tree. Older chip models have differing
timing change sequences, so they are not currently supported.Signed-off-by: Mikko Perttunen
Signed-off-by: Tomeu Vizoso
[treding@nvidia.com: use more consistent function names]
Signed-off-by: Thierry Reding -
This clock has never been able to do anything.
Signed-off-by: Mikko Perttunen
Signed-off-by: Tomeu Vizoso
Signed-off-by: Thierry Reding
10 Apr, 2015
3 commits
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The current parent, plld_out0, does not exist. The proper name is
pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to
be more consistent with other clock names.Fixes: b270491eb9a0 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux")
Signed-off-by: Thierry Reding -
Currently the Tegra clock driver simplifies the clock tree somewhat by
taking advantage of the fact that clk_m runs at the same frequency as
the oscillator. While that's true on all currently supported SoCs, it
does not apply to Tegra210 anymore. On Tegra210 clk_m is typically
divided down from the oscillator frequency. To support that setup, add
a separate clock for the oscillator that both clk_m and pll_ref derive
from.Modify the tegra_osc_clk_init() function to take an additional divider
parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210
will read the divider from a register in the clock & reset controller.Signed-off-by: Thierry Reding
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Add the clocks used for HDMI audio played through the HDA controller.
Initialize the codec clock to 48Mhz and the HDA clock to 102MHz per
the TRM.Signed-off-by: Dylan Reid
Acked-by: Stephen Warren
Signed-off-by: Thierry Reding
02 Feb, 2015
3 commits
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PLLD is the only parent for DSIA & DSIB on Tegra124 and
Tegra132. Besides, BIT 30 in PLLD_MISC register controls
the output of DSI clock.So this patch removes "dsia_mux" & "dsib_mux", and create
a new clock "plld_dsi" to represent the DSI clock enable
control.Signed-off-by: Peter De Schrijver
Signed-off-by: Mark Zhang -
Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This
patch mostly deals with the small differences.Since Tegra132 contains many of the same PLL clock sources used on
Tegra114 and Tegra124, enable them in drivers/clk/tegra/clk-pll.c when
the kernel is configured to include Tegra132 support.This patch is based on several patches from others:
1. a patch from Peter De Schrijver:
http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html
2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on
Tegra132"), and3. a patch from Allen Martin ("clk: Enable tegra clock driver for
tegra132").Signed-off-by: Paul Walmsley
Signed-off-by: Paul Walmsley
Cc: Peter De Schrijver
Cc: Allen Martin
Cc: Prashant Gaikwad
Cc: Stephen Warren
Cc: Thierry Reding
Cc: Alexandre Courbot
Cc: Bill Huang
Cc: Mike Turquette
Cc: Stephen Boyd -
Set the parent of the dsi lp clocks to pll_p and the rate
to 68MHz. The default parent is clk_m and rate is 12MHz, this
is too slow to receive data from the peripheral.Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz
will suffice.Signed-off-by: Sean Paul
Signed-off-by: Peter De Schrijver
26 Nov, 2014
1 commit
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The memory controller clock runs either at half or the same frequency as
the EMC clock.Reviewed-By: Tomeu Vizoso
Acked-by: Mike Turquette
Signed-off-by: Thierry Reding
18 Sep, 2014
1 commit
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These clocks are used as parents for some EMC timings.
Signed-off-by: Mikko Perttunen
27 Jun, 2014
1 commit
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Ensure some clocks critical for system operation are always. Also enable csite
for JTAG debugging and set the tsensor and soc_therm clock frequencies for the
upcoming soctherm driver.Signed-off-by: Peter De Schrijver
26 Jun, 2014
1 commit
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This adds two clocks, SATA and SATA_OOB, to the Tegra124 clock initialization
table. The clocks are needed for working SATA support.Signed-off-by: Mikko Perttunen
Acked-by: Stephen Warren
25 Jun, 2014
1 commit
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vi_sensor and vi_sensor2 have a wrong hw clkid on Tegra124. Fix this by
correcting the hw clkid for Tegra124 and creating the Tegra114 vi_sensor clock
from its own data. Tegra124 was also using the wrong internal clock id.Signed-off-by: Peter De Schrijver
23 May, 2014
2 commits
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Initialize the XUSB-related clocks with appropriate parents and rates
for both Tegra114 and Tegra124.Signed-off-by: Jim Lin
Signed-off-by: Andrew Bresticker
Signed-off-by: Mike Turquette -
Currently the Tegra1x4 clock init code hard-codes the mux setting
for xusb_hs_src and treats it as a fixed-factor clock. It is,
however, a mux which can be parented by either xusb_ss_src/2 or
pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an
entry in periph_clks[] for the xusb_hs_src mux.Signed-off-by: Andrew Bresticker
Signed-off-by: Mike Turquette
24 Apr, 2014
1 commit
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The Tegra124 clock driver currently provides 3 clocks that don't actually
exist; 2 for NAND and one for UART5/UARTE. Delete these.Cc:
Signed-off-by: Stephen Warren
Signed-off-by: Arnd Bergmann
21 Feb, 2014
1 commit
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Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the
vic03 and gpu clocks respectively.Signed-off-by: Peter De Schrijver
17 Feb, 2014
5 commits
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The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with
6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114
and Tegra124 to use these clocks instead.Signed-off-by: Andrew Bresticker
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The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents.
Change thte id to tegra_clk_host1x_8 so that the correct clock gets
registered.Signed-off-by: Mark Zhang
Signed-off-by: Andrew Bresticker -
Set correct pll_d2_out0 divider and correct the p div values for pll_d2.
Signed-off-by: David Ung
Signed-off-by: Andrew Bresticker -
PLLD was using the same mnp table as PLLP. Fix it to use its own
table which is different from PLLP's.Signed-off-by: Rhyland Klein
Signed-off-by: Andrew Bresticker -
This table had settings for 216MHz, but PLLP is (and is supposed to be)
configured at 408MHz. If that table is used and PLLP_BASE_OVRRIDE is
not set, the kernel will panic in clk_pll_recalc_rate().Signed-off-by: Gabe Black
Signed-off-by: Andrew Bresticker
12 Dec, 2013
1 commit
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The Tegra CAR module implements both a clock and reset controller. So
far, the driver exposes the clock feature via the common clock API and
the reset feature using a custom API. This patch adds an implementation
of the common reset framework API (include/linux/reset*.h). The legacy
reset implementation will be removed once all drivers have been
converted.Signed-off-by: Stephen Warren
Reviewed-by: Thierry Reding
Acked-By: Peter De Schrijver
27 Nov, 2013
2 commits
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This clock is needed to ensure the FUSE registers can be accessed
without freezing the system.Signed-off-by: Alexandre Courbot
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Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.Cc: Mike Turquette
Signed-off-by: Joseph Lo
Acked-by: Stephen Warren
