Eric Lee / smarc-fsl-linux-kernel

31 Aug, 2016

1 commit

  • 9217a5bf6   dmaengine: dw: keep copy of custom slave config in dwc ... Browse Code »

    It seems we need to extend custom slave configuration by one more member to
    support Intel Quart UART. It becomes a burden to manage all members of struct
    dw_dma_slave one-by-one.

    Replace the set of fields by embedding struct dw_dma_slave into struct
    dw_dma_chan.

    Acked-by: Vinod Koul
    Signed-off-by: Andy Shevchenko
    Tested-by: Bryan O'Donoghue
    Signed-off-by: Greg Kroah-Hartman

    Andy Shevchenko
     

02 May, 2016

1 commit

19 Apr, 2016

1 commit

  • ab703f818   dmaengine: dw: lazy allocation of dma descriptors ... Browse Code »

    This patch changes the driver to allocate DMA descriptors when
    needed. This stops memory resources to be wasted and letting
    them sit idle in the free_list structure when the device doesn't
    need it... This also solves the problem, that a driver has to
    guess the number of how many descriptors it needs to allocate
    in advance. Currently, the dma engine will just fail when put
    under load by sata_dwc_460ex.

    Signed-off-by: Christian Lamparter
    Signed-off-by: Vinod Koul

    Christian Lamparter
     

14 Apr, 2016

7 commits

  • b68fd0976   dmaengine: dw: move residue to a descriptor ... Browse Code »

    Residue is a property of any active descriptor. So, any descriptor may be in
    different state but residue is a feature of active descriptor. Check if the
    asked descriptor is active and return proper residue value for it.

    Signed-off-by: Andy Shevchenko
    Signed-off-by: Vinod Koul

    Andy Shevchenko
     
  • 423f9cbf2   dmaengine: dw: move dwc->initialized to dwc->flags ... Browse Code »

    We have already dedicated variable for flags, therefore no need to create an
    additional storage for that. Covert dwc->initialized to use dwc->flags.

    Signed-off-by: Andy Shevchenko
    Signed-off-by: Vinod Koul

    Andy Shevchenko
     
  • 5e09f98e7   dmaengine: dw: move dwc->paused to dwc->flags ... Browse Code »

    We have already dedicated variable for flags, therefore no need to create an
    additional storage for that. Convert dwc->paused to use dwc->flags.

    Signed-off-by: Andy Shevchenko
    Signed-off-by: Vinod Koul

    Andy Shevchenko
     
  • 897e40d3b   dmaengine: dw: substitute dma_read_byaddr by dma_readl_native ... Browse Code »

    Since struct dw_dma is allocated and regs member is assigned properly we can
    use standard IO accessors to the DMA registers.

    Signed-off-by: Andy Shevchenko
    Signed-off-by: Vinod Koul

    Andy Shevchenko
     
  • 2a0fae025   dmaengine: dw: set LMS field in descriptors ... Browse Code »

    The LMS field indicates from which master the descriptor is to be
    read. This patch assumes this is always the same as the memory
    side in a peripheral transfer which is true for all known systems.

    Signed-off-by: Mans Rullgard
    Acked-by: Andy Shevchenko
    Signed-off-by: Vinod Koul

    Mans Rullgard
     
  • df1f3a230   dmaengine: dw: fix byte order of hw descriptor fields ... Browse Code »

    If the DMA controller uses a different byte order than the host CPU,
    the hardware linked list descriptor fields need to be byte-swapped.

    This patch makes the driver write these fields using the same byte
    order it uses for mmio accesses to the DMA engine. I do not know
    if this is guaranteed to always be correct.

    Signed-off-by: Mans Rullgard
    Acked-by: Andy Shevchenko
    Signed-off-by: Vinod Koul

    Mans Rullgard
     
  • c422025c1   dmaengine: dw: rename masters to reflect actual topology ... Browse Code »

    The source and destination masters are reflecting buses or their layers to
    where the different devices can be connected. The patch changes the master
    names to reflect which one is related to which independently on the transfer
    direction.

    The outcome of the change is that the memory data width is now always limited
    by a data width of the master which is dedicated to communicate to memory.

    The patch will not break anything since all current users have the same data
    width for all masters. Though it would be nice to revisit avr32 platforms to
    check what is the actual hardware topology in use there. It seems that it has
    one bus and two masters on it as stated by Table 8-2, that's why everything
    works independently on the master in use. The purpose of the sequential patch
    is to fix the driver for configuration of more than one bus.

    The change is done in the assumption that src_master and dst_master are
    reflecting a connection to the memory and peripheral correspondently on avr32
    and otherwise on the rest.

    Acked-by: Hans-Christian Egtvedt
    Acked-by: Mark Brown
    Signed-off-by: Andy Shevchenko
    Signed-off-by: Vinod Koul

    Andy Shevchenko
     

25 Jan, 2016

1 commit

05 Feb, 2015

1 commit

22 Dec, 2014

1 commit

15 Oct, 2014

2 commits

11 Sep, 2014

3 commits

  • a15636e83   dmaengine: dw: move clock operations to platform.c ... Browse Code »

    On BayTrail platform DMA is not functional in the PCI mode, whereby it always
    failed and exit at the point when it tries to get a clock. It causes the PCI
    mode probe to exit with the error message:
    dw_dmac_pci: probe of 0000:00:1e.0 failed with error -2

    This patch moves clock operations to where it belongs to. Thus, the clock is
    provided only in ACPI / non-PCI cases.

    Reported-by: Chew, Chiau Ee
    Signed-off-by: Andy Shevchenko
    Signed-off-by: Vinod Koul

    Andy Shevchenko
     
  • 895005202   dmaengine: dw: apply both HS interfaces and remove slave_id usage ... Browse Code »

    Instead of one request line member let's use both source and destination ones.
    Usually we have no such hardware except Atmel MMC controller found on AVR32
    platform (see arch/avr32/mach-at32ap/at32ap700x.c and
    drivers/mmc/host/atmel-mci.c).

    This patch removes slave_id usage since it'll be removed from the generic
    structure in later. This breaks the non-ACPI / non-DT cases for the users of
    the driver, i.e. SPI and HSUART. However, these cases mean only PCI enumerated
    devices for now, which is anyway broken (considering more than one DMA
    controller in the system) and this patch series is intended to fix that
    eventually.

    The ACPI and DT cases shall be aware of the channel direction when setting
    request lines, but this is a minor problem that would be addressed in future.

    Suggested-by: Arnd Bergmann
    Signed-off-by: Andy Shevchenko
    Signed-off-by: Vinod Koul

    Andy Shevchenko
     
  • 3d598f47e   dmaengine: dw: move dw_dmac.h to where it belongs to ... Browse Code »

    There is a common storage for platform data related structures and definitions
    inside kernel source tree. The patch moves file from include/linux to
    include/linux/platform_data and renames it acoordingly. The users are also
    updated.

    Signed-off-by: Andy Shevchenko
    Acked-by: Viresh Kumar
    [For the arch/avr32/.* and .*sound/atmel.*]
    Acked-by: Hans-Christian Egtvedt
    Signed-off-by: Vinod Koul

    Andy Shevchenko
     

26 Mar, 2014

1 commit

05 Jul, 2013

2 commits