28 Feb, 2018
1 commit
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Signed-off-by: Laurentiu Palcu
26 Jan, 2018
1 commit
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Define hdmi pixel select clocks.
Define av_pll_bypass clock.Signed-off-by: Sandor Yu
Reviewed-by: Robby Cai
(cherry picked from commit a2f7ef2212ab227adea6753e5090c64a503387fe)
08 Jan, 2018
1 commit
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Rename imx8x mipi csi i2c power domain.
Acked-by: Fugang Duan
Signed-off-by: Sandor Yu
15 Dec, 2017
1 commit
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The CCGR RAWNAND is shared by apbh-dma and gpmi clocks, so must use
imx_clk_gate2_shared2 to produce two clocks. Otherwise, apbh-dma clock
won't be enabled individually.Signed-off-by: Ye Li
Reviewed-by: Bai Ping
13 Dec, 2017
1 commit
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Add uSDHC clock MUX to allow uSDHC driver to select
parent, currently only support PLL0 and PLL1 as
uSDHC clock's parent.Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
Tested-by: Haibo Chen
11 Dec, 2017
10 commits
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This patch adds IMX8QXP_DC0_DPR1_APB_CLK and IMX8QXP_DC0_DPR1_B_CLK clocks
support.Signed-off-by: Liu Ying
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Add CLKO2 for i.MX8MQ
Set parent for MIPI CSI1/2 CORE/PHY_REF/ESCSigned-off-by: Robby Cai
Reviewed-by: Sandor Yu -
The Video PLL2 has a output enable bit to do clk gate,
So we need to register this gate to save power.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang -
Add missing clocks for MIPI-DSI SS: RX_ESC and TX_ESC
Also added the posibility to select clock parents for MIPI-DSI versus
LVDS.
The SCFW was changed, so now the LVDS pixel and phy clocks need to
specify their parrents.
Also, the TX_ESC and RX_ESC clocks from MIPI-DSI need to specify their
parrents in DTS files.Signed-off-by: Robert Chiras
Signed-off-by: Oliver Brown -
Merge community clock code change for i.MX7D.
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT
and NAND_CLK_ROOT. However, the gate has been in the chain of the
latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT
only, e.g. as required by APBH-Bridge-DMA.Add new clocks which represent the clock after the gate, and use a
shared clock gate to correctly model the hardware.Signed-off-by: Han Xu
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add the mu clock
Signed-off-by: Richard Zhu
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On i.MX8MQ, the dram core clock can be sourced from dram_pll or
the dram_alt clock, when sourced from the dram_alt, it has a fix
divider(1/4). When the DDRC core clock is lower than 800MHz, we
can swith the core clock to dram_alt source.The dram apb clock's mux option 2 should be sys1_pll_40m, so fixed it.
Signed-off-by: Bai Ping
Reviewed-by: Anson Huang -
There're two M4 I2C instances in MX8QM.
Signed-off-by: Dong Aisheng
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Add the cm41 ipg clk
BuildInfo:
- SCFW a6fd9a48, IMX-MKIMAGE 0, ATF 0
- U-Boot 2017.03-imx_v2017.03_4.9.11_imx8_alpha+g258936cSigned-off-by: Richard Zhu
Reviewed-by: Robin Gong
Reviewed-by: Dong Aisheng
Tested-by: Andy Duan -
Add the cm40 ipg clk
BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0Signed-off-by: Richard Zhu
05 Oct, 2017
25 commits
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Add clk for dsi0-i2c1, dsi1-i2c0 and dsi1-i2c1
Signed-off-by: Robert Chiras
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DC clocks can choose their clock source between PLL1, PLL2 and
bypass input.
This patch introduces a multiplexer in the dc clock topology to
allow this choice and introduces one set of parents that will be used
for both display0 and display1 clocks.Clock paths tested:
1. PLL2(dc0_pll1_clk)->DC0_DISP1(dc0_disp1_clk)->LVDS
2. BYP(dc0_bypass0_clk)->DC0_DISP1(dc0_disp1_clk)->LVDS(BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0)
Signed-off-by: Adriana Reus
Reviewed by: Ranjani Vaidyanathan -
Add focaltech new touch panel ft5246 support.
Set the ft5426 as default panel for dts. If want to use the old panel, then
it needs to boot with imx7ulp-evk-ft5416.dtb file.Signed-off-by: Fugang Duan
(cherry picked from commit:963fea909ef5e42294cb2e656e5e3870a2171c01) -
Add OCOTP clock support.
Signed-off-by: Peng Fan
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Define three root clocks for DCSS module:
.IMX8MQ_CLK_DISP_AXI_ROOT
.IMX8MQ_CLK_DISP_APB_ROOT
.IMX8MQ_CLK_DISP_RTRM_ROOTThese root clocks share one clock gate along with
'IMX8MQ_CLK_DISP_ROOT' clock. So change its type
to be shared gate clock too.Signed-off-by: Fancy Fang
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Add VPU encoder/decoder clocks.
Signed-off-by: Ranjani Vaidyanathan
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Add cm40 I2C clock for imx8qxp
Signed-off-by: Shengjiu Wang
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add clk for dsi0 i2c0
Signed-off-by: Gao Pan
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Ensure that both PLL and IPG clocks are enabled and set by
the HDMI irqsteer device tree entry.
Fix some HDMI clock names.Signed-off-by: Ranjani Vaidyanathan
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The mclk_out clock is used as codec's mclk, so need to add
its power domain to codec node.Signed-off-by: Shengjiu Wang
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Add the tmu root clock for i.mx8mq.
Signed-off-by: Bai Ping
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IMX7d does not contain an M0 Core and this particular
clock doesn't seem connected to anything else.
Remove this entry from the CCM driver.Signed-off-by: Adriana Reus
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Add video_pll2 SSCG PLL clock in anamix which can
be used by HDMI and DCSS.Signed-off-by: Fancy Fang
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"
commit a645f3c4c529e1f8cc5a624a047a3af56cfd39e1
Author: Ranjani Vaidyanathan
Date: Thu Jun 29 15:21:53 2017 -0500Turn off all HDMI-TX clocks by default. This is required for setting
the rate of the DIG PLL.
Add code to enable/disable the correct clocks before SECO accesses the HDMI SS.Signed-off-by: Ranjani Vaidyanathan
"Signed-off-by: Ranjani Vaidyanathan
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Add the ahb and ipg clocks for mipi dsi rxesc and txesc.
Signed-off-by: Fancy Fang
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Add wdog nodes in dtsi.
Enable wdog1 for imx8mq evk board.
Enable imx wdt in defconfig.
Correct clock, offset 0x4550 is actually for wdog3.Signed-off-by: Peng Fan
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imx8mq iomux header file uart part select_input config are
wrong that cause most of uart pin not work.
Add DCE and DTE string to distinguish the pin is for uart
which function, and clear all select_input for output pin.Signed-off-by: Fugang Duan
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add audio ipg clock, sai ipg clock and correct some wrong
place in clock tree.Signed-off-by: Mihai Serban
Signed-off-by: Shengjiu Wang -
add sdma clock and ipg clock on i.mx8mq.
Signed-off-by: Robin Gong
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Add i.MX8MQ clock and pinctrl file.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
Signed-off-by: Peng Fan -
Add mipi csi local interrupter clock
Signed-off-by: Sandor Yu
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Add imx8 image subsystem power domain name.
Signed-off-by: Sandor Yu
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- use one standalone hsio node to share the region to
pciea, pcieb and sata.
- axi master slave and dbi clks and pipe_clk are required
- enable pcieb
change the pd of the pcieb, otherwise, clk is failed to enable
- add the cpu addr offset
Bit[31:24]
pciea 60 - 6f ---> 40 - 4f
pcieb 70 - 7f ---> 80 - 8fSigned-off-by: Richard Zhu
Reviewed-by: Frank Li -
This patch adds some clocks support for DC and MIPI-LVDS subsystems.
Signed-off-by: Liu Ying
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Add lvds subsystem LIS ipg clock.
Signed-off-by: Fugang Duan
