10 Jul, 2019
1 commit
15 Jan, 2017
1 commit
01 Jul, 2016
1 commit
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Change the hardware reset gpio to 'GPIO6_IO15' for mipi dsi to
allow fec2 and mipi dsi can run at the same time. This needs
some hardware rework as follows:
"
1. Replace R631 with 100K resistor;
2. Remove D14, D24;
3. Solder the Cathode of the diode to R471,
you can use BAT54HT1(ONSEMI) or NSR0320MW2T1G(ONSEMI);
4. Solder the wire to the Anode end of the diode;
5. Scrape the solder mask(Green oil) of the MIPI Reset via,
then solder the end of the wire to the via.
"Signed-off-by: Fancy Fang
(cherry picked from commit 0af28564e73f006f742a9af0db4bc5b8588e3490)
27 Jun, 2016
1 commit
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In this notifier, we can power on/off the two LDO's which are needed
for USB HSIC.Signed-off-by: Peter Chen
22 Jun, 2016
1 commit
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During suspend, as 24MHz will be disabled, but system counter
needs to be running in order to maintain accurate clock source,
so we need to switch system counter's clock from base clock(24MHz)
to alternate clock(32K) before system enter STOP mode, otherwise,
the suspend time will NOT be counted into system time when issue
a "date" command.Signed-off-by: Anson Huang
15 Jun, 2016
4 commits
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Add the dts support for the new mipi panel 'TFT3P5581'.
Signed-off-by: Fancy Fang
(cherry picked from commit 3b2b9a727c8c6d97e225237a52865486bab844fa) -
According to the 7d sdb schematic, only when the 'LCD_PWR_EN' is
low voltage, the 'LCD_3V3' can has the 3.3V voltage. And 'LCD_3V3'
is used to provide 3.3V power for lcd peripherals.Signed-off-by: Fancy Fang
(cherry picked from commit 2b34ed894f2efa27b336b61d4db9985a9c5e4f14) -
PAD_GPIO1_IO01 bit[31:7] are reserved, remove the setting mapping to
this reserved field.Signed-off-by: Fugang Duan
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It is missing at imx7d.dtsi, but used at source code.
Signed-off-by: Peter Chen
02 Jun, 2016
1 commit
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Panic when 'reboot recovery\bootloader'
[] (clk_enable) from [] (do_switch_recovery+0x58/0xbc)
[] (do_switch_recovery) from [] (imx_reboot_notifier_call+0x58/0x68)
[] (imx_reboot_notifier_call) from [] (notifier_call_chain+0x44/0x84)
[] (notifier_call_chain) from [] (__blocking_notifier_call_chain+0x48/0x60)
[] (__blocking_notifier_call_chain) from [] (blocking_notifier_call_chain+0x18/0x20)
[] (blocking_notifier_call_chain) from [] (kernel_restart_prepare+0x18/0x38)BSP do not have snvs clock management to save power.
So remove snvs clock management when access SNVS.
Refine the switch mode code.Signed-off-by: zhang sanshan
31 May, 2016
3 commits
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When Mega/Fast Mix off in DSM mode, RDC recovery needs PCIe/PXP/EIM
clock to be enabled, otherwise, with M4 enabled, DSM resume will fail.We only enable them before entering DSM and hardware will disable
them when DSM is entered and they will be re-enabled after resume,
then in low level resume phase, we will disable them again.Signed-off-by: Anson Huang
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For i.MX7D, current runtime clock management code will skip all
PLL/PFD/GATE enable/disable when M4 is enabled, this is NOT good
for power number in low power idle and audio playback, as M4 only
uses one high speed PFD which is from system PLL, it is never
disabled runtimely, so we can just enable the hardware operation of
PLL/PFD/GATE for A7.Signed-off-by: Anson Huang
24 May, 2016
6 commits
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Add pinctrls for usbotg1 and usbotg2 vbus control. This missing keeps
the vbus enable pin is high after power up, so vbus is on and otg port
will not enter suspend in device mode, as active usb port has high
bus freq requested, this prevents system enter low bus freq.Signed-off-by: Li Jun
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Add 'ipg' and 'axi' clocks for pxp which should
be used to control runtime power managments.Signed-off-by: Fancy Fang
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The pxp require two clocks to enable when it works, and
they are 'ipg' and 'axi' clocks. Besides, the two clocks
share the same CCGR to control clock gating.Signed-off-by: Fancy Fang
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The 'otm8018b' is the Source Driver IC which is used
by 'TFT3P5079E' panel. This patch is adding the build
support for the 'otm8018b' kernel driver.Signed-off-by: Fancy Fang
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Create a new dts for the 'TFT3P5079E' mipi panel on
imx7d sabresd revb board.Signed-off-by: Fancy Fang
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To avoid touch other bits of HW_ANADIG_SNVS_MISC_CTRL , use set/clear register
, and correct the bit29 setting:
--before: write 1 to toggle DDR power pin to high before enter DDR retention,
and write 1 again to pull pin to low when exit from DDR retention.
--now: write 1 to pull DDR power pin to high and write 0 to low.Signed-off-by: Robin Gong
16 May, 2016
1 commit
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This dts is only for USB HSIC controller test which needs
Validation Port Card on it.Disable controller 3 due to strange signal on it at arm2 board.
Signed-off-by: Peter Chen
(cherry picked from commit 8bd0739d81719ed8a09ca4e45393bb1c5ce3de83)
11 May, 2016
3 commits
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Add csis-clk-settle property to imx7D SDB mipi csi.
Signed-off-by: Sandor Yu
(cherry picked from commit 01365628fdfadc4f8343722a2d5c69d5d8037540) -
ov5647 mipi camera sensor is replaced by ov5640
on imx7D SDB RevB board.Signed-off-by: Sandor Yu
(cherry picked from commit aef2ab14e91ccd173086a9849cf64619e078ed6f) -
GPIO0~GPIO7 part:
- Commit(c8cabda5ab07) add some wrong input sel value for uart, return
them to origin setting.
- Add uart DTE pin mode setting.UART2_TX_DATA pin part:
- RM doc "iMX7D_RM_Rev0_Approval.pdf" (2016.04.25 updated in compass)
updated input sel define for UART2_RX_DATA, then set the correct input
sel for the pin.Signed-off-by: Fugang Duan
(cherry picked from commit: 90a8b06b9735dd5b8d2023ff3b95886441e0e8d9)
09 May, 2016
2 commits
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On i.MX7D, per design team's require, need to make sure
DLL is locked after DDR frequency scaled done. Although
normally there should be no issue, but it is better to
add it.Signed-off-by: Anson Huang
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On i.MX7D lpddr3, retention mode exit flow should restore
more registers to make sure the ddr controller and ddr phy
settings restored properly, otherwise, some of the boards
can NOT pass memtester after retention mode exited.Signed-off-by: Anson Huang
08 May, 2016
2 commits
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i.MX7D TO1.2 removes the DDR PAD retention mode setting
in IOMUXC GPR, it is same as TO1.0, so only apply the
IOMUXC GPR setting for TO1.1.Signed-off-by: Anson Huang
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i.MX7D 19x19 LPDDR2 ARM2 board's uSDHC1 CD pin should be
LOW active, correct it.Signed-off-by: Anson Huang
06 May, 2016
2 commits
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When A7 platform is in low power mode while M4 is NOT,
M4 should be able to send message to wake up A7, so
MU must be always as wake up source.Signed-off-by: Anson Huang
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Change when A7 signal M4 to make sure busfreq is
always up when the M4 send high bus release.
This prevents race condition for Low Power DemoSigned-off-by: Teo Hall
29 Apr, 2016
3 commits
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i.MX7d MAC1_ADDR fuse offset address is 0x640, i.MX6q/dl/sx/ul
MAC1_ADDR fuse offset address is 0x620. Correct it for i.MX7d,
otherwise read un-correct MAC address.Signed-off-by: Fugang Duan
(cherry picked from commit:74ee5313534dd9453601f4428c4916d46405669f) -
Set bcmdhd as build in type.
Signed-off-by: Haibo Chen
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i.MX7D TO1.2 fix the CKE issue, need to follow TO1.0's
precedure for DRAM frequency scaling.Signed-off-by: Anson Huang
28 Apr, 2016
3 commits
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Disable caam encrypt module in sx dts, which align with dl/dq dts
Signed-off-by: guoyin.chen
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Add configure which support uid_cputime.
Signed-off-by: zhang sanshan
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Virtual display uses 32bpp as render target.
But framebuffer uses 16bpp as render target.
EGL can't handle different bpp configuration in one thread.
So, it will lose some precision when do 32bpp render.
change 6sx display bpp to 32 to match CTS test.Signed-off-by: Xiaowen Liu
26 Apr, 2016
2 commits
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Add the LDB clock parents to the device tree.
Signed-off-by: Fabio Estevam
Signed-off-by: Ranjani Vaidyanathan
(cherry picked from commit 1a6cd019c1ab62ca0dc23bbc6b033df3f15850a5) -
performance governor is not added in scaling_available_governors,
need support performance governor as some benchmark should test
on performance mode.BSP set CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y, it will auto add
CPU_FREQ_GOV_PERFORMANCE in drivers/cpufreq/Kconfig, but android
set CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y so we need indicate
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y in imx_v7_android_defconfig.Signed-off-by: Richard Liu
21 Apr, 2016
1 commit
20 Apr, 2016
1 commit
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For imx6sx-sabreauto board, the usdhc4 is used for the sd slot locate on the
base board, so need to improve the pad drive strength, otherwise we will meet
many CRC error or timeout error when insert a sd card.Signed-off-by: Haibo Chen
(cherry picked from commit 1cbfce01e4e076d7f7e3b879c2c41d217d8afa48)
19 Apr, 2016
1 commit
