13 Jul, 2014
3 commits
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The uarts only work when the parent is ras_ahb_clk. The stale 3.5
based ST tree does this in the board file.Add it to the clk init function. Not pretty, but the mess there is
amazing anyway.Signed-off-by: Thomas Gleixner
Acked-by: Viresh Kumar
Signed-off-by: Mike Turquette -
The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62c (SPEAr: Switch to common clock framework).Signed-off-by: Thomas Gleixner
Cc: stable@vger.kernel.org
Acked-by: Viresh Kumar
Signed-off-by: Mike Turquette
11 Jul, 2014
1 commit
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Follow dt clock naming convention for PCIe clocks.
Signed-off-by: Pratyush Anand
Acked-by: Viresh Kumar
[viresh: fixed logs/cclist]
Signed-off-by: Viresh Kumar
Signed-off-by: Mike Turquette
20 Dec, 2013
1 commit
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clk_frac_ops is local to this file. Make it static.
Signed-off-by: Sachin Kamat
Acked-by: Viresh Kumar
Signed-off-by: Mike Turquette
20 Aug, 2013
1 commit
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Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
being reparented during clk_set_rate.To avoid breaking existing platforms, all callers of clk_register_mux()
are adjusted to pass the new flag. Platform maintainers are encouraged
to remove the flag if they wish to allow mux reparenting on set_rate.Signed-off-by: James Hogan
Reviewed-by: Stephen Boyd
Cc: Mike Turquette
Cc: Russell King
Cc: Sascha Hauer
Cc: Stephen Warren
Cc: Viresh Kumar
Cc: Kukjin Kim
Cc: Haojian Zhuang
Cc: Chao Xie
Cc: Arnd Bergmann
Cc: "Emilio López"
Cc: Gregory CLEMENT
Cc: Maxime Ripard
Cc: Prashant Gaikwad
Cc: Thierry Reding
Cc: Peter De Schrijver
Cc: Pawel Moll
Cc: Catalin Marinas
Cc: Andrew Chew
Cc: Doug Anderson
Cc: Heiko Stuebner
Cc: Paul Walmsley
Cc: Sylwester Nawrocki
Cc: Thomas Abraham
Cc: Tomasz Figa
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: linux-tegra@vger.kernel.org
Tested-by: Haojian Zhuang
Acked-by: Stephen Warren [tegra]
Acked-by: Maxime Ripard [sunxi]
Acked-by: Sören Brinkmann [Zynq]
Signed-off-by: Mike Turquette
12 Jun, 2013
1 commit
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This patch is required to be able to disable spear320 support
after the spear320_clk_init() prototype changed for the real
function but not for the dummy.Signed-off-by: Arnd Bergmann
Acked-by: Viresh Kumar
Signed-off-by: Mike Turquette
03 May, 2013
1 commit
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Pull ARM SoC multiplatform updates from Olof Johansson:
"More multiplatform enablement for ARM platforms. The ones converted
in this branch are:- bcm2835
- cns3xxx
- sirf
- nomadik
- msx
- spear
- tegra
- ux500We're getting close to having most of them converted!
One of the larger platforms remaining is Samsung Exynos, and there are
a bunch of supporting patches in this merge window for it. There was
a patch in this branch to a early version of multiplatform conversion,
but it ended up being reverted due to need of more bake time. The
revert commit is part of the branch since it would have required
rebasing multiple dependent branches and they were stable by then"* tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits)
mmc: sdhci-s3c: Fix operation on non-single image Samsung platforms
clocksource: nomadik-mtu: fix up clocksource/timer
Revert "ARM: exynos: enable multiplatform support"
ARM: SPEAr13xx: Fix typo "ARCH_HAVE_CPUFREQ"
ARM: exynos: enable multiplatform support
rtc: s3c: make header file local
mtd: onenand/samsung: make regs-onenand.h file local
thermal/exynos: remove unnecessary header inclusions
mmc: sdhci-s3c: remove platform dependencies
ARM: samsung: move mfc device definition to s5p-dev-mfc.c
ARM: exynos: move debug-macro.S to include/debug/
ARM: exynos: prepare for sparse IRQ
ARM: exynos: introduce EXYNOS_ATAGS symbol
ARM: tegra: build assembly files with -march=armv7-a
ARM: Push selects for TWD/SCU into machine entries
ARM: ux500: build hotplug.o for ARMv7-a
ARM: ux500: move to multiplatform
ARM: ux500: make remaining headers local
ARM: ux500: make irqs.h local to platform
ARM: ux500: get rid of
...
22 Mar, 2013
1 commit
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This patch corrects wrongly configured parent clock for following
devices:* Video enc/decoder
* Video ip
* Pin control
* ACP
* camxSigned-off-by: Vipul Kumar Samar
Reviewed-by: Shiraz Hashim
Acked-by: Viresh Kumar
Signed-off-by: Mike Turquette
13 Mar, 2013
1 commit
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Device drivers should not access MMIO registers through hardcoded
platform specific address constants. Instead, we can pass the
MMIO token to the spear clock driver in the initialization routine
to contain that knowledge in the platform code itself.Ideally, the clock driver would use of_iomap() or similar to
get the address, and that can be used later, but for now, this
is the minimal change.Signed-off-by: Arnd Bergmann
Acked-by: Viresh Kumar
15 Dec, 2012
1 commit
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Pull ARM SoC device-tree updates, take 2, from Olof Johansson:
"This branch contains device-tree updates for the SPEAr platform. They
had dependencies on earlier branches from this merge window, which is
why they were broken out in a separate branch."* tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: SPEAr3xx: Shirq: Move shirq controller out of plat/
ARM: SPEAr320: DT: Add SPEAr 320 HMI board support
ARM: SPEAr3xx: DT: add shirq node for interrupt multiplexor
ARM: SPEAr3xx: shirq: simplify and move the shared irq multiplexor to DT
ARM: SPEAr1310: Fix AUXDATA for compact flash controller
ARM: SPEAr13xx: Remove fields not required for ssp controller
ARM: SPEAr1310: Move 1310 specific misc register into machine specific files
ARM: SPEAr: DT: Update device nodes
ARM: SPEAr: DT: add uart state to fix warning
ARM: SPEAr: DT: Modify DT bindings for STMMAC
ARM: SPEAr: DT: Fix existing DT support
ARM: SPEAr: DT: Update partition info for MTD devices
ARM: SPEAr: DT: Update pinctrl list
ARM: SPEAr13xx: DT: Add spics gpio controller nodes
26 Nov, 2012
1 commit
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This patch moves some global macro definitions to the files where they are used.
Its a step towards removing spear.h completely later on.Signed-off-by: Vipul Kumar Samar
Signed-off-by: Viresh Kumar
22 Nov, 2012
8 commits
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Dummy clocks were added for ARM platforms, so that clk_get() for interface clk
doesn't fail for amba devices from amba_probe(). Because there is no amba device
for SPEAr that doesn't have a valid clock with dev_id for SPEAr, we don't need
these dummy clocks. Hence, remove them.Signed-off-by: Vipul Kumar Samar
Signed-off-by: Viresh Kumar
Signed-off-by: Mike Turquette -
The patch corrects the case when the rate table is being scanned for a
given frequency, and the search frequency is beyond the maximum
frequency indexed in the table.By default, the system should be set at max frequency present in the
rate table. This patch correctly returns the corresponding index value.Signed-off-by: Deepak Sikri
Signed-off-by: Viresh Kumar
Signed-off-by: Mike Turquette -
This patch updates the existing rate tables with new frequencies.
Signed-off-by: Deepak Sikri
Signed-off-by: Vipul Kumar Samar
Signed-off-by: Rajeev Kumar
Signed-off-by: Viresh Kumar
Signed-off-by: Mike Turquette -
This patch adds missing clocks: twd and macb.
Signed-off-by: Vipul Kumar Samar
Signed-off-by: Deepak Sikri
Signed-off-by: Viresh Kumar
Signed-off-by: Mike Turquette -
Flag CLK_SET_RATE_PARENT is required for a clock, where we want to
propagate clk_set_rate to its parent. This patch adds this to multiple clocks.Signed-off-by: Vipul Kumar Samar
Signed-off-by: Shiraz Hashim
Signed-off-by: Rajeev Kumar
Signed-off-by: Vijay Kumar Mishra
Signed-off-by: Vijay Kumar Mishra
Signed-off-by: Viresh Kumar
Signed-off-by: Mike Turquette -
This patch fixes parent names of multiple clocks.
Signed-off-by: Shiraz Hashim
Signed-off-by: Vipul Kumar Samar
Signed-off-by: Rajeev Kumar
Signed-off-by: Viresh Kumar
Signed-off-by: Mike Turquette -
This patch updates mux clock names of multiple clocks. It updates _clk with
_mclk to make it more readable.Signed-off-by: Shiraz Hashim
Signed-off-by: Rajeev Kumar
Signed-off-by: Viresh Kumar
Signed-off-by: Mike Turquette -
dev_id & con_id names of multiple clocks are incorrect. This patch fixes these
names with the names that come via DT.Signed-off-by: Rajeev Kumar
Signed-off-by: Shiraz Hashim
Signed-off-by: Bhavna Yadav
Signed-off-by: Vipul Kumar Samar
Signed-off-by: Deepak Sikri
Signed-off-by: Viresh Kumar
Signed-off-by: Mike Turquette
16 Nov, 2012
1 commit
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This fixes compile error if one of SPEAr3xx implementations is not selected.
CC drivers/clk/spear/spear3xx_clock.o
drivers/clk/spear/spear3xx_clock.c: In function 'spear3xx_clk_init':
drivers/clk/spear/spear3xx_clock.c:599:3: error: implicit declaration of function 'spear300_clk_init' [-Werror=implicit-function-declaration]
drivers/clk/spear/spear3xx_clock.c:601:3: error: implicit declaration of function 'spear310_clk_init' [-Werror=implicit-function-declaration]
drivers/clk/spear/spear3xx_clock.c:603:3: error: implicit declaration of function 'spear320_clk_init' [-Werror=implicit-function-declaration]
cc1: some warnings being treated as errors
make[3]: *** [drivers/clk/spear/spear3xx_clock.o] Error 1
make[2]: *** [drivers/clk/spear] Error 2
make[1]: *** [drivers/clk] Error 2
make: *** [drivers] Error 2Signed-off-by: Axel Lin
Acked-by: Viresh Kumar
Signed-off-by: Mike Turquette
30 Oct, 2012
1 commit
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Currently we are getting following warning for SPEAr clk-vco-pll.
"warning: i is used uninitialized in this function."
This is because we are getting value of i by passing its pointer to another
routine.The variables here are really not used uninitialized.
Signed-off-by: Viresh Kumar
Signed-off-by: Mike Turquette
18 Jul, 2012
6 commits
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sys_clk has multiple parents and selection of parent depends on sys_clk_ctrl
register bit no. 23:25, with following possibilities0XX: pll1_clk
10X: sys_synth_clk
110: pll2_clk
111: pll3_clkOut of several possibilities (h/w wise) to select same clock parent for
sys_clk, current clock implementation was considering just one value.When bootloader programmed different (valid) value to select a clock
parent then Linux breaks.Here, we try to include all possibilities which can lead to same
clock selection thus making Linux independent of bootloader selection
values.Signed-off-by: Vipul Kumar Samar
Signed-off-by: Shiraz Hashim
Acked-by: Viresh Kumar -
This patch is to fix typing mistake of clk enable register of i2c1 and
uart1.Signed-off-by: Vipul Kumar Samar
Signed-off-by: Shiraz Hashim
Acked-by: Viresh Kumar -
The max limit of con_id is 16 and dev_id is 20. As of now for spear6xx, many clk
ids are exceeding this predefined limit.This patch is intended to rename clk ids like:
mux_clk -> _mclk
gate_clk -> _gclk
synth_clk -> syn_clk
ras_gen1_synth_gate_clk -> ras_syn1_gclk
pll3_48m -> pll3_Signed-off-by: Vipul Kumar Samar
Signed-off-by: Shiraz Hashim
Acked-by: Viresh Kumar
Acked-by: Arnd Bergmann -
The max limit of con_id is 16 and dev_id is 20. As of now for spear3xx, many clk
ids are exceeding this predefined limit.This patch is intended to rename clk ids like:
mux_clk -> _mclk
gate_clk -> _gclk
synth_clk -> syn_clk
ras_gen1_synth_gate_clk -> ras_syn1_gclk
ras_pll3_48m -> ras_pll3_
pll3_48m -> pll3_Signed-off-by: Vipul Kumar Samar
Signed-off-by: Shiraz Hashim
Acked-by: Viresh Kumar
Acked-by: Arnd Bergmann -
The max limit of con_id is 16 and dev_id is 20. As of now for spear1310, many
clk ids are exceeding this predefined limit.This patch is intended to rename clk ids like:
mux_clk -> _mclk
gate_clk -> _gclk
synth_clk -> syn_clk
gmac_phy -> phy_
gmii_125m_pad -> gmii_padSigned-off-by: Vipul Kumar Samar
Signed-off-by: Shiraz Hashim
Acked-by: Viresh Kumar
Acked-by: Arnd Bergmann -
The max limit of con_id is 16 and dev_id is 20. As of now for spear1340, many
clk ids are exceeding this predefined limit.This patch rename clk ids like:
mux_clk -> _mclk
gate_clk -> _gclk
synth_clk -> syn_clk
gmac_phy -> phy_
gmii_125m_pad_ -> gmii_padSigned-off-by: Vipul Kumar Samar
Signed-off-by: Shiraz Hashim
Acked-by: Viresh Kumar
Acked-by: Arnd Bergmann
26 Jun, 2012
1 commit
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Signed-off-by: Stefan Roese
Cc: Viresh Kumar
Cc: Viresh Kumar
Signed-off-by: Mike Turquette
21 Jun, 2012
1 commit
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viresh.kumar@st.com email-id doesn't exist anymore as I have left the
company. Replace ST's id with viresh.linux@gmail.com.It also updates .mailmap file to fix address for 'git shortlog'
Signed-off-by: Viresh Kumar
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
14 May, 2012
1 commit
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This patch adds SPEAr1310 and SPEAr1340's clock framework support. It is based
on earlier support for SPEAr3xx family.Signed-off-by: Viresh Kumar
Reviewed-by: Mike Turquette
13 May, 2012
5 commits
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SPEAr SoCs used its own clock framework since now. From now on they will move to
use common clock framework.This patch updates existing SPEAr machine support to adapt for common clock
framework.Signed-off-by: Viresh Kumar
Reviewed-by: Mike Turquette
Acked-by: Arnd Bergmann -
All SPEAr SoC's contain GPT Synthesizers. Their Fout is derived from
following equations:Fout= Fin/((2 ^ (N+1)) * (M+1))
This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar
Reviewed-by: Mike Turquette -
All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from
following equations:Fout = Fin / (2 * div) (division factor)
div is 17 bits:-
0-13 (fractional part)
14-16 (integer part)
div is (16-14 bits).(13-0 bits) (in binary)Fout = Fin/(2 * div)
Fout = ((Fin / 10000)/(2 * div)) * 10000
Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000div << 14 is simply 17 bit value written at register.
This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar
Reviewed-by: Mike Turquette -
All SPEAr SoC's contain Auxiliary Synthesizers. Their Fout is derived based on
values of eq, x and y.Fout from synthesizer can be given from two equations:
Fout1 = (Fin * X/Y)/2 EQ1
Fout2 = Fin * X/Y EQ2This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar
Reviewed-by: Mike Turquette -
All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations
- In normal mode
vco = (2 * M[15:8] * Fin)/N- In Dithered mode
vco = (2 * M[15:0] * Fin)/(256 * N)pll_rate = vco/2^p
vco and pll are very closely bound to each other,
"vco needs to program: mode, m & n" and "pll needs to program p",
both share common enable/disable logic and registers.This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar
Reviewed-by: Mike Turquette