Blame view
arch/arm/dts/socfpga_cyclone5_sockit.dts
3.49 KB
83d290c56 SPDX: Convert all... |
1 |
// SPDX-License-Identifier: GPL-2.0+ |
952caa289 arm: socfpga: Add... |
2 |
/* |
c402e8170 dts: arm: socfpga... |
3 |
* Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> |
952caa289 arm: socfpga: Add... |
4 5 6 7 8 9 |
*/ #include "socfpga_cyclone5.dtsi" / { model = "Terasic SoCkit"; |
c402e8170 dts: arm: socfpga... |
10 |
compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga"; |
952caa289 arm: socfpga: Add... |
11 12 |
chosen { |
c402e8170 dts: arm: socfpga... |
13 |
bootargs = "earlyprintk"; |
79a436d56 arm: socfpga: fix... |
14 |
stdout-path = "serial0:115200n8"; |
952caa289 arm: socfpga: Add... |
15 |
}; |
c402e8170 dts: arm: socfpga... |
16 17 18 19 20 |
memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; |
225217da2 arm: socfpga: soc... |
21 |
aliases { |
c402e8170 dts: arm: socfpga... |
22 23 24 |
/* this allow the ethaddr uboot environmnet variable contents * to be added to the gmac1 device tree blob. */ |
952caa289 arm: socfpga: Add... |
25 |
ethernet0 = &gmac1; |
225217da2 arm: socfpga: soc... |
26 |
}; |
952caa289 arm: socfpga: Add... |
27 |
|
c402e8170 dts: arm: socfpga... |
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 |
leds { compatible = "gpio-leds"; hps_led0 { label = "hps:blue:led0"; gpios = <&portb 24 0>; /* HPS_GPIO53 */ linux,default-trigger = "heartbeat"; }; hps_led1 { label = "hps:blue:led1"; gpios = <&portb 25 0>; /* HPS_GPIO54 */ linux,default-trigger = "heartbeat"; }; hps_led2 { label = "hps:blue:led2"; gpios = <&portb 26 0>; /* HPS_GPIO55 */ linux,default-trigger = "heartbeat"; }; hps_led3 { label = "hps:blue:led3"; gpios = <&portb 27 0>; /* HPS_GPIO56 */ linux,default-trigger = "heartbeat"; }; }; gpio-keys { compatible = "gpio-keys"; hps_sw0 { label = "hps_sw0"; gpios = <&portc 20 0>; /* HPS_GPI7 */ linux,input-type = <5>; /* EV_SW */ linux,code = <0x0>; /* SW_LID */ }; hps_sw1 { label = "hps_sw1"; gpios = <&portc 19 0>; /* HPS_GPI6 */ linux,input-type = <5>; /* EV_SW */ linux,code = <0x5>; /* SW_DOCK */ }; hps_sw2 { label = "hps_sw2"; gpios = <&portc 18 0>; /* HPS_GPI5 */ linux,input-type = <5>; /* EV_SW */ linux,code = <0xa>; /* SW_KEYPAD_SLIDE */ }; hps_sw3 { label = "hps_sw3"; gpios = <&portc 17 0>; /* HPS_GPI4 */ linux,input-type = <5>; /* EV_SW */ linux,code = <0xc>; /* SW_ROTATE_LOCK */ }; hps_hkey0 { label = "hps_hkey0"; gpios = <&portc 21 1>; /* HPS_GPI8 */ linux,code = <187>; /* KEY_F17 */ }; hps_hkey1 { label = "hps_hkey1"; gpios = <&portc 22 1>; /* HPS_GPI9 */ linux,code = <188>; /* KEY_F18 */ }; hps_hkey2 { label = "hps_hkey2"; gpios = <&portc 23 1>; /* HPS_GPI10 */ linux,code = <189>; /* KEY_F19 */ }; hps_hkey3 { label = "hps_hkey3"; gpios = <&portc 24 1>; /* HPS_GPI11 */ linux,code = <190>; /* KEY_F20 */ }; |
952caa289 arm: socfpga: Add... |
110 |
}; |
c402e8170 dts: arm: socfpga... |
111 112 113 114 115 |
regulator_3_3v: vcc3p3-regulator { compatible = "regulator-fixed"; regulator-name = "VCC3P3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; |
952caa289 arm: socfpga: Add... |
116 117 118 119 120 121 122 123 124 125 126 127 |
}; }; &gmac1 { status = "okay"; phy-mode = "rgmii"; rxd0-skew-ps = <0>; rxd1-skew-ps = <0>; rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; txen-skew-ps = <0>; |
83f71ef55 net: phy: micrel:... |
128 |
txc-skew-ps = <1560>; |
952caa289 arm: socfpga: Add... |
129 |
rxdv-skew-ps = <0>; |
83f71ef55 net: phy: micrel:... |
130 |
rxc-skew-ps = <1200>; |
952caa289 arm: socfpga: Add... |
131 |
}; |
c402e8170 dts: arm: socfpga... |
132 |
&gpio0 { /* GPIO 0..29 */ |
952caa289 arm: socfpga: Add... |
133 134 |
status = "okay"; }; |
c402e8170 dts: arm: socfpga... |
135 |
&gpio1 { /* GPIO 30..57 */ |
952caa289 arm: socfpga: Add... |
136 137 |
status = "okay"; }; |
c402e8170 dts: arm: socfpga... |
138 |
&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ |
952caa289 arm: socfpga: Add... |
139 140 |
status = "okay"; }; |
c402e8170 dts: arm: socfpga... |
141 |
&i2c1 { |
952caa289 arm: socfpga: Add... |
142 |
status = "okay"; |
c402e8170 dts: arm: socfpga... |
143 144 145 146 147 148 |
accel1: accelerometer@53 { compatible = "adi,adxl345"; reg = <0x53>; interrupt-parent = <&portc>; interrupts = <3 2>; |
952caa289 arm: socfpga: Add... |
149 150 151 152 |
}; }; &mmc0 { |
c402e8170 dts: arm: socfpga... |
153 154 |
vmmc-supply = <®ulator_3_3v>; vqmmc-supply = <®ulator_3_3v>; |
952caa289 arm: socfpga: Add... |
155 |
status = "okay"; |
952caa289 arm: socfpga: Add... |
156 157 158 159 |
}; &qspi { status = "okay"; |
952caa289 arm: socfpga: Add... |
160 |
|
c402e8170 dts: arm: socfpga... |
161 |
flash: flash@0 { |
952caa289 arm: socfpga: Add... |
162 163 |
#address-cells = <1>; #size-cells = <1>; |
c402e8170 dts: arm: socfpga... |
164 165 166 |
compatible = "n25q00"; reg = <0>; spi-max-frequency = <100000000>; |
952caa289 arm: socfpga: Add... |
167 |
m25p,fast-read; |
c402e8170 dts: arm: socfpga... |
168 169 170 |
cdns,page-size = <256>; cdns,block-size = <16>; cdns,read-delay = <4>; |
6e62b178e dts: cadence_spi:... |
171 172 173 174 |
cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; |
952caa289 arm: socfpga: Add... |
175 176 |
}; }; |
225217da2 arm: socfpga: soc... |
177 178 179 180 |
&usb1 { status = "okay"; }; |