Eric Lee / smarc-uboot

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Commit c402e8170245a0ca2b9398185638b349eeff10a3

Authored by Simon Goldschmidt
Committed by Marek Vasut
1 parent 2a3a99932b
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

dts: arm: socfpga: merge gen5 devicetrees from linux 

Add -u-boot.dtsi files to keep the current U-Boot behaviour:
- add u-boot,dm-pre-reloc where required
- disable watchdog
- set uart clock frequency
- add gpio bank-name properties
where appropriate:
- make qspi work (add alias for spi0, fix compatible for flash)
- enable usb (status okay, add alias for udc0)

Adapt board dts files that are not in Linux to keep their old
behaviour.

Change licenses to SPDX.

(Patman warnings/errors are in 1:1 copied files from Linux)

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Showing 20 changed files with 1222 additions and 329 deletions Side-by-side Diff

arch/arm/dts/socfpga.dtsi
Diff comments   View file @ c402e81
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3   - * Copyright (C) 2012 Altera <www.altera.com>
  3 + * Copyright (C) 2012 Altera <www.altera.com>
4 4 */
5 5  
6   -#include "skeleton.dtsi"
7 6 #include <dt-bindings/reset/altr,rst-mgr.h>
8 7  
9 8 / {
10 9  
11 10  
12 11  
13 12  
... ... @@ -11,34 +10,26 @@
11 10 #size-cells = <1>;
12 11  
13 12 aliases {
14   - ethernet0 = &gmac0;
15   - ethernet1 = &gmac1;
16   - i2c0 = &i2c0;
17   - i2c1 = &i2c1;
18   - i2c2 = &i2c2;
19   - i2c3 = &i2c3;
20 13 serial0 = &uart0;
21 14 serial1 = &uart1;
22 15 timer0 = &timer0;
23 16 timer1 = &timer1;
24 17 timer2 = &timer2;
25 18 timer3 = &timer3;
26   - spi0 = &qspi;
27   - spi1 = &spi0;
28   - spi2 = &spi1;
29 19 };
30 20  
31 21 cpus {
32 22 #address-cells = <1>;
33 23 #size-cells = <0>;
  24 + enable-method = "altr,socfpga-smp";
34 25  
35   - cpu@0 {
  26 + cpu0: cpu@0 {
36 27 compatible = "arm,cortex-a9";
37 28 device_type = "cpu";
38 29 reg = <0>;
39 30 next-level-cache = <&L2>;
40 31 };
41   - cpu@1 {
  32 + cpu1: cpu@1 {
42 33 compatible = "arm,cortex-a9";
43 34 device_type = "cpu";
44 35 reg = <1>;
... ... @@ -46,6 +37,15 @@
46 37 };
47 38 };
48 39  
  40 + pmu: pmu@ff111000 {
  41 + compatible = "arm,cortex-a9-pmu";
  42 + interrupt-parent = <&intc>;
  43 + interrupts = <0 176 4>, <0 177 4>;
  44 + interrupt-affinity = <&cpu0>, <&cpu1>;
  45 + reg = <0xff111000 0x1000>,
  46 + <0xff113000 0x1000>;
  47 + };
  48 +
49 49 intc: intc@fffed000 {
50 50 compatible = "arm,cortex-a9-gic";
51 51 #interrupt-cells = <3>;
... ... @@ -63,7 +63,7 @@
63 63 ranges;
64 64  
65 65 amba {
66   - compatible = "arm,amba-bus";
  66 + compatible = "simple-bus";
67 67 #address-cells = <1>;
68 68 #size-cells = <1>;
69 69 ranges;
... ... @@ -87,6 +87,14 @@
87 87 };
88 88 };
89 89  
  90 + base_fpga_region {
  91 + compatible = "fpga-region";
  92 + fpga-mgr = <&fpgamgr0>;
  93 +
  94 + #address-cells = <0x1>;
  95 + #size-cells = <0x1>;
  96 + };
  97 +
90 98 can0: can@ffc00000 {
91 99 compatible = "bosch,d_can";
92 100 reg = <0xffc00000 0x1000>;
... ... @@ -131,7 +139,7 @@
131 139 compatible = "fixed-clock";
132 140 };
133 141  
134   - main_pll: main_pll {
  142 + main_pll: main_pll@40 {
135 143 #address-cells = <1>;
136 144 #size-cells = <0>;
137 145 #clock-cells = <0>;
... ... @@ -139,7 +147,7 @@
139 147 clocks = <&osc1>;
140 148 reg = <0x40>;
141 149  
142   - mpuclk: mpuclk {
  150 + mpuclk: mpuclk@48 {
143 151 #clock-cells = <0>;
144 152 compatible = "altr,socfpga-perip-clk";
145 153 clocks = <&main_pll>;
... ... @@ -147,7 +155,7 @@
147 155 reg = <0x48>;
148 156 };
149 157  
150   - mainclk: mainclk {
  158 + mainclk: mainclk@4c {
151 159 #clock-cells = <0>;
152 160 compatible = "altr,socfpga-perip-clk";
153 161 clocks = <&main_pll>;
154 162  
155 163  
156 164  
157 165  
... ... @@ -155,29 +163,29 @@
155 163 reg = <0x4C>;
156 164 };
157 165  
158   - dbg_base_clk: dbg_base_clk {
  166 + dbg_base_clk: dbg_base_clk@50 {
159 167 #clock-cells = <0>;
160 168 compatible = "altr,socfpga-perip-clk";
161   - clocks = <&main_pll>;
  169 + clocks = <&main_pll>, <&osc1>;
162 170 div-reg = <0xe8 0 9>;
163 171 reg = <0x50>;
164 172 };
165 173  
166   - main_qspi_clk: main_qspi_clk {
  174 + main_qspi_clk: main_qspi_clk@54 {
167 175 #clock-cells = <0>;
168 176 compatible = "altr,socfpga-perip-clk";
169 177 clocks = <&main_pll>;
170 178 reg = <0x54>;
171 179 };
172 180  
173   - main_nand_sdmmc_clk: main_nand_sdmmc_clk {
  181 + main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
174 182 #clock-cells = <0>;
175 183 compatible = "altr,socfpga-perip-clk";
176 184 clocks = <&main_pll>;
177 185 reg = <0x58>;
178 186 };
179 187  
180   - cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
  188 + cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
181 189 #clock-cells = <0>;
182 190 compatible = "altr,socfpga-perip-clk";
183 191 clocks = <&main_pll>;
... ... @@ -185,7 +193,7 @@
185 193 };
186 194 };
187 195  
188   - periph_pll: periph_pll {
  196 + periph_pll: periph_pll@80 {
189 197 #address-cells = <1>;
190 198 #size-cells = <0>;
191 199 #clock-cells = <0>;
192 200  
193 201  
194 202  
195 203  
196 204  
... ... @@ -193,42 +201,42 @@
193 201 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
194 202 reg = <0x80>;
195 203  
196   - emac0_clk: emac0_clk {
  204 + emac0_clk: emac0_clk@88 {
197 205 #clock-cells = <0>;
198 206 compatible = "altr,socfpga-perip-clk";
199 207 clocks = <&periph_pll>;
200 208 reg = <0x88>;
201 209 };
202 210  
203   - emac1_clk: emac1_clk {
  211 + emac1_clk: emac1_clk@8c {
204 212 #clock-cells = <0>;
205 213 compatible = "altr,socfpga-perip-clk";
206 214 clocks = <&periph_pll>;
207 215 reg = <0x8C>;
208 216 };
209 217  
210   - per_qspi_clk: per_qsi_clk {
  218 + per_qspi_clk: per_qsi_clk@90 {
211 219 #clock-cells = <0>;
212 220 compatible = "altr,socfpga-perip-clk";
213 221 clocks = <&periph_pll>;
214 222 reg = <0x90>;
215 223 };
216 224  
217   - per_nand_mmc_clk: per_nand_mmc_clk {
  225 + per_nand_mmc_clk: per_nand_mmc_clk@94 {
218 226 #clock-cells = <0>;
219 227 compatible = "altr,socfpga-perip-clk";
220 228 clocks = <&periph_pll>;
221 229 reg = <0x94>;
222 230 };
223 231  
224   - per_base_clk: per_base_clk {
  232 + per_base_clk: per_base_clk@98 {
225 233 #clock-cells = <0>;
226 234 compatible = "altr,socfpga-perip-clk";
227 235 clocks = <&periph_pll>;
228 236 reg = <0x98>;
229 237 };
230 238  
231   - h2f_usr1_clk: h2f_usr1_clk {
  239 + h2f_usr1_clk: h2f_usr1_clk@9c {
232 240 #clock-cells = <0>;
233 241 compatible = "altr,socfpga-perip-clk";
234 242 clocks = <&periph_pll>;
... ... @@ -236,7 +244,7 @@
236 244 };
237 245 };
238 246  
239   - sdram_pll: sdram_pll {
  247 + sdram_pll: sdram_pll@c0 {
240 248 #address-cells = <1>;
241 249 #size-cells = <0>;
242 250 #clock-cells = <0>;
243 251  
244 252  
245 253  
... ... @@ -244,28 +252,28 @@
244 252 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
245 253 reg = <0xC0>;
246 254  
247   - ddr_dqs_clk: ddr_dqs_clk {
  255 + ddr_dqs_clk: ddr_dqs_clk@c8 {
248 256 #clock-cells = <0>;
249 257 compatible = "altr,socfpga-perip-clk";
250 258 clocks = <&sdram_pll>;
251 259 reg = <0xC8>;
252 260 };
253 261  
254   - ddr_2x_dqs_clk: ddr_2x_dqs_clk {
  262 + ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
255 263 #clock-cells = <0>;
256 264 compatible = "altr,socfpga-perip-clk";
257 265 clocks = <&sdram_pll>;
258 266 reg = <0xCC>;
259 267 };
260 268  
261   - ddr_dq_clk: ddr_dq_clk {
  269 + ddr_dq_clk: ddr_dq_clk@d0 {
262 270 #clock-cells = <0>;
263 271 compatible = "altr,socfpga-perip-clk";
264 272 clocks = <&sdram_pll>;
265 273 reg = <0xD0>;
266 274 };
267 275  
268   - h2f_usr2_clk: h2f_usr2_clk {
  276 + h2f_usr2_clk: h2f_usr2_clk@d4 {
269 277 #clock-cells = <0>;
270 278 compatible = "altr,socfpga-perip-clk";
271 279 clocks = <&sdram_pll>;
... ... @@ -312,7 +320,7 @@
312 320 l3_sp_clk: l3_sp_clk {
313 321 #clock-cells = <0>;
314 322 compatible = "altr,socfpga-gate-clk";
315   - clocks = <&mainclk>;
  323 + clocks = <&l3_mp_clk>;
316 324 div-reg = <0x64 2 2>;
317 325 };
318 326  
... ... @@ -343,7 +351,7 @@
343 351 dbg_clk: dbg_clk {
344 352 #clock-cells = <0>;
345 353 compatible = "altr,socfpga-gate-clk";
346   - clocks = <&dbg_base_clk>;
  354 + clocks = <&dbg_at_clk>;
347 355 div-reg = <0x68 2 2>;
348 356 clk-gate = <0x60 5>;
349 357 };
... ... @@ -446,6 +454,14 @@
446 454 clk-phase = <0 135>;
447 455 };
448 456  
  457 + sdmmc_clk_divided: sdmmc_clk_divided {
  458 + #clock-cells = <0>;
  459 + compatible = "altr,socfpga-gate-clk";
  460 + clocks = <&sdmmc_clk>;
  461 + clk-gate = <0xa0 8>;
  462 + fixed-divider = <4>;
  463 + };
  464 +
449 465 nand_x_clk: nand_x_clk {
450 466 #clock-cells = <0>;
451 467 compatible = "altr,socfpga-gate-clk";
452 468  
... ... @@ -453,10 +469,17 @@
453 469 clk-gate = <0xa0 9>;
454 470 };
455 471  
  472 + nand_ecc_clk: nand_ecc_clk {
  473 + #clock-cells = <0>;
  474 + compatible = "altr,socfpga-gate-clk";
  475 + clocks = <&nand_x_clk>;
  476 + clk-gate = <0xa0 9>;
  477 + };
  478 +
456 479 nand_clk: nand_clk {
457 480 #clock-cells = <0>;
458 481 compatible = "altr,socfpga-gate-clk";
459   - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
  482 + clocks = <&nand_x_clk>;
460 483 clk-gate = <0xa0 10>;
461 484 fixed-divider = <4>;
462 485 };
463 486  
464 487  
... ... @@ -467,9 +490,59 @@
467 490 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
468 491 clk-gate = <0xa0 11>;
469 492 };
  493 +
  494 + ddr_dqs_clk_gate: ddr_dqs_clk_gate {
  495 + #clock-cells = <0>;
  496 + compatible = "altr,socfpga-gate-clk";
  497 + clocks = <&ddr_dqs_clk>;
  498 + clk-gate = <0xd8 0>;
  499 + };
  500 +
  501 + ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
  502 + #clock-cells = <0>;
  503 + compatible = "altr,socfpga-gate-clk";
  504 + clocks = <&ddr_2x_dqs_clk>;
  505 + clk-gate = <0xd8 1>;
  506 + };
  507 +
  508 + ddr_dq_clk_gate: ddr_dq_clk_gate {
  509 + #clock-cells = <0>;
  510 + compatible = "altr,socfpga-gate-clk";
  511 + clocks = <&ddr_dq_clk>;
  512 + clk-gate = <0xd8 2>;
  513 + };
  514 +
  515 + h2f_user2_clk: h2f_user2_clk {
  516 + #clock-cells = <0>;
  517 + compatible = "altr,socfpga-gate-clk";
  518 + clocks = <&h2f_usr2_clk>;
  519 + clk-gate = <0xd8 3>;
  520 + };
  521 +
470 522 };
471   - };
  523 + };
472 524  
  525 + fpga_bridge0: fpga_bridge@ff400000 {
  526 + compatible = "altr,socfpga-lwhps2fpga-bridge";
  527 + reg = <0xff400000 0x100000>;
  528 + resets = <&rst LWHPS2FPGA_RESET>;
  529 + clocks = <&l4_main_clk>;
  530 + };
  531 +
  532 + fpga_bridge1: fpga_bridge@ff500000 {
  533 + compatible = "altr,socfpga-hps2fpga-bridge";
  534 + reg = <0xff500000 0x10000>;
  535 + resets = <&rst HPS2FPGA_RESET>;
  536 + clocks = <&l4_main_clk>;
  537 + };
  538 +
  539 + fpgamgr0: fpgamgr@ff706000 {
  540 + compatible = "altr,socfpga-fpga-mgr";
  541 + reg = <0xff706000 0x1000
  542 + 0xffb90000 0x4>;
  543 + interrupts = <0 175 4>;
  544 + };
  545 +
473 546 gmac0: ethernet@ff700000 {
474 547 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
475 548 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
476 549  
... ... @@ -477,12 +550,14 @@
477 550 interrupts = <0 115 4>;
478 551 interrupt-names = "macirq";
479 552 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
480   - clocks = <&emac0_clk>;
  553 + clocks = <&emac_0_clk>;
481 554 clock-names = "stmmaceth";
482 555 resets = <&rst EMAC0_RESET>;
483 556 reset-names = "stmmaceth";
484 557 snps,multicast-filter-bins = <256>;
485 558 snps,perfect-filter-entries = <128>;
  559 + tx-fifo-depth = <4096>;
  560 + rx-fifo-depth = <4096>;
486 561 status = "disabled";
487 562 };
488 563  
489 564  
490 565  
491 566  
492 567  
... ... @@ -493,74 +568,27 @@
493 568 interrupts = <0 120 4>;
494 569 interrupt-names = "macirq";
495 570 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
496   - clocks = <&emac1_clk>;
  571 + clocks = <&emac_1_clk>;
497 572 clock-names = "stmmaceth";
498 573 resets = <&rst EMAC1_RESET>;
499 574 reset-names = "stmmaceth";
500 575 snps,multicast-filter-bins = <256>;
501 576 snps,perfect-filter-entries = <128>;
  577 + tx-fifo-depth = <4096>;
  578 + rx-fifo-depth = <4096>;
502 579 status = "disabled";
503 580 };
504 581  
505   - i2c0: i2c@ffc04000 {
506   - #address-cells = <1>;
507   - #size-cells = <0>;
508   - compatible = "snps,designware-i2c";
509   - reg = <0xffc04000 0x1000>;
510   - clocks = <&l4_sp_clk>;
511   - resets = <&rst I2C0_RESET>;
512   - reset-names = "i2c";
513   - interrupts = <0 158 0x4>;
514   - status = "disabled";
515   - };
516   -
517   - i2c1: i2c@ffc05000 {
518   - #address-cells = <1>;
519   - #size-cells = <0>;
520   - compatible = "snps,designware-i2c";
521   - reg = <0xffc05000 0x1000>;
522   - clocks = <&l4_sp_clk>;
523   - resets = <&rst I2C1_RESET>;
524   - reset-names = "i2c";
525   - interrupts = <0 159 0x4>;
526   - status = "disabled";
527   - };
528   -
529   - i2c2: i2c@ffc06000 {
530   - #address-cells = <1>;
531   - #size-cells = <0>;
532   - compatible = "snps,designware-i2c";
533   - reg = <0xffc06000 0x1000>;
534   - clocks = <&l4_sp_clk>;
535   - resets = <&rst I2C2_RESET>;
536   - reset-names = "i2c";
537   - interrupts = <0 160 0x4>;
538   - status = "disabled";
539   - };
540   -
541   - i2c3: i2c@ffc07000 {
542   - #address-cells = <1>;
543   - #size-cells = <0>;
544   - compatible = "snps,designware-i2c";
545   - reg = <0xffc07000 0x1000>;
546   - clocks = <&l4_sp_clk>;
547   - resets = <&rst I2C3_RESET>;
548   - reset-names = "i2c";
549   - interrupts = <0 161 0x4>;
550   - status = "disabled";
551   - };
552   -
553 582 gpio0: gpio@ff708000 {
554 583 #address-cells = <1>;
555 584 #size-cells = <0>;
556 585 compatible = "snps,dw-apb-gpio";
557 586 reg = <0xff708000 0x1000>;
558   - clocks = <&per_base_clk>;
  587 + clocks = <&l4_mp_clk>;
559 588 status = "disabled";
560 589  
561 590 porta: gpio-controller@0 {
562 591 compatible = "snps,dw-apb-gpio-port";
563   - bank-name = "porta";
564 592 gpio-controller;
565 593 #gpio-cells = <2>;
566 594 snps,nr-gpios = <29>;
567 595  
... ... @@ -576,12 +604,11 @@
576 604 #size-cells = <0>;
577 605 compatible = "snps,dw-apb-gpio";
578 606 reg = <0xff709000 0x1000>;
579   - clocks = <&per_base_clk>;
  607 + clocks = <&l4_mp_clk>;
580 608 status = "disabled";
581 609  
582 610 portb: gpio-controller@0 {
583 611 compatible = "snps,dw-apb-gpio-port";
584   - bank-name = "portb";
585 612 gpio-controller;
586 613 #gpio-cells = <2>;
587 614 snps,nr-gpios = <29>;
588 615  
... ... @@ -597,12 +624,11 @@
597 624 #size-cells = <0>;
598 625 compatible = "snps,dw-apb-gpio";
599 626 reg = <0xff70a000 0x1000>;
600   - clocks = <&per_base_clk>;
  627 + clocks = <&l4_mp_clk>;
601 628 status = "disabled";
602 629  
603 630 portc: gpio-controller@0 {
604 631 compatible = "snps,dw-apb-gpio-port";
605   - bank-name = "portc";
606 632 gpio-controller;
607 633 #gpio-cells = <2>;
608 634 snps,nr-gpios = <27>;
609 635  
610 636  
... ... @@ -613,17 +639,70 @@
613 639 };
614 640 };
615 641  
616   - sdr: sdr@ffc25000 {
617   - compatible = "syscon";
618   - reg = <0xffc25000 0x1000>;
  642 + i2c0: i2c@ffc04000 {
  643 + #address-cells = <1>;
  644 + #size-cells = <0>;
  645 + compatible = "snps,designware-i2c";
  646 + reg = <0xffc04000 0x1000>;
  647 + resets = <&rst I2C0_RESET>;
  648 + clocks = <&l4_sp_clk>;
  649 + interrupts = <0 158 0x4>;
  650 + status = "disabled";
619 651 };
620 652  
621   - sdramedac {
622   - compatible = "altr,sdram-edac";
623   - altr,sdr-syscon = <&sdr>;
624   - interrupts = <0 39 4>;
  653 + i2c1: i2c@ffc05000 {
  654 + #address-cells = <1>;
  655 + #size-cells = <0>;
  656 + compatible = "snps,designware-i2c";
  657 + reg = <0xffc05000 0x1000>;
  658 + resets = <&rst I2C1_RESET>;
  659 + clocks = <&l4_sp_clk>;
  660 + interrupts = <0 159 0x4>;
  661 + status = "disabled";
625 662 };
626 663  
  664 + i2c2: i2c@ffc06000 {
  665 + #address-cells = <1>;
  666 + #size-cells = <0>;
  667 + compatible = "snps,designware-i2c";
  668 + reg = <0xffc06000 0x1000>;
  669 + resets = <&rst I2C2_RESET>;
  670 + clocks = <&l4_sp_clk>;
  671 + interrupts = <0 160 0x4>;
  672 + status = "disabled";
  673 + };
  674 +
  675 + i2c3: i2c@ffc07000 {
  676 + #address-cells = <1>;
  677 + #size-cells = <0>;
  678 + compatible = "snps,designware-i2c";
  679 + reg = <0xffc07000 0x1000>;
  680 + resets = <&rst I2C3_RESET>;
  681 + clocks = <&l4_sp_clk>;
  682 + interrupts = <0 161 0x4>;
  683 + status = "disabled";
  684 + };
  685 +
  686 + eccmgr: eccmgr {
  687 + compatible = "altr,socfpga-ecc-manager";
  688 + #address-cells = <1>;
  689 + #size-cells = <1>;
  690 + ranges;
  691 +
  692 + l2-ecc@ffd08140 {
  693 + compatible = "altr,socfpga-l2-ecc";
  694 + reg = <0xffd08140 0x4>;
  695 + interrupts = <0 36 1>, <0 37 1>;
  696 + };
  697 +
  698 + ocram-ecc@ffd08144 {
  699 + compatible = "altr,socfpga-ocram-ecc";
  700 + reg = <0xffd08144 0x4>;
  701 + iram = <&ocram>;
  702 + interrupts = <0 178 1>, <0 179 1>;
  703 + };
  704 + };
  705 +
627 706 L2: l2-cache@fffef000 {
628 707 compatible = "arm,pl310-cache";
629 708 reg = <0xfffef000 0x1000>;
630 709  
631 710  
632 711  
633 712  
634 713  
635 714  
636 715  
637 716  
638 717  
... ... @@ -632,36 +711,89 @@
632 711 cache-level = <2>;
633 712 arm,tag-latency = <1 1 1>;
634 713 arm,data-latency = <2 1 1>;
  714 + prefetch-data = <1>;
  715 + prefetch-instr = <1>;
  716 + arm,shared-override;
  717 + arm,double-linefill = <1>;
  718 + arm,double-linefill-incr = <0>;
  719 + arm,double-linefill-wrap = <1>;
  720 + arm,prefetch-drop = <0>;
  721 + arm,prefetch-offset = <7>;
635 722 };
636 723  
637   - mmc0: dwmmc0@ff704000 {
  724 + l3regs@0xff800000 {
  725 + compatible = "altr,l3regs", "syscon";
  726 + reg = <0xff800000 0x1000>;
  727 + };
  728 +
  729 + mmc: dwmmc0@ff704000 {
638 730 compatible = "altr,socfpga-dw-mshc";
639 731 reg = <0xff704000 0x1000>;
640 732 interrupts = <0 139 4>;
641 733 fifo-depth = <0x400>;
642 734 #address-cells = <1>;
643 735 #size-cells = <0>;
644   - clocks = <&l4_mp_clk>, <&sdmmc_clk>;
  736 + clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
645 737 clock-names = "biu", "ciu";
  738 + status = "disabled";
646 739 };
647 740  
  741 + nand0: nand@ff900000 {
  742 + #address-cells = <0x1>;
  743 + #size-cells = <0x1>;
  744 + compatible = "altr,socfpga-denali-nand";
  745 + reg = <0xff900000 0x100000>,
  746 + <0xffb80000 0x10000>;
  747 + reg-names = "nand_data", "denali_reg";
  748 + interrupts = <0x0 0x90 0x4>;
  749 + dma-mask = <0xffffffff>;
  750 + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
  751 + clock-names = "nand", "nand_x", "ecc";
  752 + status = "disabled";
  753 + };
  754 +
  755 + ocram: sram@ffff0000 {
  756 + compatible = "mmio-sram";
  757 + reg = <0xffff0000 0x10000>;
  758 + };
  759 +
648 760 qspi: spi@ff705000 {
649 761 compatible = "cdns,qspi-nor";
650   - #address-cells = <1>;
  762 + #address-cells = <1>;
651 763 #size-cells = <0>;
652 764 reg = <0xff705000 0x1000>,
653   - <0xffa00000 0x1000>;
  765 + <0xffa00000 0x1000>;
654 766 interrupts = <0 151 4>;
655   - clocks = <&qspi_clk>;
656   - ext-decoder = <0>; /* external decoder */
657   - num-cs = <4>;
658 767 cdns,fifo-depth = <128>;
659 768 cdns,fifo-width = <4>;
660 769 cdns,trigger-address = <0x00000000>;
661   - bus-num = <2>;
  770 + clocks = <&qspi_clk>;
662 771 status = "disabled";
663 772 };
664 773  
  774 + rst: rstmgr@ffd05000 {
  775 + #reset-cells = <1>;
  776 + compatible = "altr,rst-mgr";
  777 + reg = <0xffd05000 0x1000>;
  778 + altr,modrst-offset = <0x10>;
  779 + };
  780 +
  781 + scu: snoop-control-unit@fffec000 {
  782 + compatible = "arm,cortex-a9-scu";
  783 + reg = <0xfffec000 0x100>;
  784 + };
  785 +
  786 + sdr: sdr@ffc25000 {
  787 + compatible = "altr,sdr-ctl", "syscon";
  788 + reg = <0xffc25000 0x1000>;
  789 + };
  790 +
  791 + sdramedac {
  792 + compatible = "altr,sdram-edac";
  793 + altr,sdr-syscon = <&sdr>;
  794 + interrupts = <0 39 4>;
  795 + };
  796 +
665 797 spi0: spi@fff00000 {
666 798 compatible = "snps,dw-apb-ssi";
667 799 #address-cells = <1>;
... ... @@ -669,10 +801,7 @@
669 801 reg = <0xfff00000 0x1000>;
670 802 interrupts = <0 154 4>;
671 803 num-cs = <4>;
672   - bus-num = <0>;
673   - tx-dma-channel = <&pdma 16>;
674   - rx-dma-channel = <&pdma 17>;
675   - clocks = <&per_base_clk>;
  804 + clocks = <&spi_m_clk>;
676 805 status = "disabled";
677 806 };
678 807  
679 808  
680 809  
681 810  
... ... @@ -681,20 +810,22 @@
681 810 #address-cells = <1>;
682 811 #size-cells = <0>;
683 812 reg = <0xfff01000 0x1000>;
684   - interrupts = <0 156 4>;
  813 + interrupts = <0 155 4>;
685 814 num-cs = <4>;
686   - bus-num = <1>;
687   - tx-dma-channel = <&pdma 20>;
688   - rx-dma-channel = <&pdma 21>;
689   - clocks = <&per_base_clk>;
  815 + clocks = <&spi_m_clk>;
690 816 status = "disabled";
691 817 };
692 818  
  819 + sysmgr: sysmgr@ffd08000 {
  820 + compatible = "altr,sys-mgr", "syscon";
  821 + reg = <0xffd08000 0x4000>;
  822 + };
  823 +
693 824 /* Local timer */
694 825 timer@fffec600 {
695 826 compatible = "arm,cortex-a9-twd-timer";
696 827 reg = <0xfffec600 0x100>;
697   - interrupts = <1 13 0xf04>;
  828 + interrupts = <1 13 0xf01>;
698 829 clocks = <&mpu_periph_clk>;
699 830 };
700 831  
... ... @@ -704,6 +835,8 @@
704 835 reg = <0xffc08000 0x1000>;
705 836 clocks = <&l4_sp_clk>;
706 837 clock-names = "timer";
  838 + resets = <&rst SPTIMER0_RESET>;
  839 + reset-names = "timer";
707 840 };
708 841  
709 842 timer1: timer1@ffc09000 {
... ... @@ -712,6 +845,8 @@
712 845 reg = <0xffc09000 0x1000>;
713 846 clocks = <&l4_sp_clk>;
714 847 clock-names = "timer";
  848 + resets = <&rst SPTIMER1_RESET>;
  849 + reset-names = "timer";
715 850 };
716 851  
717 852 timer2: timer2@ffd00000 {
... ... @@ -720,6 +855,8 @@
720 855 reg = <0xffd00000 0x1000>;
721 856 clocks = <&osc1>;
722 857 clock-names = "timer";
  858 + resets = <&rst OSC1TIMER0_RESET>;
  859 + reset-names = "timer";
723 860 };
724 861  
725 862 timer3: timer3@ffd01000 {
... ... @@ -728,6 +865,8 @@
728 865 reg = <0xffd01000 0x1000>;
729 866 clocks = <&osc1>;
730 867 clock-names = "timer";
  868 + resets = <&rst OSC1TIMER1_RESET>;
  869 + reset-names = "timer";
731 870 };
732 871  
733 872 uart0: serial0@ffc02000 {
... ... @@ -737,7 +876,9 @@
737 876 reg-shift = <2>;
738 877 reg-io-width = <4>;
739 878 clocks = <&l4_sp_clk>;
740   - clock-frequency = <100000000>;
  879 + dmas = <&pdma 28>,
  880 + <&pdma 29>;
  881 + dma-names = "tx", "rx";
741 882 };
742 883  
743 884 uart1: serial1@ffc03000 {
744 885  
... ... @@ -747,16 +888,12 @@
747 888 reg-shift = <2>;
748 889 reg-io-width = <4>;
749 890 clocks = <&l4_sp_clk>;
750   - clock-frequency = <100000000>;
  891 + dmas = <&pdma 30>,
  892 + <&pdma 31>;
  893 + dma-names = "tx", "rx";
751 894 };
752 895  
753   - rst: rstmgr@ffd05000 {
754   - #reset-cells = <1>;
755   - compatible = "altr,rst-mgr";
756   - reg = <0xffd05000 0x1000>;
757   - };
758   -
759   - usbphy0: usbphy@0 {
  896 + usbphy0: usbphy {
760 897 #phy-cells = <0>;
761 898 compatible = "usb-nop-xceiv";
762 899 status = "okay";
... ... @@ -768,6 +905,8 @@
768 905 interrupts = <0 125 4>;
769 906 clocks = <&usb_mp_clk>;
770 907 clock-names = "otg";
  908 + resets = <&rst USB0_RESET>;
  909 + reset-names = "dwc2";
771 910 phys = <&usbphy0>;
772 911 phy-names = "usb2-phy";
773 912 status = "disabled";
... ... @@ -779,6 +918,8 @@
779 918 interrupts = <0 128 4>;
780 919 clocks = <&usb_mp_clk>;
781 920 clock-names = "otg";
  921 + resets = <&rst USB1_RESET>;
  922 + reset-names = "dwc2";
782 923 phys = <&usbphy0>;
783 924 phy-names = "usb2-phy";
784 925 status = "disabled";
... ... @@ -798,11 +939,6 @@
798 939 interrupts = <0 172 4>;
799 940 clocks = <&osc1>;
800 941 status = "disabled";
801   - };
802   -
803   - sysmgr: sysmgr@ffd08000 {
804   - compatible = "altr,sys-mgr", "syscon";
805   - reg = <0xffd08000 0x4000>;
806 942 };
807 943 };
808 944 };
arch/arm/dts/socfpga_arria5.dtsi
Diff comments   View file @ c402e81
1   -// SPDX-License-Identifier: GPL-2.0+
  1 +// SPDX-License-Identifier: GPL-2.0
2 2 /*
3   - * Copyright (C) 2013 Altera Corporation <www.altera.com>
  3 + * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 4 */
5 5  
6 6 /dts-v1/;
7 7  
8 8  
... ... @@ -19,18 +19,19 @@
19 19 };
20 20  
21 21 mmc0: dwmmc0@ff704000 {
22   - num-slots = <1>;
23 22 broken-cd;
24 23 bus-width = <4>;
25 24 cap-mmc-highspeed;
26 25 cap-sd-highspeed;
27   - drvsel = <3>;
28   - smplsel = <0>;
29 26 };
30 27  
31 28 sysmgr@ffd08000 {
32 29 cpu1-start-addr = <0xffd080c4>;
33 30 };
34 31 };
  32 +};
  33 +
  34 +&watchdog0 {
  35 + status = "okay";
35 36 };
arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
Diff comments   View file @ c402e81
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * U-Boot additions
  4 + *
  5 + * Copyright (C) 2013 Altera Corporation <www.altera.com>
  6 + * Copyright (c) 2018 Simon Goldschmidt
  7 + */
  8 +
  9 +/{
  10 + aliases {
  11 + spi0 = "/soc/spi@ff705000";
  12 + udc0 = &usb1;
  13 + };
  14 +
  15 + soc {
  16 + u-boot,dm-pre-reloc;
  17 + };
  18 +};
  19 +
  20 +&watchdog0 {
  21 + status = "disabled";
  22 +};
  23 +
  24 +&mmc {
  25 + u-boot,dm-pre-reloc;
  26 +};
  27 +
  28 +&qspi {
  29 + u-boot,dm-pre-reloc;
  30 +};
  31 +
  32 +&flash {
  33 + compatible = "n25q00", "spi-flash";
  34 + u-boot,dm-pre-reloc;
  35 +};
  36 +
  37 +&uart0 {
  38 + clock-frequency = <100000000>;
  39 + u-boot,dm-pre-reloc;
  40 +};
  41 +
  42 +&uart1 {
  43 + clock-frequency = <100000000>;
  44 +};
  45 +
  46 +&porta {
  47 + bank-name = "porta";
  48 +};
  49 +
  50 +&portb {
  51 + bank-name = "portb";
  52 +};
  53 +
  54 +&portc {
  55 + bank-name = "portc";
  56 +};
arch/arm/dts/socfpga_arria5_socdk.dts
Diff comments   View file @ c402e81
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3   - * Copyright (C) 2013 Altera Corporation <www.altera.com>
  3 + * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 4 */
5 5  
6 6 #include "socfpga_arria5.dtsi"
7 7  
8 8  
9 9  
10 10  
11 11  
... ... @@ -10,34 +10,52 @@
10 10 compatible = "altr,socfpga-arria5", "altr,socfpga";
11 11  
12 12 chosen {
13   - bootargs = "console=ttyS0,115200";
  13 + bootargs = "earlyprintk";
14 14 stdout-path = "serial0:115200n8";
15 15 };
16 16  
17   - memory {
  17 + memory@0 {
18 18 name = "memory";
19 19 device_type = "memory";
20 20 reg = <0x0 0x40000000>; /* 1GB */
21 21 };
22 22  
23 23 aliases {
24   - /* this allow the ethaddr uboot environment variable contents
25   - * to be added to the gmac1 device tree blob.
26   - */
  24 + /* this allow the ethaddr uboot environmnet variable contents
  25 + * to be added to the gmac1 device tree blob.
  26 + */
27 27 ethernet0 = &gmac1;
28   - udc0 = &usb1;
29 28 };
30 29  
  30 + leds {
  31 + compatible = "gpio-leds";
  32 + hps0 {
  33 + label = "hps_led0";
  34 + gpios = <&porta 0 1>;
  35 + };
  36 +
  37 + hps1 {
  38 + label = "hps_led1";
  39 + gpios = <&portb 11 1>;
  40 + };
  41 +
  42 + hps2 {
  43 + label = "hps_led2";
  44 + gpios = <&porta 17 1>;
  45 + };
  46 +
  47 + hps3 {
  48 + label = "hps_led3";
  49 + gpios = <&porta 18 1>;
  50 + };
  51 + };
  52 +
31 53 regulator_3_3v: 3-3-v-regulator {
32 54 compatible = "regulator-fixed";
33 55 regulator-name = "3.3V";
34 56 regulator-min-microvolt = <3300000>;
35 57 regulator-max-microvolt = <3300000>;
36 58 };
37   -
38   - soc {
39   - u-boot,dm-pre-reloc;
40   - };
41 59 };
42 60  
43 61 &gmac1 {
44 62  
45 63  
... ... @@ -54,9 +72,29 @@
54 72 rxc-skew-ps = <2000>;
55 73 };
56 74  
  75 +&gpio0 {
  76 + status = "okay";
  77 +};
  78 +
  79 +&gpio1 {
  80 + status = "okay";
  81 +};
  82 +
  83 +&gpio2 {
  84 + status = "okay";
  85 +};
  86 +
57 87 &i2c0 {
58 88 status = "okay";
  89 + clock-frequency = <100000>;
59 90  
  91 + /*
  92 + * adjust the falling times to decrease the i2c frequency to 50Khz
  93 + * because the LCD module does not work at the standard 100Khz
  94 + */
  95 + i2c-sda-falling-time-ns = <5000>;
  96 + i2c-scl-falling-time-ns = <5000>;
  97 +
60 98 eeprom@51 {
61 99 compatible = "atmel,24c32";
62 100 reg = <0x51>;
63 101  
64 102  
65 103  
66 104  
67 105  
68 106  
... ... @@ -72,36 +110,43 @@
72 110 &mmc0 {
73 111 vmmc-supply = <&regulator_3_3v>;
74 112 vqmmc-supply = <&regulator_3_3v>;
75   - bus-width = <4>;
76   - u-boot,dm-pre-reloc;
77   -};
78   -
79   -&usb1 {
80 113 status = "okay";
81 114 };
82 115  
83 116 &qspi {
84 117 status = "okay";
85   - u-boot,dm-pre-reloc;
86 118  
87   - flash0: n25q00@0 {
88   - u-boot,dm-pre-reloc;
  119 + flash: flash@0 {
89 120 #address-cells = <1>;
90 121 #size-cells = <1>;
91   - compatible = "n25q00", "spi-flash";
92   - reg = <0>; /* chip select */
93   - spi-max-frequency = <50000000>;
  122 + compatible = "n25q256a";
  123 + reg = <0>;
  124 + spi-max-frequency = <100000000>;
  125 +
94 126 m25p,fast-read;
95   - page-size = <256>;
96   - block-size = <16>; /* 2^16, 64KB */
  127 + cdns,page-size = <256>;
  128 + cdns,block-size = <16>;
  129 + cdns,read-delay = <4>;
97 130 cdns,tshsl-ns = <50>;
98 131 cdns,tsd2d-ns = <50>;
99 132 cdns,tchsh-ns = <4>;
100 133 cdns,tslch-ns = <4>;
  134 +
  135 + partition@qspi-boot {
  136 + /* 8MB for raw data. */
  137 + label = "Flash 0 Raw Data";
  138 + reg = <0x0 0x800000>;
  139 + };
  140 +
  141 + partition@qspi-rootfs {
  142 + /* 120MB for jffs2 data. */
  143 + label = "Flash 0 jffs2 Filesystem";
  144 + reg = <0x800000 0x7800000>;
  145 + };
101 146 };
102 147 };
103 148  
104   -&uart0 {
105   - u-boot,dm-pre-reloc;
  149 +&usb1 {
  150 + status = "okay";
106 151 };
arch/arm/dts/socfpga_cyclone5.dtsi
Diff comments   View file @ c402e81
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3   - * Copyright (C) 2012 Altera Corporation <www.altera.com>
  3 + * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 4 */
5 5  
6 6 /dts-v1/;
7 7  
8 8  
... ... @@ -19,18 +19,19 @@
19 19 };
20 20  
21 21 mmc0: dwmmc0@ff704000 {
22   - num-slots = <1>;
23 22 broken-cd;
24 23 bus-width = <4>;
25 24 cap-mmc-highspeed;
26 25 cap-sd-highspeed;
27   - drvsel = <3>;
28   - smplsel = <0>;
29 26 };
30 27  
31 28 sysmgr@ffd08000 {
32 29 cpu1-start-addr = <0xffd080c4>;
33 30 };
34 31 };
  32 +};
  33 +
  34 +&watchdog0 {
  35 + status = "okay";
35 36 };
arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
Diff comments   View file @ c402e81
... ... @@ -47,9 +47,20 @@
47 47 status = "okay";
48 48 };
49 49  
  50 +&porta {
  51 + bank-name = "porta";
  52 +};
  53 +
  54 +&portb {
  55 + bank-name = "portb";
  56 +};
  57 +
  58 +&portc {
  59 + bank-name = "portc";
  60 +};
  61 +
50 62 &mmc0 {
51 63 status = "okay";
52   - bus-width = <4>;
53 64 u-boot,dm-pre-reloc;
54 65 };
55 66  
... ... @@ -60,5 +71,9 @@
60 71  
61 72 &uart0 {
62 73 u-boot,dm-pre-reloc;
  74 +};
  75 +
  76 +&watchdog0 {
  77 + status = "disabled";
63 78 };
arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
Diff comments   View file @ c402e81
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * U-Boot additions
  4 + *
  5 + * Copyright Altera Corporation (C) 2015
  6 + * Copyright (c) 2018 Simon Goldschmidt
  7 + */
  8 +
  9 +/{
  10 + aliases {
  11 + udc0 = &usb1;
  12 + };
  13 +
  14 + soc {
  15 + u-boot,dm-pre-reloc;
  16 + };
  17 +};
  18 +
  19 +&watchdog0 {
  20 + status = "disabled";
  21 +};
  22 +
  23 +&mmc {
  24 + u-boot,dm-pre-reloc;
  25 +};
  26 +
  27 +&uart0 {
  28 + clock-frequency = <100000000>;
  29 + u-boot,dm-pre-reloc;
  30 +};
  31 +
  32 +&uart1 {
  33 + clock-frequency = <100000000>;
  34 +};
  35 +
  36 +&porta {
  37 + bank-name = "porta";
  38 +};
  39 +
  40 +&portb {
  41 + bank-name = "portb";
  42 +};
  43 +
  44 +&portc {
  45 + bank-name = "portc";
  46 +};
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
Diff comments   View file @ c402e81
1   -// SPDX-License-Identifier: GPL-2.0+
  1 +// SPDX-License-Identifier: GPL-2.0
2 2 /*
3   - * Copyright Altera Corporation (C) 2015
  3 + * Copyright Altera Corporation (C) 2015. All rights reserved.
4 4 */
5 5  
6 6 #include "socfpga_cyclone5.dtsi"
7 7  
8 8 / {
9   - model = "Terasic DE0-Nano(Atlas)";
10   - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
  9 + model = "Terasic DE-0(Atlas)";
  10 + compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
11 11  
12 12 chosen {
13   - bootargs = "console=ttyS0,115200";
  13 + bootargs = "earlyprintk";
14 14 stdout-path = "serial0:115200n8";
15 15 };
16 16  
  17 + memory@0 {
  18 + name = "memory";
  19 + device_type = "memory";
  20 + reg = <0x0 0x40000000>; /* 1GB */
  21 + };
  22 +
17 23 aliases {
18 24 ethernet0 = &gmac1;
19   - udc0 = &usb1;
20 25 };
21 26  
22   - memory {
23   - name = "memory";
24   - device_type = "memory";
25   - reg = <0x0 0x40000000>; /* 1GB */
  27 + regulator_3_3v: 3-3-v-regulator {
  28 + compatible = "regulator-fixed";
  29 + regulator-name = "3.3V";
  30 + regulator-min-microvolt = <3300000>;
  31 + regulator-max-microvolt = <3300000>;
26 32 };
27 33  
28   - soc {
29   - u-boot,dm-pre-reloc;
  34 + leds {
  35 + compatible = "gpio-leds";
  36 + hps0 {
  37 + label = "hps_led0";
  38 + gpios = <&portb 24 0>;
  39 + linux,default-trigger = "heartbeat";
  40 + };
30 41 };
31 42 };
32 43  
... ... @@ -34,14 +45,20 @@
34 45 status = "okay";
35 46 phy-mode = "rgmii";
36 47  
37   - rxd0-skew-ps = <420>;
38   - rxd1-skew-ps = <420>;
39   - rxd2-skew-ps = <420>;
40   - rxd3-skew-ps = <420>;
41   - txen-skew-ps = <0>;
42   - txc-skew-ps = <1860>;
43   - rxdv-skew-ps = <420>;
44   - rxc-skew-ps = <1680>;
  48 + txd0-skew-ps = <0>; /* -420ps */
  49 + txd1-skew-ps = <0>; /* -420ps */
  50 + txd2-skew-ps = <0>; /* -420ps */
  51 + txd3-skew-ps = <0>; /* -420ps */
  52 + rxd0-skew-ps = <420>; /* 0ps */
  53 + rxd1-skew-ps = <420>; /* 0ps */
  54 + rxd2-skew-ps = <420>; /* 0ps */
  55 + rxd3-skew-ps = <420>; /* 0ps */
  56 + txen-skew-ps = <0>; /* -420ps */
  57 + txc-skew-ps = <1860>; /* 960ps */
  58 + rxdv-skew-ps = <420>; /* 0ps */
  59 + rxc-skew-ps = <1680>; /* 780ps */
  60 +
  61 + max-frame-size = <3800>;
45 62 };
46 63  
47 64 &gpio0 {
48 65  
... ... @@ -58,8 +75,9 @@
58 75  
59 76 &i2c0 {
60 77 status = "okay";
  78 + clock-frequency = <100000>;
61 79  
62   - dxl345: adxl345@0 {
  80 + adxl345: adxl345@53 {
63 81 compatible = "adi,adxl345";
64 82 reg = <0x53>;
65 83  
66 84  
67 85  
68 86  
... ... @@ -69,15 +87,16 @@
69 87 };
70 88  
71 89 &mmc0 {
  90 + vmmc-supply = <&regulator_3_3v>;
  91 + vqmmc-supply = <&regulator_3_3v>;
72 92 status = "okay";
73   - u-boot,dm-pre-reloc;
74 93 };
75 94  
76   -&usb1 {
  95 +&uart0 {
77 96 status = "okay";
78 97 };
79 98  
80   -&uart0 {
81   - u-boot,dm-pre-reloc;
  99 +&usb1 {
  100 + status = "okay";
82 101 };
arch/arm/dts/socfpga_cyclone5_de10_nano.dts
Diff comments   View file @ c402e81
... ... @@ -58,6 +58,18 @@
58 58 status = "okay";
59 59 };
60 60  
  61 +&porta {
  62 + bank-name = "porta";
  63 +};
  64 +
  65 +&portb {
  66 + bank-name = "portb";
  67 +};
  68 +
  69 +&portc {
  70 + bank-name = "portc";
  71 +};
  72 +
61 73 &mmc0 {
62 74 status = "okay";
63 75 u-boot,dm-pre-reloc;
... ... @@ -69,5 +81,9 @@
69 81  
70 82 &uart0 {
71 83 u-boot,dm-pre-reloc;
  84 +};
  85 +
  86 +&watchdog0 {
  87 + status = "disabled";
72 88 };
arch/arm/dts/socfpga_cyclone5_de1_soc.dts
Diff comments   View file @ c402e81
... ... @@ -56,6 +56,18 @@
56 56 status = "okay";
57 57 };
58 58  
  59 +&porta {
  60 + bank-name = "porta";
  61 +};
  62 +
  63 +&portb {
  64 + bank-name = "portb";
  65 +};
  66 +
  67 +&portc {
  68 + bank-name = "portc";
  69 +};
  70 +
59 71 &mmc0 {
60 72 status = "okay";
61 73 u-boot,dm-pre-reloc;
... ... @@ -67,5 +79,9 @@
67 79  
68 80 &uart0 {
69 81 u-boot,dm-pre-reloc;
  82 +};
  83 +
  84 +&watchdog0 {
  85 + status = "disabled";
70 86 };
arch/arm/dts/socfpga_cyclone5_is1.dts
Diff comments   View file @ c402e81
... ... @@ -55,6 +55,10 @@
55 55 status = "okay";
56 56 };
57 57  
  58 +&porta {
  59 + bank-name = "porta";
  60 +};
  61 +
58 62 &i2c0 {
59 63 status = "okay";
60 64  
... ... @@ -106,5 +110,9 @@
106 110  
107 111 &uart0 {
108 112 u-boot,dm-pre-reloc;
  113 +};
  114 +
  115 +&watchdog0 {
  116 + status = "disabled";
109 117 };
arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
Diff comments   View file @ c402e81
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * U-Boot additions
  4 + *
  5 + * Copyright (C) 2012 Altera Corporation <www.altera.com>
  6 + * Copyright (c) 2018 Simon Goldschmidt
  7 + */
  8 +
  9 +/{
  10 + aliases {
  11 + spi0 = "/soc/spi@ff705000";
  12 + udc0 = &usb1;
  13 + };
  14 +
  15 + soc {
  16 + u-boot,dm-pre-reloc;
  17 + };
  18 +};
  19 +
  20 +&can0 {
  21 + status = "okay";
  22 +};
  23 +
  24 +&watchdog0 {
  25 + status = "disabled";
  26 +};
  27 +
  28 +&mmc {
  29 + u-boot,dm-pre-reloc;
  30 +};
  31 +
  32 +&qspi {
  33 + u-boot,dm-pre-reloc;
  34 +};
  35 +
  36 +&flash0 {
  37 + compatible = "n25q00", "spi-flash";
  38 + u-boot,dm-pre-reloc;
  39 +
  40 + partition@qspi-boot {
  41 + /* 8MB for raw data. */
  42 + label = "Flash 0 Raw Data";
  43 + reg = <0x0 0x800000>;
  44 + };
  45 +
  46 + partition@qspi-rootfs {
  47 + /* 120MB for jffs2 data. */
  48 + label = "Flash 0 jffs2 Filesystem";
  49 + reg = <0x800000 0x7800000>;
  50 + };
  51 +};
  52 +
  53 +&uart0 {
  54 + clock-frequency = <100000000>;
  55 + u-boot,dm-pre-reloc;
  56 +};
  57 +
  58 +&uart1 {
  59 + clock-frequency = <100000000>;
  60 +};
  61 +
  62 +&porta {
  63 + bank-name = "porta";
  64 +};
  65 +
  66 +&portb {
  67 + bank-name = "portb";
  68 +};
  69 +
  70 +&portc {
  71 + bank-name = "portc";
  72 +};
arch/arm/dts/socfpga_cyclone5_socdk.dts
Diff comments   View file @ c402e81
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3   - * Copyright (C) 2012 Altera Corporation <www.altera.com>
  3 + * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 4 */
5 5  
6 6 #include "socfpga_cyclone5.dtsi"
7 7  
8 8 / {
9 9 model = "Altera SOCFPGA Cyclone V SoC Development Kit";
10   - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
  10 + compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";
11 11  
12 12 chosen {
13   - bootargs = "console=ttyS0,115200";
  13 + bootargs = "earlyprintk";
14 14 stdout-path = "serial0:115200n8";
15 15 };
16 16  
17   - memory {
  17 + memory@0 {
18 18 name = "memory";
19 19 device_type = "memory";
20 20 reg = <0x0 0x40000000>; /* 1GB */
21 21 };
22 22  
23 23 aliases {
24   - /* this allow the ethaddr uboot environment variable contents
  24 + /* this allow the ethaddr uboot environmnet variable contents
25 25 * to be added to the gmac1 device tree blob.
26 26 */
27 27 ethernet0 = &gmac1;
28   - udc0 = &usb1;
29 28 };
30 29  
  30 + leds {
  31 + compatible = "gpio-leds";
  32 + hps0 {
  33 + label = "hps_led0";
  34 + gpios = <&portb 15 1>;
  35 + };
  36 +
  37 + hps1 {
  38 + label = "hps_led1";
  39 + gpios = <&portb 14 1>;
  40 + };
  41 +
  42 + hps2 {
  43 + label = "hps_led2";
  44 + gpios = <&portb 13 1>;
  45 + };
  46 +
  47 + hps3 {
  48 + label = "hps_led3";
  49 + gpios = <&portb 12 1>;
  50 + };
  51 + };
  52 +
31 53 regulator_3_3v: 3-3-v-regulator {
32 54 compatible = "regulator-fixed";
33 55 regulator-name = "3.3V";
34 56 regulator-min-microvolt = <3300000>;
35 57 regulator-max-microvolt = <3300000>;
36 58 };
  59 +};
37 60  
38   - soc {
39   - u-boot,dm-pre-reloc;
40   - };
  61 +&can0 {
  62 + status = "okay";
41 63 };
42 64  
43 65 &gmac1 {
44 66  
... ... @@ -68,7 +90,15 @@
68 90  
69 91 &i2c0 {
70 92 status = "okay";
  93 + clock-frequency = <100000>;
71 94  
  95 + /*
  96 + * adjust the falling times to decrease the i2c frequency to 50Khz
  97 + * because the LCD module does not work at the standard 100Khz
  98 + */
  99 + i2c-sda-falling-time-ns = <5000>;
  100 + i2c-scl-falling-time-ns = <5000>;
  101 +
72 102 eeprom@51 {
73 103 compatible = "atmel,24c32";
74 104 reg = <0x51>;
75 105  
76 106  
77 107  
78 108  
79 109  
80 110  
81 111  
82 112  
83 113  
84 114  
... ... @@ -82,40 +112,56 @@
82 112 };
83 113  
84 114 &mmc0 {
85   - status = "okay";
86   - u-boot,dm-pre-reloc;
87   -
88 115 cd-gpios = <&portb 18 0>;
89 116 vmmc-supply = <&regulator_3_3v>;
90 117 vqmmc-supply = <&regulator_3_3v>;
  118 + status = "okay";
91 119 };
92 120  
93 121 &qspi {
94 122 status = "okay";
95   - u-boot,dm-pre-reloc;
96 123  
97 124 flash0: n25q00@0 {
98   - u-boot,dm-pre-reloc;
99 125 #address-cells = <1>;
100 126 #size-cells = <1>;
101   - compatible = "n25q00", "spi-flash";
102   - reg = <0>; /* chip select */
  127 + compatible = "n25q00";
  128 + reg = <0>; /* chip select */
103 129 spi-max-frequency = <100000000>;
  130 +
104 131 m25p,fast-read;
105   - page-size = <256>;
106   - block-size = <16>; /* 2^16, 64KB */
  132 + cdns,page-size = <256>;
  133 + cdns,block-size = <16>;
  134 + cdns,read-delay = <4>;
107 135 cdns,tshsl-ns = <50>;
108 136 cdns,tsd2d-ns = <50>;
109 137 cdns,tchsh-ns = <4>;
110 138 cdns,tslch-ns = <4>;
  139 +
  140 + partition@qspi-boot {
  141 + /* 8MB for raw data. */
  142 + label = "Flash 0 Raw Data";
  143 + reg = <0x0 0x800000>;
  144 + };
  145 +
  146 + partition@qspi-rootfs {
  147 + /* 120MB for jffs2 data. */
  148 + label = "Flash 0 jffs2 Filesystem";
  149 + reg = <0x800000 0x7800000>;
  150 + };
111 151 };
112 152 };
113 153  
114   -&usb1 {
  154 +&spi0 {
115 155 status = "okay";
  156 +
  157 + spidev@0 {
  158 + compatible = "rohm,dh2228fv";
  159 + reg = <0>;
  160 + spi-max-frequency = <1000000>;
  161 + };
116 162 };
117 163  
118   -&uart0 {
119   - u-boot,dm-pre-reloc;
  164 +&usb1 {
  165 + status = "okay";
120 166 };
arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
Diff comments   View file @ c402e81
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * U-Boot additions
  4 + *
  5 + * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
  6 + * Copyright (c) 2018 Simon Goldschmidt
  7 + */
  8 +
  9 +/{
  10 + aliases {
  11 + spi0 = "/soc/spi@ff705000";
  12 + udc0 = &usb1;
  13 + };
  14 +
  15 + soc {
  16 + u-boot,dm-pre-reloc;
  17 + };
  18 +};
  19 +
  20 +&watchdog0 {
  21 + status = "disabled";
  22 +};
  23 +
  24 +&mmc {
  25 + u-boot,dm-pre-reloc;
  26 +};
  27 +
  28 +&qspi {
  29 + u-boot,dm-pre-reloc;
  30 +};
  31 +
  32 +&flash {
  33 + compatible = "n25q00", "spi-flash";
  34 + u-boot,dm-pre-reloc;
  35 +};
  36 +
  37 +&uart0 {
  38 + clock-frequency = <100000000>;
  39 + u-boot,dm-pre-reloc;
  40 +};
  41 +
  42 +&uart1 {
  43 + clock-frequency = <100000000>;
  44 +};
  45 +
  46 +&porta {
  47 + bank-name = "porta";
  48 +};
  49 +
  50 +&portb {
  51 + bank-name = "portb";
  52 +};
  53 +
  54 +&portc {
  55 + bank-name = "portc";
  56 +};
arch/arm/dts/socfpga_cyclone5_sockit.dts
Diff comments   View file @ c402e81
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3   - * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
  3 + * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
4 4 */
5 5  
6 6 #include "socfpga_cyclone5.dtsi"
7 7  
8 8 / {
9 9 model = "Terasic SoCkit";
10   - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
  10 + compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga";
11 11  
12 12 chosen {
13   - bootargs = "console=ttyS0,115200";
  13 + bootargs = "earlyprintk";
14 14 stdout-path = "serial0:115200n8";
15 15 };
16 16  
  17 + memory@0 {
  18 + name = "memory";
  19 + device_type = "memory";
  20 + reg = <0x0 0x40000000>; /* 1GB */
  21 + };
  22 +
17 23 aliases {
  24 + /* this allow the ethaddr uboot environmnet variable contents
  25 + * to be added to the gmac1 device tree blob.
  26 + */
18 27 ethernet0 = &gmac1;
19   - udc0 = &usb1;
20 28 };
21 29  
22   - memory {
23   - name = "memory";
24   - device_type = "memory";
25   - reg = <0x0 0x40000000>; /* 1GB */
  30 + leds {
  31 + compatible = "gpio-leds";
  32 +
  33 + hps_led0 {
  34 + label = "hps:blue:led0";
  35 + gpios = <&portb 24 0>; /* HPS_GPIO53 */
  36 + linux,default-trigger = "heartbeat";
  37 + };
  38 +
  39 + hps_led1 {
  40 + label = "hps:blue:led1";
  41 + gpios = <&portb 25 0>; /* HPS_GPIO54 */
  42 + linux,default-trigger = "heartbeat";
  43 + };
  44 +
  45 + hps_led2 {
  46 + label = "hps:blue:led2";
  47 + gpios = <&portb 26 0>; /* HPS_GPIO55 */
  48 + linux,default-trigger = "heartbeat";
  49 + };
  50 +
  51 + hps_led3 {
  52 + label = "hps:blue:led3";
  53 + gpios = <&portb 27 0>; /* HPS_GPIO56 */
  54 + linux,default-trigger = "heartbeat";
  55 + };
26 56 };
27 57  
28   - soc {
29   - u-boot,dm-pre-reloc;
  58 + gpio-keys {
  59 + compatible = "gpio-keys";
  60 +
  61 + hps_sw0 {
  62 + label = "hps_sw0";
  63 + gpios = <&portc 20 0>; /* HPS_GPI7 */
  64 + linux,input-type = <5>; /* EV_SW */
  65 + linux,code = <0x0>; /* SW_LID */
  66 + };
  67 +
  68 + hps_sw1 {
  69 + label = "hps_sw1";
  70 + gpios = <&portc 19 0>; /* HPS_GPI6 */
  71 + linux,input-type = <5>; /* EV_SW */
  72 + linux,code = <0x5>; /* SW_DOCK */
  73 + };
  74 +
  75 + hps_sw2 {
  76 + label = "hps_sw2";
  77 + gpios = <&portc 18 0>; /* HPS_GPI5 */
  78 + linux,input-type = <5>; /* EV_SW */
  79 + linux,code = <0xa>; /* SW_KEYPAD_SLIDE */
  80 + };
  81 +
  82 + hps_sw3 {
  83 + label = "hps_sw3";
  84 + gpios = <&portc 17 0>; /* HPS_GPI4 */
  85 + linux,input-type = <5>; /* EV_SW */
  86 + linux,code = <0xc>; /* SW_ROTATE_LOCK */
  87 + };
  88 +
  89 + hps_hkey0 {
  90 + label = "hps_hkey0";
  91 + gpios = <&portc 21 1>; /* HPS_GPI8 */
  92 + linux,code = <187>; /* KEY_F17 */
  93 + };
  94 +
  95 + hps_hkey1 {
  96 + label = "hps_hkey1";
  97 + gpios = <&portc 22 1>; /* HPS_GPI9 */
  98 + linux,code = <188>; /* KEY_F18 */
  99 + };
  100 +
  101 + hps_hkey2 {
  102 + label = "hps_hkey2";
  103 + gpios = <&portc 23 1>; /* HPS_GPI10 */
  104 + linux,code = <189>; /* KEY_F19 */
  105 + };
  106 +
  107 + hps_hkey3 {
  108 + label = "hps_hkey3";
  109 + gpios = <&portc 24 1>; /* HPS_GPI11 */
  110 + linux,code = <190>; /* KEY_F20 */
  111 + };
30 112 };
  113 +
  114 + regulator_3_3v: vcc3p3-regulator {
  115 + compatible = "regulator-fixed";
  116 + regulator-name = "VCC3P3";
  117 + regulator-min-microvolt = <3300000>;
  118 + regulator-max-microvolt = <3300000>;
  119 + };
31 120 };
32 121  
33 122 &gmac1 {
34 123  
35 124  
36 125  
37 126  
38 127  
39 128  
40 129  
41 130  
42 131  
43 132  
... ... @@ -44,46 +133,50 @@
44 133 rxc-skew-ps = <2000>;
45 134 };
46 135  
47   -&gpio0 {
  136 +&gpio0 { /* GPIO 0..29 */
48 137 status = "okay";
49 138 };
50 139  
51   -&gpio1 {
  140 +&gpio1 { /* GPIO 30..57 */
52 141 status = "okay";
53 142 };
54 143  
55   -&gpio2 {
  144 +&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
56 145 status = "okay";
57 146 };
58 147  
59   -&i2c0 {
  148 +&i2c1 {
60 149 status = "okay";
61 150  
62   - rtc: rtc@68 {
63   - compatible = "stm,m41t82";
64   - reg = <0x68>;
  151 + accel1: accelerometer@53 {
  152 + compatible = "adi,adxl345";
  153 + reg = <0x53>;
  154 +
  155 + interrupt-parent = <&portc>;
  156 + interrupts = <3 2>;
65 157 };
66 158 };
67 159  
68 160 &mmc0 {
  161 + vmmc-supply = <&regulator_3_3v>;
  162 + vqmmc-supply = <&regulator_3_3v>;
69 163 status = "okay";
70   - u-boot,dm-pre-reloc;
71 164 };
72 165  
73 166 &qspi {
74 167 status = "okay";
75   - u-boot,dm-pre-reloc;
76 168  
77   - flash0: n25q00@0 {
78   - u-boot,dm-pre-reloc;
  169 + flash: flash@0 {
79 170 #address-cells = <1>;
80 171 #size-cells = <1>;
81   - compatible = "n25q00", "spi-flash";
82   - reg = <0>; /* chip select */
83   - spi-max-frequency = <50000000>;
  172 + compatible = "n25q00";
  173 + reg = <0>;
  174 + spi-max-frequency = <100000000>;
  175 +
84 176 m25p,fast-read;
85   - page-size = <256>;
86   - block-size = <16>; /* 2^16, 64KB */
  177 + cdns,page-size = <256>;
  178 + cdns,block-size = <16>;
  179 + cdns,read-delay = <4>;
87 180 cdns,tshsl-ns = <50>;
88 181 cdns,tsd2d-ns = <50>;
89 182 cdns,tchsh-ns = <4>;
... ... @@ -93,9 +186,5 @@
93 186  
94 187 &usb1 {
95 188 status = "okay";
96   -};
97   -
98   -&uart0 {
99   - u-boot,dm-pre-reloc;
100 189 };
arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
Diff comments   View file @ c402e81
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * U-Boot additions
  4 + *
  5 + * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
  6 + * Copyright (c) 2018 Simon Goldschmidt
  7 + */
  8 +
  9 +/{
  10 + aliases {
  11 + spi0 = "/soc/spi@ff705000";
  12 + udc0 = &usb1;
  13 + };
  14 +
  15 + soc {
  16 + u-boot,dm-pre-reloc;
  17 + };
  18 +};
  19 +
  20 +&watchdog0 {
  21 + status = "disabled";
  22 +};
  23 +
  24 +&mmc {
  25 + u-boot,dm-pre-reloc;
  26 +};
  27 +
  28 +&qspi {
  29 + u-boot,dm-pre-reloc;
  30 +};
  31 +
  32 +&flash {
  33 + compatible = "n25q256a", "spi-flash";
  34 + u-boot,dm-pre-reloc;
  35 +};
  36 +
  37 +&uart0 {
  38 + clock-frequency = <100000000>;
  39 + u-boot,dm-pre-reloc;
  40 +};
  41 +
  42 +&uart1 {
  43 + clock-frequency = <100000000>;
  44 +};
  45 +
  46 +&usb1 {
  47 + status = "okay";
  48 +};
  49 +
  50 +&porta {
  51 + bank-name = "porta";
  52 +};
  53 +
  54 +&portb {
  55 + bank-name = "portb";
  56 +};
  57 +
  58 +&portc {
  59 + bank-name = "portc";
  60 +};
arch/arm/dts/socfpga_cyclone5_socrates.dts
Diff comments   View file @ c402e81
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3   - * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
  3 + * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
4 4 */
5 5  
6 6 #include "socfpga_cyclone5.dtsi"
7 7  
8 8  
9 9  
10 10  
11 11  
12 12  
13 13  
14 14  
15 15  
16 16  
17 17  
18 18  
19 19  
20 20  
21 21  
22 22  
... ... @@ -9,84 +9,87 @@
9 9 model = "EBV SOCrates";
10 10 compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
11 11  
12   - chosen {
13   - bootargs = "console=ttyS0,115200";
14   - stdout-path = "serial0:115200n8";
15   - };
16   -
17 12 aliases {
18   - /*
19   - * This allows the ethaddr uboot environment variable
20   - * contents to be added to the gmac1 device tree blob.
21   - */
22 13 ethernet0 = &gmac1;
23   - udc0 = &usb1;
24 14 };
25 15  
26   - memory {
  16 + chosen {
  17 + bootargs = "earlyprintk";
  18 + stdout-path = "serial0:115200n8";
  19 + };
  20 +
  21 + memory@0 {
27 22 name = "memory";
28 23 device_type = "memory";
29 24 reg = <0x0 0x40000000>; /* 1GB */
30 25 };
31 26  
32   - soc {
33   - u-boot,dm-pre-reloc;
  27 + leds: gpio-leds {
34 28 };
35 29 };
36 30  
37 31 &gmac1 {
38   - status = "okay";
39 32 phy-mode = "rgmii";
  33 + status = "okay";
  34 +};
40 35  
41   - rxd0-skew-ps = <0>;
42   - rxd1-skew-ps = <0>;
43   - rxd2-skew-ps = <0>;
44   - rxd3-skew-ps = <0>;
45   - txen-skew-ps = <0>;
46   - txc-skew-ps = <2600>;
47   - rxdv-skew-ps = <0>;
48   - rxc-skew-ps = <2000>;
  36 +&gpio0 {
  37 + status = "okay";
49 38 };
50 39  
  40 +&gpio1 {
  41 + status = "okay";
  42 +};
  43 +
51 44 &i2c0 {
52 45 status = "okay";
53 46  
54 47 rtc: rtc@68 {
55   - compatible = "stm,m41t82";
  48 + compatible = "st,m41t82";
56 49 reg = <0x68>;
57 50 };
58 51 };
59 52  
60   -&mmc0 {
  53 +&leds {
  54 + compatible = "gpio-leds";
  55 +
  56 + led0 {
  57 + label = "led:green:heartbeat";
  58 + gpios = <&porta 28 1>;
  59 + linux,default-trigger = "heartbeat";
  60 + };
  61 +
  62 + led1 {
  63 + label = "led:green:D7";
  64 + gpios = <&portb 19 1>;
  65 + };
  66 +
  67 + led2 {
  68 + label = "led:green:D8";
  69 + gpios = <&portb 25 1>;
  70 + };
  71 +};
  72 +
  73 +&mmc {
61 74 status = "okay";
62   - u-boot,dm-pre-reloc;
63 75 };
64 76  
65 77 &qspi {
66 78 status = "okay";
67 79  
68   - flash0: n25q00@0 {
  80 + flash: flash@0 {
69 81 #address-cells = <1>;
70 82 #size-cells = <1>;
71   - compatible = "n25q00", "spi-flash";
72   - reg = <0>; /* chip select */
73   - spi-max-frequency = <50000000>;
  83 + compatible = "n25q256a";
  84 + reg = <0>;
  85 + spi-max-frequency = <100000000>;
74 86 m25p,fast-read;
75   - page-size = <256>;
76   - block-size = <16>; /* 2^16, 64KB */
  87 + cdns,read-delay = <4>;
77 88 cdns,tshsl-ns = <50>;
78 89 cdns,tsd2d-ns = <50>;
79 90 cdns,tchsh-ns = <4>;
80 91 cdns,tslch-ns = <4>;
  92 + status = "okay";
81 93 };
82   -};
83   -
84   -&usb1 {
85   - disable-over-current;
86   - status = "okay";
87   -};
88   -
89   -&uart0 {
90   - u-boot,dm-pre-reloc;
91 94 };
arch/arm/dts/socfpga_cyclone5_sr1500.dts
Diff comments   View file @ c402e81
... ... @@ -50,6 +50,18 @@
50 50 status = "okay";
51 51 };
52 52  
  53 +&porta {
  54 + bank-name = "porta";
  55 +};
  56 +
  57 +&portb {
  58 + bank-name = "portb";
  59 +};
  60 +
  61 +&portc {
  62 + bank-name = "portc";
  63 +};
  64 +
53 65 &i2c0 {
54 66 status = "okay";
55 67 speed-mode = <0>;
arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
Diff comments   View file @ c402e81
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
  2 +/*
  3 + * U-Boot additions
  4 + *
  5 + * Copyright (C) 2015 Marek Vasut <marex@denx.de>
  6 + * Copyright (c) 2018 Simon Goldschmidt
  7 + */
  8 +
  9 +/{
  10 + aliases {
  11 + spi0 = "/soc/spi@ff705000";
  12 + udc0 = &usb0;
  13 + };
  14 +
  15 + soc {
  16 + u-boot,dm-pre-reloc;
  17 + };
  18 +};
  19 +
  20 +&watchdog0 {
  21 + status = "disabled";
  22 +};
  23 +
  24 +&mmc {
  25 + u-boot,dm-pre-reloc;
  26 +};
  27 +
  28 +&qspi {
  29 + u-boot,dm-pre-reloc;
  30 +
  31 + n25q128@0 {
  32 + compatible = "n25q128", "spi-flash";
  33 + u-boot,dm-pre-reloc;
  34 + };
  35 + n25q00@1 {
  36 + compatible = "n25q00", "spi-flash";
  37 + u-boot,dm-pre-reloc;
  38 + };
  39 +};
  40 +
  41 +&uart0 {
  42 + clock-frequency = <100000000>;
  43 + u-boot,dm-pre-reloc;
  44 +};
  45 +
  46 +&uart1 {
  47 + clock-frequency = <100000000>;
  48 +};
  49 +
  50 +&porta {
  51 + bank-name = "porta";
  52 +};
  53 +
  54 +&portb {
  55 + bank-name = "portb";
  56 +};
  57 +
  58 +&portc {
  59 + bank-name = "portc";
  60 +};
arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
Diff comments   View file @ c402e81
1   -// SPDX-License-Identifier: GPL-2.0+
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
2 2 /*
3 3 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
4 4 */
5 5  
6 6 #include "socfpga_cyclone5.dtsi"
  7 +#include <dt-bindings/gpio/gpio.h>
  8 +#include <dt-bindings/input/input.h>
7 9  
8 10 / {
9 11 model = "samtec VIN|ING FPGA";
10   - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
  12 + compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
11 13  
12 14 chosen {
13   - bootargs = "console=ttyS0,115200";
  15 + bootargs = "earlyprintk";
14 16 stdout-path = "serial0:115200n8";
15 17 };
16 18  
  19 + memory@0 {
  20 + name = "memory";
  21 + device_type = "memory";
  22 + reg = <0x0 0x40000000>; /* 1GB */
  23 + };
  24 +
17 25 aliases {
  26 + /*
  27 + * This allow the ethaddr uboot environment variable contents
  28 + * to be added to the gmac1 device tree blob.
  29 + */
18 30 ethernet0 = &gmac1;
19   - udc0 = &usb0;
  31 + ethernet1 = &gmac0;
20 32 };
21 33  
22   - memory {
23   - name = "memory";
24   - device_type = "memory";
25   - reg = <0x0 0x40000000>; /* 1GB */
  34 + gpio-keys {
  35 + compatible = "gpio-keys";
  36 +
  37 + hps_temp0 {
  38 + label = "BTN_0"; /* TEMP_OS */
  39 + gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPIO60 */
  40 + linux,code = <BTN_0>;
  41 + };
  42 +
  43 + hps_hkey0 {
  44 + label = "BTN_1"; /* DIS_PWR */
  45 + gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPIO61 */
  46 + linux,code = <BTN_1>;
  47 + };
  48 +
  49 + hps_hkey1 {
  50 + label = "hps_hkey1"; /* POWER_DOWN */
  51 + gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */
  52 + linux,code = <KEY_POWER>;
  53 + };
26 54 };
27 55  
28   - soc {
29   - u-boot,dm-pre-reloc;
  56 + regulator-usb-nrst {
  57 + compatible = "regulator-fixed";
  58 + regulator-name = "usb_nrst";
  59 + regulator-min-microvolt = <5000000>;
  60 + regulator-max-microvolt = <5000000>;
  61 + gpio = <&portb 5 GPIO_ACTIVE_HIGH>;
  62 + startup-delay-us = <70000>;
  63 + enable-active-high;
  64 + regulator-always-on;
30 65 };
31 66 };
32 67  
33 68 &gmac1 {
34 69 status = "okay";
35 70 phy-mode = "rgmii";
  71 + phy-handle = <&phy1>;
36 72  
37   - rxd0-skew-ps = <0>;
38   - rxd1-skew-ps = <0>;
39   - rxd2-skew-ps = <0>;
40   - rxd3-skew-ps = <0>;
41   - txen-skew-ps = <0>;
42   - txc-skew-ps = <2600>;
43   - rxdv-skew-ps = <0>;
44   - rxc-skew-ps = <2000>;
  73 + snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>;
  74 + snps,reset-active-low;
  75 + snps,reset-delays-us = <10000 10000 10000>;
  76 +
  77 + mdio0 {
  78 + #address-cells = <1>;
  79 + #size-cells = <0>;
  80 + compatible = "snps,dwmac-mdio";
  81 + phy1: ethernet-phy@1 {
  82 + reg = <1>;
  83 + rxd0-skew-ps = <0>;
  84 + rxd1-skew-ps = <0>;
  85 + rxd2-skew-ps = <0>;
  86 + rxd3-skew-ps = <0>;
  87 + txen-skew-ps = <0>;
  88 + txc-skew-ps = <2600>;
  89 + rxdv-skew-ps = <0>;
  90 + rxc-skew-ps = <2000>;
  91 + };
  92 + };
45 93 };
46 94  
47   -&gpio0 {
  95 +&gpio0 { /* GPIO 0..29 */
48 96 status = "okay";
49 97 };
50 98  
51   -&gpio1 {
  99 +&gpio1 { /* GPIO 30..57 */
52 100 status = "okay";
53 101 };
54 102  
55   -&gpio2 {
  103 +&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
56 104 status = "okay";
57 105 };
58 106  
59 107 &i2c0 {
60 108 status = "okay";
61 109  
62   - rtc: rtc@68 {
63   - compatible = "stm,m41t82";
64   - reg = <0x68>;
  110 + gpio: pca9557@1f {
  111 + compatible = "nxp,pca9557";
  112 + reg = <0x1f>;
  113 + gpio-controller;
  114 + #gpio-cells = <2>;
65 115 };
  116 +
  117 + temp: lm75@48 {
  118 + compatible = "lm75";
  119 + reg = <0x48>;
  120 + };
  121 +
  122 + at24@50 {
  123 + compatible = "atmel,24c01";
  124 + pagesize = <8>;
  125 + reg = <0x50>;
  126 + };
  127 +
  128 + i2cswitch@70 {
  129 + compatible = "nxp,pca9548";
  130 + #address-cells = <1>;
  131 + #size-cells = <0>;
  132 + reg = <0x70>;
  133 +
  134 + i2c@0 {
  135 + #address-cells = <1>;
  136 + #size-cells = <0>;
  137 + reg = <0>;
  138 + };
  139 +
  140 + i2c@1 {
  141 + #address-cells = <1>;
  142 + #size-cells = <0>;
  143 + reg = <1>;
  144 + };
  145 +
  146 + i2c@2 {
  147 + #address-cells = <1>;
  148 + #size-cells = <0>;
  149 + reg = <2>;
  150 + };
  151 +
  152 + i2c@3 {
  153 + #address-cells = <1>;
  154 + #size-cells = <0>;
  155 + reg = <3>;
  156 + };
  157 +
  158 + i2c@4 {
  159 + #address-cells = <1>;
  160 + #size-cells = <0>;
  161 + reg = <4>;
  162 + };
  163 +
  164 + i2c@5 {
  165 + #address-cells = <1>;
  166 + #size-cells = <0>;
  167 + reg = <5>;
  168 + };
  169 +
  170 + i2c@6 { /* Backplane EEPROM */
  171 + #address-cells = <1>;
  172 + #size-cells = <0>;
  173 + reg = <6>;
  174 + eeprom@51 {
  175 + compatible = "atmel,24c01";
  176 + pagesize = <8>;
  177 + reg = <0x51>;
  178 + };
  179 + };
  180 +
  181 + i2c@7 { /* Power board EEPROM */
  182 + #address-cells = <1>;
  183 + #size-cells = <0>;
  184 + reg = <7>;
  185 + eeprom@51 {
  186 + compatible = "atmel,24c01";
  187 + pagesize = <8>;
  188 + reg = <0x51>;
  189 + };
  190 + };
  191 + };
66 192 };
67 193  
  194 +&i2c1 {
  195 + status = "okay";
  196 + clock-frequency = <100000>;
  197 +
  198 + at24@50 {
  199 + compatible = "atmel,24c02";
  200 + pagesize = <8>;
  201 + reg = <0x50>;
  202 + };
  203 +};
  204 +
68 205 &qspi {
69 206 status = "okay";
70   - u-boot,dm-pre-reloc;
71 207  
72   - flash0: n25q128@0 {
73   - u-boot,dm-pre-reloc;
  208 + n25q128@0 {
74 209 #address-cells = <1>;
75 210 #size-cells = <1>;
76   - compatible = "n25q128", "spi-flash";
77   - reg = <0>; /* chip select */
78   - spi-max-frequency = <50000000>;
  211 + compatible = "n25q128";
  212 + reg = <0>; /* chip select */
  213 + spi-max-frequency = <100000000>;
79 214 m25p,fast-read;
80   - page-size = <256>;
81   - block-size = <16>; /* 2^16, 64KB */
  215 +
  216 + cdns,page-size = <256>;
  217 + cdns,block-size = <16>;
  218 + cdns,read-delay = <4>;
82 219 cdns,tshsl-ns = <50>;
83 220 cdns,tsd2d-ns = <50>;
84 221 cdns,tchsh-ns = <4>;
85 222 cdns,tslch-ns = <4>;
86 223 };
87 224  
88   - flash1: n25q00@1 {
89   - u-boot,dm-pre-reloc;
  225 + n25q00@1 {
90 226 #address-cells = <1>;
91 227 #size-cells = <1>;
92   - compatible = "n25q00", "spi-flash";
93   - reg = <1>; /* chip select */
94   - spi-max-frequency = <50000000>;
  228 + compatible = "n25q00";
  229 + reg = <1>; /* chip select */
  230 + spi-max-frequency = <100000000>;
95 231 m25p,fast-read;
96   - page-size = <256>;
97   - block-size = <16>; /* 2^16, 64KB */
  232 +
  233 + cdns,page-size = <256>;
  234 + cdns,block-size = <16>;
  235 + cdns,read-delay = <4>;
98 236 cdns,tshsl-ns = <50>;
99 237 cdns,tsd2d-ns = <50>;
100 238 cdns,tchsh-ns = <4>;
101 239  
102 240  
... ... @@ -103,14 +241,12 @@
103 241 };
104 242  
105 243 &usb0 {
  244 + dr_mode = "host";
106 245 status = "okay";
107 246 };
108 247  
109 248 &usb1 {
  249 + dr_mode = "peripheral";
110 250 status = "okay";
111   -};
112   -
113   -&uart0 {
114   - u-boot,dm-pre-reloc;
115 251 };