Commit 952caa289ee10c7426d28e37bb3130e95a6d6431
1 parent
a665b051b5
Exists in
v2017.01-smarct4x
and in
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arm: socfpga: Add support for Terasic SoCkit board
Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>
Showing 12 changed files with 1622 additions and 0 deletions Side-by-side Diff
- arch/arm/dts/Makefile
- arch/arm/dts/socfpga_cyclone5_sockit.dts
- arch/arm/mach-socfpga/Kconfig
- board/terasic/sockit/MAINTAINERS
- board/terasic/sockit/Makefile
- board/terasic/sockit/qts/iocsr_config.h
- board/terasic/sockit/qts/pinmux_config.h
- board/terasic/sockit/qts/pll_config.h
- board/terasic/sockit/qts/sdram_config.h
- board/terasic/sockit/socfpga.c
- configs/socfpga_sockit_defconfig
- include/configs/socfpga_sockit.h
arch/arm/dts/Makefile
| ... | ... | @@ -61,6 +61,7 @@ |
| 61 | 61 | dtb-$(CONFIG_ARCH_SOCFPGA) += \ |
| 62 | 62 | socfpga_arria5_socdk.dtb \ |
| 63 | 63 | socfpga_cyclone5_socdk.dtb \ |
| 64 | + socfpga_cyclone5_sockit.dtb \ | |
| 64 | 65 | socfpga_cyclone5_socrates.dtb |
| 65 | 66 | dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb |
| 66 | 67 | dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb |
arch/arm/dts/socfpga_cyclone5_sockit.dts
| 1 | +/* | |
| 2 | + * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#include "socfpga_cyclone5.dtsi" | |
| 8 | + | |
| 9 | +/ { | |
| 10 | + model = "Terasic SoCkit"; | |
| 11 | + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; | |
| 12 | + | |
| 13 | + chosen { | |
| 14 | + bootargs = "console=ttyS0,115200"; | |
| 15 | + }; | |
| 16 | + | |
| 17 | + aliases { | |
| 18 | + ethernet0 = &gmac1; | |
| 19 | + }; | |
| 20 | + | |
| 21 | + memory { | |
| 22 | + name = "memory"; | |
| 23 | + device_type = "memory"; | |
| 24 | + reg = <0x0 0x40000000>; /* 1GB */ | |
| 25 | + }; | |
| 26 | + | |
| 27 | + soc { | |
| 28 | + u-boot,dm-pre-reloc; | |
| 29 | + }; | |
| 30 | +}; | |
| 31 | + | |
| 32 | +&gmac1 { | |
| 33 | + status = "okay"; | |
| 34 | + phy-mode = "rgmii"; | |
| 35 | + | |
| 36 | + rxd0-skew-ps = <0>; | |
| 37 | + rxd1-skew-ps = <0>; | |
| 38 | + rxd2-skew-ps = <0>; | |
| 39 | + rxd3-skew-ps = <0>; | |
| 40 | + txen-skew-ps = <0>; | |
| 41 | + txc-skew-ps = <2600>; | |
| 42 | + rxdv-skew-ps = <0>; | |
| 43 | + rxc-skew-ps = <2000>; | |
| 44 | +}; | |
| 45 | + | |
| 46 | +&gpio0 { | |
| 47 | + status = "okay"; | |
| 48 | +}; | |
| 49 | + | |
| 50 | +&gpio1 { | |
| 51 | + status = "okay"; | |
| 52 | +}; | |
| 53 | + | |
| 54 | +&gpio2 { | |
| 55 | + status = "okay"; | |
| 56 | +}; | |
| 57 | + | |
| 58 | +&i2c0 { | |
| 59 | + status = "okay"; | |
| 60 | + | |
| 61 | + rtc: rtc@68 { | |
| 62 | + compatible = "stm,m41t82"; | |
| 63 | + reg = <0x68>; | |
| 64 | + }; | |
| 65 | +}; | |
| 66 | + | |
| 67 | +&mmc0 { | |
| 68 | + status = "okay"; | |
| 69 | + u-boot,dm-pre-reloc; | |
| 70 | +}; | |
| 71 | + | |
| 72 | +&qspi { | |
| 73 | + status = "okay"; | |
| 74 | + u-boot,dm-pre-reloc; | |
| 75 | + | |
| 76 | + flash0: n25q00@0 { | |
| 77 | + u-boot,dm-pre-reloc; | |
| 78 | + #address-cells = <1>; | |
| 79 | + #size-cells = <1>; | |
| 80 | + compatible = "n25q00", "spi-flash"; | |
| 81 | + reg = <0>; /* chip select */ | |
| 82 | + spi-max-frequency = <50000000>; | |
| 83 | + m25p,fast-read; | |
| 84 | + page-size = <256>; | |
| 85 | + block-size = <16>; /* 2^16, 64KB */ | |
| 86 | + read-delay = <4>; /* delay value in read data capture register */ | |
| 87 | + tshsl-ns = <50>; | |
| 88 | + tsd2d-ns = <50>; | |
| 89 | + tchsh-ns = <4>; | |
| 90 | + tslch-ns = <4>; | |
| 91 | + }; | |
| 92 | +}; |
arch/arm/mach-socfpga/Kconfig
| ... | ... | @@ -18,15 +18,21 @@ |
| 18 | 18 | bool "Altera SOCFPGA SoCDK (Cyclone V)" |
| 19 | 19 | select TARGET_SOCFPGA_CYCLONE5 |
| 20 | 20 | |
| 21 | +config TARGET_SOCFPGA_TERASIC_SOCKIT | |
| 22 | + bool "Terasic SoCkit (Cyclone V)" | |
| 23 | + select TARGET_SOCFPGA_CYCLONE5 | |
| 24 | + | |
| 21 | 25 | endchoice |
| 22 | 26 | |
| 23 | 27 | config SYS_BOARD |
| 24 | 28 | default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 25 | 29 | default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK |
| 30 | + default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT | |
| 26 | 31 | |
| 27 | 32 | config SYS_VENDOR |
| 28 | 33 | default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 29 | 34 | default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK |
| 35 | + default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT | |
| 30 | 36 | |
| 31 | 37 | config SYS_SOC |
| 32 | 38 | default "socfpga" |
| ... | ... | @@ -34,6 +40,7 @@ |
| 34 | 40 | config SYS_CONFIG_NAME |
| 35 | 41 | default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 36 | 42 | default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK |
| 43 | + default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT | |
| 37 | 44 | |
| 38 | 45 | endif |
board/terasic/sockit/MAINTAINERS
board/terasic/sockit/Makefile
board/terasic/sockit/qts/iocsr_config.h
| 1 | +/* | |
| 2 | + * Altera SoCFPGA IOCSR configuration | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: BSD-3-Clause | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ | |
| 8 | +#define __SOCFPGA_IOCSR_CONFIG_H__ | |
| 9 | + | |
| 10 | +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 | |
| 11 | +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 | |
| 12 | +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 | |
| 13 | +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 | |
| 14 | + | |
| 15 | +const unsigned long iocsr_scan_chain0_table[] = { | |
| 16 | + 0x00000000, | |
| 17 | + 0x00000000, | |
| 18 | + 0x0FF00000, | |
| 19 | + 0xC0000000, | |
| 20 | + 0x0000003F, | |
| 21 | + 0x00008000, | |
| 22 | + 0x00060180, | |
| 23 | + 0x18060000, | |
| 24 | + 0x18000000, | |
| 25 | + 0x00018060, | |
| 26 | + 0x00000000, | |
| 27 | + 0x00004000, | |
| 28 | + 0x000300C0, | |
| 29 | + 0x0C030000, | |
| 30 | + 0x0C000000, | |
| 31 | + 0x00000030, | |
| 32 | + 0x0000C030, | |
| 33 | + 0x00002000, | |
| 34 | + 0x00018060, | |
| 35 | + 0x06018000, | |
| 36 | + 0x06000000, | |
| 37 | + 0x00000018, | |
| 38 | + 0x00006018, | |
| 39 | + 0x00001000, | |
| 40 | +}; | |
| 41 | + | |
| 42 | +const unsigned long iocsr_scan_chain1_table[] = { | |
| 43 | + 0x00100000, | |
| 44 | + 0x300C0000, | |
| 45 | + 0x300000C0, | |
| 46 | + 0x000000C0, | |
| 47 | + 0x000300C0, | |
| 48 | + 0x00008000, | |
| 49 | + 0x00080000, | |
| 50 | + 0x20000000, | |
| 51 | + 0x00000000, | |
| 52 | + 0x00000080, | |
| 53 | + 0x00020000, | |
| 54 | + 0x00004000, | |
| 55 | + 0x000300C0, | |
| 56 | + 0x10000000, | |
| 57 | + 0x0C000000, | |
| 58 | + 0x00000030, | |
| 59 | + 0x0000C030, | |
| 60 | + 0x00002000, | |
| 61 | + 0x06018060, | |
| 62 | + 0x06018000, | |
| 63 | + 0x01FE0000, | |
| 64 | + 0xF8000000, | |
| 65 | + 0x00000007, | |
| 66 | + 0x00001000, | |
| 67 | + 0x0000C030, | |
| 68 | + 0x0300C000, | |
| 69 | + 0x03000000, | |
| 70 | + 0x0000300C, | |
| 71 | + 0x0000300C, | |
| 72 | + 0x00000800, | |
| 73 | + 0x00000000, | |
| 74 | + 0x00000000, | |
| 75 | + 0x01800000, | |
| 76 | + 0x00000006, | |
| 77 | + 0x00002000, | |
| 78 | + 0x00000400, | |
| 79 | + 0x00000000, | |
| 80 | + 0x00C03000, | |
| 81 | + 0x00000003, | |
| 82 | + 0x00000000, | |
| 83 | + 0x00000000, | |
| 84 | + 0x00000200, | |
| 85 | + 0x00601806, | |
| 86 | + 0x00000000, | |
| 87 | + 0x80600000, | |
| 88 | + 0x80000601, | |
| 89 | + 0x00000601, | |
| 90 | + 0x00000100, | |
| 91 | + 0x00300C03, | |
| 92 | + 0xC0300C00, | |
| 93 | + 0xC0300000, | |
| 94 | + 0xC0000300, | |
| 95 | + 0x000C0300, | |
| 96 | + 0x00000080, | |
| 97 | +}; | |
| 98 | + | |
| 99 | +const unsigned long iocsr_scan_chain2_table[] = { | |
| 100 | + 0x300C0300, | |
| 101 | + 0x00000000, | |
| 102 | + 0x0FF00000, | |
| 103 | + 0x00000000, | |
| 104 | + 0x0C0300C0, | |
| 105 | + 0x00008000, | |
| 106 | + 0x18060180, | |
| 107 | + 0x18060000, | |
| 108 | + 0x18000000, | |
| 109 | + 0x00018060, | |
| 110 | + 0x00018060, | |
| 111 | + 0x00004000, | |
| 112 | + 0x000300C0, | |
| 113 | + 0x0C030000, | |
| 114 | + 0x00000030, | |
| 115 | + 0x00000000, | |
| 116 | + 0x0300C030, | |
| 117 | + 0x00002000, | |
| 118 | + 0x00018060, | |
| 119 | + 0x06018000, | |
| 120 | + 0x06000000, | |
| 121 | + 0x00000018, | |
| 122 | + 0x00006018, | |
| 123 | + 0x00001000, | |
| 124 | + 0x0000C030, | |
| 125 | + 0x00000000, | |
| 126 | + 0x03000000, | |
| 127 | + 0x0000000C, | |
| 128 | + 0x00C0300C, | |
| 129 | + 0x00000800, | |
| 130 | +}; | |
| 131 | + | |
| 132 | +const unsigned long iocsr_scan_chain3_table[] = { | |
| 133 | + 0x0C420D80, | |
| 134 | + 0x082000FF, | |
| 135 | + 0x0A804001, | |
| 136 | + 0x07900000, | |
| 137 | + 0x08020000, | |
| 138 | + 0x00100000, | |
| 139 | + 0x0A800000, | |
| 140 | + 0x07900000, | |
| 141 | + 0x08020000, | |
| 142 | + 0x00100000, | |
| 143 | + 0xC8800000, | |
| 144 | + 0x00003001, | |
| 145 | + 0x00C00722, | |
| 146 | + 0x00000000, | |
| 147 | + 0x00000021, | |
| 148 | + 0x82000004, | |
| 149 | + 0x05400000, | |
| 150 | + 0x03C80000, | |
| 151 | + 0x04010000, | |
| 152 | + 0x00080000, | |
| 153 | + 0x05400000, | |
| 154 | + 0x03C80000, | |
| 155 | + 0x05400000, | |
| 156 | + 0x03C80000, | |
| 157 | + 0xE4400000, | |
| 158 | + 0x00001800, | |
| 159 | + 0x00600391, | |
| 160 | + 0x800E4400, | |
| 161 | + 0x00000001, | |
| 162 | + 0x40000002, | |
| 163 | + 0x02A00000, | |
| 164 | + 0x01E40000, | |
| 165 | + 0x02A00000, | |
| 166 | + 0x01E40000, | |
| 167 | + 0x02A00000, | |
| 168 | + 0x01E40000, | |
| 169 | + 0x02A00000, | |
| 170 | + 0x01E40000, | |
| 171 | + 0x72200000, | |
| 172 | + 0x80000C00, | |
| 173 | + 0x003001C8, | |
| 174 | + 0xC0072200, | |
| 175 | + 0x1C880000, | |
| 176 | + 0x20000300, | |
| 177 | + 0x00040000, | |
| 178 | + 0x50670000, | |
| 179 | + 0x00000010, | |
| 180 | + 0x24590000, | |
| 181 | + 0x00001000, | |
| 182 | + 0xA0000034, | |
| 183 | + 0x0D000001, | |
| 184 | + 0x40680208, | |
| 185 | + 0x41034051, | |
| 186 | + 0x12481A00, | |
| 187 | + 0x802080D0, | |
| 188 | + 0x34051406, | |
| 189 | + 0x01A02490, | |
| 190 | + 0x080D0000, | |
| 191 | + 0x51406802, | |
| 192 | + 0x02490340, | |
| 193 | + 0xD000001A, | |
| 194 | + 0x0680A280, | |
| 195 | + 0x10040000, | |
| 196 | + 0x00200000, | |
| 197 | + 0x10040000, | |
| 198 | + 0x00200000, | |
| 199 | + 0x15000000, | |
| 200 | + 0x0F200000, | |
| 201 | + 0x15000000, | |
| 202 | + 0x0F200000, | |
| 203 | + 0x01FE0000, | |
| 204 | + 0x00000000, | |
| 205 | + 0x01800E44, | |
| 206 | + 0x00391000, | |
| 207 | + 0x007F8006, | |
| 208 | + 0x00000000, | |
| 209 | + 0x0A800001, | |
| 210 | + 0x07900000, | |
| 211 | + 0x0A800000, | |
| 212 | + 0x07900000, | |
| 213 | + 0x0A800000, | |
| 214 | + 0x07900000, | |
| 215 | + 0x08020000, | |
| 216 | + 0x00100000, | |
| 217 | + 0xC8800000, | |
| 218 | + 0x00003001, | |
| 219 | + 0x00C00722, | |
| 220 | + 0x00000FF0, | |
| 221 | + 0x72200000, | |
| 222 | + 0x80000C00, | |
| 223 | + 0x05400000, | |
| 224 | + 0x02480000, | |
| 225 | + 0x04000000, | |
| 226 | + 0x00080000, | |
| 227 | + 0x05400000, | |
| 228 | + 0x03C80000, | |
| 229 | + 0x05400000, | |
| 230 | + 0x03C80000, | |
| 231 | + 0x6A1C0000, | |
| 232 | + 0x00001800, | |
| 233 | + 0x00600391, | |
| 234 | + 0x800E4400, | |
| 235 | + 0x1A870001, | |
| 236 | + 0x40000600, | |
| 237 | + 0x02A00040, | |
| 238 | + 0x01E40000, | |
| 239 | + 0x02A00000, | |
| 240 | + 0x01E40000, | |
| 241 | + 0x02A00000, | |
| 242 | + 0x01E40000, | |
| 243 | + 0x02A00000, | |
| 244 | + 0x01E40000, | |
| 245 | + 0x72200000, | |
| 246 | + 0x80000C00, | |
| 247 | + 0x003001C8, | |
| 248 | + 0xC0072200, | |
| 249 | + 0x1C880000, | |
| 250 | + 0x20000300, | |
| 251 | + 0x00040000, | |
| 252 | + 0x50670000, | |
| 253 | + 0x00000010, | |
| 254 | + 0x24590000, | |
| 255 | + 0x00001000, | |
| 256 | + 0xA0000034, | |
| 257 | + 0x0D000001, | |
| 258 | + 0x40680208, | |
| 259 | + 0x49034051, | |
| 260 | + 0x12481A02, | |
| 261 | + 0x80A280D0, | |
| 262 | + 0x34030C06, | |
| 263 | + 0x01A00040, | |
| 264 | + 0x280D0002, | |
| 265 | + 0x5140680A, | |
| 266 | + 0x02490340, | |
| 267 | + 0xD012481A, | |
| 268 | + 0x0680A280, | |
| 269 | + 0x10040000, | |
| 270 | + 0x00200000, | |
| 271 | + 0x10040000, | |
| 272 | + 0x00200000, | |
| 273 | + 0x15000000, | |
| 274 | + 0x0F200000, | |
| 275 | + 0x15000000, | |
| 276 | + 0x0F200000, | |
| 277 | + 0x01FE0000, | |
| 278 | + 0x00000000, | |
| 279 | + 0x01800E44, | |
| 280 | + 0x00391000, | |
| 281 | + 0x007F8006, | |
| 282 | + 0x00000000, | |
| 283 | + 0x99300001, | |
| 284 | + 0x34343400, | |
| 285 | + 0xAA0D4000, | |
| 286 | + 0x01C3A800, | |
| 287 | + 0xAA0D4000, | |
| 288 | + 0x01C3A800, | |
| 289 | + 0xAA0D4000, | |
| 290 | + 0x01C3A800, | |
| 291 | + 0x00040100, | |
| 292 | + 0x00000800, | |
| 293 | + 0x00000000, | |
| 294 | + 0x00001208, | |
| 295 | + 0x00482000, | |
| 296 | + 0x01000000, | |
| 297 | + 0x00000000, | |
| 298 | + 0x00410482, | |
| 299 | + 0x0006A000, | |
| 300 | + 0x0001B400, | |
| 301 | + 0x00020000, | |
| 302 | + 0x00000400, | |
| 303 | + 0x0002A000, | |
| 304 | + 0x0001E400, | |
| 305 | + 0x5506A000, | |
| 306 | + 0x00E1D400, | |
| 307 | + 0x00000000, | |
| 308 | + 0xC880090C, | |
| 309 | + 0x00003001, | |
| 310 | + 0x90400000, | |
| 311 | + 0x00000000, | |
| 312 | + 0x2020C243, | |
| 313 | + 0x2A835000, | |
| 314 | + 0x0070EA00, | |
| 315 | + 0x2A835000, | |
| 316 | + 0x0070EA00, | |
| 317 | + 0x2A835000, | |
| 318 | + 0x0070EA00, | |
| 319 | + 0x00010040, | |
| 320 | + 0x00000200, | |
| 321 | + 0x00000000, | |
| 322 | + 0x00000482, | |
| 323 | + 0x00120800, | |
| 324 | + 0x00002000, | |
| 325 | + 0x80000000, | |
| 326 | + 0x00104120, | |
| 327 | + 0x00000200, | |
| 328 | + 0xAC0D5F80, | |
| 329 | + 0xFFFFFFFF, | |
| 330 | + 0x14F3690D, | |
| 331 | + 0x1A041414, | |
| 332 | + 0x00D00000, | |
| 333 | + 0x04864000, | |
| 334 | + 0x59647A01, | |
| 335 | + 0xD32CA3DE, | |
| 336 | + 0xF551451E, | |
| 337 | + 0x034CD348, | |
| 338 | + 0x821A0000, | |
| 339 | + 0x0000D000, | |
| 340 | + 0x05140680, | |
| 341 | + 0xD669A47A, | |
| 342 | + 0x1ED32CA3, | |
| 343 | + 0x48F55E79, | |
| 344 | + 0x00034C92, | |
| 345 | + 0x00080200, | |
| 346 | + 0x00001000, | |
| 347 | + 0x00080200, | |
| 348 | + 0x00001000, | |
| 349 | + 0x000A8000, | |
| 350 | + 0x00075000, | |
| 351 | + 0x541A8000, | |
| 352 | + 0x03875001, | |
| 353 | + 0x10000000, | |
| 354 | + 0x00000000, | |
| 355 | + 0x0080C000, | |
| 356 | + 0x41000000, | |
| 357 | + 0x00003FC2, | |
| 358 | + 0x00820000, | |
| 359 | + 0xAA0D4000, | |
| 360 | + 0x01C3A800, | |
| 361 | + 0xAA0D4000, | |
| 362 | + 0x01C3A800, | |
| 363 | + 0xAA0D4000, | |
| 364 | + 0x01C3A800, | |
| 365 | + 0x00040100, | |
| 366 | + 0x00000800, | |
| 367 | + 0x00000000, | |
| 368 | + 0x00001208, | |
| 369 | + 0x00482000, | |
| 370 | + 0x00008000, | |
| 371 | + 0x00000000, | |
| 372 | + 0x00410482, | |
| 373 | + 0x0006A000, | |
| 374 | + 0x0001B400, | |
| 375 | + 0x00020000, | |
| 376 | + 0x00000400, | |
| 377 | + 0x00020080, | |
| 378 | + 0x00000400, | |
| 379 | + 0x5506A000, | |
| 380 | + 0x00E1D400, | |
| 381 | + 0x00000000, | |
| 382 | + 0x0000090C, | |
| 383 | + 0x00000010, | |
| 384 | + 0x90400000, | |
| 385 | + 0x00000000, | |
| 386 | + 0x2020C243, | |
| 387 | + 0x2A835000, | |
| 388 | + 0x0070EA00, | |
| 389 | + 0x2A835000, | |
| 390 | + 0x0070EA00, | |
| 391 | + 0x2A835000, | |
| 392 | + 0x0070EA00, | |
| 393 | + 0x00015000, | |
| 394 | + 0x0000F200, | |
| 395 | + 0x00000000, | |
| 396 | + 0x00000482, | |
| 397 | + 0x00120800, | |
| 398 | + 0x00600391, | |
| 399 | + 0x80000000, | |
| 400 | + 0x00104120, | |
| 401 | + 0x00000200, | |
| 402 | + 0xAC0D5F80, | |
| 403 | + 0xFFFFFFFF, | |
| 404 | + 0x14F3690D, | |
| 405 | + 0x1A041414, | |
| 406 | + 0x00D00000, | |
| 407 | + 0x14864000, | |
| 408 | + 0x59647A05, | |
| 409 | + 0x9228A3DE, | |
| 410 | + 0xF65E791E, | |
| 411 | + 0x034CD348, | |
| 412 | + 0x821A0186, | |
| 413 | + 0x0000D000, | |
| 414 | + 0x00000680, | |
| 415 | + 0xD669A47A, | |
| 416 | + 0x1E9228A3, | |
| 417 | + 0x48F65E79, | |
| 418 | + 0x00034CD3, | |
| 419 | + 0x00080200, | |
| 420 | + 0x00001000, | |
| 421 | + 0x00080200, | |
| 422 | + 0x00001000, | |
| 423 | + 0x000A8000, | |
| 424 | + 0x00075000, | |
| 425 | + 0x541A8000, | |
| 426 | + 0x03875001, | |
| 427 | + 0x10000000, | |
| 428 | + 0x00000000, | |
| 429 | + 0x0080C000, | |
| 430 | + 0x41000000, | |
| 431 | + 0x04000002, | |
| 432 | + 0x00820000, | |
| 433 | + 0xAA0D4000, | |
| 434 | + 0x01C3A800, | |
| 435 | + 0xAA0D4000, | |
| 436 | + 0x01C3A800, | |
| 437 | + 0xAA0D4000, | |
| 438 | + 0x01C3A800, | |
| 439 | + 0x00040100, | |
| 440 | + 0x00000800, | |
| 441 | + 0x00000000, | |
| 442 | + 0x00001208, | |
| 443 | + 0x00482000, | |
| 444 | + 0x00008000, | |
| 445 | + 0x00000000, | |
| 446 | + 0x00410482, | |
| 447 | + 0x0006A000, | |
| 448 | + 0x0001B400, | |
| 449 | + 0x00020000, | |
| 450 | + 0x00000400, | |
| 451 | + 0x0002A000, | |
| 452 | + 0x0001E400, | |
| 453 | + 0x5506A000, | |
| 454 | + 0x00E1D400, | |
| 455 | + 0x00000000, | |
| 456 | + 0xC880090C, | |
| 457 | + 0x00003001, | |
| 458 | + 0x90400000, | |
| 459 | + 0x00000000, | |
| 460 | + 0x2020C243, | |
| 461 | + 0x2A835000, | |
| 462 | + 0x0070EA00, | |
| 463 | + 0x2A835000, | |
| 464 | + 0x0070EA00, | |
| 465 | + 0x2A835000, | |
| 466 | + 0x0070EA00, | |
| 467 | + 0x00010040, | |
| 468 | + 0x00000200, | |
| 469 | + 0x00000000, | |
| 470 | + 0x00000482, | |
| 471 | + 0x00120800, | |
| 472 | + 0x00002000, | |
| 473 | + 0x80000000, | |
| 474 | + 0x00104120, | |
| 475 | + 0x00000200, | |
| 476 | + 0xAC0D5F80, | |
| 477 | + 0xFFFFFFFF, | |
| 478 | + 0x14F3690D, | |
| 479 | + 0x1A041414, | |
| 480 | + 0x00D00000, | |
| 481 | + 0x0C864000, | |
| 482 | + 0x79E47A03, | |
| 483 | + 0xB2AAA3D1, | |
| 484 | + 0xF551451E, | |
| 485 | + 0x035CD348, | |
| 486 | + 0x821A0000, | |
| 487 | + 0x0000D000, | |
| 488 | + 0x00000680, | |
| 489 | + 0xD159647A, | |
| 490 | + 0x1ED32CA3, | |
| 491 | + 0x48F55145, | |
| 492 | + 0x00035CD3, | |
| 493 | + 0x00080200, | |
| 494 | + 0x00001000, | |
| 495 | + 0x00080200, | |
| 496 | + 0x00001000, | |
| 497 | + 0x000A8000, | |
| 498 | + 0x00075000, | |
| 499 | + 0x541A8000, | |
| 500 | + 0x03875001, | |
| 501 | + 0x10000000, | |
| 502 | + 0x00000000, | |
| 503 | + 0x0080C000, | |
| 504 | + 0x41000000, | |
| 505 | + 0x04000002, | |
| 506 | + 0x00820000, | |
| 507 | + 0xAA0D4000, | |
| 508 | + 0x01C3A800, | |
| 509 | + 0xAA0D4000, | |
| 510 | + 0x01C3A800, | |
| 511 | + 0xAA0D4000, | |
| 512 | + 0x01C3A800, | |
| 513 | + 0x00040100, | |
| 514 | + 0x00000800, | |
| 515 | + 0x00000000, | |
| 516 | + 0x00001208, | |
| 517 | + 0x00482000, | |
| 518 | + 0x00008000, | |
| 519 | + 0x00000000, | |
| 520 | + 0x00410482, | |
| 521 | + 0x0006A000, | |
| 522 | + 0x0001B400, | |
| 523 | + 0x00020000, | |
| 524 | + 0x00000400, | |
| 525 | + 0x00020080, | |
| 526 | + 0x00000400, | |
| 527 | + 0x5506A000, | |
| 528 | + 0x00E1D400, | |
| 529 | + 0x00000000, | |
| 530 | + 0x0000090C, | |
| 531 | + 0x00000010, | |
| 532 | + 0x90400000, | |
| 533 | + 0x00000000, | |
| 534 | + 0x2020C243, | |
| 535 | + 0x2A835000, | |
| 536 | + 0x0070EA00, | |
| 537 | + 0x2A835000, | |
| 538 | + 0x0070EA00, | |
| 539 | + 0x2A835000, | |
| 540 | + 0x0070EA00, | |
| 541 | + 0x00010040, | |
| 542 | + 0x00000200, | |
| 543 | + 0x00000000, | |
| 544 | + 0x00000482, | |
| 545 | + 0x00120800, | |
| 546 | + 0x00400000, | |
| 547 | + 0x80000000, | |
| 548 | + 0x00104120, | |
| 549 | + 0x00000200, | |
| 550 | + 0xAC0D5F80, | |
| 551 | + 0xFFFFFFFF, | |
| 552 | + 0x14F1690D, | |
| 553 | + 0x1A041414, | |
| 554 | + 0x00D00000, | |
| 555 | + 0x04864000, | |
| 556 | + 0x69A47A01, | |
| 557 | + 0x9228A3D6, | |
| 558 | + 0xF65E791E, | |
| 559 | + 0x034C9248, | |
| 560 | + 0x821A0000, | |
| 561 | + 0x0000D000, | |
| 562 | + 0x00000680, | |
| 563 | + 0xDE59647A, | |
| 564 | + 0x1ED32CA3, | |
| 565 | + 0x48F55E79, | |
| 566 | + 0x00034CD3, | |
| 567 | + 0x00080200, | |
| 568 | + 0x00001000, | |
| 569 | + 0x00080200, | |
| 570 | + 0x00001000, | |
| 571 | + 0x000A8000, | |
| 572 | + 0x00075000, | |
| 573 | + 0x541A8000, | |
| 574 | + 0x03875001, | |
| 575 | + 0x10000000, | |
| 576 | + 0x00000000, | |
| 577 | + 0x0080C000, | |
| 578 | + 0x41000000, | |
| 579 | + 0x04000002, | |
| 580 | + 0x00820000, | |
| 581 | + 0x00489800, | |
| 582 | + 0x801A1A1A, | |
| 583 | + 0x00000200, | |
| 584 | + 0x80000004, | |
| 585 | + 0x00000200, | |
| 586 | + 0x80000004, | |
| 587 | + 0x00000200, | |
| 588 | + 0x80000004, | |
| 589 | + 0x00000200, | |
| 590 | + 0x00000004, | |
| 591 | + 0x00040000, | |
| 592 | + 0x10000000, | |
| 593 | + 0x00000000, | |
| 594 | + 0x00000040, | |
| 595 | + 0x00010000, | |
| 596 | + 0x40002000, | |
| 597 | + 0x00000100, | |
| 598 | + 0x40000002, | |
| 599 | + 0x00000100, | |
| 600 | + 0x40000002, | |
| 601 | + 0x00000100, | |
| 602 | + 0x40000002, | |
| 603 | + 0x00000100, | |
| 604 | + 0x00000002, | |
| 605 | + 0x00020000, | |
| 606 | + 0x08000000, | |
| 607 | + 0x00000000, | |
| 608 | + 0x00000020, | |
| 609 | + 0x00008000, | |
| 610 | + 0x20001000, | |
| 611 | + 0x00000080, | |
| 612 | + 0x20000001, | |
| 613 | + 0x00000080, | |
| 614 | + 0x20000001, | |
| 615 | + 0x00000080, | |
| 616 | + 0x20000001, | |
| 617 | + 0x00000080, | |
| 618 | + 0x00000001, | |
| 619 | + 0x00010000, | |
| 620 | + 0x04000000, | |
| 621 | + 0x00FF0000, | |
| 622 | + 0x00000000, | |
| 623 | + 0x00004000, | |
| 624 | + 0x00000800, | |
| 625 | + 0xC0000001, | |
| 626 | + 0x00041419, | |
| 627 | + 0x40000000, | |
| 628 | + 0x04000816, | |
| 629 | + 0x000D0000, | |
| 630 | + 0x00006800, | |
| 631 | + 0x00000340, | |
| 632 | + 0xD000001A, | |
| 633 | + 0x06800000, | |
| 634 | + 0x00340000, | |
| 635 | + 0x0001A000, | |
| 636 | + 0x00000D00, | |
| 637 | + 0x40000068, | |
| 638 | + 0x1A000003, | |
| 639 | + 0x00D00000, | |
| 640 | + 0x00068000, | |
| 641 | + 0x00003400, | |
| 642 | + 0x000001A0, | |
| 643 | + 0x00000401, | |
| 644 | + 0x00000008, | |
| 645 | + 0x00000401, | |
| 646 | + 0x00000008, | |
| 647 | + 0x00000401, | |
| 648 | + 0x00000008, | |
| 649 | + 0x00000401, | |
| 650 | + 0x80000008, | |
| 651 | + 0x0000007F, | |
| 652 | + 0x20000000, | |
| 653 | + 0x00000000, | |
| 654 | + 0xE0000080, | |
| 655 | + 0x0000001F, | |
| 656 | + 0x00004000, | |
| 657 | +}; | |
| 658 | + | |
| 659 | + | |
| 660 | +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ |
board/terasic/sockit/qts/pinmux_config.h
| 1 | +/* | |
| 2 | + * Altera SoCFPGA PinMux configuration | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: BSD-3-Clause | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ | |
| 8 | +#define __SOCFPGA_PINMUX_CONFIG_H__ | |
| 9 | + | |
| 10 | +const u8 sys_mgr_init_table[] = { | |
| 11 | + 0, /* EMACIO0 */ | |
| 12 | + 2, /* EMACIO1 */ | |
| 13 | + 2, /* EMACIO2 */ | |
| 14 | + 2, /* EMACIO3 */ | |
| 15 | + 2, /* EMACIO4 */ | |
| 16 | + 2, /* EMACIO5 */ | |
| 17 | + 2, /* EMACIO6 */ | |
| 18 | + 2, /* EMACIO7 */ | |
| 19 | + 2, /* EMACIO8 */ | |
| 20 | + 0, /* EMACIO9 */ | |
| 21 | + 2, /* EMACIO10 */ | |
| 22 | + 2, /* EMACIO11 */ | |
| 23 | + 2, /* EMACIO12 */ | |
| 24 | + 2, /* EMACIO13 */ | |
| 25 | + 0, /* EMACIO14 */ | |
| 26 | + 0, /* EMACIO15 */ | |
| 27 | + 0, /* EMACIO16 */ | |
| 28 | + 0, /* EMACIO17 */ | |
| 29 | + 0, /* EMACIO18 */ | |
| 30 | + 0, /* EMACIO19 */ | |
| 31 | + 3, /* FLASHIO0 */ | |
| 32 | + 0, /* FLASHIO1 */ | |
| 33 | + 3, /* FLASHIO2 */ | |
| 34 | + 3, /* FLASHIO3 */ | |
| 35 | + 0, /* FLASHIO4 */ | |
| 36 | + 0, /* FLASHIO5 */ | |
| 37 | + 0, /* FLASHIO6 */ | |
| 38 | + 0, /* FLASHIO7 */ | |
| 39 | + 0, /* FLASHIO8 */ | |
| 40 | + 3, /* FLASHIO9 */ | |
| 41 | + 3, /* FLASHIO10 */ | |
| 42 | + 3, /* FLASHIO11 */ | |
| 43 | + 0, /* GENERALIO0 */ | |
| 44 | + 1, /* GENERALIO1 */ | |
| 45 | + 1, /* GENERALIO2 */ | |
| 46 | + 1, /* GENERALIO3 */ | |
| 47 | + 1, /* GENERALIO4 */ | |
| 48 | + 0, /* GENERALIO5 */ | |
| 49 | + 0, /* GENERALIO6 */ | |
| 50 | + 0, /* GENERALIO7 */ | |
| 51 | + 0, /* GENERALIO8 */ | |
| 52 | + 3, /* GENERALIO9 */ | |
| 53 | + 3, /* GENERALIO10 */ | |
| 54 | + 3, /* GENERALIO11 */ | |
| 55 | + 3, /* GENERALIO12 */ | |
| 56 | + 0, /* GENERALIO13 */ | |
| 57 | + 0, /* GENERALIO14 */ | |
| 58 | + 1, /* GENERALIO15 */ | |
| 59 | + 1, /* GENERALIO16 */ | |
| 60 | + 1, /* GENERALIO17 */ | |
| 61 | + 1, /* GENERALIO18 */ | |
| 62 | + 0, /* GENERALIO19 */ | |
| 63 | + 0, /* GENERALIO20 */ | |
| 64 | + 0, /* GENERALIO21 */ | |
| 65 | + 0, /* GENERALIO22 */ | |
| 66 | + 0, /* GENERALIO23 */ | |
| 67 | + 0, /* GENERALIO24 */ | |
| 68 | + 0, /* GENERALIO25 */ | |
| 69 | + 0, /* GENERALIO26 */ | |
| 70 | + 0, /* GENERALIO27 */ | |
| 71 | + 0, /* GENERALIO28 */ | |
| 72 | + 0, /* GENERALIO29 */ | |
| 73 | + 0, /* GENERALIO30 */ | |
| 74 | + 0, /* GENERALIO31 */ | |
| 75 | + 2, /* MIXED1IO0 */ | |
| 76 | + 2, /* MIXED1IO1 */ | |
| 77 | + 2, /* MIXED1IO2 */ | |
| 78 | + 2, /* MIXED1IO3 */ | |
| 79 | + 2, /* MIXED1IO4 */ | |
| 80 | + 2, /* MIXED1IO5 */ | |
| 81 | + 2, /* MIXED1IO6 */ | |
| 82 | + 2, /* MIXED1IO7 */ | |
| 83 | + 2, /* MIXED1IO8 */ | |
| 84 | + 2, /* MIXED1IO9 */ | |
| 85 | + 2, /* MIXED1IO10 */ | |
| 86 | + 2, /* MIXED1IO11 */ | |
| 87 | + 2, /* MIXED1IO12 */ | |
| 88 | + 2, /* MIXED1IO13 */ | |
| 89 | + 0, /* MIXED1IO14 */ | |
| 90 | + 3, /* MIXED1IO15 */ | |
| 91 | + 3, /* MIXED1IO16 */ | |
| 92 | + 3, /* MIXED1IO17 */ | |
| 93 | + 3, /* MIXED1IO18 */ | |
| 94 | + 3, /* MIXED1IO19 */ | |
| 95 | + 3, /* MIXED1IO20 */ | |
| 96 | + 0, /* MIXED1IO21 */ | |
| 97 | + 0, /* MIXED2IO0 */ | |
| 98 | + 0, /* MIXED2IO1 */ | |
| 99 | + 0, /* MIXED2IO2 */ | |
| 100 | + 0, /* MIXED2IO3 */ | |
| 101 | + 0, /* MIXED2IO4 */ | |
| 102 | + 0, /* MIXED2IO5 */ | |
| 103 | + 0, /* MIXED2IO6 */ | |
| 104 | + 0, /* MIXED2IO7 */ | |
| 105 | + 0, /* GPLINMUX48 */ | |
| 106 | + 0, /* GPLINMUX49 */ | |
| 107 | + 0, /* GPLINMUX50 */ | |
| 108 | + 0, /* GPLINMUX51 */ | |
| 109 | + 0, /* GPLINMUX52 */ | |
| 110 | + 0, /* GPLINMUX53 */ | |
| 111 | + 0, /* GPLINMUX54 */ | |
| 112 | + 0, /* GPLINMUX55 */ | |
| 113 | + 0, /* GPLINMUX56 */ | |
| 114 | + 0, /* GPLINMUX57 */ | |
| 115 | + 0, /* GPLINMUX58 */ | |
| 116 | + 0, /* GPLINMUX59 */ | |
| 117 | + 0, /* GPLINMUX60 */ | |
| 118 | + 0, /* GPLINMUX61 */ | |
| 119 | + 0, /* GPLINMUX62 */ | |
| 120 | + 0, /* GPLINMUX63 */ | |
| 121 | + 0, /* GPLINMUX64 */ | |
| 122 | + 0, /* GPLINMUX65 */ | |
| 123 | + 0, /* GPLINMUX66 */ | |
| 124 | + 0, /* GPLINMUX67 */ | |
| 125 | + 0, /* GPLINMUX68 */ | |
| 126 | + 0, /* GPLINMUX69 */ | |
| 127 | + 0, /* GPLINMUX70 */ | |
| 128 | + 1, /* GPLMUX0 */ | |
| 129 | + 1, /* GPLMUX1 */ | |
| 130 | + 1, /* GPLMUX2 */ | |
| 131 | + 1, /* GPLMUX3 */ | |
| 132 | + 1, /* GPLMUX4 */ | |
| 133 | + 1, /* GPLMUX5 */ | |
| 134 | + 1, /* GPLMUX6 */ | |
| 135 | + 1, /* GPLMUX7 */ | |
| 136 | + 1, /* GPLMUX8 */ | |
| 137 | + 1, /* GPLMUX9 */ | |
| 138 | + 1, /* GPLMUX10 */ | |
| 139 | + 1, /* GPLMUX11 */ | |
| 140 | + 1, /* GPLMUX12 */ | |
| 141 | + 1, /* GPLMUX13 */ | |
| 142 | + 1, /* GPLMUX14 */ | |
| 143 | + 1, /* GPLMUX15 */ | |
| 144 | + 1, /* GPLMUX16 */ | |
| 145 | + 1, /* GPLMUX17 */ | |
| 146 | + 1, /* GPLMUX18 */ | |
| 147 | + 1, /* GPLMUX19 */ | |
| 148 | + 1, /* GPLMUX20 */ | |
| 149 | + 1, /* GPLMUX21 */ | |
| 150 | + 1, /* GPLMUX22 */ | |
| 151 | + 1, /* GPLMUX23 */ | |
| 152 | + 1, /* GPLMUX24 */ | |
| 153 | + 1, /* GPLMUX25 */ | |
| 154 | + 1, /* GPLMUX26 */ | |
| 155 | + 1, /* GPLMUX27 */ | |
| 156 | + 1, /* GPLMUX28 */ | |
| 157 | + 1, /* GPLMUX29 */ | |
| 158 | + 1, /* GPLMUX30 */ | |
| 159 | + 1, /* GPLMUX31 */ | |
| 160 | + 1, /* GPLMUX32 */ | |
| 161 | + 1, /* GPLMUX33 */ | |
| 162 | + 1, /* GPLMUX34 */ | |
| 163 | + 1, /* GPLMUX35 */ | |
| 164 | + 1, /* GPLMUX36 */ | |
| 165 | + 1, /* GPLMUX37 */ | |
| 166 | + 1, /* GPLMUX38 */ | |
| 167 | + 1, /* GPLMUX39 */ | |
| 168 | + 1, /* GPLMUX40 */ | |
| 169 | + 1, /* GPLMUX41 */ | |
| 170 | + 1, /* GPLMUX42 */ | |
| 171 | + 1, /* GPLMUX43 */ | |
| 172 | + 1, /* GPLMUX44 */ | |
| 173 | + 1, /* GPLMUX45 */ | |
| 174 | + 1, /* GPLMUX46 */ | |
| 175 | + 1, /* GPLMUX47 */ | |
| 176 | + 1, /* GPLMUX48 */ | |
| 177 | + 1, /* GPLMUX49 */ | |
| 178 | + 1, /* GPLMUX50 */ | |
| 179 | + 1, /* GPLMUX51 */ | |
| 180 | + 1, /* GPLMUX52 */ | |
| 181 | + 1, /* GPLMUX53 */ | |
| 182 | + 1, /* GPLMUX54 */ | |
| 183 | + 1, /* GPLMUX55 */ | |
| 184 | + 1, /* GPLMUX56 */ | |
| 185 | + 1, /* GPLMUX57 */ | |
| 186 | + 1, /* GPLMUX58 */ | |
| 187 | + 1, /* GPLMUX59 */ | |
| 188 | + 1, /* GPLMUX60 */ | |
| 189 | + 1, /* GPLMUX61 */ | |
| 190 | + 1, /* GPLMUX62 */ | |
| 191 | + 1, /* GPLMUX63 */ | |
| 192 | + 1, /* GPLMUX64 */ | |
| 193 | + 1, /* GPLMUX65 */ | |
| 194 | + 1, /* GPLMUX66 */ | |
| 195 | + 1, /* GPLMUX67 */ | |
| 196 | + 1, /* GPLMUX68 */ | |
| 197 | + 1, /* GPLMUX69 */ | |
| 198 | + 1, /* GPLMUX70 */ | |
| 199 | + 0, /* NANDUSEFPGA */ | |
| 200 | + 0, /* UART0USEFPGA */ | |
| 201 | + 0, /* RGMII1USEFPGA */ | |
| 202 | + 0, /* SPIS0USEFPGA */ | |
| 203 | + 0, /* CAN0USEFPGA */ | |
| 204 | + 0, /* I2C0USEFPGA */ | |
| 205 | + 0, /* SDMMCUSEFPGA */ | |
| 206 | + 0, /* QSPIUSEFPGA */ | |
| 207 | + 0, /* SPIS1USEFPGA */ | |
| 208 | + 0, /* RGMII0USEFPGA */ | |
| 209 | + 0, /* UART1USEFPGA */ | |
| 210 | + 0, /* CAN1USEFPGA */ | |
| 211 | + 0, /* USB1USEFPGA */ | |
| 212 | + 0, /* I2C3USEFPGA */ | |
| 213 | + 0, /* I2C2USEFPGA */ | |
| 214 | + 0, /* I2C1USEFPGA */ | |
| 215 | + 0, /* SPIM1USEFPGA */ | |
| 216 | + 0, /* USB0USEFPGA */ | |
| 217 | + 0 /* SPIM0USEFPGA */ | |
| 218 | +}; | |
| 219 | +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ |
board/terasic/sockit/qts/pll_config.h
| 1 | +/* | |
| 2 | + * Altera SoCFPGA Clock and PLL configuration | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: BSD-3-Clause | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#ifndef __SOCFPGA_PLL_CONFIG_H__ | |
| 8 | +#define __SOCFPGA_PLL_CONFIG_H__ | |
| 9 | + | |
| 10 | +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 | |
| 11 | + | |
| 12 | +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 | |
| 13 | +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73 | |
| 14 | +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 | |
| 15 | +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 | |
| 16 | +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 | |
| 17 | +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 | |
| 18 | +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 | |
| 19 | +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 | |
| 20 | +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 | |
| 21 | +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 | |
| 22 | +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 | |
| 23 | +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 | |
| 24 | +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 | |
| 25 | +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 | |
| 26 | +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 | |
| 27 | +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 | |
| 28 | +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 | |
| 29 | + | |
| 30 | +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 | |
| 31 | +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 | |
| 32 | +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 | |
| 33 | +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 | |
| 34 | +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 | |
| 35 | +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 | |
| 36 | +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 | |
| 37 | +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 | |
| 38 | +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 | |
| 39 | +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 | |
| 40 | +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 | |
| 41 | +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 | |
| 42 | +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 | |
| 43 | +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 | |
| 44 | +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 | |
| 45 | +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 | |
| 46 | +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 | |
| 47 | + | |
| 48 | +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 | |
| 49 | +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 | |
| 50 | +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 | |
| 51 | +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 | |
| 52 | +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 | |
| 53 | +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 | |
| 54 | +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 | |
| 55 | +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 | |
| 56 | +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 | |
| 57 | +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 | |
| 58 | +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 | |
| 59 | + | |
| 60 | +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 | |
| 61 | +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 | |
| 62 | +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 | |
| 63 | +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 | |
| 64 | +#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000 | |
| 65 | +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 | |
| 66 | +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 | |
| 67 | +#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 | |
| 68 | +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 | |
| 69 | +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 | |
| 70 | +#define CONFIG_HPS_CLK_NAND_HZ 50000000 | |
| 71 | +#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 | |
| 72 | +#define CONFIG_HPS_CLK_QSPI_HZ 370000000 | |
| 73 | +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 | |
| 74 | +#define CONFIG_HPS_CLK_CAN0_HZ 12500000 | |
| 75 | +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 | |
| 76 | +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 | |
| 77 | +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 | |
| 78 | +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 | |
| 79 | + | |
| 80 | +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 | |
| 81 | +#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 | |
| 82 | +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 | |
| 83 | + | |
| 84 | + | |
| 85 | +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ |
board/terasic/sockit/qts/sdram_config.h
| 1 | +/* | |
| 2 | + * Altera SoCFPGA SDRAM configuration | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: BSD-3-Clause | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ | |
| 8 | +#define __SOCFPGA_SDRAM_CONFIG_H__ | |
| 9 | + | |
| 10 | +/* SDRAM configuration */ | |
| 11 | +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A | |
| 12 | +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 | |
| 13 | +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 | |
| 14 | +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 | |
| 15 | +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 | |
| 16 | +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 | |
| 17 | +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 | |
| 18 | +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 | |
| 19 | +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 | |
| 20 | +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 | |
| 21 | +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 | |
| 22 | +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 | |
| 23 | +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 | |
| 24 | +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 | |
| 25 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 | |
| 26 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 | |
| 27 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 | |
| 28 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 | |
| 29 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 | |
| 30 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 | |
| 31 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 | |
| 32 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 | |
| 33 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 | |
| 34 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 | |
| 35 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 | |
| 36 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 | |
| 37 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 | |
| 38 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 | |
| 39 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 | |
| 40 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 | |
| 41 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 | |
| 42 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 | |
| 43 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 | |
| 44 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 | |
| 45 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 | |
| 46 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 | |
| 47 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 | |
| 48 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 | |
| 49 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 | |
| 50 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 | |
| 51 | +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 | |
| 52 | +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 | |
| 53 | +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 | |
| 54 | +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF | |
| 55 | +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 | |
| 56 | +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 | |
| 57 | +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 | |
| 58 | +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 | |
| 59 | +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 | |
| 60 | +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 | |
| 61 | +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 | |
| 62 | +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 | |
| 63 | +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 | |
| 64 | +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 | |
| 65 | +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 | |
| 66 | +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 | |
| 67 | +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 | |
| 68 | +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 | |
| 69 | +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 | |
| 70 | +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 | |
| 71 | +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 | |
| 72 | +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 | |
| 73 | +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 | |
| 74 | +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 | |
| 75 | +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 | |
| 76 | +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 | |
| 77 | +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 | |
| 78 | + | |
| 79 | +/* Sequencer auto configuration */ | |
| 80 | +#define RW_MGR_ACTIVATE_0_AND_1 0x0D | |
| 81 | +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E | |
| 82 | +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 | |
| 83 | +#define RW_MGR_ACTIVATE_1 0x0F | |
| 84 | +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 | |
| 85 | +#define RW_MGR_GUARANTEED_READ 0x4C | |
| 86 | +#define RW_MGR_GUARANTEED_READ_CONT 0x54 | |
| 87 | +#define RW_MGR_GUARANTEED_WRITE 0x18 | |
| 88 | +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B | |
| 89 | +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F | |
| 90 | +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 | |
| 91 | +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D | |
| 92 | +#define RW_MGR_IDLE 0x00 | |
| 93 | +#define RW_MGR_IDLE_LOOP1 0x7B | |
| 94 | +#define RW_MGR_IDLE_LOOP2 0x7A | |
| 95 | +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F | |
| 96 | +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 | |
| 97 | +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 | |
| 98 | +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 | |
| 99 | +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 | |
| 100 | +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 | |
| 101 | +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 | |
| 102 | +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 | |
| 103 | +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 | |
| 104 | +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 | |
| 105 | +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 | |
| 106 | +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 | |
| 107 | +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 | |
| 108 | +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 | |
| 109 | +#define RW_MGR_MRS0_DLL_RESET 0x02 | |
| 110 | +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 | |
| 111 | +#define RW_MGR_MRS0_USER 0x07 | |
| 112 | +#define RW_MGR_MRS0_USER_MIRR 0x0C | |
| 113 | +#define RW_MGR_MRS1 0x03 | |
| 114 | +#define RW_MGR_MRS1_MIRR 0x09 | |
| 115 | +#define RW_MGR_MRS2 0x04 | |
| 116 | +#define RW_MGR_MRS2_MIRR 0x0A | |
| 117 | +#define RW_MGR_MRS3 0x05 | |
| 118 | +#define RW_MGR_MRS3_MIRR 0x0B | |
| 119 | +#define RW_MGR_PRECHARGE_ALL 0x12 | |
| 120 | +#define RW_MGR_READ_B2B 0x59 | |
| 121 | +#define RW_MGR_READ_B2B_WAIT1 0x61 | |
| 122 | +#define RW_MGR_READ_B2B_WAIT2 0x6B | |
| 123 | +#define RW_MGR_REFRESH_ALL 0x14 | |
| 124 | +#define RW_MGR_RETURN 0x01 | |
| 125 | +#define RW_MGR_SGLE_READ 0x7D | |
| 126 | +#define RW_MGR_ZQCL 0x06 | |
| 127 | + | |
| 128 | +/* Sequencer defines configuration */ | |
| 129 | +#define AFI_RATE_RATIO 1 | |
| 130 | +#define CALIB_LFIFO_OFFSET 8 | |
| 131 | +#define CALIB_VFIFO_OFFSET 6 | |
| 132 | +#define ENABLE_SUPER_QUICK_CALIBRATION 0 | |
| 133 | +#define IO_DELAY_PER_DCHAIN_TAP 25 | |
| 134 | +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 | |
| 135 | +#define IO_DELAY_PER_OPA_TAP 312 | |
| 136 | +#define IO_DLL_CHAIN_LENGTH 8 | |
| 137 | +#define IO_DQDQS_OUT_PHASE_MAX 0 | |
| 138 | +#define IO_DQS_EN_DELAY_MAX 31 | |
| 139 | +#define IO_DQS_EN_DELAY_OFFSET 0 | |
| 140 | +#define IO_DQS_EN_PHASE_MAX 7 | |
| 141 | +#define IO_DQS_IN_DELAY_MAX 31 | |
| 142 | +#define IO_DQS_IN_RESERVE 4 | |
| 143 | +#define IO_DQS_OUT_RESERVE 4 | |
| 144 | +#define IO_IO_IN_DELAY_MAX 31 | |
| 145 | +#define IO_IO_OUT1_DELAY_MAX 31 | |
| 146 | +#define IO_IO_OUT2_DELAY_MAX 0 | |
| 147 | +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 | |
| 148 | +#define MAX_LATENCY_COUNT_WIDTH 5 | |
| 149 | +#define READ_VALID_FIFO_SIZE 16 | |
| 150 | +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d | |
| 151 | +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 | |
| 152 | +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 | |
| 153 | +#define RW_MGR_MEM_DATA_WIDTH 32 | |
| 154 | +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 | |
| 155 | +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 | |
| 156 | +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 | |
| 157 | +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 | |
| 158 | +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 | |
| 159 | +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 | |
| 160 | +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 | |
| 161 | +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 | |
| 162 | +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 | |
| 163 | +#define TINIT_CNTR0_VAL 99 | |
| 164 | +#define TINIT_CNTR1_VAL 32 | |
| 165 | +#define TINIT_CNTR2_VAL 32 | |
| 166 | +#define TRESET_CNTR0_VAL 99 | |
| 167 | +#define TRESET_CNTR1_VAL 99 | |
| 168 | +#define TRESET_CNTR2_VAL 10 | |
| 169 | + | |
| 170 | +/* Sequencer ac_rom_init configuration */ | |
| 171 | +const u32 ac_rom_init[] = { | |
| 172 | + 0x20700000, | |
| 173 | + 0x20780000, | |
| 174 | + 0x10080431, | |
| 175 | + 0x10080530, | |
| 176 | + 0x10090044, | |
| 177 | + 0x100a0008, | |
| 178 | + 0x100b0000, | |
| 179 | + 0x10380400, | |
| 180 | + 0x10080449, | |
| 181 | + 0x100804c8, | |
| 182 | + 0x100a0024, | |
| 183 | + 0x10090010, | |
| 184 | + 0x100b0000, | |
| 185 | + 0x30780000, | |
| 186 | + 0x38780000, | |
| 187 | + 0x30780000, | |
| 188 | + 0x10680000, | |
| 189 | + 0x106b0000, | |
| 190 | + 0x10280400, | |
| 191 | + 0x10480000, | |
| 192 | + 0x1c980000, | |
| 193 | + 0x1c9b0000, | |
| 194 | + 0x1c980008, | |
| 195 | + 0x1c9b0008, | |
| 196 | + 0x38f80000, | |
| 197 | + 0x3cf80000, | |
| 198 | + 0x38780000, | |
| 199 | + 0x18180000, | |
| 200 | + 0x18980000, | |
| 201 | + 0x13580000, | |
| 202 | + 0x135b0000, | |
| 203 | + 0x13580008, | |
| 204 | + 0x135b0008, | |
| 205 | + 0x33780000, | |
| 206 | + 0x10580008, | |
| 207 | + 0x10780000 | |
| 208 | +}; | |
| 209 | + | |
| 210 | +/* Sequencer inst_rom_init configuration */ | |
| 211 | +const u32 inst_rom_init[] = { | |
| 212 | + 0x80000, | |
| 213 | + 0x80680, | |
| 214 | + 0x8180, | |
| 215 | + 0x8200, | |
| 216 | + 0x8280, | |
| 217 | + 0x8300, | |
| 218 | + 0x8380, | |
| 219 | + 0x8100, | |
| 220 | + 0x8480, | |
| 221 | + 0x8500, | |
| 222 | + 0x8580, | |
| 223 | + 0x8600, | |
| 224 | + 0x8400, | |
| 225 | + 0x800, | |
| 226 | + 0x8680, | |
| 227 | + 0x880, | |
| 228 | + 0xa680, | |
| 229 | + 0x80680, | |
| 230 | + 0x900, | |
| 231 | + 0x80680, | |
| 232 | + 0x980, | |
| 233 | + 0xa680, | |
| 234 | + 0x8680, | |
| 235 | + 0x80680, | |
| 236 | + 0xb68, | |
| 237 | + 0xcce8, | |
| 238 | + 0xae8, | |
| 239 | + 0x8ce8, | |
| 240 | + 0xb88, | |
| 241 | + 0xec88, | |
| 242 | + 0xa08, | |
| 243 | + 0xac88, | |
| 244 | + 0x80680, | |
| 245 | + 0xce00, | |
| 246 | + 0xcd80, | |
| 247 | + 0xe700, | |
| 248 | + 0xc00, | |
| 249 | + 0x20ce0, | |
| 250 | + 0x20ce0, | |
| 251 | + 0x20ce0, | |
| 252 | + 0x20ce0, | |
| 253 | + 0xd00, | |
| 254 | + 0x680, | |
| 255 | + 0x680, | |
| 256 | + 0x680, | |
| 257 | + 0x680, | |
| 258 | + 0x60e80, | |
| 259 | + 0x61080, | |
| 260 | + 0x61080, | |
| 261 | + 0x61080, | |
| 262 | + 0xa680, | |
| 263 | + 0x8680, | |
| 264 | + 0x80680, | |
| 265 | + 0xce00, | |
| 266 | + 0xcd80, | |
| 267 | + 0xe700, | |
| 268 | + 0xc00, | |
| 269 | + 0x30ce0, | |
| 270 | + 0x30ce0, | |
| 271 | + 0x30ce0, | |
| 272 | + 0x30ce0, | |
| 273 | + 0xd00, | |
| 274 | + 0x680, | |
| 275 | + 0x680, | |
| 276 | + 0x680, | |
| 277 | + 0x680, | |
| 278 | + 0x70e80, | |
| 279 | + 0x71080, | |
| 280 | + 0x71080, | |
| 281 | + 0x71080, | |
| 282 | + 0xa680, | |
| 283 | + 0x8680, | |
| 284 | + 0x80680, | |
| 285 | + 0x1158, | |
| 286 | + 0x6d8, | |
| 287 | + 0x80680, | |
| 288 | + 0x1168, | |
| 289 | + 0x7e8, | |
| 290 | + 0x7e8, | |
| 291 | + 0x87e8, | |
| 292 | + 0x40fe8, | |
| 293 | + 0x410e8, | |
| 294 | + 0x410e8, | |
| 295 | + 0x410e8, | |
| 296 | + 0x1168, | |
| 297 | + 0x7e8, | |
| 298 | + 0x7e8, | |
| 299 | + 0xa7e8, | |
| 300 | + 0x80680, | |
| 301 | + 0x40e88, | |
| 302 | + 0x41088, | |
| 303 | + 0x41088, | |
| 304 | + 0x41088, | |
| 305 | + 0x40f68, | |
| 306 | + 0x410e8, | |
| 307 | + 0x410e8, | |
| 308 | + 0x410e8, | |
| 309 | + 0xa680, | |
| 310 | + 0x40fe8, | |
| 311 | + 0x410e8, | |
| 312 | + 0x410e8, | |
| 313 | + 0x410e8, | |
| 314 | + 0x41008, | |
| 315 | + 0x41088, | |
| 316 | + 0x41088, | |
| 317 | + 0x41088, | |
| 318 | + 0x1100, | |
| 319 | + 0xc680, | |
| 320 | + 0x8680, | |
| 321 | + 0xe680, | |
| 322 | + 0x80680, | |
| 323 | + 0x0, | |
| 324 | + 0x8000, | |
| 325 | + 0xa000, | |
| 326 | + 0xc000, | |
| 327 | + 0x80000, | |
| 328 | + 0x80, | |
| 329 | + 0x8080, | |
| 330 | + 0xa080, | |
| 331 | + 0xc080, | |
| 332 | + 0x80080, | |
| 333 | + 0x9180, | |
| 334 | + 0x8680, | |
| 335 | + 0xa680, | |
| 336 | + 0x80680, | |
| 337 | + 0x40f08, | |
| 338 | + 0x80680 | |
| 339 | +}; | |
| 340 | + | |
| 341 | +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ |
board/terasic/sockit/socfpga.c
| 1 | +/* | |
| 2 | + * Copyright (C) 2012 Altera Corporation <www.altera.com> | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#include <common.h> | |
| 8 | +#include <asm/arch/reset_manager.h> | |
| 9 | +#include <asm/io.h> | |
| 10 | + | |
| 11 | +#include <usb.h> | |
| 12 | +#include <usb/s3c_udc.h> | |
| 13 | +#include <usb_mass_storage.h> | |
| 14 | + | |
| 15 | +#include <micrel.h> | |
| 16 | +#include <netdev.h> | |
| 17 | +#include <phy.h> | |
| 18 | + | |
| 19 | +DECLARE_GLOBAL_DATA_PTR; | |
| 20 | + | |
| 21 | +void s_init(void) {} | |
| 22 | + | |
| 23 | +/* | |
| 24 | + * Miscellaneous platform dependent initialisations | |
| 25 | + */ | |
| 26 | +int board_init(void) | |
| 27 | +{ | |
| 28 | + /* Address of boot parameters for ATAG (if ATAG is used) */ | |
| 29 | + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; | |
| 30 | + | |
| 31 | + return 0; | |
| 32 | +} | |
| 33 | + | |
| 34 | +/* | |
| 35 | + * PHY configuration | |
| 36 | + */ | |
| 37 | +#ifdef CONFIG_PHY_MICREL_KSZ9021 | |
| 38 | +int board_phy_config(struct phy_device *phydev) | |
| 39 | +{ | |
| 40 | + int ret; | |
| 41 | + /* | |
| 42 | + * These skew settings for the KSZ9021 ethernet phy is required for ethernet | |
| 43 | + * to work reliably on most flavors of cyclone5 boards. | |
| 44 | + */ | |
| 45 | + ret = ksz9021_phy_extended_write(phydev, | |
| 46 | + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, | |
| 47 | + 0x0); | |
| 48 | + if (ret) | |
| 49 | + return ret; | |
| 50 | + | |
| 51 | + ret = ksz9021_phy_extended_write(phydev, | |
| 52 | + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, | |
| 53 | + 0x0); | |
| 54 | + if (ret) | |
| 55 | + return ret; | |
| 56 | + | |
| 57 | + ret = ksz9021_phy_extended_write(phydev, | |
| 58 | + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, | |
| 59 | + 0xf0f0); | |
| 60 | + if (ret) | |
| 61 | + return ret; | |
| 62 | + | |
| 63 | + if (phydev->drv->config) | |
| 64 | + return phydev->drv->config(phydev); | |
| 65 | + | |
| 66 | + return 0; | |
| 67 | +} | |
| 68 | +#endif | |
| 69 | + | |
| 70 | +#ifdef CONFIG_USB_GADGET | |
| 71 | +struct s3c_plat_otg_data socfpga_otg_data = { | |
| 72 | + .regs_otg = CONFIG_USB_DWC2_REG_ADDR, | |
| 73 | + .usb_gusbcfg = 0x1417, | |
| 74 | +}; | |
| 75 | + | |
| 76 | +int board_usb_init(int index, enum usb_init_type init) | |
| 77 | +{ | |
| 78 | + return s3c_udc_probe(&socfpga_otg_data); | |
| 79 | +} | |
| 80 | + | |
| 81 | +int g_dnl_board_usb_cable_connected(void) | |
| 82 | +{ | |
| 83 | + return 1; | |
| 84 | +} | |
| 85 | +#endif |
configs/socfpga_sockit_defconfig
| 1 | +CONFIG_ARM=y | |
| 2 | +CONFIG_ARCH_SOCFPGA=y | |
| 3 | +CONFIG_TARGET_SOCFPGA_CYCLONE5=y | |
| 4 | +CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y | |
| 5 | +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit" | |
| 6 | +CONFIG_SPL=y | |
| 7 | +# CONFIG_CMD_IMLS is not set | |
| 8 | +# CONFIG_CMD_FLASH is not set | |
| 9 | +CONFIG_OF_CONTROL=y | |
| 10 | +CONFIG_SPI_FLASH=y | |
| 11 | +CONFIG_SPI_FLASH_USE_4K_SECTORS=n | |
| 12 | +CONFIG_DM_ETH=y | |
| 13 | +CONFIG_NETDEVICES=y | |
| 14 | +CONFIG_ETH_DESIGNWARE=y | |
| 15 | +CONFIG_DM_GPIO=y | |
| 16 | +CONFIG_DWAPB_GPIO=y | |
| 17 | +CONFIG_SPL_DM=y | |
| 18 | +CONFIG_SPL_MMC_SUPPORT=y | |
| 19 | +CONFIG_DM_SEQ_ALIAS=y | |
| 20 | +CONFIG_SPL_SIMPLE_BUS=y | |
| 21 | +CONFIG_DM_SPI=y | |
| 22 | +CONFIG_DM_SPI_FLASH=y | |
| 23 | +CONFIG_SPL_SPI_SUPPORT=y | |
| 24 | +CONFIG_SPL_STACK_R=y | |
| 25 | +CONFIG_SPL_STACK_R_ADDR=0x00800000 | |
| 26 | +CONFIG_SYS_MALLOC_F_LEN=0x2000 |
include/configs/socfpga_sockit.h
| 1 | +/* | |
| 2 | + * Copyright (C) 2015 Marek Vasut <marex@denx.de> | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | + */ | |
| 6 | +#ifndef __CONFIG_TERASIC_SOCKIT_H__ | |
| 7 | +#define __CONFIG_TERASIC_SOCKIT_H__ | |
| 8 | + | |
| 9 | +#include <asm/arch/socfpga_base_addrs.h> | |
| 10 | + | |
| 11 | +/* U-Boot Commands */ | |
| 12 | +#define CONFIG_SYS_NO_FLASH | |
| 13 | +#define CONFIG_DOS_PARTITION | |
| 14 | +#define CONFIG_FAT_WRITE | |
| 15 | +#define CONFIG_HW_WATCHDOG | |
| 16 | + | |
| 17 | +#define CONFIG_CMD_ASKENV | |
| 18 | +#define CONFIG_CMD_BOOTZ | |
| 19 | +#define CONFIG_CMD_CACHE | |
| 20 | +#define CONFIG_CMD_DFU | |
| 21 | +#define CONFIG_CMD_DHCP | |
| 22 | +#define CONFIG_CMD_EXT4 | |
| 23 | +#define CONFIG_CMD_EXT4_WRITE | |
| 24 | +#define CONFIG_CMD_FAT | |
| 25 | +#define CONFIG_CMD_FS_GENERIC | |
| 26 | +#define CONFIG_CMD_GPIO | |
| 27 | +#define CONFIG_CMD_GREPENV | |
| 28 | +#define CONFIG_CMD_MII | |
| 29 | +#define CONFIG_CMD_MMC | |
| 30 | +#define CONFIG_CMD_PING | |
| 31 | +#define CONFIG_CMD_USB | |
| 32 | +#define CONFIG_CMD_USB_MASS_STORAGE | |
| 33 | + | |
| 34 | +/* Memory configurations */ | |
| 35 | +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ | |
| 36 | + | |
| 37 | +/* Booting Linux */ | |
| 38 | +#define CONFIG_BOOTDELAY 3 | |
| 39 | +#define CONFIG_BOOTFILE "fitImage" | |
| 40 | +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) | |
| 41 | +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | |
| 42 | +#define CONFIG_BOOTCOMMAND "run ramboot" | |
| 43 | +#else | |
| 44 | +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" | |
| 45 | +#endif | |
| 46 | +#define CONFIG_LOADADDR 0x01000000 | |
| 47 | +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
| 48 | + | |
| 49 | +/* Ethernet on SoC (EMAC) */ | |
| 50 | +#if defined(CONFIG_CMD_NET) | |
| 51 | + | |
| 52 | +/* PHY */ | |
| 53 | +#define CONFIG_PHY_MICREL | |
| 54 | +#define CONFIG_PHY_MICREL_KSZ9021 | |
| 55 | +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" | |
| 56 | +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 | |
| 57 | +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" | |
| 58 | +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 | |
| 59 | + | |
| 60 | +#endif | |
| 61 | + | |
| 62 | +/* USB */ | |
| 63 | +#ifdef CONFIG_CMD_USB | |
| 64 | +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS | |
| 65 | +#endif | |
| 66 | +#define CONFIG_G_DNL_MANUFACTURER "Terasic" | |
| 67 | + | |
| 68 | +/* Extra Environment */ | |
| 69 | +#define CONFIG_HOSTNAME socfpga_sockit | |
| 70 | + | |
| 71 | +#define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 72 | + "verify=n\0" \ | |
| 73 | + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ | |
| 74 | + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ | |
| 75 | + "bootm ${loadaddr} - ${fdt_addr}\0" \ | |
| 76 | + "bootimage=zImage\0" \ | |
| 77 | + "fdt_addr=100\0" \ | |
| 78 | + "fdtimage=socfpga.dtb\0" \ | |
| 79 | + "fsloadcmd=ext2load\0" \ | |
| 80 | + "bootm ${loadaddr} - ${fdt_addr}\0" \ | |
| 81 | + "mmcroot=/dev/mmcblk0p2\0" \ | |
| 82 | + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ | |
| 83 | + " root=${mmcroot} rw rootwait;" \ | |
| 84 | + "bootz ${loadaddr} - ${fdt_addr}\0" \ | |
| 85 | + "mmcload=mmc rescan;" \ | |
| 86 | + "load mmc 0:1 ${loadaddr} ${bootimage};" \ | |
| 87 | + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ | |
| 88 | + | |
| 89 | +/* The rest of the configuration is shared */ | |
| 90 | +#include <configs/socfpga_common.h> | |
| 91 | + | |
| 92 | +#endif /* __CONFIG_TERASIC_SOCKIT_H__ */ |