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board/ti/am43xx/board.c
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/* * board.c * * Board functions for TI AM43XX based boards * * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> |
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#include <i2c.h> #include <asm/errno.h> |
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#include <spl.h> |
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#include <usb.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/sys_proto.h> #include <asm/arch/mux.h> |
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#include <asm/arch/ddr_defs.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/emif.h> |
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#include "board.h" |
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#include <power/pmic.h> |
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#include <power/tps65218.h> |
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#include <power/tps62362.h> |
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#include <miiphy.h> #include <cpsw.h> |
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#include <linux/usb/gadget.h> #include <dwc3-uboot.h> #include <dwc3-omap-uboot.h> #include <ti-usb-phy-uboot.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
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/* * Read header information from EEPROM into global structure. */ static int read_eeprom(struct am43xx_board_id *header) { /* Check if baseboard eeprom is available */ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { printf("Could not probe the EEPROM at 0x%x ", CONFIG_SYS_I2C_EEPROM_ADDR); return -ENODEV; } /* read the eeprom using i2c */ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, sizeof(struct am43xx_board_id))) { printf("Could not read the EEPROM "); return -EIO; } if (header->magic != 0xEE3355AA) { /* * read the eeprom using i2c again, * but use only a 1 byte address */ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, sizeof(struct am43xx_board_id))) { printf("Could not read the EEPROM at 0x%x ", CONFIG_SYS_I2C_EEPROM_ADDR); return -EIO; } if (header->magic != 0xEE3355AA) { printf("Incorrect magic number (0x%x) in EEPROM ", header->magic); return -EINVAL; } } strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); am43xx_board_name[sizeof(header->name)] = 0; |
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strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version)); am43xx_board_rev[sizeof(header->version)] = 0; |
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return 0; } |
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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#define NUM_OPPS 6 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { { /* 19.2 MHz */ |
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{125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ |
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ |
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{125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ |
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}, { /* 24 MHz */ {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ }, { /* 25 MHz */ {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ }, { /* 26 MHz */ {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ }, }; const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { |
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{625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ |
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{1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ }; const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { |
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{400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ |
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{384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ |
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{480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ |
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}; |
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const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ }; |
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const struct dpll_params gp_evm_dpll_ddr = { |
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50, 2, 1, -1, 2, -1, -1}; |
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static const struct dpll_params idk_dpll_ddr = { 400, 23, 1, -1, 2, -1, -1 }; |
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static const u32 ext_phy_ctrl_const_base_lpddr2[] = { 0x00500050, 0x00350035, 0x00350035, 0x00350035, 0x00350035, 0x00350035, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40001000, 0x08102040 }; |
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const struct ctrl_ioregs ioregs_lpddr2 = { .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, .emif_sdram_config_ext = 0x1, }; const struct emif_regs emif_regs_lpddr2 = { .sdram_config = 0x808012BA, .ref_ctrl = 0x0000040D, .sdram_tim1 = 0xEA86B411, .sdram_tim2 = 0x103A094A, .sdram_tim3 = 0x0F6BA37F, .read_idle_ctrl = 0x00050000, .zq_config = 0x50074BE4, .temp_alert_config = 0x0, .emif_rd_wr_lvl_rmp_win = 0x0, .emif_rd_wr_lvl_rmp_ctl = 0x0, .emif_rd_wr_lvl_ctl = 0x0, |
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.emif_ddr_phy_ctlr_1 = 0x0E284006, |
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.emif_rd_wr_exec_thresh = 0x80000405, |
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.emif_ddr_ext_phy_ctrl_1 = 0x04010040, .emif_ddr_ext_phy_ctrl_2 = 0x00500050, .emif_ddr_ext_phy_ctrl_3 = 0x00500050, .emif_ddr_ext_phy_ctrl_4 = 0x00500050, |
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.emif_ddr_ext_phy_ctrl_5 = 0x00500050, .emif_prio_class_serv_map = 0x80000001, .emif_connect_id_serv_1_map = 0x80000094, .emif_connect_id_serv_2_map = 0x00000000, .emif_cos_config = 0x000FFFFF |
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}; |
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const struct ctrl_ioregs ioregs_ddr3 = { .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, |
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.emif_sdram_config_ext = 0xc163, |
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}; const struct emif_regs ddr3_emif_regs_400Mhz = { .sdram_config = 0x638413B2, .ref_ctrl = 0x00000C30, .sdram_tim1 = 0xEAAAD4DB, .sdram_tim2 = 0x266B7FDA, .sdram_tim3 = 0x107F8678, .read_idle_ctrl = 0x00050000, .zq_config = 0x50074BE4, .temp_alert_config = 0x0, |
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.emif_ddr_phy_ctlr_1 = 0x0E004008, |
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.emif_ddr_ext_phy_ctrl_1 = 0x08020080, .emif_ddr_ext_phy_ctrl_2 = 0x00400040, .emif_ddr_ext_phy_ctrl_3 = 0x00400040, .emif_ddr_ext_phy_ctrl_4 = 0x00400040, .emif_ddr_ext_phy_ctrl_5 = 0x00400040, .emif_rd_wr_lvl_rmp_win = 0x0, .emif_rd_wr_lvl_rmp_ctl = 0x0, .emif_rd_wr_lvl_ctl = 0x0, |
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.emif_rd_wr_exec_thresh = 0x80000405, .emif_prio_class_serv_map = 0x80000001, .emif_connect_id_serv_1_map = 0x80000094, .emif_connect_id_serv_2_map = 0x00000000, .emif_cos_config = 0x000FFFFF |
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}; |
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/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ const struct emif_regs ddr3_emif_regs_400Mhz_beta = { .sdram_config = 0x638413B2, .ref_ctrl = 0x00000C30, .sdram_tim1 = 0xEAAAD4DB, .sdram_tim2 = 0x266B7FDA, .sdram_tim3 = 0x107F8678, .read_idle_ctrl = 0x00050000, .zq_config = 0x50074BE4, .temp_alert_config = 0x0, .emif_ddr_phy_ctlr_1 = 0x0E004008, .emif_ddr_ext_phy_ctrl_1 = 0x08020080, .emif_ddr_ext_phy_ctrl_2 = 0x00000065, .emif_ddr_ext_phy_ctrl_3 = 0x00000091, .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, |
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.emif_rd_wr_exec_thresh = 0x80000405, .emif_prio_class_serv_map = 0x80000001, .emif_connect_id_serv_1_map = 0x80000094, .emif_connect_id_serv_2_map = 0x00000000, .emif_cos_config = 0x000FFFFF |
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}; /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ const struct emif_regs ddr3_emif_regs_400Mhz_production = { .sdram_config = 0x638413B2, .ref_ctrl = 0x00000C30, .sdram_tim1 = 0xEAAAD4DB, .sdram_tim2 = 0x266B7FDA, .sdram_tim3 = 0x107F8678, .read_idle_ctrl = 0x00050000, .zq_config = 0x50074BE4, .temp_alert_config = 0x0, .emif_ddr_phy_ctlr_1 = 0x0E004008, .emif_ddr_ext_phy_ctrl_1 = 0x08020080, .emif_ddr_ext_phy_ctrl_2 = 0x00000066, .emif_ddr_ext_phy_ctrl_3 = 0x00000091, .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, |
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.emif_rd_wr_exec_thresh = 0x80000405, .emif_prio_class_serv_map = 0x80000001, .emif_connect_id_serv_1_map = 0x80000094, .emif_connect_id_serv_2_map = 0x00000000, .emif_cos_config = 0x000FFFFF |
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}; |
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static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { .sdram_config = 0x638413b2, .sdram_config2 = 0x00000000, .ref_ctrl = 0x00000c30, .sdram_tim1 = 0xeaaad4db, .sdram_tim2 = 0x266b7fda, .sdram_tim3 = 0x107f8678, .read_idle_ctrl = 0x00050000, .zq_config = 0x50074be4, .temp_alert_config = 0x0, .emif_ddr_phy_ctlr_1 = 0x0e084008, .emif_ddr_ext_phy_ctrl_1 = 0x08020080, .emif_ddr_ext_phy_ctrl_2 = 0x89, .emif_ddr_ext_phy_ctrl_3 = 0x90, .emif_ddr_ext_phy_ctrl_4 = 0x8e, .emif_ddr_ext_phy_ctrl_5 = 0x8d, .emif_rd_wr_lvl_rmp_win = 0x0, .emif_rd_wr_lvl_rmp_ctl = 0x00000000, .emif_rd_wr_lvl_ctl = 0x00000000, |
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.emif_rd_wr_exec_thresh = 0x80000000, .emif_prio_class_serv_map = 0x80000001, .emif_connect_id_serv_1_map = 0x80000094, .emif_connect_id_serv_2_map = 0x00000000, .emif_cos_config = 0x000FFFFF |
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}; |
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static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { .sdram_config = 0x61a11b32, .sdram_config2 = 0x00000000, .ref_ctrl = 0x00000c30, .sdram_tim1 = 0xeaaad4db, .sdram_tim2 = 0x266b7fda, .sdram_tim3 = 0x107f8678, .read_idle_ctrl = 0x00050000, .zq_config = 0x50074be4, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1 = 0x00008009, .emif_ddr_ext_phy_ctrl_1 = 0x08020080, .emif_ddr_ext_phy_ctrl_2 = 0x00000040, .emif_ddr_ext_phy_ctrl_3 = 0x0000003e, .emif_ddr_ext_phy_ctrl_4 = 0x00000051, .emif_ddr_ext_phy_ctrl_5 = 0x00000051, .emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x00000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000405, .emif_prio_class_serv_map = 0x00000000, .emif_connect_id_serv_1_map = 0x00000000, .emif_connect_id_serv_2_map = 0x00000000, .emif_cos_config = 0x00ffffff }; |
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void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) { if (board_is_eposevm()) { *regs = ext_phy_ctrl_const_base_lpddr2; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); } return; } |
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/* * get_sys_clk_index : returns the index of the sys_clk read from * ctrl status register. This value is either * read from efuse or sysboot pins. */ static u32 get_sys_clk_index(void) { struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; u32 ind = readl(&ctrl->statusreg), src; src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); else /* Value read from SYS BOOT pins */ return ((ind & CTRL_SYSBOOT_15_14_MASK) >> CTRL_SYSBOOT_15_14_SHIFT); } |
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const struct dpll_params *get_dpll_ddr_params(void) { int ind = get_sys_clk_index(); if (board_is_eposevm()) return &epos_evm_dpll_ddr[ind]; else if (board_is_gpevm() || board_is_sk()) return &gp_evm_dpll_ddr; |
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else if (board_is_idk()) return &idk_dpll_ddr; |
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printf(" Board '%s' not supported ", am43xx_board_name); return NULL; } |
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/* * get_opp_offset: * Returns the index for safest OPP of the device to boot. * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. * This data is read from dev_attribute register which is e-fused. * A'1' in bit indicates OPP disabled and not available, a '0' indicates * OPP available. Lowest OPP starts with min_off. So returning the * bit with rightmost '0'. */ static int get_opp_offset(int max_off, int min_off) { struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; |
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int opp, offset, i; /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; |
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for (i = max_off; i >= min_off; i--) { offset = opp & (1 << i); if (!offset) return i; } return min_off; } const struct dpll_params *get_dpll_mpu_params(void) { int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); u32 ind = get_sys_clk_index(); return &dpll_mpu[ind][opp]; } const struct dpll_params *get_dpll_core_params(void) { int ind = get_sys_clk_index(); return &dpll_core[ind]; } const struct dpll_params *get_dpll_per_params(void) { int ind = get_sys_clk_index(); return &dpll_per[ind]; |
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} |
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void scale_vcores_generic(u32 m) |
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{ |
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int mpu_vdd; |
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if (i2c_probe(TPS65218_CHIP_PM)) return; |
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switch (m) { |
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case 1000: |
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mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; |
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break; |
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case 800: mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; break; case 720: mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; break; |
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case 600: |
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mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; |
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break; |
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case 300: mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; break; |
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default: |
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puts("Unknown MPU clock, not scaling "); return; } /* Set DCDC1 (CORE) voltage to 1.1V */ if (tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV)) { |
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printf("%s failure ", __func__); |
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return; } /* Set DCDC2 (MPU) voltage */ if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { |
403d70abd board: ti: am43xx... |
464 465 |
printf("%s failure ", __func__); |
83bad1026 arm:am43xx: Add T... |
466 467 468 |
return; } } |
403d70abd board: ti: am43xx... |
469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 |
void scale_vcores_idk(u32 m) { int mpu_vdd; if (i2c_probe(TPS62362_I2C_ADDR)) return; switch (m) { case 1000: mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; break; case 800: mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV; break; case 720: mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV; break; case 600: mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV; break; case 300: mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; break; default: puts("Unknown MPU clock, not scaling "); return; } /* Set VDD_MPU voltage */ if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) { printf("%s failure ", __func__); return; } } void scale_vcores(void) { const struct dpll_params *mpu_params; struct am43xx_board_id header; enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); if (read_eeprom(&header) < 0) puts("Could not get board ID. "); /* Get the frequency */ mpu_params = get_dpll_mpu_params(); if (board_is_idk()) scale_vcores_idk(mpu_params->m); else scale_vcores_generic(mpu_params->m); } |
fbf2728da ARM: AM43xx: Add ... |
525 526 527 528 529 530 531 532 533 |
void set_uart_mux_conf(void) { enable_uart0_pin_mux(); } void set_mux_conf_regs(void) { enable_board_pin_mux(); } |
b5e01eecc ARM: AM43xx: GP_E... |
534 535 536 537 538 |
static void enable_vtt_regulator(void) { u32 temp; /* enable module */ |
cd8341b7e ARM: AM43xx: GP-E... |
539 540 541 542 543 544 545 546 |
writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); /* enable output for GPIO5_7 */ writel(GPIO_SETDATAOUT(7), AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); temp = temp & ~(GPIO_OE_ENABLE(7)); writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); |
b5e01eecc ARM: AM43xx: GP_E... |
547 |
} |
fbf2728da ARM: AM43xx: Add ... |
548 549 |
void sdram_init(void) { |
b5e01eecc ARM: AM43xx: GP_E... |
550 551 552 553 554 555 556 |
/* * EPOS EVM has 1GB LPDDR2 connected to EMIF. * GP EMV has 1GB DDR3 connected to EMIF * along with VTT regulator. */ if (board_is_eposevm()) { config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); |
2c9521116 am43xx: Update EM... |
557 558 559 560 561 562 563 564 |
} else if (board_is_evm_14_or_later()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz_production, 0); } else if (board_is_evm_12_or_later()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz_beta, 0); |
b5e01eecc ARM: AM43xx: GP_E... |
565 566 567 568 |
} else if (board_is_gpevm()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz, 0); |
9cb9f3331 board: ti: am43xx... |
569 570 571 |
} else if (board_is_sk()) { config_ddr(400, &ioregs_ddr3, NULL, NULL, &ddr3_sk_emif_regs_400Mhz, 0); |
403d70abd board: ti: am43xx... |
572 573 574 |
} else if (board_is_idk()) { config_ddr(400, &ioregs_ddr3, NULL, NULL, &ddr3_idk_emif_regs_400Mhz, 0); |
b5e01eecc ARM: AM43xx: GP_E... |
575 |
} |
fbf2728da ARM: AM43xx: Add ... |
576 577 |
} #endif |
7aa5598aa tps65218/am43xx_e... |
578 579 580 581 |
/* setup board specific PMIC */ int power_init_board(void) { struct pmic *p; |
403d70abd board: ti: am43xx... |
582 583 584 585 586 587 588 589 590 591 592 593 594 |
if (board_is_idk()) { power_tps62362_init(I2C_PMIC); p = pmic_get("TPS62362"); if (p && !pmic_probe(p)) puts("PMIC: TPS62362 "); } else { power_tps65218_init(I2C_PMIC); p = pmic_get("TPS65218_PMIC"); if (p && !pmic_probe(p)) puts("PMIC: TPS65218 "); } |
7aa5598aa tps65218/am43xx_e... |
595 596 597 |
return 0; } |
fbf2728da ARM: AM43xx: Add ... |
598 599 |
int board_init(void) { |
8038b497e am43xx: Tune the ... |
600 601 602 |
struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, modena_init0_bw_integer, modena_init0_watermark_0; |
369cbe1e1 ARM: AM43xx: Adap... |
603 |
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
e53ad4b44 board/ti/am43xx: ... |
604 |
gpmc_init(); |
fbf2728da ARM: AM43xx: Add ... |
605 |
|
8038b497e am43xx: Tune the ... |
606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 |
/* Clear all important bits for DSS errata that may need to be tweaked*/ mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & MREQPRIO_0_SAB_INIT0_MASK; mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & BW_LIMITER_BW_FRAC_MASK; modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & BW_LIMITER_BW_INT_MASK; modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & BW_LIMITER_BW_WATERMARK_MASK; /* Setting MReq Priority of the DSS*/ mreqprio_0 |= 0x77; /* * Set L3 Fast Configuration Register * Limiting bandwith for ARM core to 700 MBPS */ modena_init0_bw_fractional |= 0x10; modena_init0_bw_integer |= 0x3; writel(mreqprio_0, &cdev->mreqprio_0); writel(mreqprio_1, &cdev->mreqprio_1); writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); |
fbf2728da ARM: AM43xx: Add ... |
637 638 639 640 641 642 |
return 0; } #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { |
f4af163e6 ARM: AM43XX: Add ... |
643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 |
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG char safe_string[HDR_NAME_LEN + 1]; struct am43xx_board_id header; if (read_eeprom(&header) < 0) puts("Could not get board ID. "); /* Now set variables based on the header. */ strncpy(safe_string, (char *)header.name, sizeof(header.name)); safe_string[sizeof(header.name)] = 0; setenv("board_name", safe_string); strncpy(safe_string, (char *)header.version, sizeof(header.version)); safe_string[sizeof(header.version)] = 0; setenv("board_rev", safe_string); #endif |
fbf2728da ARM: AM43xx: Add ... |
660 661 662 |
return 0; } #endif |
4cdd7fda9 ARM: AM43xx: Add ... |
663 |
|
9f81eb77e board: ti: AM43xx... |
664 665 666 667 668 669 670 671 672 673 674 |
#ifdef CONFIG_USB_DWC3 static struct dwc3_device usb_otg_ss1 = { .maximum_speed = USB_SPEED_HIGH, .base = USB_OTG_SS1_BASE, .tx_fifo_resize = false, .index = 0, }; static struct dwc3_omap_device usb_otg_ss1_glue = { .base = (void *)USB_OTG_SS1_GLUE_BASE, .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, |
9f81eb77e board: ti: AM43xx... |
675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 |
.index = 0, }; static struct ti_usb_phy_device usb_phy1_device = { .usb2_phy_power = (void *)USB2_PHY1_POWER, .index = 0, }; static struct dwc3_device usb_otg_ss2 = { .maximum_speed = USB_SPEED_HIGH, .base = USB_OTG_SS2_BASE, .tx_fifo_resize = false, .index = 1, }; static struct dwc3_omap_device usb_otg_ss2_glue = { .base = (void *)USB_OTG_SS2_GLUE_BASE, .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, |
9f81eb77e board: ti: AM43xx... |
693 694 695 696 697 698 699 700 701 702 |
.index = 1, }; static struct ti_usb_phy_device usb_phy2_device = { .usb2_phy_power = (void *)USB2_PHY2_POWER, .index = 1, }; int board_usb_init(int index, enum usb_init_type init) { |
6f1af1e35 board: ti: invoke... |
703 |
enable_usb_clocks(index); |
9f81eb77e board: ti: AM43xx... |
704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 |
switch (index) { case 0: if (init == USB_INIT_DEVICE) { usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; } else { usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; } dwc3_omap_uboot_init(&usb_otg_ss1_glue); ti_usb_phy_uboot_init(&usb_phy1_device); dwc3_uboot_init(&usb_otg_ss1); break; case 1: if (init == USB_INIT_DEVICE) { usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; } else { usb_otg_ss2.dr_mode = USB_DR_MODE_HOST; usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; } ti_usb_phy_uboot_init(&usb_phy2_device); dwc3_omap_uboot_init(&usb_otg_ss2_glue); dwc3_uboot_init(&usb_otg_ss2); break; default: printf("Invalid Controller Index "); } return 0; } int board_usb_cleanup(int index, enum usb_init_type init) { switch (index) { case 0: case 1: ti_usb_phy_uboot_exit(index); dwc3_uboot_exit(index); dwc3_omap_uboot_exit(index); break; default: printf("Invalid Controller Index "); } |
6f1af1e35 board: ti: invoke... |
752 |
disable_usb_clocks(index); |
9f81eb77e board: ti: AM43xx... |
753 754 755 |
return 0; } |
2d48aa69b usb: modify usb_g... |
756 |
int usb_gadget_handle_interrupts(int index) |
9f81eb77e board: ti: AM43xx... |
757 758 |
{ u32 status; |
2d48aa69b usb: modify usb_g... |
759 |
status = dwc3_omap_uboot_interrupt_status(index); |
9f81eb77e board: ti: AM43xx... |
760 |
if (status) |
2d48aa69b usb: modify usb_g... |
761 |
dwc3_uboot_handle_interrupt(index); |
9f81eb77e board: ti: AM43xx... |
762 763 764 765 |
return 0; } #endif |
4cdd7fda9 ARM: AM43xx: Add ... |
766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 |
#ifdef CONFIG_DRIVER_TI_CPSW static void cpsw_control(int enabled) { /* Additional controls can be added here */ return; } static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, .phy_addr = 16, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, .phy_addr = 1, }, }; static struct cpsw_platform_data cpsw_data = { .mdio_base = CPSW_MDIO_BASE, .cpsw_base = CPSW_BASE, .mdio_div = 0xff, .channels = 8, .cpdma_reg_ofs = 0x800, .slaves = 1, .slave_data = cpsw_slaves, .ale_reg_ofs = 0xd00, .ale_entries = 1024, .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, }; int board_eth_init(bd_t *bis) { int rv; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (!getenv("ethaddr")) { puts("<ethaddr> not set. Validating first E-fuse MAC "); |
0adb5b761 net: cosmetic: Na... |
825 |
if (is_valid_ethaddr(mac_addr)) |
4cdd7fda9 ARM: AM43xx: Add ... |
826 827 828 829 830 831 832 833 834 835 836 837 838 |
eth_setenv_enetaddr("ethaddr", mac_addr); } mac_lo = readl(&cdev->macid1l); mac_hi = readl(&cdev->macid1h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (!getenv("eth1addr")) { |
0adb5b761 net: cosmetic: Na... |
839 |
if (is_valid_ethaddr(mac_addr)) |
4cdd7fda9 ARM: AM43xx: Add ... |
840 841 842 843 844 845 846 |
eth_setenv_enetaddr("eth1addr", mac_addr); } if (board_is_eposevm()) { writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; cpsw_slaves[0].phy_addr = 16; |
619ce62d2 board: ti: am43xx... |
847 848 849 850 851 |
} else if (board_is_sk()) { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; cpsw_slaves[0].phy_addr = 4; cpsw_slaves[1].phy_addr = 5; |
403d70abd board: ti: am43xx... |
852 853 854 855 |
} else if (board_is_idk()) { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; cpsw_slaves[0].phy_addr = 0; |
4cdd7fda9 ARM: AM43xx: Add ... |
856 857 858 859 860 861 862 863 864 865 866 867 868 869 |
} else { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; cpsw_slaves[0].phy_addr = 0; } rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch ", rv); return rv; } #endif |