Eric Lee / smarc-uboot

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Commit 8038b497e742af2845523ed09b560bfc8cb42089

Authored by Cooper Jr., Franklin
Committed by Tom Rini
1 parent 2c95211167
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

am43xx: Tune the system to avoid DSS underflows 

* This is done by limiting the ARM's bandwidth and setting DSS priority in
  the EMIF controller to ensure underflows do not occur.

Showing 5 changed files with 111 additions and 10 deletions Side-by-side Diff

arch/arm/cpu/armv7/am33xx/ddr.c
Diff comments   View file @ 8038b49
... ... @@ -94,6 +94,18 @@
94 94 writel(regs->emif_rd_wr_exec_thresh,
95 95 &emif_reg[nr]->emif_rd_wr_exec_thresh);
96 96  
  97 + /*
  98 + * for most SOCs these registers won't need to be changed so only
  99 + * write to these registers if someone explicitly has set the
  100 + * register's value.
  101 + */
  102 + if(regs->emif_cos_config) {
  103 + writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
  104 + writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
  105 + writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
  106 + writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
  107 + }
  108 +
97 109 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
98 110 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
99 111 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
arch/arm/include/asm/arch-am33xx/cpu.h
Diff comments   View file @ 8038b49
... ... @@ -489,6 +489,12 @@
489 489 #define OMAP_GPIO_SETDATAOUT 0x0194
490 490  
491 491 /* Control Device Register */
  492 +
  493 + /* Control Device Register */
  494 +#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
  495 +#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
  496 +#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
  497 +
492 498 struct ctrl_dev {
493 499 unsigned int deviceid; /* offset 0x00 */
494 500 unsigned int resv1[7];
495 501  
... ... @@ -502,8 +508,23 @@
502 508 unsigned int macid1h; /* offset 0x3c */
503 509 unsigned int resv4[4];
504 510 unsigned int miisel; /* offset 0x50 */
505   - unsigned int resv5[106];
  511 + unsigned int resv5[7];
  512 + unsigned int mreqprio_0; /* offset 0x70 */
  513 + unsigned int mreqprio_1; /* offset 0x74 */
  514 + unsigned int resv6[97];
506 515 unsigned int efuse_sma; /* offset 0x1FC */
  516 +};
  517 +
  518 +/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
  519 +#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
  520 +#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
  521 +#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
  522 +
  523 +struct l3f_cfg_bwlimiter {
  524 + u32 padding0[2];
  525 + u32 modena_init0_bw_fractional;
  526 + u32 modena_init0_bw_integer;
  527 + u32 modena_init0_watermark_0;
507 528 };
508 529  
509 530 /* gmii_sel register defines */
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
Diff comments   View file @ 8038b49
... ... @@ -13,6 +13,9 @@
13 13  
14 14 /* Module base addresses */
15 15  
  16 +/* L3 Fast Configuration Bandwidth Limiter Base Address */
  17 +#define L3F_CFG_BWLIMITER 0x44005200
  18 +
16 19 /* UART Base Address */
17 20 #define UART0_BASE 0x44E09000
18 21  
arch/arm/include/asm/emif.h
Diff comments   View file @ 8038b49
... ... @@ -642,11 +642,16 @@
642 642 u32 emif_ddr_phy_ctrl_1;
643 643 u32 emif_ddr_phy_ctrl_1_shdw;
644 644 u32 emif_ddr_phy_ctrl_2;
645   - u32 padding7[12];
  645 + u32 padding7[4];
  646 + u32 emif_prio_class_serv_map;
  647 + u32 emif_connect_id_serv_1_map;
  648 + u32 emif_connect_id_serv_2_map;
  649 + u32 padding8[5];
646 650 u32 emif_rd_wr_exec_thresh;
647   - u32 padding8[7];
  651 + u32 emif_cos_config;
  652 + u32 padding9[6];
648 653 u32 emif_ddr_phy_status[21];
649   - u32 padding9[27];
  654 + u32 padding10[27];
650 655 u32 emif_ddr_ext_phy_ctrl_1;
651 656 u32 emif_ddr_ext_phy_ctrl_1_shdw;
652 657 u32 emif_ddr_ext_phy_ctrl_2;
... ... @@ -1137,6 +1142,10 @@
1137 1142 u32 emif_rd_wr_lvl_rmp_ctl;
1138 1143 u32 emif_rd_wr_lvl_ctl;
1139 1144 u32 emif_rd_wr_exec_thresh;
  1145 + u32 emif_prio_class_serv_map;
  1146 + u32 emif_connect_id_serv_1_map;
  1147 + u32 emif_connect_id_serv_2_map;
  1148 + u32 emif_cos_config;
1140 1149 };
1141 1150  
1142 1151 struct lpddr2_mr_regs {
board/ti/am43xx/board.c
Diff comments   View file @ 8038b49
... ... @@ -157,12 +157,16 @@
157 157 .emif_rd_wr_lvl_rmp_ctl = 0x0,
158 158 .emif_rd_wr_lvl_ctl = 0x0,
159 159 .emif_ddr_phy_ctlr_1 = 0x0E084006,
160   - .emif_rd_wr_exec_thresh = 0x00000405,
  160 + .emif_rd_wr_exec_thresh = 0x80000405,
161 161 .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
162 162 .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
163 163 .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
164 164 .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
165   - .emif_ddr_ext_phy_ctrl_5 = 0x00500050
  165 + .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
  166 + .emif_prio_class_serv_map = 0x80000001,
  167 + .emif_connect_id_serv_1_map = 0x80000094,
  168 + .emif_connect_id_serv_2_map = 0x00000000,
  169 + .emif_cos_config = 0x000FFFFF
166 170 };
167 171  
168 172 const u32 ext_phy_ctrl_const_base_lpddr2[] = {
... ... @@ -217,7 +221,11 @@
217 221 .emif_rd_wr_lvl_rmp_win = 0x0,
218 222 .emif_rd_wr_lvl_rmp_ctl = 0x0,
219 223 .emif_rd_wr_lvl_ctl = 0x0,
220   - .emif_rd_wr_exec_thresh = 0x00000405
  224 + .emif_rd_wr_exec_thresh = 0x80000405,
  225 + .emif_prio_class_serv_map = 0x80000001,
  226 + .emif_connect_id_serv_1_map = 0x80000094,
  227 + .emif_connect_id_serv_2_map = 0x00000000,
  228 + .emif_cos_config = 0x000FFFFF
221 229 };
222 230  
223 231 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
... ... @@ -236,7 +244,11 @@
236 244 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
237 245 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
238 246 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
239   - .emif_rd_wr_exec_thresh = 0x00000405
  247 + .emif_rd_wr_exec_thresh = 0x80000405,
  248 + .emif_prio_class_serv_map = 0x80000001,
  249 + .emif_connect_id_serv_1_map = 0x80000094,
  250 + .emif_connect_id_serv_2_map = 0x00000000,
  251 + .emif_cos_config = 0x000FFFFF
240 252 };
241 253  
242 254 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
... ... @@ -255,7 +267,11 @@
255 267 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
256 268 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
257 269 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
258   - .emif_rd_wr_exec_thresh = 0x00000405
  270 + .emif_rd_wr_exec_thresh = 0x80000405,
  271 + .emif_prio_class_serv_map = 0x80000001,
  272 + .emif_connect_id_serv_1_map = 0x80000094,
  273 + .emif_connect_id_serv_2_map = 0x00000000,
  274 + .emif_cos_config = 0x000FFFFF
259 275 };
260 276  
261 277 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
... ... @@ -277,7 +293,11 @@
277 293 .emif_rd_wr_lvl_rmp_win = 0x0,
278 294 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
279 295 .emif_rd_wr_lvl_ctl = 0x00000000,
280   - .emif_rd_wr_exec_thresh = 0x00000000,
  296 + .emif_rd_wr_exec_thresh = 0x80000000,
  297 + .emif_prio_class_serv_map = 0x80000001,
  298 + .emif_connect_id_serv_1_map = 0x80000094,
  299 + .emif_connect_id_serv_2_map = 0x00000000,
  300 + .emif_cos_config = 0x000FFFFF
281 301 };
282 302  
283 303 const u32 ext_phy_ctrl_const_base_ddr3[] = {
284 304  
... ... @@ -587,7 +607,43 @@
587 607  
588 608 int board_init(void)
589 609 {
  610 + struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
  611 + u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
  612 + modena_init0_bw_integer, modena_init0_watermark_0;
  613 +
590 614 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  615 +
  616 + /* Clear all important bits for DSS errata that may need to be tweaked*/
  617 + mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
  618 + MREQPRIO_0_SAB_INIT0_MASK;
  619 +
  620 + mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
  621 +
  622 + modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
  623 + BW_LIMITER_BW_FRAC_MASK;
  624 +
  625 + modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
  626 + BW_LIMITER_BW_INT_MASK;
  627 +
  628 + modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
  629 + BW_LIMITER_BW_WATERMARK_MASK;
  630 +
  631 + /* Setting MReq Priority of the DSS*/
  632 + mreqprio_0 |= 0x77;
  633 +
  634 + /*
  635 + * Set L3 Fast Configuration Register
  636 + * Limiting bandwith for ARM core to 700 MBPS
  637 + */
  638 + modena_init0_bw_fractional |= 0x10;
  639 + modena_init0_bw_integer |= 0x3;
  640 +
  641 + writel(mreqprio_0, &cdev->mreqprio_0);
  642 + writel(mreqprio_1, &cdev->mreqprio_1);
  643 +
  644 + writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
  645 + writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
  646 + writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
591 647  
592 648 return 0;
593 649 }