arm:am43xx: Add TPS65218 support to scale voltages up

This family is supported by the TPS65218 PMIC. Implement a scale_vcores to set the MPU and CORE voltage correctly to the max frequency that is supported (and what we will be scaling them to in setup_dplls()). Signed-off-by: Tom Rini <trini@ti.com>

arm:am43xx: Add TPS65218 support to scale voltages up
This family is supported by the TPS65218 PMIC. Implement a scale_vcores to set the MPU and CORE voltage correctly to the max frequency that is supported (and what we will be scaling them to in setup_dplls()). Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini
1 parent 86db550b38
Showing 2 changed files with 45 additions and 7 deletions Side-by-side Diff
board/ti/am43xx/board.c
include/configs/am43xx_evm.h
@@ -19,6 +19,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/emif.h>
 #include "board.h"
+#include <power/tps65218.h>
 #include <miiphy.h>
 #include <cpsw.h>
  
@@ -254,13 +255,6 @@
  
 const struct dpll_params *get_dpll_ddr_params(void)
 {
-	struct am43xx_board_id header;
-
-	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-	if (read_eeprom(&header) < 0)
-		puts("Could not get board ID.\n");
-
 	if (board_is_eposevm())
 		return &epos_evm_dpll_ddr;
 	else if (board_is_gpevm())
@@ -336,6 +330,46 @@
 	int ind = get_sys_clk_index();
  
 	return &dpll_per[ind];
+}
+
+void scale_vcores(void)
+{
+	const struct dpll_params *mpu_params;
+	int mpu_vdd;
+	struct am43xx_board_id header;
+
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	if (read_eeprom(&header) < 0)
+		puts("Could not get board ID.\n");
+
+	/* Get the frequency */
+	mpu_params = get_dpll_mpu_params();
+
+	if (i2c_probe(TPS65218_CHIP_PM))
+		return;
+
+	if (mpu_params->m == 1000) {
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
+	} else if (mpu_params->m == 600) {
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
+	} else {
+		puts("Unknown MPU clock, not scaling\n");
+		return;
+	}
+
+	/* Set DCDC1 (CORE) voltage to 1.1V */
+	if (tps65218_voltage_update(TPS65218_DCDC1,
+				    TPS65218_DCDC_VOLT_SEL_1100MV)) {
+		puts("tps65218_voltage_update failure\n");
+		return;
+	}
+
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
+		puts("tps65218_voltage_update failure\n");
+		return;
+	}
 }
  
 void set_uart_mux_conf(void)
@@ -32,11 +32,15 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
  
+/* Power */
+#define CONFIG_POWER_TPS65218
+
 /* SPL defines. */
 #define CONFIG_SPL_TEXT_BASE		0x40300350
 #define CONFIG_SPL_MAX_SIZE		(220 << 10)	/* 220KB */
 #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
 					 (128 << 20))
+#define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_YMODEM_SUPPORT
  
 /* Enabling L2 Cache */
...	...	@@ -19,6 +19,7 @@
19	19	#include <asm/arch/gpio.h>
20	20	#include <asm/emif.h>
21	21	#include "board.h"
	22	+#include <power/tps65218.h>
22	23	#include <miiphy.h>
23	24	#include <cpsw.h>
24	25
...	...	@@ -254,13 +255,6 @@
254	255
255	256	const struct dpll_params *get_dpll_ddr_params(void)
256	257	{
257		- struct am43xx_board_id header;
258		-
259		- enable_i2c0_pin_mux();
260		- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
261		- if (read_eeprom(&header) < 0)
262		- puts("Could not get board ID.\n");
263		-
264	258	if (board_is_eposevm())
265	259	return &epos_evm_dpll_ddr;
266	260	else if (board_is_gpevm())
...	...	@@ -336,6 +330,46 @@
336	330	int ind = get_sys_clk_index();
337	331
338	332	return &dpll_per[ind];
	333	+}
	334	+
	335	+void scale_vcores(void)
	336	+{
	337	+ const struct dpll_params *mpu_params;
	338	+ int mpu_vdd;
	339	+ struct am43xx_board_id header;
	340	+
	341	+ enable_i2c0_pin_mux();
	342	+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
	343	+ if (read_eeprom(&header) < 0)
	344	+ puts("Could not get board ID.\n");
	345	+
	346	+ /* Get the frequency */
	347	+ mpu_params = get_dpll_mpu_params();
	348	+
	349	+ if (i2c_probe(TPS65218_CHIP_PM))
	350	+ return;
	351	+
	352	+ if (mpu_params->m == 1000) {
	353	+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
	354	+ } else if (mpu_params->m == 600) {
	355	+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
	356	+ } else {
	357	+ puts("Unknown MPU clock, not scaling\n");
	358	+ return;
	359	+ }
	360	+
	361	+ /* Set DCDC1 (CORE) voltage to 1.1V */
	362	+ if (tps65218_voltage_update(TPS65218_DCDC1,
	363	+ TPS65218_DCDC_VOLT_SEL_1100MV)) {
	364	+ puts("tps65218_voltage_update failure\n");
	365	+ return;
	366	+ }
	367	+
	368	+ /* Set DCDC2 (MPU) voltage */
	369	+ if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
	370	+ puts("tps65218_voltage_update failure\n");
	371	+ return;
	372	+ }
339	373	}
340	374
341	375	void set_uart_mux_conf(void)
...	...	@@ -32,11 +32,15 @@
32	32	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
33	33	#define CONFIG_SYS_I2C_MULTI_EEPROMS
34	34
	35	+/* Power */
	36	+#define CONFIG_POWER_TPS65218
	37	+
35	38	/* SPL defines. */
36	39	#define CONFIG_SPL_TEXT_BASE 0x40300350
37	40	#define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */
38	41	#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
39	42	(128 << 20))
	43	+#define CONFIG_SPL_POWER_SUPPORT
40	44	#define CONFIG_SPL_YMODEM_SUPPORT
41	45
42	46	/* Enabling L2 Cache */