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drivers/mmc/sdhci.c
14.1 KB
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/* * Copyright 2011, Marvell Semiconductor Inc. * Lei Wen <leiwen@marvell.com> * |
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* SPDX-License-Identifier: GPL-2.0+ |
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* * Back ported to the 8xx platform (from the 8260 platform) by * Murray.Jensen@cmst.csiro.au, 27-Jan-01. */ #include <common.h> #include <malloc.h> #include <mmc.h> #include <sdhci.h> |
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#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER; #else |
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void *aligned_buffer; |
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#endif |
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static void sdhci_reset(struct sdhci_host *host, u8 mask) { unsigned long timeout; /* Wait max 100 ms */ timeout = 100; sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { if (timeout == 0) { |
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printf("%s: Reset 0x%x never completed. ", __func__, (int)mask); |
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return; } timeout--; udelay(1000); } } static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) { int i; if (cmd->resp_type & MMC_RSP_136) { /* CRC is stripped so we need to do some shifting. */ for (i = 0; i < 4; i++) { cmd->response[i] = sdhci_readl(host, SDHCI_RESPONSE + (3-i)*4) << 8; if (i != 3) cmd->response[i] |= sdhci_readb(host, SDHCI_RESPONSE + (3-i)*4-1); } } else { cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); } } static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) { int i; char *offs; for (i = 0; i < data->blocksize; i += 4) { offs = data->dest + i; if (data->flags == MMC_DATA_READ) *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); else sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); } } static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, unsigned int start_addr) { |
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unsigned int stat, rdy, mask, timeout, block = 0; |
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#ifdef CONFIG_MMC_SDMA unsigned char ctrl; |
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
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ctrl &= ~SDHCI_CTRL_DMA_MASK; |
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
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#endif |
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timeout = 1000000; |
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rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; do { stat = sdhci_readl(host, SDHCI_INT_STATUS); if (stat & SDHCI_INT_ERROR) { |
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printf("%s: Error detected in status(0x%X)! ", __func__, stat); |
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return -1; } if (stat & rdy) { if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) continue; sdhci_writel(host, rdy, SDHCI_INT_STATUS); sdhci_transfer_pio(host, data); data->dest += data->blocksize; if (++block >= data->blocks) break; } #ifdef CONFIG_MMC_SDMA if (stat & SDHCI_INT_DMA_END) { sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); |
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start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); |
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start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); } #endif |
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if (timeout-- > 0) udelay(10); else { |
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printf("%s: Transfer data timeout ", __func__); |
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return -1; } |
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} while (!(stat & SDHCI_INT_DATA_END)); return 0; } |
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/* * No command will be sent by driver if card is busy, so driver must wait * for card ready state. * Every time when card is busy after timeout then (last) timeout value will be * increased twice but only if it doesn't exceed global defined maximum. * Each function call will use last timeout value. Max timeout can be redefined * in board config file. */ #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200 #endif #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100 |
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static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, |
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struct mmc_data *data) { |
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struct sdhci_host *host = mmc->priv; |
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unsigned int stat = 0; int ret = 0; int trans_bytes = 0, is_aligned = 1; u32 mask, flags, mode; |
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unsigned int time = 0, start_addr = 0; |
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int mmc_dev = mmc->block_dev.dev; |
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unsigned start = get_timer(0); |
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/* Timeout unit - ms */ static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT; |
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sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; /* We shouldn't wait for data inihibit for stop commands, even though they might use busy signaling */ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) mask &= ~SDHCI_DATA_INHIBIT; while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
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if (time >= cmd_timeout) { |
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printf("%s: MMC: %d busy ", __func__, mmc_dev); |
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if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) { cmd_timeout += cmd_timeout; printf("timeout increasing to: %u ms. ", cmd_timeout); } else { puts("timeout. "); return COMM_ERR; } |
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} |
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time++; |
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udelay(1000); } mask = SDHCI_INT_RESPONSE; if (!(cmd->resp_type & MMC_RSP_PRESENT)) flags = SDHCI_CMD_RESP_NONE; else if (cmd->resp_type & MMC_RSP_136) flags = SDHCI_CMD_RESP_LONG; else if (cmd->resp_type & MMC_RSP_BUSY) { flags = SDHCI_CMD_RESP_SHORT_BUSY; mask |= SDHCI_INT_DATA_END; } else flags = SDHCI_CMD_RESP_SHORT; if (cmd->resp_type & MMC_RSP_CRC) flags |= SDHCI_CMD_CRC; if (cmd->resp_type & MMC_RSP_OPCODE) flags |= SDHCI_CMD_INDEX; if (data) flags |= SDHCI_CMD_DATA; |
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/* Set Transfer mode regarding to data flag */ |
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if (data != 0) { sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); mode = SDHCI_TRNS_BLK_CNT_EN; trans_bytes = data->blocks * data->blocksize; if (data->blocks > 1) mode |= SDHCI_TRNS_MULTI; if (data->flags == MMC_DATA_READ) mode |= SDHCI_TRNS_READ; #ifdef CONFIG_MMC_SDMA if (data->flags == MMC_DATA_READ) |
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start_addr = (unsigned long)data->dest; |
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else |
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start_addr = (unsigned long)data->src; |
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if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && (start_addr & 0x7) != 0x0) { is_aligned = 0; |
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start_addr = (unsigned long)aligned_buffer; |
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if (data->flags != MMC_DATA_READ) memcpy(aligned_buffer, data->src, trans_bytes); } |
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#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) /* * Always use this bounce-buffer when * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined */ is_aligned = 0; start_addr = (unsigned long)aligned_buffer; if (data->flags != MMC_DATA_READ) memcpy(aligned_buffer, data->src, trans_bytes); #endif |
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sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); mode |= SDHCI_TRNS_DMA; #endif sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, data->blocksize), SDHCI_BLOCK_SIZE); sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
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} else if (cmd->resp_type & MMC_RSP_BUSY) { sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); |
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} sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); #ifdef CONFIG_MMC_SDMA |
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flush_cache(start_addr, trans_bytes); |
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#endif sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); |
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start = get_timer(0); |
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do { stat = sdhci_readl(host, SDHCI_INT_STATUS); if (stat & SDHCI_INT_ERROR) break; |
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} while (((stat & mask) != mask) && (get_timer(start) < CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT)); |
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if (get_timer(start) >= CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT) { |
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if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) return 0; else { |
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printf("%s: Timeout for status update! ", __func__); |
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return TIMEOUT; } } |
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if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { sdhci_cmd_done(host, cmd); sdhci_writel(host, mask, SDHCI_INT_STATUS); } else ret = -1; if (!ret && data) ret = sdhci_transfer_data(host, data, start_addr); |
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if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) udelay(1000); |
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stat = sdhci_readl(host, SDHCI_INT_STATUS); sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); if (!ret) { if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !is_aligned && (data->flags == MMC_DATA_READ)) memcpy(data->dest, aligned_buffer, trans_bytes); return 0; } sdhci_reset(host, SDHCI_RESET_CMD); sdhci_reset(host, SDHCI_RESET_DATA); if (stat & SDHCI_INT_TIMEOUT) return TIMEOUT; else return COMM_ERR; } static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) { |
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struct sdhci_host *host = mmc->priv; |
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unsigned int div, clk, timeout, reg; |
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/* Wait max 20 ms */ timeout = 200; while (sdhci_readl(host, SDHCI_PRESENT_STATE) & (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { if (timeout == 0) { printf("%s: Timeout to wait cmd & data inhibit ", __func__); return -1; } timeout--; udelay(100); } reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); reg &= ~SDHCI_CLOCK_CARD_EN; sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); |
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if (clock == 0) return 0; |
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if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { |
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/* Version 3.00 divisors must be a multiple of 2. */ |
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if (mmc->cfg->f_max <= clock) |
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div = 1; else { for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { |
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if ((mmc->cfg->f_max / div) <= clock) |
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break; } } } else { /* Version 2.00 divisors must be a power of 2. */ for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
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if ((mmc->cfg->f_max / div) <= clock) |
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break; } } div >>= 1; |
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if (host->set_clock) host->set_clock(host->index, div); |
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clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; clk |= SDHCI_CLOCK_INT_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); /* Wait max 20 ms */ timeout = 20; while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) & SDHCI_CLOCK_INT_STABLE)) { if (timeout == 0) { |
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printf("%s: Internal clock never stabilised. ", __func__); |
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return -1; } timeout--; udelay(1000); } clk |= SDHCI_CLOCK_CARD_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); return 0; } static void sdhci_set_power(struct sdhci_host *host, unsigned short power) { u8 pwr = 0; if (power != (unsigned short)-1) { switch (1 << power) { case MMC_VDD_165_195: pwr = SDHCI_POWER_180; break; case MMC_VDD_29_30: case MMC_VDD_30_31: pwr = SDHCI_POWER_300; break; case MMC_VDD_32_33: case MMC_VDD_33_34: pwr = SDHCI_POWER_330; break; } } if (pwr == 0) { sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); return; } |
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if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
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pwr |= SDHCI_POWER_ON; sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); } |
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static void sdhci_set_ios(struct mmc *mmc) |
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{ u32 ctrl; |
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struct sdhci_host *host = mmc->priv; |
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if (host->set_control_reg) host->set_control_reg(host); |
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if (mmc->clock != host->clock) sdhci_set_clock(mmc, mmc->clock); /* Set bus width */ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); if (mmc->bus_width == 8) { ctrl &= ~SDHCI_CTRL_4BITBUS; |
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if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || (host->quirks & SDHCI_QUIRK_USE_WIDE8)) |
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ctrl |= SDHCI_CTRL_8BITBUS; } else { |
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if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || (host->quirks & SDHCI_QUIRK_USE_WIDE8)) |
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ctrl &= ~SDHCI_CTRL_8BITBUS; if (mmc->bus_width == 4) ctrl |= SDHCI_CTRL_4BITBUS; else ctrl &= ~SDHCI_CTRL_4BITBUS; } if (mmc->clock > 26000000) ctrl |= SDHCI_CTRL_HISPD; else ctrl &= ~SDHCI_CTRL_HISPD; |
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if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ctrl &= ~SDHCI_CTRL_HISPD; |
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); } |
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static int sdhci_init(struct mmc *mmc) |
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{ |
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struct sdhci_host *host = mmc->priv; |
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if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { aligned_buffer = memalign(8, 512*1024); if (!aligned_buffer) { |
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printf("%s: Aligned buffer alloc failed!!! ", __func__); |
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return -1; } } |
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sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); |
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if (host->quirks & SDHCI_QUIRK_NO_CD) { |
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#if defined(CONFIG_PIC32_SDHCI) /* PIC32 SDHCI CD errata: * - set CD_TEST and clear CD_TEST_INS bit */ sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL); #else |
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unsigned int status; |
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sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST, |
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SDHCI_HOST_CONTROL); status = sdhci_readl(host, SDHCI_PRESENT_STATE); while ((!(status & SDHCI_CARD_PRESENT)) || (!(status & SDHCI_CARD_STATE_STABLE)) || (!(status & SDHCI_CARD_DETECT_PIN_LEVEL))) status = sdhci_readl(host, SDHCI_PRESENT_STATE); |
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#endif |
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} |
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/* Enable only interrupts served by the SD controller */ |
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sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE); |
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/* Mask all sdhci interrupt sources */ sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); |
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return 0; } |
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static const struct mmc_ops sdhci_ops = { .send_cmd = sdhci_send_command, .set_ios = sdhci_set_ios, .init = sdhci_init, }; |
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int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) { |
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unsigned int caps; |
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host->cfg.name = host->name; host->cfg.ops = &sdhci_ops; |
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caps = sdhci_readl(host, SDHCI_CAPABILITIES); #ifdef CONFIG_MMC_SDMA if (!(caps & SDHCI_CAN_DO_SDMA)) { |
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printf("%s: Your controller doesn't support SDMA!! ", __func__); |
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return -1; } #endif if (max_clk) |
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host->cfg.f_max = max_clk; |
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else { |
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if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) |
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host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) |
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>> SDHCI_CLOCK_BASE_SHIFT; else |
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host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK) |
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>> SDHCI_CLOCK_BASE_SHIFT; |
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host->cfg.f_max *= 1000000; |
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} |
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if (host->cfg.f_max == 0) { |
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printf("%s: Hardware doesn't specify base clock frequency ", __func__); |
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return -1; } if (min_clk) |
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host->cfg.f_min = min_clk; |
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else { |
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if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) |
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host->cfg.f_min = host->cfg.f_max / SDHCI_MAX_DIV_SPEC_300; |
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else |
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host->cfg.f_min = host->cfg.f_max / SDHCI_MAX_DIV_SPEC_200; |
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} |
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host->cfg.voltages = 0; |
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if (caps & SDHCI_CAN_VDD_330) |
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host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; |
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if (caps & SDHCI_CAN_VDD_300) |
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host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; |
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if (caps & SDHCI_CAN_VDD_180) |
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host->cfg.voltages |= MMC_VDD_165_195; |
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if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) |
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host->cfg.voltages |= host->voltages; |
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host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; |
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if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { |
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if (caps & SDHCI_CAN_DO_8BIT) |
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523 |
host->cfg.host_caps |= MMC_MODE_8BIT; |
1695b29a5
|
524 |
} |
429790026
|
525 526 527 |
if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) host->cfg.host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz); |
236bfecff
|
528 |
if (host->host_caps) |
93bfd6167
|
529 530 531 |
host->cfg.host_caps |= host->host_caps; host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
af62a5578
|
532 533 |
sdhci_reset(host, SDHCI_RESET_ALL); |
93bfd6167
|
534 535 536 537 538 539 540 |
host->mmc = mmc_create(&host->cfg, host); if (host->mmc == NULL) { printf("%s: mmc create fail! ", __func__); return -1; } |
af62a5578
|
541 542 543 |
return 0; } |