Blame view
doc/README.fsl-ddr
21.3 KB
a4c66509f powerpc/mpc8xxx: ... |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 |
Table of interleaving 2-4 controllers ===================================== +--------------+-----------------------------------------------------------+ |Configuration | Memory Controller | | | 1 2 3 4 | |--------------+--------------+--------------+-----------------------------+ | Two memory | Not Intlv'ed | Not Intlv'ed | | | complexes +--------------+--------------+ | | | 2-way Intlv'ed | | |--------------+--------------+--------------+--------------+ | | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | | | Three memory +--------------+--------------+--------------+ | | complexes | 2-way Intlv'ed | Not Intlv'ed | | | +-----------------------------+--------------+ | | | 3-way Intlv'ed | | +--------------+--------------+--------------+--------------+--------------+ | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | | Four memory +--------------+--------------+--------------+--------------+ | complexes | 2-way Intlv'ed | 2-way Intlv'ed | | +-----------------------------+-----------------------------+ | | 4-way Intlv'ed | +--------------+-----------------------------------------------------------+ |
c9ffd839b Check DDR interle... |
23 |
|
a4c66509f powerpc/mpc8xxx: ... |
24 25 |
Table of 2-way interleaving modes supported in cpu/8xxx/ddr/ |
c9ffd839b Check DDR interle... |
26 27 |
====================================================== +-------------+---------------------------------------------------------+ |
d1a24f061 Minor Coding Styl... |
28 29 30 31 32 |
| | Rank Interleaving | | +--------+-----------+-----------+------------+-----------+ |Memory | | | | 2x2 | 4x1 | |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ | |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} | |
c9ffd839b Check DDR interle... |
33 |
+-------------+--------+-----------+-----------+------------+-----------+ |
d1a24f061 Minor Coding Styl... |
34 |
|None | Yes | Yes | Yes | Yes | Yes | |
c9ffd839b Check DDR interle... |
35 |
+-------------+--------+-----------+-----------+------------+-----------+ |
d1a24f061 Minor Coding Styl... |
36 37 |
|Cacheline | Yes | Yes | No | No, Only(*)| Yes | | |CS0 Only| | | {CS0+CS1} | | |
c9ffd839b Check DDR interle... |
38 |
+-------------+--------+-----------+-----------+------------+-----------+ |
d1a24f061 Minor Coding Styl... |
39 40 |
|Page | Yes | Yes | No | No, Only(*)| Yes | | |CS0 Only| | | {CS0+CS1} | | |
c9ffd839b Check DDR interle... |
41 |
+-------------+--------+-----------+-----------+------------+-----------+ |
d1a24f061 Minor Coding Styl... |
42 43 |
|Bank | Yes | Yes | No | No, Only(*)| Yes | | |CS0 Only| | | {CS0+CS1} | | |
c9ffd839b Check DDR interle... |
44 |
+-------------+--------+-----------+-----------+------------+-----------+ |
d1a24f061 Minor Coding Styl... |
45 46 |
|Superbank | No | Yes | No | No, Only(*)| Yes | | | | | | {CS0+CS1} | | |
c9ffd839b Check DDR interle... |
47 48 49 50 51 |
+-------------+--------+-----------+-----------+------------+-----------+ (*) Although the hardware can be configured with memory controller interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1} from each controller. {CS2+CS3} on each controller are only rank interleaved on that controller. |
076bff8f4 powerpc/8xxx: Fix... |
52 53 |
For memory controller interleaving, identical DIMMs are suggested. Software doesn't check the size or organization of interleaved DIMMs. |
c9ffd839b Check DDR interle... |
54 55 56 57 58 |
The ways to configure the ddr interleaving mode ============================================== 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting under "CONFIG_EXTRA_ENV_SETTINGS", like: #define CONFIG_EXTRA_ENV_SETTINGS \ |
79e4e6480 powerpc/8xxx: Ena... |
59 |
"hwconfig=fsl_ddr:ctlr_intlv=bank" \ |
c9ffd839b Check DDR interle... |
60 61 62 63 64 65 |
...... 2. Run u-boot "setenv" command to configure the memory interleaving mode. Either numerical or string value is accepted. # disable memory controller interleaving |
79e4e6480 powerpc/8xxx: Ena... |
66 |
setenv hwconfig "fsl_ddr:ctlr_intlv=null" |
c9ffd839b Check DDR interle... |
67 68 |
# cacheline interleaving |
79e4e6480 powerpc/8xxx: Ena... |
69 |
setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline" |
c9ffd839b Check DDR interle... |
70 71 |
# page interleaving |
79e4e6480 powerpc/8xxx: Ena... |
72 |
setenv hwconfig "fsl_ddr:ctlr_intlv=page" |
c9ffd839b Check DDR interle... |
73 74 |
# bank interleaving |
79e4e6480 powerpc/8xxx: Ena... |
75 |
setenv hwconfig "fsl_ddr:ctlr_intlv=bank" |
c9ffd839b Check DDR interle... |
76 77 |
# superbank |
79e4e6480 powerpc/8xxx: Ena... |
78 |
setenv hwconfig "fsl_ddr:ctlr_intlv=superbank" |
c9ffd839b Check DDR interle... |
79 |
|
a4c66509f powerpc/mpc8xxx: ... |
80 81 82 83 84 85 86 87 |
# 1KB 3-way interleaving setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB" # 4KB 3-way interleaving setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB" # 8KB 3-way interleaving setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB" |
c9ffd839b Check DDR interle... |
88 |
# disable bank (chip-select) interleaving |
79e4e6480 powerpc/8xxx: Ena... |
89 |
setenv hwconfig "fsl_ddr:bank_intlv=null" |
c9ffd839b Check DDR interle... |
90 91 |
# bank(chip-select) interleaving cs0+cs1 |
79e4e6480 powerpc/8xxx: Ena... |
92 |
setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1" |
c9ffd839b Check DDR interle... |
93 94 |
# bank(chip-select) interleaving cs2+cs3 |
79e4e6480 powerpc/8xxx: Ena... |
95 |
setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3" |
c9ffd839b Check DDR interle... |
96 97 |
# bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2) |
79e4e6480 powerpc/8xxx: Ena... |
98 |
setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3" |
c9ffd839b Check DDR interle... |
99 100 |
# bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) |
79e4e6480 powerpc/8xxx: Ena... |
101 |
setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" |
89b780956 powerpc/mpc8xxx: ... |
102 103 104 105 |
# bank(chip-select) interleaving (auto) setenv hwconfig "fsl_ddr:bank_intlv=auto" This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings on DIMMs. |
7fd101c97 powerpc/8xxx: Ena... |
106 107 108 109 110 111 |
Memory controller address hashing ================================== If the DDR controller supports address hashing, it can be enabled by hwconfig. Syntax is: hwconfig=fsl_ddr:addr_hash=true |
47df8f03f mpc8xxx: Enable E... |
112 113 114 115 116 117 118 |
Memory controller ECC on/off ============================ If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC, ECC can be turned on/off by hwconfig. Syntax is hwconfig=fsl_ddr:ecc=off |
ebbe11dd3 Add memory test f... |
119 120 121 122 123 124 125 126 127 128 129 130 131 |
Memory testing options for mpc85xx ================================== 1. Memory test can be done once U-boot prompt comes up using mtest, or 2. Memory test can be done with Power-On-Self-Test function, activated at compile time. In order to enable the POST memory test, CONFIG_POST needs to be defined in board configuraiton header file. By default, POST memory test performs a fast test. A slow test can be enabled by changing the flag at compiling time. To test memory bigger than 2GB, 36BIT support is needed. Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB window to physical address so that all physical memory can be tested. |
7fd101c97 powerpc/8xxx: Ena... |
132 133 134 135 |
Combination of hwconfig ======================= Hwconfig can be combined with multiple parameters, for example, on a supported platform |
e1fd16b6f mpc85xx: Enable u... |
136 137 138 139 140 141 142 143 144 145 146 147 |
hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on Table for dynamic ODT for DDR3 ============================== For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may be needed, depending on the configuration. The numbers in the following tables are in Ohms. * denotes dynamic ODT Two slots system +-----------------------+----------+---------------+-----------------------------+-----------------------------+ |
d1a24f061 Minor Coding Styl... |
148 |
| Configuration | |DRAM controller| Slot 1 | Slot 2 | |
e1fd16b6f mpc85xx: Enable u... |
149 |
+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+ |
d1a24f061 Minor Coding Styl... |
150 151 152 |
| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 | + Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+ | | | | | | Write | Read | Write | Read | Write | Read | Write | Read | |
e1fd16b6f mpc85xx: Enable u... |
153 |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
154 |
| | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 | |
e1fd16b6f mpc85xx: Enable u... |
155 |
| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
156 |
| | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off | |
e1fd16b6f mpc85xx: Enable u... |
157 |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
158 |
| | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | | |
e1fd16b6f mpc85xx: Enable u... |
159 |
| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
160 |
| | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | | |
e1fd16b6f mpc85xx: Enable u... |
161 |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
162 |
| | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 | |
e1fd16b6f mpc85xx: Enable u... |
163 |
|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
164 |
| | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off | |
e1fd16b6f mpc85xx: Enable u... |
165 |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
166 |
| | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | | |
e1fd16b6f mpc85xx: Enable u... |
167 |
|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
168 |
| | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | | |
e1fd16b6f mpc85xx: Enable u... |
169 |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
170 |
| Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | | |
e1fd16b6f mpc85xx: Enable u... |
171 |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
172 |
| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off | |
e1fd16b6f mpc85xx: Enable u... |
173 |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
174 |
|Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | | |
e1fd16b6f mpc85xx: Enable u... |
175 |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
176 |
| Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | | |
e1fd16b6f mpc85xx: Enable u... |
177 178 179 180 |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ Single slot system +-------------+------------+---------------+-----------------------------+-----------------------------+ |
d1a24f061 Minor Coding Styl... |
181 |
| | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 | |
e1fd16b6f mpc85xx: Enable u... |
182 |
|Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
183 |
| | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read | |
e1fd16b6f mpc85xx: Enable u... |
184 |
+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
185 186 187 |
| | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off | | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off | |
e1fd16b6f mpc85xx: Enable u... |
188 |
| Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
189 190 191 |
| | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off | | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off | |
e1fd16b6f mpc85xx: Enable u... |
192 |
+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
193 |
| | R1 | off | 75 | 40 | off | off | off | |
e1fd16b6f mpc85xx: Enable u... |
194 |
| Dual Rank |------------+-------+-------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
195 |
| | R2 | off | 75 | 40 | off | off | off | |
e1fd16b6f mpc85xx: Enable u... |
196 |
+-------------+------------+-------+-------+-------+------+-------+------+ |
d1a24f061 Minor Coding Styl... |
197 |
| Single Rank | R1 | off | 75 | 40 | off | |
e1fd16b6f mpc85xx: Enable u... |
198 199 200 |
+-------------+------------+-------+-------+-------+------+ Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf |
d1a24f061 Minor Coding Styl... |
201 |
http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf |
4e57382fa powerpc/mpc8xxx: ... |
202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 |
Table for ODT for DDR2 ====================== Two slots system +-----------------------+----------+---------------+-----------------------------+-----------------------------+ | Configuration | |DRAM controller| Slot 1 | Slot 2 | +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+ | | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 | + Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+ | | | | | | Write | Read | Write | Read | Write | Read | Write | Read | +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | off | off | | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | off | off | +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | | | | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | | | +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | | | Slot 1 | off | 150 | off | off | | | 75 | 75 | off | off | |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | | | Slot 2 | off | 150 | 75 | 75 | | | off | off | off | off | +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | | | Slot 1 | off | 150 | off | off | | | 75 | 75 | | | |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | | | Slot 2 | off | 150 | 75 | 75 | | | off | off | | | +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | Dual Rank | Empty | Slot 1 | off | 75 | 150 | off | off | off | | | | | +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | Empty | Dual Rank | Slot 2 | off | 75 | | | | | 150 | off | off | off | +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |Single Rank| Empty | Slot 1 | off | 75 | 150 | off | | | | | | | +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | Empty |Single Rank| Slot 2 | off | 75 | | | | | 150 | off | | | +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ Single slot system +-------------+------------+---------------+-----------------------------+ | | |DRAM controller| Rank 1 | Rank 2 | |Configuration| Write/Read |-------+-------+-------+------+-------+------+ | | | Write | Read | Write | Read | Write | Read | +-------------+------------+-------+-------+-------+------+-------+------+ | | R1 | off | 75 | 150 | off | off | off | | Dual Rank |------------+-------+-------+-------+------+-------+------+ | | R2 | off | 75 | 150 | off | off | off | +-------------+------------+-------+-------+-------+------+-------+------+ | Single Rank | R1 | off | 75 | 150 | off | +-------------+------------+-------+-------+-------+------+ Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf |
6f5e1dc53 powerpc/8xxx: Add... |
253 254 255 |
Interactive DDR debugging =========================== |
02a9ce718 README.fsl-ddr ty... |
256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 |
For DDR parameter tuning up and debugging, the interactive DDR debugger can be activated by setting the environment variable "ddr_interactive" to any value. (The value of ddr_interactive may have a meaning in the future, but, for now, the presence of the variable will cause the debugger to run.) Once activated, U-boot will show the prompt "FSL DDR>" before enabling the DDR controller. The available commands are printed by typing "help". Another way to enter the interactive DDR debugger without setting the environment variable is to send the 'd' character early during the boot process. To save booting time, no additional delay is added, so the window to send the key press is very short -- basically, it is the time before the memory controller code starts to run. For example, when rebooting from within u-boot, the user must press 'd' IMMEDIATELY after hitting enter to initiate a 'reset' command. In case of power on/reset, the user can hold down the 'd' key while applying power or hitting the board's reset button. |
e750cfaa0 powerpc/mpc8xxx: ... |
271 |
|
6f5e1dc53 powerpc/8xxx: Add... |
272 273 274 275 |
The example flow of using interactive debugging is type command "compute" to calculate the parameters from the default type command "print" with arguments to show SPD, options, registers type command "edit" with arguments to change any if desired |
5926ee380 Add copy command ... |
276 |
type command "copy" with arguments to copy controller/dimm settings |
6f5e1dc53 powerpc/8xxx: Add... |
277 |
type command "go" to continue calculation and enable DDR controller |
02a9ce718 README.fsl-ddr ty... |
278 279 |
Additional commands to restart the debugging are: |
6f5e1dc53 powerpc/8xxx: Add... |
280 281 282 283 284 |
type command "reset" to reset the board type command "recompute" to reload SPD and start over Note, check "next_step" to show the flow. For example, after edit opts, the next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is |
02a9ce718 README.fsl-ddr ty... |
285 286 287 |
STEP_PROGRAM_REGS. Upon issuing command "go", the debugger will program the DDR controller with the current setting without further calculation and then exit to resume the booting of the machine. |
6f5e1dc53 powerpc/8xxx: Add... |
288 289 290 291 292 293 294 |
The detail syntax for each commands are print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs] c<n> - the controller number, eg. c0, c1 d<n> - the DIMM number, eg. d0, d1 spd - print SPD data |
c46bf09e0 doc: Fix some typ... |
295 |
dimmparms - DIMM parameters, calculated from SPD |
6f5e1dc53 powerpc/8xxx: Add... |
296 297 298 299 300 301 302 303 304 |
commonparms - lowest common parameters for all DIMMs opts - options addresses - address assignment (not implemented yet) regs - controller registers edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value> c<n> - the controller number, eg. c0, c1 d<n> - the DIMM number, eg. d0, d1 spd - print SPD data |
c46bf09e0 doc: Fix some typ... |
305 |
dimmparms - DIMM parameters, calculated from SPD |
6f5e1dc53 powerpc/8xxx: Add... |
306 307 308 309 310 311 312 |
commonparms - lowest common parameters for all DIMMs opts - options addresses - address assignment (not implemented yet) regs - controller registers <element> - name of the modified element byte number if the object is SPD <value> - decimal or heximal (prefixed with 0x) numbers |
5926ee380 Add copy command ... |
313 314 315 |
copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#> same as for "edit" command DIMM numbers ignored for commonparms, opts, and regs |
6f5e1dc53 powerpc/8xxx: Add... |
316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 |
reset no arguement - reset the board recompute no argument - reload SPD and start over compute no argument - recompute from current next_step next_step no argument - show current next_step help no argument - print a list of all commands go no argument - program memory controller(s) and continue with U-boot Examples of debugging flow FSL DDR>compute Detected UDIMM UG51U6400N8SU-ACF |
02a9ce718 README.fsl-ddr ty... |
338 |
FSL DDR>print |
6f5e1dc53 powerpc/8xxx: Add... |
339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 |
print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs] FSL DDR>print dimmparms DIMM parameters: Controller=0 DIMM=0 DIMM organization parameters: module part name = UG51U6400N8SU-ACF rank_density = 2147483648 bytes (2048 megabytes) capacity = 4294967296 bytes (4096 megabytes) burst_lengths_bitmask = 0C base_addresss = 0 (00000000 00000000) n_ranks = 2 data_width = 64 primary_sdram_width = 64 ec_sdram_width = 0 registered_dimm = 0 n_row_addr = 15 n_col_addr = 10 edc_config = 0 n_banks_per_sdram_device = 8 tCKmin_X_ps = 1500 tCKmin_X_minus_1_ps = 0 tCKmin_X_minus_2_ps = 0 tCKmax_ps = 0 caslat_X = 960 tAA_ps = 13125 caslat_X_minus_1 = 0 caslat_X_minus_2 = 0 caslat_lowest_derated = 0 tRCD_ps = 13125 tRP_ps = 13125 tRAS_ps = 36000 tWR_ps = 15000 tWTR_ps = 7500 tRFC_ps = 160000 tRRD_ps = 6000 tRC_ps = 49125 refresh_rate_ps = 7800000 tIS_ps = 0 tIH_ps = 0 tDS_ps = 0 tDH_ps = 0 tRTP_ps = 7500 tDQSQ_max_ps = 0 tQHS_ps = 0 FSL DDR>edit c0 opts ECC_mode 0 FSL DDR>edit c0 regs cs0_bnds 0x000000FF FSL DDR>go 2 GiB left unmapped 4 GiB (DDR3, 64-bit, CL=9, ECC off) DDR Chip-Select Interleaving Mode: CS0+CS1 Testing 0x00000000 - 0x7fffffff Testing 0x80000000 - 0xffffffff Remap DDR 2 GiB left unmapped POST memory PASSED Flash: 128 MiB L2: 128 KB enabled Corenet Platform Cache: 1024 KB enabled SERDES: timeout resetting bank 3 SRIO1: disabled SRIO2: disabled MMC: FSL_ESDHC: 0 EEPROM: Invalid ID (ff ff ff ff) PCIe1: disabled PCIe2: Root Complex, x1, regs @ 0xfe201000 01:00.0 - 8086:10d3 - Network controller PCIe2: Bus 00 - 01 PCIe3: disabled In: serial Out: serial Err: serial Net: Initializing Fman Fman1: Uploading microcode version 101.8.0 e1000: 00:1b:21:81:d2:e0 FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME] Warning: e1000#0 MAC addresses don't match: Address in SROM is 00:1b:21:81:d2:e0 Address in environment is 00:e0:0c:00:ea:05 Hit any key to stop autoboot: 0 => |