Eric Lee / smarc-uboot

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Commit c46bf09e0b567dda477da53163fe646e66c4912e

Authored by Thomas Weber
Committed by Anatolij Gustschin
1 parent 7e71dc6884
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

doc: Fix some typos in different files 

adresses/addresses
alernate/alternate
asssuming/assuming
calcualted/calculated
enviroment/environment
evalutation/evaluation
falsh/flash
labled/labeled
paramaters/parameters

Signed-off-by: Thomas Weber <thomas@tomweber.eu>
Acked-by: Anatolij Gustschin <agust@denx.de>

Showing 17 changed files with 26 additions and 26 deletions Side-by-side Diff

doc/README.AVR32-port-muxing
Diff comments   View file @ c46bf09
... ... @@ -91,7 +91,7 @@
91 91 PORTMUX_DIR_OUTPUT
92 92 PORTMUX_DIR_INPUT
93 93  
94   -These mutually-exlusive flags configure the initial direction of the
  94 +These mutually-exclusive flags configure the initial direction of the
95 95 pins. PORTMUX_DIR_OUTPUT means that the pins are driven by the CPU,
96 96 while PORTMUX_DIR_INPUT means that the pins are tristated by the CPU.
97 97 These flags are ignored by portmux_select_peripheral().
... ... @@ -125,7 +125,7 @@
125 125 PORTMUX_DRIVE_HIGH
126 126 PORTMUX_DRIVE_MAX
127 127  
128   -These mutually-exlusive flags determine the drive strength of the
  128 +These mutually-exclusive flags determine the drive strength of the
129 129 pins. PORTMUX_DRIVE_MIN will give low power-consumption, but may cause
130 130 corruption of high-speed signals. PORTMUX_DRIVE_MAX will give high
131 131 power-consumption, but may be necessary on pins toggling at very high
... ... @@ -6,7 +6,7 @@
6 6 parameter of server's IP address or environment variable
7 7 "ntpserverip". The network time is sent as UTC. So if you want to
8 8 set local time to RTC, set the offset in second from UTC to the
9   -enviroment variable "time offset".
  9 +environment variable "time offset".
10 10  
11 11 If the DHCP server provides time server's IP or time offset, you
12 12 don't need to set the above environment variables yourself.
doc/README.Sandpoint8240
Diff comments   View file @ c46bf09
... ... @@ -236,7 +236,7 @@
236 236 => setenv serverip 192.168.0.10
237 237 => setenv gatewayip=192.168.0.1
238 238 => saveenv
239   -Saving Enviroment to Flash...
  239 +Saving Environment to Flash...
240 240 Un-Protected 1 sectors
241 241 Erasing Flash...
242 242 done
... ... @@ -296,7 +296,7 @@
296 296 => cp.b 0x100000 FFF00000 1f28c
297 297 Copy to Flash... done
298 298 => saveenv
299   -Saving Enviroment to Flash...
  299 +Saving Environment to Flash...
300 300 Un-Protected 1 sectors
301 301 Erasing Flash...
302 302 done
... ... @@ -330,7 +330,7 @@
330 330 done
331 331 Erased 7 sectors
332 332 Copy to Flash... done
333   -Saving Enviroment to Flash...
  333 +Saving Environment to Flash...
334 334 Un-Protected 1 sectors
335 335 Erasing Flash...
336 336 done
... ... @@ -62,16 +62,16 @@
62 62 U-Boot environment variables can be stored at different places:
63 63 - Dataflash on SPI chip select 0 (dataflash card)
64 64 - Nand flash.
65   - - Nor falsh (not populate by default)
  65 + - Nor flash (not populate by default)
66 66  
67 67 You can choose your storage location at config step (here for at91sam9260ek) :
68 68 make at91sam9263ek_config - use data flash (spi cs0) (default)
69 69 make at91sam9263ek_nandflash_config - use nand flash
70 70 make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0)
71   - make at91sam9263ek_norflash_config - use nor falsh
  71 + make at91sam9263ek_norflash_config - use nor flash
72 72  
73 73 You can choose to boot directly from U-Boot at config step
74   - make at91sam9263ek_norflash_boot_config - boot from nor falsh
  74 + make at91sam9263ek_norflash_boot_config - boot from nor flash
75 75  
76 76  
77 77 ------------------------------------------------------------------------------
... ... @@ -4,7 +4,7 @@
4 4 =======================================================================
5 5  
6 6 This file contains some handy info regarding U-Boot and the AMCC
7   -Ebony evalutation board. See the README.ppc440 for additional
  7 +Ebony evaluation board. See the README.ppc440 for additional
8 8 information.
9 9  
10 10  
... ... @@ -250,7 +250,7 @@
250 250 c<n> - the controller number, eg. c0, c1
251 251 d<n> - the DIMM number, eg. d0, d1
252 252 spd - print SPD data
253   - dimmparms - DIMM paramaters, calcualted from SPD
  253 + dimmparms - DIMM parameters, calculated from SPD
254 254 commonparms - lowest common parameters for all DIMMs
255 255 opts - options
256 256 addresses - address assignment (not implemented yet)
... ... @@ -260,7 +260,7 @@
260 260 c<n> - the controller number, eg. c0, c1
261 261 d<n> - the DIMM number, eg. d0, d1
262 262 spd - print SPD data
263   - dimmparms - DIMM paramaters, calcualted from SPD
  263 + dimmparms - DIMM parameters, calculated from SPD
264 264 commonparms - lowest common parameters for all DIMMs
265 265 opts - options
266 266 addresses - address assignment (not implemented yet)
doc/README.mpc832xemds
Diff comments   View file @ c46bf09
... ... @@ -15,7 +15,7 @@
15 15 "On" == 0
16 16  
17 17 SW3 is switch 18 as silk-screened onto the board.
18   - SW4[8] is the bit labled 8 on Switch 4.
  18 + SW4[8] is the bit labeled 8 on Switch 4.
19 19 SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
20 20 SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
21 21 SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
doc/README.mpc8360emds
Diff comments   View file @ c46bf09
... ... @@ -15,7 +15,7 @@
15 15 "On" == 0
16 16  
17 17 SW18 is switch 18 as silk-screened onto the board.
18   - SW4[8] is the bit labled 8 on Switch 4.
  18 + SW4[8] is the bit labeled 8 on Switch 4.
19 19 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
20 20 SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
21 21 SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
doc/README.mpc837xemds
Diff comments   View file @ c46bf09
... ... @@ -14,7 +14,7 @@
14 14 "Off" == 1
15 15 "On" == 0
16 16  
17   - SW4[8] is the bit labled 8 on Switch 4.
  17 + SW4[8] is the bit labeled 8 on Switch 4.
18 18 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
19 19 SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
20 20 and bits labeled 8 is set as "Off".
doc/README.mpc8544ds
Diff comments   View file @ c46bf09
... ... @@ -22,7 +22,7 @@
22 22 Memory Map
23 23 ----------
24 24  
25   -0xff80_0000 - 0xffbf_ffff Alernate bank 4MB
  25 +0xff80_0000 - 0xffbf_ffff Alternate bank 4MB
26 26 0xffc0_0000 - 0xffff_ffff Boot bank 4MB
27 27  
28 28 0xffb8_0000 Alternate image start 512KB
doc/README.mpc8572ds
Diff comments   View file @ c46bf09
... ... @@ -19,7 +19,7 @@
19 19 Memory Map
20 20 ----------
21 21  
22   -0xe800_0000 - 0xebff_ffff Alernate bank 64MB
  22 +0xe800_0000 - 0xebff_ffff Alternate bank 64MB
23 23 0xec00_0000 - 0xefff_ffff Boot bank 64MB
24 24  
25 25 0xebf8_0000 - 0xebff_ffff Alternate u-boot address 512KB
... ... @@ -115,7 +115,7 @@
115 115 - Select "Advanced setup" -> " Prompt for advanced kernel
116 116 configuration options"
117 117 - Select "Set physical address where the kernel is loaded" and
118   - set it to 0x20000000, asssuming core1 will start from 512MB.
  118 + set it to 0x20000000, assuming core1 will start from 512MB.
119 119 - Select "Set custom page offset address"
120 120 - Select "Set custom kernel base address"
121 121 - Select "Set maximum low memory"
doc/README.mpc85xxads
Diff comments   View file @ c46bf09
... ... @@ -35,7 +35,7 @@
35 35 "On" == 0
36 36  
37 37 SW18 is switch 18 as silk-screened onto the board.
38   - SW4[8] is the bit labled 8 on Switch 4.
  38 + SW4[8] is the bit labeled 8 on Switch 4.
39 39 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2
40 40 SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3
41 41  
... ... @@ -33,7 +33,7 @@
33 33 2.4 I2C
34 34 LM75 @ 0x90 for temperature monitoring.
35 35 EEPROM @ 0xA0 for vendor specifics.
36   - image sensor interface (slave adresses depend on sensor)
  36 + image sensor interface (slave addresses depend on sensor)
37 37  
38 38 3 Flash layout.
39 39  
... ... @@ -40,10 +40,10 @@
40 40 MAX5381 DAC @ 0x60 for 1st digital input threshold.
41 41 LM75 @ 0x90 for temperature monitoring.
42 42 EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
43   - 1st image sensor interface (slave adresses depend on sensor)
  43 + 1st image sensor interface (slave addresses depend on sensor)
44 44 Bus2:
45 45 MAX5381 DAC @ 0x60 for 2nd digital input threshold.
46   - 2nd image sensor interface (slave adresses depend on sensor)
  46 + 2nd image sensor interface (slave addresses depend on sensor)
47 47  
48 48 3 Flash layout.
49 49  
... ... @@ -23,7 +23,7 @@
23 23  
24 24 2.4 I2C
25 25 EEPROM @ 0xA0 for vendor specifics.
26   - image sensor interface (slave adresses depend on sensor)
  26 + image sensor interface (slave addresses depend on sensor)
27 27  
28 28 3 Flash layout.
29 29  
... ... @@ -4,7 +4,7 @@
4 4 =======================================================================
5 5  
6 6 This file contains some handy info regarding U-Boot and the AMCC
7   -Ocotea 440gx evalutation board. See the README.ppc440 for additional
  7 +Ocotea 440gx evaluation board. See the README.ppc440 for additional
8 8 information.
9 9  
10 10  
... ... @@ -17,7 +17,7 @@
17 17  
18 18 Memory Map
19 19 ----------
20   -0xef00_0000 - 0xef7f_ffff Alernate bank 8MB
  20 +0xef00_0000 - 0xef7f_ffff Alternate bank 8MB
21 21 0xe800_0000 - 0xefff_ffff Boot bank 8MB
22 22  
23 23 0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB
... ... @@ -89,7 +89,7 @@
89 89 "Prompt for advanced kernel configuration options"
90 90 - Select
91 91 "Set physical address where the kernel is loaded"
92   - and set it to 0x20000000, asssuming core1 will
  92 + and set it to 0x20000000, assuming core1 will
93 93 start from 512MB.
94 94 - Select "Set custom page offset address"
95 95 - Select "Set custom kernel base address"