powerpc/8xxx: Enabled address hashing for 85xx

For 85xx silicon which supports address hashing, it can be activated by hwconfig. Signed-off-by: York Sun <yorksun@freescale.com>

powerpc/8xxx: Enabled address hashing for 85xx
For 85xx silicon which supports address hashing, it can be activated by hwconfig. Signed-off-by: York Sun <yorksun@freescale.com>
york · Kumar Gala
1 parent 5800e7ab32
Showing 5 changed files with 34 additions and 2 deletions Side-by-side Diff
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
arch/powerpc/cpu/mpc8xxx/ddr/options.c
arch/powerpc/include/asm/fsl_ddr_sdram.h
doc/README.fsl-ddr
@@ -33,6 +33,8 @@
 		return;
 	}
  
+	out_be32(&ddr->eor, regs->ddr_eor);
+
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		if (i == 0) {
 			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
@@ -1161,6 +1161,14 @@
 				);
 }
  
+static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
+{
+	if (popts->addr_hash) {
+		ddr->ddr_eor = 0x40000000;	/* address hash enable */
+		puts("Addess hashing enabled.\n");
+	}
+}
+
 unsigned int
 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 {
@@ -1391,6 +1399,8 @@
 		set_csn_config(dimm_number, i, ddr, popts, dimm_params);
 		set_csn_config_2(i, ddr);
 	}
+
+	set_ddr_eor(ddr, popts);
  
 #if !defined(CONFIG_FSL_DDR1)
 	set_timing_cfg_0(ddr);
@@ -341,6 +341,13 @@
 		}
 	}
  
+	if (hwconfig_sub("fsl_ddr", "addr_hash")) {
+		if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "null"))
+			popts->addr_hash = 0;
+		else if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "true"))
+			popts->addr_hash = 1;
+	}
+
 	if (pdimm[0].n_ranks == 4)
 		popts->quad_rank_present = 1;
  
@@ -119,6 +119,7 @@
 	unsigned int ddr_sr_cntr;
 	unsigned int ddr_sdram_rcw_1;
 	unsigned int ddr_sdram_rcw_2;
+	unsigned int ddr_eor;
 } fsl_ddr_cfg_regs_t;
  
 typedef struct memctl_options_partial_s {
@@ -156,6 +157,7 @@
 	unsigned int memctl_interleaving;
 	unsigned int memctl_interleaving_mode;
 	unsigned int ba_intlv_ctl;
+	unsigned int addr_hash;
  
 	/* Operational mode parameters */
 	unsigned int ECC_mode;	 /* Use ECC? */
@@ -71,6 +71,17 @@
   # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
   setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
  
-  The above memory controller interleaving and bank interleaving can be mixed. The syntax is
-  setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1"
+Memory controller address hashing
+==================================
+If the DDR controller supports address hashing, it can be enabled by hwconfig.
+
+Syntax is:
+hwconfig=fsl_ddr:addr_hash=true
+
+Combination of hwconfig
+=======================
+Hwconfig can be combined with multiple parameters, for example, on a supported
+platform
+
+hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3
...	...	@@ -33,6 +33,8 @@
33	33	return;
34	34	}
35	35
	36	+ out_be32(&ddr->eor, regs->ddr_eor);
	37	+
36	38	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
37	39	if (i == 0) {
38	40	out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
...	...	@@ -1161,6 +1161,14 @@
1161	1161	);
1162	1162	}
1163	1163
	1164	+static void set_ddr_eor(fsl_ddr_cfg_regs_t ddr, const memctl_options_t popts)
	1165	+{
	1166	+ if (popts->addr_hash) {
	1167	+ ddr->ddr_eor = 0x40000000; /* address hash enable */
	1168	+ puts("Addess hashing enabled.\n");
	1169	+ }
	1170	+}
	1171	+
1164	1172	unsigned int
1165	1173	check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1166	1174	{
...	...	@@ -1391,6 +1399,8 @@
1391	1399	set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1392	1400	set_csn_config_2(i, ddr);
1393	1401	}
	1402	+
	1403	+ set_ddr_eor(ddr, popts);
1394	1404
1395	1405	#if !defined(CONFIG_FSL_DDR1)
1396	1406	set_timing_cfg_0(ddr);
...	...	@@ -341,6 +341,13 @@
341	341	}
342	342	}
343	343
	344	+ if (hwconfig_sub("fsl_ddr", "addr_hash")) {
	345	+ if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "null"))
	346	+ popts->addr_hash = 0;
	347	+ else if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "true"))
	348	+ popts->addr_hash = 1;
	349	+ }
	350	+
344	351	if (pdimm[0].n_ranks == 4)
345	352	popts->quad_rank_present = 1;
346	353
...	...	@@ -119,6 +119,7 @@
119	119	unsigned int ddr_sr_cntr;
120	120	unsigned int ddr_sdram_rcw_1;
121	121	unsigned int ddr_sdram_rcw_2;
	122	+ unsigned int ddr_eor;
122	123	} fsl_ddr_cfg_regs_t;
123	124
124	125	typedef struct memctl_options_partial_s {
...	...	@@ -156,6 +157,7 @@
156	157	unsigned int memctl_interleaving;
157	158	unsigned int memctl_interleaving_mode;
158	159	unsigned int ba_intlv_ctl;
	160	+ unsigned int addr_hash;
159	161
160	162	/* Operational mode parameters */
161	163	unsigned int ECC_mode; /* Use ECC? */
...	...	@@ -71,6 +71,17 @@
71	71	# bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
72	72	setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
73	73
74		- The above memory controller interleaving and bank interleaving can be mixed. The syntax is
75		- setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1"
	74	+Memory controller address hashing
	75	+==================================
	76	+If the DDR controller supports address hashing, it can be enabled by hwconfig.
	77	+
	78	+Syntax is:
	79	+hwconfig=fsl_ddr:addr_hash=true
	80	+
	81	+Combination of hwconfig
	82	+=======================
	83	+Hwconfig can be combined with multiple parameters, for example, on a supported
	84	+platform
	85	+
	86	+hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3