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arch/arm/include/asm/mach-imx/regs-bch.h 9.08 KB

83d290c56 Tom Rini SPDX: Convert all...	1	/* SPDX-License-Identifier: GPL-2.0+ */
6e9a0a396 Marek Vasut iMX28: Initial su...	2 3 4 5 6 7 8	/* * Freescale i.MX28 BCH Register Definitions * * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> * on behalf of DENX Software Engineering GmbH * * Based on code from LTIB:
722f0ff0b Peng Fan MLK-12693-2 nand:...	9	* Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved.
a9f0815c2 Han Xu MLK-16034-02: ena...	10	* Copyright 2017 NXP
722f0ff0b Peng Fan MLK-12693-2 nand:...	11	*
6e9a0a396 Marek Vasut iMX28: Initial su...	12 13 14 15	*/ #ifndef __MX28_REGS_BCH_H__ #define __MX28_REGS_BCH_H__
552a848e4 Stefano Babic imx: reorganize I...	16	#include <asm/mach-imx/regs-common.h>
6e9a0a396 Marek Vasut iMX28: Initial su...	17 18	#ifndef __ASSEMBLY__
9c471142b Otavio Salvador mxs: prefix regis...	19	struct mxs_bch_regs {
ddcf13b15 Otavio Salvador mxs: prefix regis...	20 21 22 23 24 25	mxs_reg_32(hw_bch_ctrl) mxs_reg_32(hw_bch_status0) mxs_reg_32(hw_bch_mode) mxs_reg_32(hw_bch_encodeptr) mxs_reg_32(hw_bch_dataptr) mxs_reg_32(hw_bch_metaptr)
6e9a0a396 Marek Vasut iMX28: Initial su...	26 27	uint32_t reserved[4];
ddcf13b15 Otavio Salvador mxs: prefix regis...	28 29 30 31 32 33 34 35 36	mxs_reg_32(hw_bch_layoutselect) mxs_reg_32(hw_bch_flash0layout0) mxs_reg_32(hw_bch_flash0layout1) mxs_reg_32(hw_bch_flash1layout0) mxs_reg_32(hw_bch_flash1layout1) mxs_reg_32(hw_bch_flash2layout0) mxs_reg_32(hw_bch_flash2layout1) mxs_reg_32(hw_bch_flash3layout0) mxs_reg_32(hw_bch_flash3layout1)
cf02f888e Han Xu MLK-22827-1: mxs_...	37	mxs_reg_32(hw_bch_debug0)
ddcf13b15 Otavio Salvador mxs: prefix regis...	38 39 40 41 42 43	mxs_reg_32(hw_bch_dbgkesread) mxs_reg_32(hw_bch_dbgcsferead) mxs_reg_32(hw_bch_dbgsyndegread) mxs_reg_32(hw_bch_dbgahbmread) mxs_reg_32(hw_bch_blockname) mxs_reg_32(hw_bch_version)
722f0ff0b Peng Fan MLK-12693-2 nand:...	44	mxs_reg_32(hw_bch_debug1)
6e9a0a396 Marek Vasut iMX28: Initial su...	45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79	}; #endif #define BCH_CTRL_SFTRST (1 << 31) #define BCH_CTRL_CLKGATE (1 << 30) #define BCH_CTRL_DEBUGSYNDROME (1 << 22) #define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18) #define BCH_CTRL_M2M_LAYOUT_OFFSET 18 #define BCH_CTRL_M2M_ENCODE (1 << 17) #define BCH_CTRL_M2M_ENABLE (1 << 16) #define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10) #define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8) #define BCH_CTRL_BM_ERROR_IRQ (1 << 3) #define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2) #define BCH_CTRL_COMPLETE_IRQ (1 << 0) #define BCH_STATUS0_HANDLE_MASK (0xfff << 20) #define BCH_STATUS0_HANDLE_OFFSET 20 #define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16) #define BCH_STATUS0_COMPLETED_CE_OFFSET 16 #define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8) #define BCH_STATUS0_STATUS_BLK0_OFFSET 8 #define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8) #define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8) #define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8) #define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8) #define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8) #define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8) #define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8) #define BCH_STATUS0_ALLONES (1 << 4) #define BCH_STATUS0_CORRECTED (1 << 3) #define BCH_STATUS0_UNCORRECTABLE (1 << 2) #define BCH_MODE_ERASE_THRESHOLD_MASK 0xff #define BCH_MODE_ERASE_THRESHOLD_OFFSET 0
722f0ff0b Peng Fan MLK-12693-2 nand:...	80 81 82	#define BCH_MODE_ERASE_THRESHOLD(v) \ (((v) << BCH_MODE_ERASE_THRESHOLD_OFFSET) & \ BCH_MODE_ERASE_THRESHOLD_MASK)
6e9a0a396 Marek Vasut iMX28: Initial su...	83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129	#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff #define BCH_ENCODEPTR_ADDR_OFFSET 0 #define BCH_DATAPTR_ADDR_MASK 0xffffffff #define BCH_DATAPTR_ADDR_OFFSET 0 #define BCH_METAPTR_ADDR_MASK 0xffffffff #define BCH_METAPTR_ADDR_OFFSET 0 #define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30) #define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30 #define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28) #define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28 #define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26) #define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26 #define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24) #define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24 #define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22) #define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22 #define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20) #define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20 #define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18) #define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18 #define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16) #define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16 #define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14) #define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14 #define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12) #define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12 #define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10) #define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10 #define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8) #define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8 #define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6) #define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6 #define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4) #define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4 #define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2) #define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2 #define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0) #define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0 #define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24) #define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 #define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) #define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
a9f0815c2 Han Xu MLK-16034-02: ena...	130	#if (defined(CONFIG_MX6) \|\| defined(CONFIG_MX7) \|\| defined(CONFIG_IMX8) \|\| defined(CONFIG_IMX8M))
ae695b18d Stefan Roese mtd: mxs_nand: Ad...	131 132 133	#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11) #define BCH_FLASHLAYOUT0_ECC0_OFFSET 11 #else
6e9a0a396 Marek Vasut iMX28: Initial su...	134 135	#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12) #define BCH_FLASHLAYOUT0_ECC0_OFFSET 12
ae695b18d Stefan Roese mtd: mxs_nand: Ad...	136	#endif
6e9a0a396 Marek Vasut iMX28: Initial su...	137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153	#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12)
644f70768 Han Xu MLK-22723-1: mtd:...	154	#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_MASK (1 << 10)
63b29d808 Peng Fan mtd: nand: mxs su...	155	#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET 10
644f70768 Han Xu MLK-22723-1: mtd:...	156	#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0x3ff
6e9a0a396 Marek Vasut iMX28: Initial su...	157 158 159 160	#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 #define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) #define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
a9f0815c2 Han Xu MLK-16034-02: ena...	161	#if (defined(CONFIG_MX6) \|\| defined(CONFIG_MX7) \|\| defined(CONFIG_IMX8) \|\| defined(CONFIG_IMX8M))
ae695b18d Stefan Roese mtd: mxs_nand: Ad...	162 163 164	#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11) #define BCH_FLASHLAYOUT1_ECCN_OFFSET 11 #else
6e9a0a396 Marek Vasut iMX28: Initial su...	165 166	#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12) #define BCH_FLASHLAYOUT1_ECCN_OFFSET 12
ae695b18d Stefan Roese mtd: mxs_nand: Ad...	167	#endif
6e9a0a396 Marek Vasut iMX28: Initial su...	168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184	#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12)
644f70768 Han Xu MLK-22723-1: mtd:...	185	#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK (1 << 10)
63b29d808 Peng Fan mtd: nand: mxs su...	186	#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET 10
644f70768 Han Xu MLK-22723-1: mtd:...	187	#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0x3ff
6e9a0a396 Marek Vasut iMX28: Initial su...	188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233	#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 #define BCH_DEBUG0_RSVD1_MASK (0x1f << 27) #define BCH_DEBUG0_RSVD1_OFFSET 27 #define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26) #define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25) #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16) #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16) #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16) #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15) #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14) #define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13) #define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12) #define BCH_DEBUG0_KES_STANDALONE (1 << 11) #define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10) #define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9) #define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8) #define BCH_DEBUG0_RSVD0_MASK (0x3 << 6) #define BCH_DEBUG0_RSVD0_OFFSET 6 #define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f #define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0 #define BCH_DBGKESREAD_VALUES_MASK 0xffffffff #define BCH_DBGKESREAD_VALUES_OFFSET 0 #define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff #define BCH_DBGCSFEREAD_VALUES_OFFSET 0 #define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff #define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0 #define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff #define BCH_DBGAHBMREAD_VALUES_OFFSET 0 #define BCH_BLOCKNAME_NAME_MASK 0xffffffff #define BCH_BLOCKNAME_NAME_OFFSET 0 #define BCH_VERSION_MAJOR_MASK (0xff << 24) #define BCH_VERSION_MAJOR_OFFSET 24 #define BCH_VERSION_MINOR_MASK (0xff << 16) #define BCH_VERSION_MINOR_OFFSET 16 #define BCH_VERSION_STEP_MASK 0xffff #define BCH_VERSION_STEP_OFFSET 0 #endif /* __MX28_REGS_BCH_H__ */