Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit ae695b18df7c19ec3d062e36c1c25864096146f8

Authored by Stefan Roese
Committed by Stefano Babic
1 parent 99193e30b4
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

mtd: mxs_nand: Add support for i.MX6 

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>

Showing 3 changed files with 26 additions and 2 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ ae695b1
... ... @@ -30,6 +30,7 @@
30 30 #include <asm/arch/clock.h>
31 31 #include <asm/arch/sys_proto.h>
32 32 #include <asm/imx-common/boot_mode.h>
  33 +#include <asm/imx-common/dma.h>
33 34 #include <stdbool.h>
34 35  
35 36 struct scu_regs {
... ... @@ -151,6 +152,12 @@
151 152 set_vddsoc(1200); /* Set VDDSOC to 1.2V */
152 153  
153 154 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
  155 +
  156 +#ifdef CONFIG_APBH_DMA
  157 + /* Start APBH DMA */
  158 + mxs_dma_init();
  159 +#endif
  160 +
154 161 return 0;
155 162 }
156 163  
arch/arm/include/asm/imx-common/regs-bch.h
Diff comments   View file @ ae695b1
... ... @@ -136,8 +136,13 @@
136 136 #define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
137 137 #define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
138 138 #define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
  139 +#if defined(CONFIG_MX6)
  140 +#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
  141 +#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
  142 +#else
139 143 #define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12)
140 144 #define BCH_FLASHLAYOUT0_ECC0_OFFSET 12
  145 +#endif
141 146 #define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12)
142 147 #define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12)
143 148 #define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12)
144 149  
... ... @@ -161,8 +166,13 @@
161 166  
162 167 #define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
163 168 #define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
  169 +#if defined(CONFIG_MX6)
  170 +#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
  171 +#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
  172 +#else
164 173 #define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12)
165 174 #define BCH_FLASHLAYOUT1_ECCN_OFFSET 12
  175 +#endif
166 176 #define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12)
167 177 #define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12)
168 178 #define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12)
drivers/mtd/nand/mxs_nand.c
Diff comments   View file @ ae695b1
... ... @@ -42,6 +42,11 @@
42 42 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
43 43  
44 44 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
  45 +#if defined(CONFIG_MX6)
  46 +#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
  47 +#else
  48 +#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
  49 +#endif
45 50 #define MXS_NAND_METADATA_SIZE 10
46 51  
47 52 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
48 53  
... ... @@ -982,14 +987,16 @@
982 987 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
983 988 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
984 989 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
985   - tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
  990 + tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
  991 + >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
986 992 writel(tmp, &bch_regs->hw_bch_flash0layout0);
987 993  
988 994 tmp = (mtd->writesize + mtd->oobsize)
989 995 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
990 996 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
991 997 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
992   - tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
  998 + tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
  999 + >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
993 1000 writel(tmp, &bch_regs->hw_bch_flash0layout1);
994 1001  
995 1002 /* Set *all* chip selects to use layout 0 */