mxs: Add MX23 quirks into the clock code

The MX23 has different handling of the SSP clock and GPMI NAND clock sources, add necessary quirks into the clock code to properly handle these. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>

mxs: Add MX23 quirks into the clock code
The MX23 has different handling of the SSP clock and GPMI NAND clock sources, add necessary quirks into the clock code to properly handle these. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
Otavio Salvador · Stefano Babic
1 parent 4750953ed9
Showing 2 changed files with 32 additions and 11 deletions Side-by-side Diff
arch/arm/cpu/arm926ejs/mxs/clock.c
arch/arm/include/asm/arch-mxs/clock.h
 /*
- * Freescale i.MX28 clock setup code
+ * Freescale i.MX23/i.MX28 clock setup code
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
  
  
@@ -32,15 +32,24 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
  
-/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */
+/*
+ * The PLL frequency is 480MHz and XTAL frequency is 24MHz
+ *   iMX23: datasheet section 4.2
+ *   iMX28: datasheet section 10.2
+ */
 #define	PLL_FREQ_KHZ	480000
 #define	PLL_FREQ_COEF	18
-/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */
 #define	XTAL_FREQ_KHZ	24000
  
 #define	PLL_FREQ_MHZ	(PLL_FREQ_KHZ / 1000)
 #define	XTAL_FREQ_MHZ	(XTAL_FREQ_KHZ / 1000)
  
+#if defined(CONFIG_MX23)
+#define MXC_SSPCLK_MAX MXC_SSPCLK0
+#elif defined(CONFIG_MX28)
+#define MXC_SSPCLK_MAX MXC_SSPCLK3
+#endif
+
 static uint32_t mxs_get_pclk(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
@@ -120,7 +129,13 @@
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-
+#if defined(CONFIG_MX23)
+	uint8_t *reg =
+		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
+#elif defined(CONFIG_MX28)
+	uint8_t *reg =
+		&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
+#endif
 	uint32_t clkctrl, clkseq, div;
 	uint8_t clkfrac, frac;
  
@@ -134,7 +149,7 @@
 	}
  
 	/* REF Path */
-	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]);
+	clkfrac = readb(reg);
 	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
 	div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
@@ -203,7 +218,7 @@
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint32_t clk, clkreg;
  
-	if (ssp > MXC_SSPCLK3)
+	if (ssp > MXC_SSPCLK_MAX)
 		return;
  
 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
@@ -248,7 +263,7 @@
 	uint32_t clkreg;
 	uint32_t clk, tmp;
  
-	if (ssp > MXC_SSPCLK3)
+	if (ssp > MXC_SSPCLK_MAX)
 		return 0;
  
 	tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
  
  
@@ -325,16 +340,18 @@
 		return mxs_get_ioclk(MXC_IOCLK0);
 	case MXC_IO1_CLK:
 		return mxs_get_ioclk(MXC_IOCLK1);
+	case MXC_XTAL_CLK:
+		return XTAL_FREQ_KHZ * 1000;
 	case MXC_SSP0_CLK:
 		return mxs_get_sspclk(MXC_SSPCLK0);
+#ifdef CONFIG_MX28
 	case MXC_SSP1_CLK:
 		return mxs_get_sspclk(MXC_SSPCLK1);
 	case MXC_SSP2_CLK:
 		return mxs_get_sspclk(MXC_SSPCLK2);
 	case MXC_SSP3_CLK:
 		return mxs_get_sspclk(MXC_SSPCLK3);
-	case MXC_XTAL_CLK:
-		return XTAL_FREQ_KHZ * 1000;
+#endif
 	}
  
 	return 0;
 /*
- * Freescale i.MX28 Clock
+ * Freescale i.MX23/i.MX28 Clock
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
  
  
@@ -31,11 +31,13 @@
 	MXC_GPMI_CLK,
 	MXC_IO0_CLK,
 	MXC_IO1_CLK,
+	MXC_XTAL_CLK,
 	MXC_SSP0_CLK,
+#ifdef CONFIG_MX28
 	MXC_SSP1_CLK,
 	MXC_SSP2_CLK,
 	MXC_SSP3_CLK,
-	MXC_XTAL_CLK,
+#endif
 };
  
 enum mxs_ioclock {
  
@@ -45,9 +47,11 @@
  
 enum mxs_sspclock {
 	MXC_SSPCLK0 = 0,
+#ifdef CONFIG_MX28
 	MXC_SSPCLK1,
 	MXC_SSPCLK2,
 	MXC_SSPCLK3,
+#endif
 };
  
 uint32_t mxc_get_clock(enum mxc_clock clk);
1	1	/*
2		- * Freescale i.MX28 clock setup code
	2	+ * Freescale i.MX23/i.MX28 clock setup code
3	3	*
4	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5	5	* on behalf of DENX Software Engineering GmbH
6	6
7	7
...	...	@@ -32,15 +32,24 @@
32	32	#include <asm/arch/clock.h>
33	33	#include <asm/arch/imx-regs.h>
34	34
35		-/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */
	35	+/*
	36	+ * The PLL frequency is 480MHz and XTAL frequency is 24MHz
	37	+ * iMX23: datasheet section 4.2
	38	+ * iMX28: datasheet section 10.2
	39	+ */
36	40	#define PLL_FREQ_KHZ 480000
37	41	#define PLL_FREQ_COEF 18
38		-/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */
39	42	#define XTAL_FREQ_KHZ 24000
40	43
41	44	#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
42	45	#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
43	46
	47	+#if defined(CONFIG_MX23)
	48	+#define MXC_SSPCLK_MAX MXC_SSPCLK0
	49	+#elif defined(CONFIG_MX28)
	50	+#define MXC_SSPCLK_MAX MXC_SSPCLK3
	51	+#endif
	52	+
44	53	static uint32_t mxs_get_pclk(void)
45	54	{
46	55	struct mxs_clkctrl_regs *clkctrl_regs =
...	...	@@ -120,7 +129,13 @@
120	129	{
121	130	struct mxs_clkctrl_regs *clkctrl_regs =
122	131	(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
123		-
	132	+#if defined(CONFIG_MX23)
	133	+ uint8_t *reg =
	134	+ &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
	135	+#elif defined(CONFIG_MX28)
	136	+ uint8_t *reg =
	137	+ &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
	138	+#endif
124	139	uint32_t clkctrl, clkseq, div;
125	140	uint8_t clkfrac, frac;
126	141
...	...	@@ -134,7 +149,7 @@
134	149	}
135	150
136	151	/* REF Path */
137		- clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]);
	152	+ clkfrac = readb(reg);
138	153	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
139	154	div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
140	155	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
...	...	@@ -203,7 +218,7 @@
203	218	(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
204	219	uint32_t clk, clkreg;
205	220
206		- if (ssp > MXC_SSPCLK3)
	221	+ if (ssp > MXC_SSPCLK_MAX)
207	222	return;
208	223
209	224	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
...	...	@@ -248,7 +263,7 @@
248	263	uint32_t clkreg;
249	264	uint32_t clk, tmp;
250	265
251		- if (ssp > MXC_SSPCLK3)
	266	+ if (ssp > MXC_SSPCLK_MAX)
252	267	return 0;
253	268
254	269	tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
255	270
256	271
...	...	@@ -325,16 +340,18 @@
325	340	return mxs_get_ioclk(MXC_IOCLK0);
326	341	case MXC_IO1_CLK:
327	342	return mxs_get_ioclk(MXC_IOCLK1);
	343	+ case MXC_XTAL_CLK:
	344	+ return XTAL_FREQ_KHZ * 1000;
328	345	case MXC_SSP0_CLK:
329	346	return mxs_get_sspclk(MXC_SSPCLK0);
	347	+#ifdef CONFIG_MX28
330	348	case MXC_SSP1_CLK:
331	349	return mxs_get_sspclk(MXC_SSPCLK1);
332	350	case MXC_SSP2_CLK:
333	351	return mxs_get_sspclk(MXC_SSPCLK2);
334	352	case MXC_SSP3_CLK:
335	353	return mxs_get_sspclk(MXC_SSPCLK3);
336		- case MXC_XTAL_CLK:
337		- return XTAL_FREQ_KHZ * 1000;
	354	+#endif
338	355	}
339	356
340	357	return 0;
1	1	/*
2		- * Freescale i.MX28 Clock
	2	+ * Freescale i.MX23/i.MX28 Clock
3	3	*
4	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5	5	* on behalf of DENX Software Engineering GmbH
6	6
7	7
...	...	@@ -31,11 +31,13 @@
31	31	MXC_GPMI_CLK,
32	32	MXC_IO0_CLK,
33	33	MXC_IO1_CLK,
	34	+ MXC_XTAL_CLK,
34	35	MXC_SSP0_CLK,
	36	+#ifdef CONFIG_MX28
35	37	MXC_SSP1_CLK,
36	38	MXC_SSP2_CLK,
37	39	MXC_SSP3_CLK,
38		- MXC_XTAL_CLK,
	40	+#endif
39	41	};
40	42
41	43	enum mxs_ioclock {
42	44
...	...	@@ -45,9 +47,11 @@
45	47
46	48	enum mxs_sspclock {
47	49	MXC_SSPCLK0 = 0,
	50	+#ifdef CONFIG_MX28
48	51	MXC_SSPCLK1,
49	52	MXC_SSPCLK2,
50	53	MXC_SSPCLK3,
	54	+#endif
51	55	};
52	56
53	57	uint32_t mxc_get_clock(enum mxc_clock clk);