Eric Lee / smarc-uboot

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Commit 00aa453ebf56fc3a2bd5b684467bc912ba59c4d6

Authored by Masahiro Yamada
1 parent 213fcabdfd
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ARM: uniphier: remove sLD3 SoC support 

This SoC is too old.  It is difficult to maintain any longer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Showing 46 changed files with 89 additions and 1164 deletions Inline Diff

arch/arm/dts/Makefile
Diff comments   View file @ 00aa453
1 # 1 #
2 # SPDX-License-Identifier: GPL-2.0+ 2 # SPDX-License-Identifier: GPL-2.0+
3 # 3 #
4 4
5 dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \ 5 dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \
6 at91sam9g20-taurus.dtb \ 6 at91sam9g20-taurus.dtb \
7 at91sam9g45-corvus.dtb \ 7 at91sam9g45-corvus.dtb \
8 at91sam9g45-gurnard.dtb 8 at91sam9g45-gurnard.dtb
9 9
10 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb 10 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
11 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb 11 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
12 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ 12 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
13 exynos4210-smdkv310.dtb \ 13 exynos4210-smdkv310.dtb \
14 exynos4210-universal_c210.dtb \ 14 exynos4210-universal_c210.dtb \
15 exynos4210-trats.dtb \ 15 exynos4210-trats.dtb \
16 exynos4412-trats2.dtb \ 16 exynos4412-trats2.dtb \
17 exynos4412-odroid.dtb 17 exynos4412-odroid.dtb
18 18
19 dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb 19 dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb
20 20
21 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ 21 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
22 exynos5250-snow.dtb \ 22 exynos5250-snow.dtb \
23 exynos5250-spring.dtb \ 23 exynos5250-spring.dtb \
24 exynos5250-smdk5250.dtb \ 24 exynos5250-smdk5250.dtb \
25 exynos5420-smdk5420.dtb \ 25 exynos5420-smdk5420.dtb \
26 exynos5420-peach-pit.dtb \ 26 exynos5420-peach-pit.dtb \
27 exynos5800-peach-pi.dtb \ 27 exynos5800-peach-pi.dtb \
28 exynos5422-odroidxu3.dtb 28 exynos5422-odroidxu3.dtb
29 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb 29 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
30 dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 30 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
31 rk3036-sdk.dtb \ 31 rk3036-sdk.dtb \
32 rk3188-radxarock.dtb \ 32 rk3188-radxarock.dtb \
33 rk3288-evb.dtb \ 33 rk3288-evb.dtb \
34 rk3288-fennec.dtb \ 34 rk3288-fennec.dtb \
35 rk3288-firefly.dtb \ 35 rk3288-firefly.dtb \
36 rk3288-miqi.dtb \ 36 rk3288-miqi.dtb \
37 rk3288-phycore-rdk.dtb \ 37 rk3288-phycore-rdk.dtb \
38 rk3288-popmetal.dtb \ 38 rk3288-popmetal.dtb \
39 rk3288-rock2-square.dtb \ 39 rk3288-rock2-square.dtb \
40 rk3288-tinker.dtb \ 40 rk3288-tinker.dtb \
41 rk3288-veyron-jerry.dtb \ 41 rk3288-veyron-jerry.dtb \
42 rk3288-veyron-mickey.dtb \ 42 rk3288-veyron-mickey.dtb \
43 rk3288-veyron-minnie.dtb \ 43 rk3288-veyron-minnie.dtb \
44 rk3328-evb.dtb \ 44 rk3328-evb.dtb \
45 rk3368-lion.dtb \ 45 rk3368-lion.dtb \
46 rk3368-sheep.dtb \ 46 rk3368-sheep.dtb \
47 rk3368-geekbox.dtb \ 47 rk3368-geekbox.dtb \
48 rk3368-px5-evb.dtb \ 48 rk3368-px5-evb.dtb \
49 rk3399-evb.dtb \ 49 rk3399-evb.dtb \
50 rk3399-firefly.dtb \ 50 rk3399-firefly.dtb \
51 rk3399-puma-ddr1333.dtb \ 51 rk3399-puma-ddr1333.dtb \
52 rk3399-puma-ddr1600.dtb \ 52 rk3399-puma-ddr1600.dtb \
53 rk3399-puma-ddr1866.dtb \ 53 rk3399-puma-ddr1866.dtb \
54 rv1108-evb.dtb 54 rv1108-evb.dtb
55 dtb-$(CONFIG_ARCH_MESON) += \ 55 dtb-$(CONFIG_ARCH_MESON) += \
56 meson-gxbb-odroidc2.dtb 56 meson-gxbb-odroidc2.dtb
57 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ 57 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
58 tegra20-medcom-wide.dtb \ 58 tegra20-medcom-wide.dtb \
59 tegra20-paz00.dtb \ 59 tegra20-paz00.dtb \
60 tegra20-plutux.dtb \ 60 tegra20-plutux.dtb \
61 tegra20-seaboard.dtb \ 61 tegra20-seaboard.dtb \
62 tegra20-tec.dtb \ 62 tegra20-tec.dtb \
63 tegra20-trimslice.dtb \ 63 tegra20-trimslice.dtb \
64 tegra20-ventana.dtb \ 64 tegra20-ventana.dtb \
65 tegra20-colibri.dtb \ 65 tegra20-colibri.dtb \
66 tegra30-apalis.dtb \ 66 tegra30-apalis.dtb \
67 tegra30-beaver.dtb \ 67 tegra30-beaver.dtb \
68 tegra30-cardhu.dtb \ 68 tegra30-cardhu.dtb \
69 tegra30-colibri.dtb \ 69 tegra30-colibri.dtb \
70 tegra30-tec-ng.dtb \ 70 tegra30-tec-ng.dtb \
71 tegra114-dalmore.dtb \ 71 tegra114-dalmore.dtb \
72 tegra124-apalis.dtb \ 72 tegra124-apalis.dtb \
73 tegra124-jetson-tk1.dtb \ 73 tegra124-jetson-tk1.dtb \
74 tegra124-nyan-big.dtb \ 74 tegra124-nyan-big.dtb \
75 tegra124-cei-tk1-som.dtb \ 75 tegra124-cei-tk1-som.dtb \
76 tegra124-venice2.dtb \ 76 tegra124-venice2.dtb \
77 tegra186-p2771-0000-000.dtb \ 77 tegra186-p2771-0000-000.dtb \
78 tegra186-p2771-0000-500.dtb \ 78 tegra186-p2771-0000-500.dtb \
79 tegra210-e2220-1170.dtb \ 79 tegra210-e2220-1170.dtb \
80 tegra210-p2371-0000.dtb \ 80 tegra210-p2371-0000.dtb \
81 tegra210-p2371-2180.dtb \ 81 tegra210-p2371-2180.dtb \
82 tegra210-p2571.dtb 82 tegra210-p2571.dtb
83 83
84 dtb-$(CONFIG_ARCH_MVEBU) += \ 84 dtb-$(CONFIG_ARCH_MVEBU) += \
85 armada-3720-db.dtb \ 85 armada-3720-db.dtb \
86 armada-3720-espressobin.dtb \ 86 armada-3720-espressobin.dtb \
87 armada-375-db.dtb \ 87 armada-375-db.dtb \
88 armada-388-clearfog.dtb \ 88 armada-388-clearfog.dtb \
89 armada-388-gp.dtb \ 89 armada-388-gp.dtb \
90 armada-385-amc.dtb \ 90 armada-385-amc.dtb \
91 armada-7040-db.dtb \ 91 armada-7040-db.dtb \
92 armada-7040-db-nand.dtb \ 92 armada-7040-db-nand.dtb \
93 armada-8040-db.dtb \ 93 armada-8040-db.dtb \
94 armada-8040-mcbin.dtb \ 94 armada-8040-mcbin.dtb \
95 armada-xp-gp.dtb \ 95 armada-xp-gp.dtb \
96 armada-xp-maxbcm.dtb \ 96 armada-xp-maxbcm.dtb \
97 armada-xp-synology-ds414.dtb \ 97 armada-xp-synology-ds414.dtb \
98 armada-xp-theadorable.dtb \ 98 armada-xp-theadorable.dtb \
99 armada-38x-controlcenterdc.dtb 99 armada-38x-controlcenterdc.dtb
100 100
101 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ 101 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
102 uniphier-ld11-global.dtb \ 102 uniphier-ld11-global.dtb \
103 uniphier-ld11-ref.dtb 103 uniphier-ld11-ref.dtb
104 dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \ 104 dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \
105 uniphier-ld20-global.dtb \ 105 uniphier-ld20-global.dtb \
106 uniphier-ld20-ref.dtb 106 uniphier-ld20-ref.dtb
107 dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \ 107 dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \
108 uniphier-ld4-ref.dtb 108 uniphier-ld4-ref.dtb
109 dtb-$(CONFIG_ARCH_UNIPHIER_LD6B) += \ 109 dtb-$(CONFIG_ARCH_UNIPHIER_LD6B) += \
110 uniphier-ld6b-ref.dtb 110 uniphier-ld6b-ref.dtb
111 dtb-$(CONFIG_ARCH_UNIPHIER_PRO4) += \ 111 dtb-$(CONFIG_ARCH_UNIPHIER_PRO4) += \
112 uniphier-pro4-ace.dtb \ 112 uniphier-pro4-ace.dtb \
113 uniphier-pro4-ref.dtb \ 113 uniphier-pro4-ref.dtb \
114 uniphier-pro4-sanji.dtb 114 uniphier-pro4-sanji.dtb
115 dtb-$(CONFIG_ARCH_UNIPHIER_PRO5) += \ 115 dtb-$(CONFIG_ARCH_UNIPHIER_PRO5) += \
116 uniphier-pro5-4kbox.dtb 116 uniphier-pro5-4kbox.dtb
117 dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \ 117 dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \
118 uniphier-pxs2-gentil.dtb \ 118 uniphier-pxs2-gentil.dtb \
119 uniphier-pxs2-vodka.dtb 119 uniphier-pxs2-vodka.dtb
120 dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \ 120 dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \
121 uniphier-pxs3-ref.dtb 121 uniphier-pxs3-ref.dtb
122 dtb-$(CONFIG_ARCH_UNIPHIER_SLD3) += \
123 uniphier-sld3-ref.dtb
124 dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \ 122 dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
125 uniphier-sld8-ref.dtb 123 uniphier-sld8-ref.dtb
126 124
127 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ 125 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
128 zynq-zc706.dtb \ 126 zynq-zc706.dtb \
129 zynq-zed.dtb \ 127 zynq-zed.dtb \
130 zynq-zybo.dtb \ 128 zynq-zybo.dtb \
131 zynq-microzed.dtb \ 129 zynq-microzed.dtb \
132 zynq-picozed.dtb \ 130 zynq-picozed.dtb \
133 zynq-topic-miami.dtb \ 131 zynq-topic-miami.dtb \
134 zynq-topic-miamilite.dtb \ 132 zynq-topic-miamilite.dtb \
135 zynq-topic-miamiplus.dtb \ 133 zynq-topic-miamiplus.dtb \
136 zynq-zturn-myir.dtb \ 134 zynq-zturn-myir.dtb \
137 zynq-zc770-xm010.dtb \ 135 zynq-zc770-xm010.dtb \
138 zynq-zc770-xm011.dtb \ 136 zynq-zc770-xm011.dtb \
139 zynq-zc770-xm012.dtb \ 137 zynq-zc770-xm012.dtb \
140 zynq-zc770-xm013.dtb 138 zynq-zc770-xm013.dtb
141 dtb-$(CONFIG_ARCH_ZYNQMP) += \ 139 dtb-$(CONFIG_ARCH_ZYNQMP) += \
142 zynqmp-ep108.dtb \ 140 zynqmp-ep108.dtb \
143 zynqmp-zcu102-revA.dtb \ 141 zynqmp-zcu102-revA.dtb \
144 zynqmp-zcu102-revB.dtb \ 142 zynqmp-zcu102-revB.dtb \
145 zynqmp-zc1751-xm015-dc1.dtb \ 143 zynqmp-zc1751-xm015-dc1.dtb \
146 zynqmp-zc1751-xm016-dc2.dtb \ 144 zynqmp-zc1751-xm016-dc2.dtb \
147 zynqmp-zc1751-xm018-dc4.dtb \ 145 zynqmp-zc1751-xm018-dc4.dtb \
148 zynqmp-zc1751-xm019-dc5.dtb 146 zynqmp-zc1751-xm019-dc5.dtb
149 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ 147 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
150 am335x-draco.dtb \ 148 am335x-draco.dtb \
151 am335x-evm.dtb \ 149 am335x-evm.dtb \
152 am335x-evmsk.dtb \ 150 am335x-evmsk.dtb \
153 am335x-bonegreen.dtb \ 151 am335x-bonegreen.dtb \
154 am335x-icev2.dtb \ 152 am335x-icev2.dtb \
155 am335x-pxm50.dtb \ 153 am335x-pxm50.dtb \
156 am335x-rut.dtb 154 am335x-rut.dtb
157 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ 155 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
158 am43x-epos-evm.dtb \ 156 am43x-epos-evm.dtb \
159 am437x-idk-evm.dtb 157 am437x-idk-evm.dtb
160 dtb-$(CONFIG_TI816X) += dm8168-evm.dtb 158 dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
161 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb 159 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
162 160
163 dtb-$(CONFIG_ARCH_SOCFPGA) += \ 161 dtb-$(CONFIG_ARCH_SOCFPGA) += \
164 socfpga_arria10_socdk_sdmmc.dtb \ 162 socfpga_arria10_socdk_sdmmc.dtb \
165 socfpga_arria5_socdk.dtb \ 163 socfpga_arria5_socdk.dtb \
166 socfpga_cyclone5_is1.dtb \ 164 socfpga_cyclone5_is1.dtb \
167 socfpga_cyclone5_mcvevk.dtb \ 165 socfpga_cyclone5_mcvevk.dtb \
168 socfpga_cyclone5_socdk.dtb \ 166 socfpga_cyclone5_socdk.dtb \
169 socfpga_cyclone5_de0_nano_soc.dtb \ 167 socfpga_cyclone5_de0_nano_soc.dtb \
170 socfpga_cyclone5_de1_soc.dtb \ 168 socfpga_cyclone5_de1_soc.dtb \
171 socfpga_cyclone5_de10_nano.dtb \ 169 socfpga_cyclone5_de10_nano.dtb \
172 socfpga_cyclone5_sockit.dtb \ 170 socfpga_cyclone5_sockit.dtb \
173 socfpga_cyclone5_socrates.dtb \ 171 socfpga_cyclone5_socrates.dtb \
174 socfpga_cyclone5_sr1500.dtb \ 172 socfpga_cyclone5_sr1500.dtb \
175 socfpga_cyclone5_vining_fpga.dtb 173 socfpga_cyclone5_vining_fpga.dtb
176 174
177 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ 175 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
178 dra72-evm-revc.dtb dra71-evm.dtb 176 dra72-evm-revc.dtb dra71-evm.dtb
179 dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ 177 dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
180 am57xx-beagle-x15-revb1.dtb \ 178 am57xx-beagle-x15-revb1.dtb \
181 am572x-idk.dtb \ 179 am572x-idk.dtb \
182 am571x-idk.dtb 180 am571x-idk.dtb
183 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb 181 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
184 182
185 dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ 183 dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
186 ls1021a-qds-lpuart.dtb \ 184 ls1021a-qds-lpuart.dtb \
187 ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ 185 ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
188 ls1021a-iot-duart.dtb 186 ls1021a-iot-duart.dtb
189 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ 187 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
190 fsl-ls2080a-rdb.dtb \ 188 fsl-ls2080a-rdb.dtb \
191 fsl-ls2081a-rdb.dtb \ 189 fsl-ls2081a-rdb.dtb \
192 fsl-ls2088a-rdb-qspi.dtb 190 fsl-ls2088a-rdb-qspi.dtb
193 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ 191 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
194 fsl-ls1043a-qds-lpuart.dtb \ 192 fsl-ls1043a-qds-lpuart.dtb \
195 fsl-ls1043a-rdb.dtb \ 193 fsl-ls1043a-rdb.dtb \
196 fsl-ls1046a-qds-duart.dtb \ 194 fsl-ls1046a-qds-duart.dtb \
197 fsl-ls1046a-qds-lpuart.dtb \ 195 fsl-ls1046a-qds-lpuart.dtb \
198 fsl-ls1046a-rdb.dtb \ 196 fsl-ls1046a-rdb.dtb \
199 fsl-ls1012a-qds.dtb \ 197 fsl-ls1012a-qds.dtb \
200 fsl-ls1012a-rdb.dtb \ 198 fsl-ls1012a-rdb.dtb \
201 fsl-ls1012a-frdm.dtb 199 fsl-ls1012a-frdm.dtb
202 200
203 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb 201 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
204 202
205 dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ 203 dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
206 stm32f769-disco.dtb 204 stm32f769-disco.dtb
207 205
208 dtb-$(CONFIG_MACH_SUN4I) += \ 206 dtb-$(CONFIG_MACH_SUN4I) += \
209 sun4i-a10-a1000.dtb \ 207 sun4i-a10-a1000.dtb \
210 sun4i-a10-ba10-tvbox.dtb \ 208 sun4i-a10-ba10-tvbox.dtb \
211 sun4i-a10-chuwi-v7-cw0825.dtb \ 209 sun4i-a10-chuwi-v7-cw0825.dtb \
212 sun4i-a10-cubieboard.dtb \ 210 sun4i-a10-cubieboard.dtb \
213 sun4i-a10-dserve-dsrv9703c.dtb \ 211 sun4i-a10-dserve-dsrv9703c.dtb \
214 sun4i-a10-gemei-g9.dtb \ 212 sun4i-a10-gemei-g9.dtb \
215 sun4i-a10-hackberry.dtb \ 213 sun4i-a10-hackberry.dtb \
216 sun4i-a10-hyundai-a7hd.dtb \ 214 sun4i-a10-hyundai-a7hd.dtb \
217 sun4i-a10-inet1.dtb \ 215 sun4i-a10-inet1.dtb \
218 sun4i-a10-inet-3f.dtb \ 216 sun4i-a10-inet-3f.dtb \
219 sun4i-a10-inet-3w.dtb \ 217 sun4i-a10-inet-3w.dtb \
220 sun4i-a10-inet97fv2.dtb \ 218 sun4i-a10-inet97fv2.dtb \
221 sun4i-a10-inet9f-rev03.dtb \ 219 sun4i-a10-inet9f-rev03.dtb \
222 sun4i-a10-itead-iteaduino-plus.dtb \ 220 sun4i-a10-itead-iteaduino-plus.dtb \
223 sun4i-a10-jesurun-q5.dtb \ 221 sun4i-a10-jesurun-q5.dtb \
224 sun4i-a10-marsboard.dtb \ 222 sun4i-a10-marsboard.dtb \
225 sun4i-a10-mini-xplus.dtb \ 223 sun4i-a10-mini-xplus.dtb \
226 sun4i-a10-mk802.dtb \ 224 sun4i-a10-mk802.dtb \
227 sun4i-a10-mk802ii.dtb \ 225 sun4i-a10-mk802ii.dtb \
228 sun4i-a10-olinuxino-lime.dtb \ 226 sun4i-a10-olinuxino-lime.dtb \
229 sun4i-a10-pcduino.dtb \ 227 sun4i-a10-pcduino.dtb \
230 sun4i-a10-pcduino2.dtb \ 228 sun4i-a10-pcduino2.dtb \
231 sun4i-a10-pov-protab2-ips9.dtb 229 sun4i-a10-pov-protab2-ips9.dtb
232 dtb-$(CONFIG_MACH_SUN5I) += \ 230 dtb-$(CONFIG_MACH_SUN5I) += \
233 sun5i-a10s-auxtek-t003.dtb \ 231 sun5i-a10s-auxtek-t003.dtb \
234 sun5i-a10s-auxtek-t004.dtb \ 232 sun5i-a10s-auxtek-t004.dtb \
235 sun5i-a10s-mk802.dtb \ 233 sun5i-a10s-mk802.dtb \
236 sun5i-a10s-olinuxino-micro.dtb \ 234 sun5i-a10s-olinuxino-micro.dtb \
237 sun5i-a10s-r7-tv-dongle.dtb \ 235 sun5i-a10s-r7-tv-dongle.dtb \
238 sun5i-a10s-wobo-i5.dtb \ 236 sun5i-a10s-wobo-i5.dtb \
239 sun5i-a13-ampe-a76.dtb \ 237 sun5i-a13-ampe-a76.dtb \
240 sun5i-a13-difrnce-dit4350.dtb \ 238 sun5i-a13-difrnce-dit4350.dtb \
241 sun5i-a13-empire-electronix-d709.dtb \ 239 sun5i-a13-empire-electronix-d709.dtb \
242 sun5i-a13-empire-electronix-m712.dtb \ 240 sun5i-a13-empire-electronix-m712.dtb \
243 sun5i-a13-hsg-h702.dtb \ 241 sun5i-a13-hsg-h702.dtb \
244 sun5i-a13-inet-86vs.dtb \ 242 sun5i-a13-inet-86vs.dtb \
245 sun5i-a13-inet-98v-rev2.dtb \ 243 sun5i-a13-inet-98v-rev2.dtb \
246 sun5i-a13-olinuxino.dtb \ 244 sun5i-a13-olinuxino.dtb \
247 sun5i-a13-olinuxino-micro.dtb \ 245 sun5i-a13-olinuxino-micro.dtb \
248 sun5i-a13-q8-tablet.dtb \ 246 sun5i-a13-q8-tablet.dtb \
249 sun5i-a13-utoo-p66.dtb \ 247 sun5i-a13-utoo-p66.dtb \
250 sun5i-gr8-chip-pro.dtb \ 248 sun5i-gr8-chip-pro.dtb \
251 sun5i-r8-chip.dtb 249 sun5i-r8-chip.dtb
252 dtb-$(CONFIG_MACH_SUN6I) += \ 250 dtb-$(CONFIG_MACH_SUN6I) += \
253 sun6i-a31-app4-evb1.dtb \ 251 sun6i-a31-app4-evb1.dtb \
254 sun6i-a31-colombus.dtb \ 252 sun6i-a31-colombus.dtb \
255 sun6i-a31-hummingbird.dtb \ 253 sun6i-a31-hummingbird.dtb \
256 sun6i-a31-i7.dtb \ 254 sun6i-a31-i7.dtb \
257 sun6i-a31-m9.dtb \ 255 sun6i-a31-m9.dtb \
258 sun6i-a31-mele-a1000g-quad.dtb \ 256 sun6i-a31-mele-a1000g-quad.dtb \
259 sun6i-a31-mixtile-loftq.dtb \ 257 sun6i-a31-mixtile-loftq.dtb \
260 sun6i-a31s-colorfly-e708-q1.dtb \ 258 sun6i-a31s-colorfly-e708-q1.dtb \
261 sun6i-a31s-cs908.dtb \ 259 sun6i-a31s-cs908.dtb \
262 sun6i-a31s-inet-q972.dtb \ 260 sun6i-a31s-inet-q972.dtb \
263 sun6i-a31s-primo81.dtb \ 261 sun6i-a31s-primo81.dtb \
264 sun6i-a31s-sina31s.dtb \ 262 sun6i-a31s-sina31s.dtb \
265 sun6i-a31s-sinovoip-bpi-m2.dtb \ 263 sun6i-a31s-sinovoip-bpi-m2.dtb \
266 sun6i-a31s-yones-toptech-bs1078-v2.dtb 264 sun6i-a31s-yones-toptech-bs1078-v2.dtb
267 dtb-$(CONFIG_MACH_SUN7I) += \ 265 dtb-$(CONFIG_MACH_SUN7I) += \
268 sun7i-a20-ainol-aw1.dtb \ 266 sun7i-a20-ainol-aw1.dtb \
269 sun7i-a20-bananapi.dtb \ 267 sun7i-a20-bananapi.dtb \
270 sun7i-a20-bananapi-m1-plus.dtb \ 268 sun7i-a20-bananapi-m1-plus.dtb \
271 sun7i-a20-bananapro.dtb \ 269 sun7i-a20-bananapro.dtb \
272 sun7i-a20-cubieboard2.dtb \ 270 sun7i-a20-cubieboard2.dtb \
273 sun7i-a20-cubietruck.dtb \ 271 sun7i-a20-cubietruck.dtb \
274 sun7i-a20-hummingbird.dtb \ 272 sun7i-a20-hummingbird.dtb \
275 sun7i-a20-i12-tvbox.dtb \ 273 sun7i-a20-i12-tvbox.dtb \
276 sun7i-a20-icnova-swac.dtb \ 274 sun7i-a20-icnova-swac.dtb \
277 sun7i-a20-itead-ibox.dtb \ 275 sun7i-a20-itead-ibox.dtb \
278 sun7i-a20-lamobo-r1.dtb \ 276 sun7i-a20-lamobo-r1.dtb \
279 sun7i-a20-m3.dtb \ 277 sun7i-a20-m3.dtb \
280 sun7i-a20-m5.dtb \ 278 sun7i-a20-m5.dtb \
281 sun7i-a20-mk808c.dtb \ 279 sun7i-a20-mk808c.dtb \
282 sun7i-a20-olimex-som-evb.dtb \ 280 sun7i-a20-olimex-som-evb.dtb \
283 sun7i-a20-olinuxino-lime.dtb \ 281 sun7i-a20-olinuxino-lime.dtb \
284 sun7i-a20-olinuxino-lime2.dtb \ 282 sun7i-a20-olinuxino-lime2.dtb \
285 sun7i-a20-olinuxino-lime2-emmc.dtb \ 283 sun7i-a20-olinuxino-lime2-emmc.dtb \
286 sun7i-a20-olinuxino-micro.dtb \ 284 sun7i-a20-olinuxino-micro.dtb \
287 sun7i-a20-orangepi.dtb \ 285 sun7i-a20-orangepi.dtb \
288 sun7i-a20-orangepi-mini.dtb \ 286 sun7i-a20-orangepi-mini.dtb \
289 sun7i-a20-pcduino3.dtb \ 287 sun7i-a20-pcduino3.dtb \
290 sun7i-a20-pcduino3-nano.dtb \ 288 sun7i-a20-pcduino3-nano.dtb \
291 sun7i-a20-primo73.dtb \ 289 sun7i-a20-primo73.dtb \
292 sun7i-a20-wexler-tab7200.dtb \ 290 sun7i-a20-wexler-tab7200.dtb \
293 sun7i-a20-wits-pro-a20-dkt.dtb \ 291 sun7i-a20-wits-pro-a20-dkt.dtb \
294 sun7i-a20-yones-toptech-bd1078.dtb 292 sun7i-a20-yones-toptech-bd1078.dtb
295 dtb-$(CONFIG_MACH_SUN8I_A23) += \ 293 dtb-$(CONFIG_MACH_SUN8I_A23) += \
296 sun8i-a23-evb.dtb \ 294 sun8i-a23-evb.dtb \
297 sun8i-a23-gt90h-v4.dtb \ 295 sun8i-a23-gt90h-v4.dtb \
298 sun8i-a23-inet86dz.dtb \ 296 sun8i-a23-inet86dz.dtb \
299 sun8i-a23-polaroid-mid2407pxe03.dtb \ 297 sun8i-a23-polaroid-mid2407pxe03.dtb \
300 sun8i-a23-polaroid-mid2809pxe04.dtb \ 298 sun8i-a23-polaroid-mid2809pxe04.dtb \
301 sun8i-a23-q8-tablet.dtb 299 sun8i-a23-q8-tablet.dtb
302 dtb-$(CONFIG_MACH_SUN8I_A33) += \ 300 dtb-$(CONFIG_MACH_SUN8I_A33) += \
303 sun8i-a33-ga10h-v1.1.dtb \ 301 sun8i-a33-ga10h-v1.1.dtb \
304 sun8i-a33-inet-d978-rev2.dtb \ 302 sun8i-a33-inet-d978-rev2.dtb \
305 sun8i-a33-olinuxino.dtb \ 303 sun8i-a33-olinuxino.dtb \
306 sun8i-a33-q8-tablet.dtb \ 304 sun8i-a33-q8-tablet.dtb \
307 sun8i-a33-sinlinx-sina33.dtb \ 305 sun8i-a33-sinlinx-sina33.dtb \
308 sun8i-r16-nintendo-nes-classic-edition.dtb \ 306 sun8i-r16-nintendo-nes-classic-edition.dtb \
309 sun8i-r16-parrot.dtb 307 sun8i-r16-parrot.dtb
310 dtb-$(CONFIG_MACH_SUN8I_A83T) += \ 308 dtb-$(CONFIG_MACH_SUN8I_A83T) += \
311 sun8i-a83t-allwinner-h8homlet-v2.dtb \ 309 sun8i-a83t-allwinner-h8homlet-v2.dtb \
312 sun8i-a83t-cubietruck-plus.dtb \ 310 sun8i-a83t-cubietruck-plus.dtb \
313 sun8i-a83t-sinovoip-bpi-m3.dtb 311 sun8i-a83t-sinovoip-bpi-m3.dtb
314 dtb-$(CONFIG_MACH_SUN8I_H3) += \ 312 dtb-$(CONFIG_MACH_SUN8I_H3) += \
315 sun8i-h2-plus-orangepi-zero.dtb \ 313 sun8i-h2-plus-orangepi-zero.dtb \
316 sun8i-h3-bananapi-m2-plus.dtb \ 314 sun8i-h3-bananapi-m2-plus.dtb \
317 sun8i-h3-orangepi-2.dtb \ 315 sun8i-h3-orangepi-2.dtb \
318 sun8i-h3-orangepi-lite.dtb \ 316 sun8i-h3-orangepi-lite.dtb \
319 sun8i-h3-orangepi-one.dtb \ 317 sun8i-h3-orangepi-one.dtb \
320 sun8i-h3-orangepi-pc.dtb \ 318 sun8i-h3-orangepi-pc.dtb \
321 sun8i-h3-orangepi-pc-plus.dtb \ 319 sun8i-h3-orangepi-pc-plus.dtb \
322 sun8i-h3-orangepi-plus.dtb \ 320 sun8i-h3-orangepi-plus.dtb \
323 sun8i-h3-orangepi-plus2e.dtb \ 321 sun8i-h3-orangepi-plus2e.dtb \
324 sun8i-h3-nanopi-m1.dtb \ 322 sun8i-h3-nanopi-m1.dtb \
325 sun8i-h3-nanopi-m1-plus.dtb \ 323 sun8i-h3-nanopi-m1-plus.dtb \
326 sun8i-h3-nanopi-neo.dtb \ 324 sun8i-h3-nanopi-neo.dtb \
327 sun8i-h3-nanopi-neo-air.dtb 325 sun8i-h3-nanopi-neo-air.dtb
328 dtb-$(CONFIG_MACH_SUN8I_R40) += \ 326 dtb-$(CONFIG_MACH_SUN8I_R40) += \
329 sun8i-r40-bananapi-m2-ultra.dtb 327 sun8i-r40-bananapi-m2-ultra.dtb
330 dtb-$(CONFIG_MACH_SUN8I_V3S) += \ 328 dtb-$(CONFIG_MACH_SUN8I_V3S) += \
331 sun8i-v3s-licheepi-zero.dtb 329 sun8i-v3s-licheepi-zero.dtb
332 dtb-$(CONFIG_MACH_SUN50I_H5) += \ 330 dtb-$(CONFIG_MACH_SUN50I_H5) += \
333 sun50i-h5-nanopi-neo2.dtb \ 331 sun50i-h5-nanopi-neo2.dtb \
334 sun50i-h5-orangepi-pc2.dtb \ 332 sun50i-h5-orangepi-pc2.dtb \
335 sun50i-h5-orangepi-prime.dtb \ 333 sun50i-h5-orangepi-prime.dtb \
336 sun50i-h5-orangepi-zero-plus2.dtb 334 sun50i-h5-orangepi-zero-plus2.dtb
337 dtb-$(CONFIG_MACH_SUN50I) += \ 335 dtb-$(CONFIG_MACH_SUN50I) += \
338 sun50i-a64-bananapi-m64.dtb \ 336 sun50i-a64-bananapi-m64.dtb \
339 sun50i-a64-nanopi-a64.dtb \ 337 sun50i-a64-nanopi-a64.dtb \
340 sun50i-a64-olinuxino.dtb \ 338 sun50i-a64-olinuxino.dtb \
341 sun50i-a64-orangepi-win.dtb \ 339 sun50i-a64-orangepi-win.dtb \
342 sun50i-a64-pine64-plus.dtb \ 340 sun50i-a64-pine64-plus.dtb \
343 sun50i-a64-pine64.dtb 341 sun50i-a64-pine64.dtb
344 dtb-$(CONFIG_MACH_SUN9I) += \ 342 dtb-$(CONFIG_MACH_SUN9I) += \
345 sun9i-a80-optimus.dtb \ 343 sun9i-a80-optimus.dtb \
346 sun9i-a80-cubieboard4.dtb \ 344 sun9i-a80-cubieboard4.dtb \
347 sun9i-a80-cx-a99.dtb 345 sun9i-a80-cx-a99.dtb
348 346
349 dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ 347 dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
350 vf610-colibri.dtb \ 348 vf610-colibri.dtb \
351 vf610-twr.dtb \ 349 vf610-twr.dtb \
352 pcm052.dtb \ 350 pcm052.dtb \
353 bk4r1.dtb 351 bk4r1.dtb
354 352
355 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb 353 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
356 354
357 dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ 355 dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
358 imx6sl-evk.dtb \ 356 imx6sl-evk.dtb \
359 imx6sll-evk.dtb \ 357 imx6sll-evk.dtb \
360 imx6dl-icore.dtb \ 358 imx6dl-icore.dtb \
361 imx6dl-icore-rqs.dtb \ 359 imx6dl-icore-rqs.dtb \
362 imx6q-cm-fx6.dtb \ 360 imx6q-cm-fx6.dtb \
363 imx6q-icore.dtb \ 361 imx6q-icore.dtb \
364 imx6q-icore-rqs.dtb \ 362 imx6q-icore-rqs.dtb \
365 imx6q-logicpd.dtb \ 363 imx6q-logicpd.dtb \
366 imx6sx-sabreauto.dtb \ 364 imx6sx-sabreauto.dtb \
367 imx6ul-geam-kit.dtb \ 365 imx6ul-geam-kit.dtb \
368 imx6ul-isiot-emmc.dtb \ 366 imx6ul-isiot-emmc.dtb \
369 imx6ul-isiot-mmc.dtb \ 367 imx6ul-isiot-mmc.dtb \
370 imx6ul-isiot-nand.dtb \ 368 imx6ul-isiot-nand.dtb \
371 imx6ul-opos6uldev.dtb 369 imx6ul-opos6uldev.dtb
372 370
373 dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ 371 dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
374 imx7d-sdb.dtb 372 imx7d-sdb.dtb
375 373
376 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb 374 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
377 375
378 dtb-$(CONFIG_RCAR_GEN3) += \ 376 dtb-$(CONFIG_RCAR_GEN3) += \
379 r8a7795-h3ulcb.dtb \ 377 r8a7795-h3ulcb.dtb \
380 r8a7795-salvator-x.dtb \ 378 r8a7795-salvator-x.dtb \
381 r8a7796-m3ulcb.dtb \ 379 r8a7796-m3ulcb.dtb \
382 r8a7796-salvator-x.dtb 380 r8a7796-salvator-x.dtb
383 381
384 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ 382 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
385 keystone-k2l-evm.dtb \ 383 keystone-k2l-evm.dtb \
386 keystone-k2e-evm.dtb \ 384 keystone-k2e-evm.dtb \
387 keystone-k2g-evm.dtb \ 385 keystone-k2g-evm.dtb \
388 keystone-k2g-generic.dtb \ 386 keystone-k2g-generic.dtb \
389 keystone-k2g-ice.dtb 387 keystone-k2g-ice.dtb
390 388
391 dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb 389 dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
392 390
393 dtb-$(CONFIG_TARGET_PM9263) += at91sam9263ek.dtb 391 dtb-$(CONFIG_TARGET_PM9263) += at91sam9263ek.dtb
394 392
395 dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb 393 dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb
396 394
397 dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb 395 dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb
398 396
399 dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \ 397 dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \
400 at91sam9260ek.dtb \ 398 at91sam9260ek.dtb \
401 at91sam9g20ek.dtb \ 399 at91sam9g20ek.dtb \
402 at91sam9g20ek_2mmc.dtb 400 at91sam9g20ek_2mmc.dtb
403 401
404 dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb 402 dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb
405 403
406 dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ 404 dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
407 at91sam9g15ek.dtb \ 405 at91sam9g15ek.dtb \
408 at91sam9g25ek.dtb \ 406 at91sam9g25ek.dtb \
409 at91sam9g35ek.dtb \ 407 at91sam9g35ek.dtb \
410 at91sam9x25ek.dtb \ 408 at91sam9x25ek.dtb \
411 at91sam9x35ek.dtb 409 at91sam9x35ek.dtb
412 410
413 dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb 411 dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
414 412
415 dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \ 413 dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \
416 logicpd-torpedo-37xx-devkit.dtb \ 414 logicpd-torpedo-37xx-devkit.dtb \
417 logicpd-som-lv-37xx-devkit.dtb 415 logicpd-som-lv-37xx-devkit.dtb
418 416
419 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ 417 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
420 at91-sama5d2_xplained.dtb 418 at91-sama5d2_xplained.dtb
421 419
422 dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ 420 dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
423 sama5d31ek.dtb \ 421 sama5d31ek.dtb \
424 sama5d33ek.dtb \ 422 sama5d33ek.dtb \
425 sama5d34ek.dtb \ 423 sama5d34ek.dtb \
426 sama5d35ek.dtb \ 424 sama5d35ek.dtb \
427 sama5d36ek.dtb \ 425 sama5d36ek.dtb \
428 sama5d36ek_cmp.dtb 426 sama5d36ek_cmp.dtb
429 427
430 dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \ 428 dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \
431 at91-sama5d3_xplained.dtb 429 at91-sama5d3_xplained.dtb
432 430
433 dtb-$(CONFIG_TARGET_SAMA5D4EK) += \ 431 dtb-$(CONFIG_TARGET_SAMA5D4EK) += \
434 at91-sama5d4ek.dtb 432 at91-sama5d4ek.dtb
435 433
436 dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \ 434 dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \
437 at91-sama5d4_xplained.dtb 435 at91-sama5d4_xplained.dtb
438 436
439 dtb-$(CONFIG_ARCH_BCM283X) += \ 437 dtb-$(CONFIG_ARCH_BCM283X) += \
440 bcm2835-rpi-a-plus.dtb \ 438 bcm2835-rpi-a-plus.dtb \
441 bcm2835-rpi-a.dtb \ 439 bcm2835-rpi-a.dtb \
442 bcm2835-rpi-b-plus.dtb \ 440 bcm2835-rpi-b-plus.dtb \
443 bcm2835-rpi-b-rev2.dtb \ 441 bcm2835-rpi-b-rev2.dtb \
444 bcm2835-rpi-b.dtb \ 442 bcm2835-rpi-b.dtb \
445 bcm2836-rpi-2-b.dtb \ 443 bcm2836-rpi-2-b.dtb \
446 bcm2837-rpi-3-b.dtb 444 bcm2837-rpi-3-b.dtb
447 445
448 dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb 446 dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
449 447
450 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb 448 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
451 449
452 targets += $(dtb-y) 450 targets += $(dtb-y)
453 451
454 # Add any required device tree compiler flags here 452 # Add any required device tree compiler flags here
455 DTC_FLAGS += 453 DTC_FLAGS +=
456 454
457 PHONY += dtbs 455 PHONY += dtbs
458 dtbs: $(addprefix $(obj)/, $(dtb-y)) 456 dtbs: $(addprefix $(obj)/, $(dtb-y))
459 @: 457 @:
460 458
461 clean-files := *.dtb 459 clean-files := *.dtb
462 460
arch/arm/dts/uniphier-sld3-ref.dts
View file @ 00aa453
1 /* File was deleted
2 * Device Tree Source for UniPhier sLD3 Reference Board
3 *
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
9
10 /dts-v1/;
11 /include/ "uniphier-sld3.dtsi"
12 /include/ "uniphier-ref-daughter.dtsi"
13 /include/ "uniphier-support-card.dtsi"
14
15 / {
16 model = "UniPhier sLD3 Reference Board";
17 compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3";
18
19 chosen {
20 stdout-path = "serial0:115200n8";
21 };
22
23 aliases {
24 serial0 = &serial0;
25 serial1 = &serial1;
26 serial2 = &serial2;
27 i2c0 = &i2c0;
28 i2c1 = &i2c1;
29 i2c2 = &i2c2;
30 i2c3 = &i2c3;
31 i2c4 = &i2c4;
32 };
33
34 memory@8000000 {
35 device_type = "memory";
36 reg = <0x80000000 0x20000000
37 0xc0000000 0x20000000>;
38 };
39 };
40
41 &ethsc {
42 interrupts = <0 49 4>;
43 };
44
45 &serial0 {
46 status = "okay";
47 };
48
49 &serial1 {
50 status = "okay";
51 };
52
53 &serial2 {
54 status = "okay";
55 };
56
57 &i2c0 {
58 status = "okay";
59 };
60
61 &emmc {
62 status = "okay";
63 };
64
65 &sd {
66 status = "okay";
67 };
68
69 &usb0 {
70 status = "okay";
71 };
72
73 &usb1 {
74 status = "okay";
75 };
76
77 &usb2 {
78 status = "okay";
79 };
80
81 &usb3 {
82 status = "okay";
83 };
84
85 /* for U-Boot only */
86 &serial0 {
87 u-boot,dm-pre-reloc;
88 };
89
90 &emmc {
91 u-boot,dm-pre-reloc;
92 };
93
94 &pinctrl_uart0 {
95 u-boot,dm-pre-reloc;
96 };
97
98 &pinctrl_emmc {
99 u-boot,dm-pre-reloc;
100 };
101 1 /*
arch/arm/dts/uniphier-sld3.dtsi
View file @ 00aa453
1 /* File was deleted
2 * Device Tree Source for UniPhier sLD3 SoC
3 *
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
9
10 / {
11 compatible = "socionext,uniphier-sld3";
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
23 enable-method = "psci";
24 next-level-cache = <&l2>;
25 };
26
27 cpu@1 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a9";
30 reg = <1>;
31 enable-method = "psci";
32 next-level-cache = <&l2>;
33 };
34 };
35
36 psci {
37 compatible = "arm,psci-0.2";
38 method = "smc";
39 };
40
41 clocks {
42 refclk: ref {
43 #clock-cells = <0>;
44 compatible = "fixed-clock";
45 clock-frequency = <24576000>;
46 };
47
48 arm_timer_clk: arm_timer_clk {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <50000000>;
52 };
53 };
54
55 soc {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60 interrupt-parent = <&intc>;
61 u-boot,dm-pre-reloc;
62
63 timer@20000200 {
64 compatible = "arm,cortex-a9-global-timer";
65 reg = <0x20000200 0x20>;
66 interrupts = <1 11 0x304>;
67 clocks = <&arm_timer_clk>;
68 };
69
70 timer@20000600 {
71 compatible = "arm,cortex-a9-twd-timer";
72 reg = <0x20000600 0x20>;
73 interrupts = <1 13 0x304>;
74 clocks = <&arm_timer_clk>;
75 };
76
77 intc: interrupt-controller@20001000 {
78 compatible = "arm,cortex-a9-gic";
79 #interrupt-cells = <3>;
80 interrupt-controller;
81 reg = <0x20001000 0x1000>,
82 <0x20000100 0x100>;
83 };
84
85 l2: l2-cache@500c0000 {
86 compatible = "socionext,uniphier-system-cache";
87 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
88 <0x506c0000 0x400>;
89 interrupts = <0 174 4>, <0 175 4>;
90 cache-unified;
91 cache-size = <(512 * 1024)>;
92 cache-sets = <256>;
93 cache-line-size = <128>;
94 cache-level = <2>;
95 };
96
97 serial0: serial@54006800 {
98 compatible = "socionext,uniphier-uart";
99 status = "disabled";
100 reg = <0x54006800 0x40>;
101 interrupts = <0 33 4>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_uart0>;
104 clocks = <&sys_clk 0>;
105 clock-frequency = <36864000>;
106 };
107
108 serial1: serial@54006900 {
109 compatible = "socionext,uniphier-uart";
110 status = "disabled";
111 reg = <0x54006900 0x40>;
112 interrupts = <0 35 4>;
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_uart1>;
115 clocks = <&sys_clk 0>;
116 clock-frequency = <36864000>;
117 };
118
119 serial2: serial@54006a00 {
120 compatible = "socionext,uniphier-uart";
121 status = "disabled";
122 reg = <0x54006a00 0x40>;
123 interrupts = <0 37 4>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_uart2>;
126 clocks = <&sys_clk 0>;
127 clock-frequency = <36864000>;
128 };
129
130 port0x: gpio@55000008 {
131 compatible = "socionext,uniphier-gpio";
132 reg = <0x55000008 0x8>;
133 gpio-controller;
134 #gpio-cells = <2>;
135 };
136
137 port1x: gpio@55000010 {
138 compatible = "socionext,uniphier-gpio";
139 reg = <0x55000010 0x8>;
140 gpio-controller;
141 #gpio-cells = <2>;
142 };
143
144 port2x: gpio@55000018 {
145 compatible = "socionext,uniphier-gpio";
146 reg = <0x55000018 0x8>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 };
150
151 port3x: gpio@55000020 {
152 compatible = "socionext,uniphier-gpio";
153 reg = <0x55000020 0x8>;
154 gpio-controller;
155 #gpio-cells = <2>;
156 };
157
158 port4: gpio@55000028 {
159 compatible = "socionext,uniphier-gpio";
160 reg = <0x55000028 0x8>;
161 gpio-controller;
162 #gpio-cells = <2>;
163 };
164
165 port5x: gpio@55000030 {
166 compatible = "socionext,uniphier-gpio";
167 reg = <0x55000030 0x8>;
168 gpio-controller;
169 #gpio-cells = <2>;
170 };
171
172 port6x: gpio@55000038 {
173 compatible = "socionext,uniphier-gpio";
174 reg = <0x55000038 0x8>;
175 gpio-controller;
176 #gpio-cells = <2>;
177 };
178
179 port7x: gpio@55000040 {
180 compatible = "socionext,uniphier-gpio";
181 reg = <0x55000040 0x8>;
182 gpio-controller;
183 #gpio-cells = <2>;
184 };
185
186 port8x: gpio@55000048 {
187 compatible = "socionext,uniphier-gpio";
188 reg = <0x55000048 0x8>;
189 gpio-controller;
190 #gpio-cells = <2>;
191 };
192
193 port9x: gpio@55000050 {
194 compatible = "socionext,uniphier-gpio";
195 reg = <0x55000050 0x8>;
196 gpio-controller;
197 #gpio-cells = <2>;
198 };
199
200 port10x: gpio@55000058 {
201 compatible = "socionext,uniphier-gpio";
202 reg = <0x55000058 0x8>;
203 gpio-controller;
204 #gpio-cells = <2>;
205 };
206
207 port11x: gpio@55000060 {
208 compatible = "socionext,uniphier-gpio";
209 reg = <0x55000060 0x8>;
210 gpio-controller;
211 #gpio-cells = <2>;
212 };
213
214 port12x: gpio@55000068 {
215 compatible = "socionext,uniphier-gpio";
216 reg = <0x55000068 0x8>;
217 gpio-controller;
218 #gpio-cells = <2>;
219 };
220
221 port13x: gpio@55000070 {
222 compatible = "socionext,uniphier-gpio";
223 reg = <0x55000070 0x8>;
224 gpio-controller;
225 #gpio-cells = <2>;
226 };
227
228 port14x: gpio@55000078 {
229 compatible = "socionext,uniphier-gpio";
230 reg = <0x55000078 0x8>;
231 gpio-controller;
232 #gpio-cells = <2>;
233 };
234
235 port16x: gpio@55000088 {
236 compatible = "socionext,uniphier-gpio";
237 reg = <0x55000088 0x8>;
238 gpio-controller;
239 #gpio-cells = <2>;
240 };
241
242 i2c0: i2c@58400000 {
243 compatible = "socionext,uniphier-i2c";
244 status = "disabled";
245 reg = <0x58400000 0x40>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 interrupts = <0 41 1>;
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_i2c0>;
251 clocks = <&sys_clk 1>;
252 clock-frequency = <100000>;
253 };
254
255 i2c1: i2c@58480000 {
256 compatible = "socionext,uniphier-i2c";
257 status = "disabled";
258 reg = <0x58480000 0x40>;
259 #address-cells = <1>;
260 #size-cells = <0>;
261 interrupts = <0 42 1>;
262 clocks = <&sys_clk 1>;
263 clock-frequency = <100000>;
264 };
265
266 i2c2: i2c@58500000 {
267 compatible = "socionext,uniphier-i2c";
268 status = "disabled";
269 reg = <0x58500000 0x40>;
270 #address-cells = <1>;
271 #size-cells = <0>;
272 interrupts = <0 43 1>;
273 clocks = <&sys_clk 1>;
274 clock-frequency = <100000>;
275 };
276
277 i2c3: i2c@58580000 {
278 compatible = "socionext,uniphier-i2c";
279 status = "disabled";
280 reg = <0x58580000 0x40>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 interrupts = <0 44 1>;
284 clocks = <&sys_clk 1>;
285 clock-frequency = <100000>;
286 };
287
288 /* chip-internal connection for DMD */
289 i2c4: i2c@58600000 {
290 compatible = "socionext,uniphier-i2c";
291 reg = <0x58600000 0x40>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 interrupts = <0 45 1>;
295 clocks = <&sys_clk 1>;
296 clock-frequency = <400000>;
297 };
298
299 system_bus: system-bus@58c00000 {
300 compatible = "socionext,uniphier-system-bus";
301 status = "disabled";
302 reg = <0x58c00000 0x400>;
303 #address-cells = <2>;
304 #size-cells = <1>;
305 };
306
307 smpctrl@59801000 {
308 compatible = "socionext,uniphier-smpctrl";
309 reg = <0x59801000 0x400>;
310 };
311
312 mioctrl@59810000 {
313 compatible = "socionext,uniphier-sld3-mioctrl",
314 "simple-mfd", "syscon";
315 reg = <0x59810000 0x800>;
316 u-boot,dm-pre-reloc;
317
318 mio_clk: clock {
319 compatible = "socionext,uniphier-sld3-mio-clock";
320 #clock-cells = <1>;
321 u-boot,dm-pre-reloc;
322 };
323
324 mio_rst: reset {
325 compatible = "socionext,uniphier-sld3-mio-reset";
326 #reset-cells = <1>;
327 };
328 };
329
330 emmc: sdhc@5a400000 {
331 compatible = "socionext,uniphier-sdhc";
332 status = "disabled";
333 reg = <0x5a400000 0x200>;
334 interrupts = <0 78 4>;
335 pinctrl-names = "default", "1.8v";
336 pinctrl-0 = <&pinctrl_emmc>;
337 pinctrl-1 = <&pinctrl_emmc_1v8>;
338 clocks = <&mio_clk 1>;
339 reset-names = "host", "bridge";
340 resets = <&mio_rst 1>, <&mio_rst 4>;
341 bus-width = <8>;
342 non-removable;
343 cap-mmc-highspeed;
344 cap-mmc-hw-reset;
345 };
346
347 sd: sdhc@5a500000 {
348 compatible = "socionext,uniphier-sdhc";
349 status = "disabled";
350 reg = <0x5a500000 0x200>;
351 interrupts = <0 76 4>;
352 pinctrl-names = "default", "1.8v";
353 pinctrl-0 = <&pinctrl_sd>;
354 pinctrl-1 = <&pinctrl_sd_1v8>;
355 clocks = <&mio_clk 0>;
356 reset-names = "host", "bridge";
357 resets = <&mio_rst 0>, <&mio_rst 3>;
358 bus-width = <4>;
359 cap-sd-highspeed;
360 sd-uhs-sdr12;
361 sd-uhs-sdr25;
362 sd-uhs-sdr50;
363 };
364
365 usb0: usb@5a800100 {
366 compatible = "socionext,uniphier-ehci", "generic-ehci";
367 status = "disabled";
368 reg = <0x5a800100 0x100>;
369 interrupts = <0 80 4>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_usb0>;
372 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
373 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
374 <&mio_rst 12>;
375 };
376
377 usb1: usb@5a810100 {
378 compatible = "socionext,uniphier-ehci", "generic-ehci";
379 status = "disabled";
380 reg = <0x5a810100 0x100>;
381 interrupts = <0 81 4>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_usb1>;
384 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
385 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
386 <&mio_rst 13>;
387 };
388
389 usb2: usb@5a820100 {
390 compatible = "socionext,uniphier-ehci", "generic-ehci";
391 status = "disabled";
392 reg = <0x5a820100 0x100>;
393 interrupts = <0 82 4>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_usb2>;
396 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
397 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
398 <&mio_rst 14>;
399 };
400
401 usb3: usb@5a830100 {
402 compatible = "socionext,uniphier-ehci", "generic-ehci";
403 status = "disabled";
404 reg = <0x5a830100 0x100>;
405 interrupts = <0 83 4>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_usb3>;
408 clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
409 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
410 <&mio_rst 15>;
411 };
412
413 soc-glue@5f800000 {
414 compatible = "socionext,uniphier-sld3-soc-glue",
415 "simple-mfd", "syscon";
416 reg = <0x5f800000 0x2000>;
417 u-boot,dm-pre-reloc;
418
419 pinctrl: pinctrl {
420 compatible = "socionext,uniphier-sld3-pinctrl";
421 u-boot,dm-pre-reloc;
422 };
423 };
424
425 aidet@f1830000 {
426 compatible = "simple-mfd", "syscon";
427 reg = <0xf1830000 0x200>;
428 };
429
430 sysctrl@f1840000 {
431 compatible = "socionext,uniphier-sld3-sysctrl",
432 "simple-mfd", "syscon";
433 reg = <0xf1840000 0x10000>;
434
435 sys_clk: clock {
436 compatible = "socionext,uniphier-sld3-clock";
437 #clock-cells = <1>;
438 };
439
440 sys_rst: reset {
441 compatible = "socionext,uniphier-sld3-reset";
442 #reset-cells = <1>;
443 };
444 };
445
446 nand: nand@f8000000 {
447 compatible = "socionext,uniphier-denali-nand-v5a";
448 status = "disabled";
449 reg-names = "nand_data", "denali_reg";
450 reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
451 interrupts = <0 65 4>;
452 clocks = <&sys_clk 2>;
453 nand-ecc-strength = <8>;
454 };
455 };
456 };
457
458 /include/ "uniphier-pinctrl.dtsi"
459 1 /*
arch/arm/mach-uniphier/Kconfig
Diff comments   View file @ 00aa453
1 if ARCH_UNIPHIER 1 if ARCH_UNIPHIER
2 2
3 config SYS_CONFIG_NAME 3 config SYS_CONFIG_NAME
4 default "uniphier" 4 default "uniphier"
5 5
6 config ARCH_UNIPHIER_32BIT 6 config ARCH_UNIPHIER_32BIT
7 bool 7 bool
8 select CPU_V7 8 select CPU_V7
9 select CPU_V7_HAS_NONSEC 9 select CPU_V7_HAS_NONSEC
10 select ARMV7_NONSEC 10 select ARMV7_NONSEC
11 select ARCH_SUPPORT_PSCI 11 select ARCH_SUPPORT_PSCI
12 imply NAND 12 imply NAND
13 13
14 choice 14 choice
15 prompt "UniPhier SoC select" 15 prompt "UniPhier SoC select"
16 default ARCH_UNIPHIER_PRO4 16 default ARCH_UNIPHIER_PRO4
17 17
18 config ARCH_UNIPHIER_SLD3
19 bool "UniPhier sLD3 SoC"
20 select ARCH_UNIPHIER_32BIT
21
22 config ARCH_UNIPHIER_LD4_SLD8 18 config ARCH_UNIPHIER_LD4_SLD8
23 bool "UniPhier LD4/sLD8 SoCs" 19 bool "UniPhier LD4/sLD8 SoCs"
24 select ARCH_UNIPHIER_32BIT 20 select ARCH_UNIPHIER_32BIT
25 21
26 config ARCH_UNIPHIER_PRO4 22 config ARCH_UNIPHIER_PRO4
27 bool "UniPhier Pro4 SoC" 23 bool "UniPhier Pro4 SoC"
28 select ARCH_UNIPHIER_32BIT 24 select ARCH_UNIPHIER_32BIT
29 25
30 config ARCH_UNIPHIER_PRO5_PXS2_LD6B 26 config ARCH_UNIPHIER_PRO5_PXS2_LD6B
31 bool "UniPhier Pro5/PXs2/LD6b SoCs" 27 bool "UniPhier Pro5/PXs2/LD6b SoCs"
32 select ARCH_UNIPHIER_32BIT 28 select ARCH_UNIPHIER_32BIT
33 29
34 config ARCH_UNIPHIER_V8_MULTI 30 config ARCH_UNIPHIER_V8_MULTI
35 bool "UniPhier V8 SoCs" 31 bool "UniPhier V8 SoCs"
36 depends on !SPL 32 depends on !SPL
37 select ARM64 33 select ARM64
38 select CMD_UNZIP 34 select CMD_UNZIP
39 35
40 endchoice 36 endchoice
41 37
42 config ARCH_UNIPHIER_LD4 38 config ARCH_UNIPHIER_LD4
43 bool "Enable UniPhier LD4 SoC support" 39 bool "Enable UniPhier LD4 SoC support"
44 depends on ARCH_UNIPHIER_LD4_SLD8 40 depends on ARCH_UNIPHIER_LD4_SLD8
45 default y 41 default y
46 42
47 config ARCH_UNIPHIER_SLD8 43 config ARCH_UNIPHIER_SLD8
48 bool "Enable UniPhier sLD8 SoC support" 44 bool "Enable UniPhier sLD8 SoC support"
49 depends on ARCH_UNIPHIER_LD4_SLD8 45 depends on ARCH_UNIPHIER_LD4_SLD8
50 default y 46 default y
51 47
52 config ARCH_UNIPHIER_PRO5 48 config ARCH_UNIPHIER_PRO5
53 bool "Enable UniPhier Pro5 SoC support" 49 bool "Enable UniPhier Pro5 SoC support"
54 depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B 50 depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
55 default y 51 default y
56 52
57 config ARCH_UNIPHIER_PXS2 53 config ARCH_UNIPHIER_PXS2
58 bool "Enable UniPhier Pxs2 SoC support" 54 bool "Enable UniPhier Pxs2 SoC support"
59 depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B 55 depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
60 default y 56 default y
61 57
62 config ARCH_UNIPHIER_LD6B 58 config ARCH_UNIPHIER_LD6B
63 bool "Enable UniPhier LD6b SoC support" 59 bool "Enable UniPhier LD6b SoC support"
64 depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B 60 depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
65 default y 61 default y
66 62
67 config ARCH_UNIPHIER_LD11 63 config ARCH_UNIPHIER_LD11
68 bool "Enable UniPhier LD11 SoC support" 64 bool "Enable UniPhier LD11 SoC support"
69 depends on ARCH_UNIPHIER_V8_MULTI 65 depends on ARCH_UNIPHIER_V8_MULTI
70 default y 66 default y
71 67
72 config ARCH_UNIPHIER_LD20 68 config ARCH_UNIPHIER_LD20
73 bool "Enable UniPhier LD20 SoC support" 69 bool "Enable UniPhier LD20 SoC support"
74 depends on ARCH_UNIPHIER_V8_MULTI 70 depends on ARCH_UNIPHIER_V8_MULTI
75 select OF_BOARD_SETUP 71 select OF_BOARD_SETUP
76 default y 72 default y
77 73
78 config ARCH_UNIPHIER_PXS3 74 config ARCH_UNIPHIER_PXS3
79 bool "Enable UniPhier PXs3 SoC support" 75 bool "Enable UniPhier PXs3 SoC support"
80 depends on ARCH_UNIPHIER_V8_MULTI 76 depends on ARCH_UNIPHIER_V8_MULTI
81 default y 77 default y
82 78
83 config CACHE_UNIPHIER 79 config CACHE_UNIPHIER
84 bool "Enable the UniPhier L2 cache controller" 80 bool "Enable the UniPhier L2 cache controller"
85 depends on ARCH_UNIPHIER_32BIT 81 depends on ARCH_UNIPHIER_32BIT
86 select SYS_CACHE_SHIFT_7 82 select SYS_CACHE_SHIFT_7
87 default y 83 default y
88 help 84 help
89 This option allows to use the UniPhier System Cache as L2 cache. 85 This option allows to use the UniPhier System Cache as L2 cache.
90 86
91 config MICRO_SUPPORT_CARD 87 config MICRO_SUPPORT_CARD
92 bool "Use Micro Support Card" 88 bool "Use Micro Support Card"
93 help 89 help
94 This option provides support for the expansion board, available 90 This option provides support for the expansion board, available
95 on some UniPhier reference boards. 91 on some UniPhier reference boards.
96 92
97 Say Y to use the on-board UART, Ether, LED devices. 93 Say Y to use the on-board UART, Ether, LED devices.
98 94
99 config CMD_PINMON 95 config CMD_PINMON
100 bool "Enable boot mode pins monitor command" 96 bool "Enable boot mode pins monitor command"
101 default y 97 default y
102 help 98 help
103 The command "pinmon" shows the state of the boot mode pins. 99 The command "pinmon" shows the state of the boot mode pins.
104 The boot mode pins are latched when the system reset is deasserted 100 The boot mode pins are latched when the system reset is deasserted
105 and determine which device the system should load a boot image from. 101 and determine which device the system should load a boot image from.
106 102
107 config CMD_DDRPHY_DUMP 103 config CMD_DDRPHY_DUMP
108 bool "Enable dump command of DDR PHY parameters" 104 bool "Enable dump command of DDR PHY parameters"
109 depends on ARCH_UNIPHIER_LD4 || ARCH_UNIPHIER_PRO4 || \ 105 depends on ARCH_UNIPHIER_LD4 || ARCH_UNIPHIER_PRO4 || \
110 ARCH_UNIPHIER_SLD8 || ARCH_UNIPHIER_LD11 106 ARCH_UNIPHIER_SLD8 || ARCH_UNIPHIER_LD11
111 default y 107 default y
112 help 108 help
113 The command "ddrphy" shows the resulting parameters of DDR PHY 109 The command "ddrphy" shows the resulting parameters of DDR PHY
114 training; it is useful for the evaluation of DDR PHY training. 110 training; it is useful for the evaluation of DDR PHY training.
115 111
116 config CMD_DDRMPHY_DUMP 112 config CMD_DDRMPHY_DUMP
117 bool "Enable dump command of DDR Multi PHY parameters" 113 bool "Enable dump command of DDR Multi PHY parameters"
118 depends on ARCH_UNIPHIER_PXS2 || ARCH_UNIPHIER_LD6B 114 depends on ARCH_UNIPHIER_PXS2 || ARCH_UNIPHIER_LD6B
119 default y 115 default y
120 help 116 help
121 The command "ddrmphy" shows the resulting parameters of DDR Multi PHY 117 The command "ddrmphy" shows the resulting parameters of DDR Multi PHY
122 training; it is useful for the evaluation of DDR Multi PHY training. 118 training; it is useful for the evaluation of DDR Multi PHY training.
123 119
124 endif 120 endif
125 121
arch/arm/mach-uniphier/arm32/cache-uniphier.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2012-2014 Panasonic Corporation 2 * Copyright (C) 2012-2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc. 3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <common.h> 9 #include <common.h>
10 #include <linux/io.h> 10 #include <linux/io.h>
11 #include <linux/kernel.h> 11 #include <linux/kernel.h>
12 #include <asm/armv7.h> 12 #include <asm/armv7.h>
13 #include <asm/processor.h> 13 #include <asm/processor.h>
14 14
15 #include "cache-uniphier.h" 15 #include "cache-uniphier.h"
16 16
17 /* control registers */ 17 /* control registers */
18 #define UNIPHIER_SSCC 0x500c0000 /* Control Register */ 18 #define UNIPHIER_SSCC 0x500c0000 /* Control Register */
19 #define UNIPHIER_SSCC_BST (0x1 << 20) /* UCWG burst read */ 19 #define UNIPHIER_SSCC_BST (0x1 << 20) /* UCWG burst read */
20 #define UNIPHIER_SSCC_ACT (0x1 << 19) /* Inst-Data separate */ 20 #define UNIPHIER_SSCC_ACT (0x1 << 19) /* Inst-Data separate */
21 #define UNIPHIER_SSCC_WTG (0x1 << 18) /* WT gathering on */ 21 #define UNIPHIER_SSCC_WTG (0x1 << 18) /* WT gathering on */
22 #define UNIPHIER_SSCC_PRD (0x1 << 17) /* enable pre-fetch */ 22 #define UNIPHIER_SSCC_PRD (0x1 << 17) /* enable pre-fetch */
23 #define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */ 23 #define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */
24 #define UNIPHIER_SSCLPDAWCR 0x500c0030 /* Unified/Data Active Way Control */ 24 #define UNIPHIER_SSCLPDAWCR 0x500c0030 /* Unified/Data Active Way Control */
25 #define UNIPHIER_SSCLPIAWCR 0x500c0034 /* Instruction Active Way Control */ 25 #define UNIPHIER_SSCLPIAWCR 0x500c0034 /* Instruction Active Way Control */
26 26
27 /* revision registers */ 27 /* revision registers */
28 #define UNIPHIER_SSCID 0x503c0100 /* ID Register */ 28 #define UNIPHIER_SSCID 0x503c0100 /* ID Register */
29 29
30 /* operation registers */ 30 /* operation registers */
31 #define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */ 31 #define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */
32 #define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */ 32 #define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */
33 #define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */ 33 #define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */
34 #define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */ 34 #define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */
35 #define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */ 35 #define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */
36 #define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */ 36 #define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
37 #define UNIPHIER_SSCOQM 0x506c0248 37 #define UNIPHIER_SSCOQM 0x506c0248
38 #define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21) 38 #define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21)
39 #define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21) 39 #define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21)
40 #define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21) 40 #define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21)
41 #define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21) 41 #define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21)
42 #define UNIPHIER_SSCOQM_S_MASK (0x3 << 17) 42 #define UNIPHIER_SSCOQM_S_MASK (0x3 << 17)
43 #define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17) 43 #define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17)
44 #define UNIPHIER_SSCOQM_S_ALL (0x1 << 17) 44 #define UNIPHIER_SSCOQM_S_ALL (0x1 << 17)
45 #define UNIPHIER_SSCOQM_S_WAY (0x2 << 17) 45 #define UNIPHIER_SSCOQM_S_WAY (0x2 << 17)
46 #define UNIPHIER_SSCOQM_CE (0x1 << 15) /* notify completion */ 46 #define UNIPHIER_SSCOQM_CE (0x1 << 15) /* notify completion */
47 #define UNIPHIER_SSCOQM_CW (0x1 << 14) 47 #define UNIPHIER_SSCOQM_CW (0x1 << 14)
48 #define UNIPHIER_SSCOQM_CM_MASK (0x7) 48 #define UNIPHIER_SSCOQM_CM_MASK (0x7)
49 #define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */ 49 #define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */
50 #define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */ 50 #define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */
51 #define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */ 51 #define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */
52 #define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */ 52 #define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */
53 #define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */ 53 #define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */
54 #define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */ 54 #define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */
55 #define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */ 55 #define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */
56 #define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */ 56 #define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */
57 #define UNIPHIER_SSCOQAD 0x506c024c /* Cache Operation Queue Address */ 57 #define UNIPHIER_SSCOQAD 0x506c024c /* Cache Operation Queue Address */
58 #define UNIPHIER_SSCOQSZ 0x506c0250 /* Cache Operation Queue Size */ 58 #define UNIPHIER_SSCOQSZ 0x506c0250 /* Cache Operation Queue Size */
59 #define UNIPHIER_SSCOQMASK 0x506c0254 /* Cache Operation Queue Address Mask */ 59 #define UNIPHIER_SSCOQMASK 0x506c0254 /* Cache Operation Queue Address Mask */
60 #define UNIPHIER_SSCOQWN 0x506c0258 /* Cache Operation Queue Way Number */ 60 #define UNIPHIER_SSCOQWN 0x506c0258 /* Cache Operation Queue Way Number */
61 #define UNIPHIER_SSCOPPQSEF 0x506c025c /* Cache Operation Queue Set Complete */ 61 #define UNIPHIER_SSCOPPQSEF 0x506c025c /* Cache Operation Queue Set Complete */
62 #define UNIPHIER_SSCOPPQSEF_FE (0x1 << 1) 62 #define UNIPHIER_SSCOPPQSEF_FE (0x1 << 1)
63 #define UNIPHIER_SSCOPPQSEF_OE (0x1 << 0) 63 #define UNIPHIER_SSCOPPQSEF_OE (0x1 << 0)
64 #define UNIPHIER_SSCOLPQS 0x506c0260 /* Cache Operation Queue Status */ 64 #define UNIPHIER_SSCOLPQS 0x506c0260 /* Cache Operation Queue Status */
65 #define UNIPHIER_SSCOLPQS_EF (0x1 << 2) 65 #define UNIPHIER_SSCOLPQS_EF (0x1 << 2)
66 #define UNIPHIER_SSCOLPQS_EST (0x1 << 1) 66 #define UNIPHIER_SSCOLPQS_EST (0x1 << 1)
67 #define UNIPHIER_SSCOLPQS_QST (0x1 << 0) 67 #define UNIPHIER_SSCOLPQS_QST (0x1 << 0)
68 68
69 #define UNIPHIER_SSC_LINE_SIZE 128 69 #define UNIPHIER_SSC_LINE_SIZE 128
70 #define UNIPHIER_SSC_RANGE_OP_MAX_SIZE (0x00400000 - (UNIPHIER_SSC_LINE_SIZE)) 70 #define UNIPHIER_SSC_RANGE_OP_MAX_SIZE (0x00400000 - (UNIPHIER_SSC_LINE_SIZE))
71 71
72 #define UNIPHIER_SSCOQAD_IS_NEEDED(op) \ 72 #define UNIPHIER_SSCOQAD_IS_NEEDED(op) \
73 ((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE) 73 ((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE)
74 #define UNIPHIER_SSCOQWM_IS_NEEDED(op) \ 74 #define UNIPHIER_SSCOQWM_IS_NEEDED(op) \
75 (((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_WAY) || \ 75 (((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_WAY) || \
76 ((op & UNIPHIER_SSCOQM_TID_MASK) == UNIPHIER_SSCOQM_TID_WAY)) 76 ((op & UNIPHIER_SSCOQM_TID_MASK) == UNIPHIER_SSCOQM_TID_WAY))
77 77
78 /* uniphier_cache_sync - perform a sync point for a particular cache level */ 78 /* uniphier_cache_sync - perform a sync point for a particular cache level */
79 static void uniphier_cache_sync(void) 79 static void uniphier_cache_sync(void)
80 { 80 {
81 /* drain internal buffers */ 81 /* drain internal buffers */
82 writel(UNIPHIER_SSCOPE_CM_SYNC, UNIPHIER_SSCOPE); 82 writel(UNIPHIER_SSCOPE_CM_SYNC, UNIPHIER_SSCOPE);
83 /* need a read back to confirm */ 83 /* need a read back to confirm */
84 readl(UNIPHIER_SSCOPE); 84 readl(UNIPHIER_SSCOPE);
85 } 85 }
86 86
87 /** 87 /**
88 * uniphier_cache_maint_common - run a queue operation 88 * uniphier_cache_maint_common - run a queue operation
89 * 89 *
90 * @start: start address of range operation (don't care for "all" operation) 90 * @start: start address of range operation (don't care for "all" operation)
91 * @size: data size of range operation (don't care for "all" operation) 91 * @size: data size of range operation (don't care for "all" operation)
92 * @ways: target ways (don't care for operations other than pre-fetch, touch 92 * @ways: target ways (don't care for operations other than pre-fetch, touch
93 * @operation: flags to specify the desired cache operation 93 * @operation: flags to specify the desired cache operation
94 */ 94 */
95 static void uniphier_cache_maint_common(u32 start, u32 size, u32 ways, 95 static void uniphier_cache_maint_common(u32 start, u32 size, u32 ways,
96 u32 operation) 96 u32 operation)
97 { 97 {
98 /* clear the complete notification flag */ 98 /* clear the complete notification flag */
99 writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS); 99 writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS);
100 100
101 do { 101 do {
102 /* set cache operation */ 102 /* set cache operation */
103 writel(UNIPHIER_SSCOQM_CE | operation, UNIPHIER_SSCOQM); 103 writel(UNIPHIER_SSCOQM_CE | operation, UNIPHIER_SSCOQM);
104 104
105 /* set address range if needed */ 105 /* set address range if needed */
106 if (likely(UNIPHIER_SSCOQAD_IS_NEEDED(operation))) { 106 if (likely(UNIPHIER_SSCOQAD_IS_NEEDED(operation))) {
107 writel(start, UNIPHIER_SSCOQAD); 107 writel(start, UNIPHIER_SSCOQAD);
108 writel(size, UNIPHIER_SSCOQSZ); 108 writel(size, UNIPHIER_SSCOQSZ);
109 } 109 }
110 110
111 /* set target ways if needed */ 111 /* set target ways if needed */
112 if (unlikely(UNIPHIER_SSCOQWM_IS_NEEDED(operation))) 112 if (unlikely(UNIPHIER_SSCOQWM_IS_NEEDED(operation)))
113 writel(ways, UNIPHIER_SSCOQWN); 113 writel(ways, UNIPHIER_SSCOQWN);
114 } while (unlikely(readl(UNIPHIER_SSCOPPQSEF) & 114 } while (unlikely(readl(UNIPHIER_SSCOPPQSEF) &
115 (UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE))); 115 (UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE)));
116 116
117 /* wait until the operation is completed */ 117 /* wait until the operation is completed */
118 while (likely(readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF)) 118 while (likely(readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF))
119 cpu_relax(); 119 cpu_relax();
120 } 120 }
121 121
122 static void uniphier_cache_maint_all(u32 operation) 122 static void uniphier_cache_maint_all(u32 operation)
123 { 123 {
124 uniphier_cache_maint_common(0, 0, 0, UNIPHIER_SSCOQM_S_ALL | operation); 124 uniphier_cache_maint_common(0, 0, 0, UNIPHIER_SSCOQM_S_ALL | operation);
125 125
126 uniphier_cache_sync(); 126 uniphier_cache_sync();
127 } 127 }
128 128
129 static void uniphier_cache_maint_range(u32 start, u32 end, u32 ways, 129 static void uniphier_cache_maint_range(u32 start, u32 end, u32 ways,
130 u32 operation) 130 u32 operation)
131 { 131 {
132 u32 size; 132 u32 size;
133 133
134 /* 134 /*
135 * If the start address is not aligned, 135 * If the start address is not aligned,
136 * perform a cache operation for the first cache-line 136 * perform a cache operation for the first cache-line
137 */ 137 */
138 start = start & ~(UNIPHIER_SSC_LINE_SIZE - 1); 138 start = start & ~(UNIPHIER_SSC_LINE_SIZE - 1);
139 139
140 size = end - start; 140 size = end - start;
141 141
142 if (unlikely(size >= (u32)(-UNIPHIER_SSC_LINE_SIZE))) { 142 if (unlikely(size >= (u32)(-UNIPHIER_SSC_LINE_SIZE))) {
143 /* this means cache operation for all range */ 143 /* this means cache operation for all range */
144 uniphier_cache_maint_all(operation); 144 uniphier_cache_maint_all(operation);
145 return; 145 return;
146 } 146 }
147 147
148 /* 148 /*
149 * If the end address is not aligned, 149 * If the end address is not aligned,
150 * perform a cache operation for the last cache-line 150 * perform a cache operation for the last cache-line
151 */ 151 */
152 size = ALIGN(size, UNIPHIER_SSC_LINE_SIZE); 152 size = ALIGN(size, UNIPHIER_SSC_LINE_SIZE);
153 153
154 while (size) { 154 while (size) {
155 u32 chunk_size = min_t(u32, size, UNIPHIER_SSC_RANGE_OP_MAX_SIZE); 155 u32 chunk_size = min_t(u32, size, UNIPHIER_SSC_RANGE_OP_MAX_SIZE);
156 156
157 uniphier_cache_maint_common(start, chunk_size, ways, 157 uniphier_cache_maint_common(start, chunk_size, ways,
158 UNIPHIER_SSCOQM_S_RANGE | operation); 158 UNIPHIER_SSCOQM_S_RANGE | operation);
159 159
160 start += chunk_size; 160 start += chunk_size;
161 size -= chunk_size; 161 size -= chunk_size;
162 } 162 }
163 163
164 uniphier_cache_sync(); 164 uniphier_cache_sync();
165 } 165 }
166 166
167 void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways) 167 void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways)
168 { 168 {
169 uniphier_cache_maint_range(start, end, ways, 169 uniphier_cache_maint_range(start, end, ways,
170 UNIPHIER_SSCOQM_TID_WAY | 170 UNIPHIER_SSCOQM_TID_WAY |
171 UNIPHIER_SSCOQM_CM_PREFETCH); 171 UNIPHIER_SSCOQM_CM_PREFETCH);
172 } 172 }
173 173
174 void uniphier_cache_touch_range(u32 start, u32 end, u32 ways) 174 void uniphier_cache_touch_range(u32 start, u32 end, u32 ways)
175 { 175 {
176 uniphier_cache_maint_range(start, end, ways, 176 uniphier_cache_maint_range(start, end, ways,
177 UNIPHIER_SSCOQM_TID_WAY | 177 UNIPHIER_SSCOQM_TID_WAY |
178 UNIPHIER_SSCOQM_CM_TOUCH); 178 UNIPHIER_SSCOQM_CM_TOUCH);
179 } 179 }
180 180
181 void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways) 181 void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways)
182 { 182 {
183 uniphier_cache_maint_range(start, end, ways, 183 uniphier_cache_maint_range(start, end, ways,
184 UNIPHIER_SSCOQM_TID_WAY | 184 UNIPHIER_SSCOQM_TID_WAY |
185 UNIPHIER_SSCOQM_CM_TOUCH_ZERO); 185 UNIPHIER_SSCOQM_CM_TOUCH_ZERO);
186 } 186 }
187 187
188 void uniphier_cache_inv_way(u32 ways) 188 void uniphier_cache_inv_way(u32 ways)
189 { 189 {
190 uniphier_cache_maint_common(0, 0, ways, 190 uniphier_cache_maint_common(0, 0, ways,
191 UNIPHIER_SSCOQM_S_WAY | 191 UNIPHIER_SSCOQM_S_WAY |
192 UNIPHIER_SSCOQM_CM_INV); 192 UNIPHIER_SSCOQM_CM_INV);
193 } 193 }
194 194
195 void uniphier_cache_set_active_ways(int cpu, u32 active_ways) 195 void uniphier_cache_set_active_ways(int cpu, u32 active_ways)
196 { 196 {
197 void __iomem *base = (void __iomem *)UNIPHIER_SSCC + 0xc00; 197 void __iomem *base = (void __iomem *)UNIPHIER_SSCC + 0xc00;
198 198
199 switch (readl(UNIPHIER_SSCID)) { /* revision */ 199 switch (readl(UNIPHIER_SSCID)) { /* revision */
200 case 0x11: /* sLD3 */
201 base = (void __iomem *)UNIPHIER_SSCC + 0x870;
202 break;
203 case 0x12: /* LD4 */ 200 case 0x12: /* LD4 */
204 case 0x16: /* sld8 */ 201 case 0x16: /* sld8 */
205 base = (void __iomem *)UNIPHIER_SSCC + 0x840; 202 base = (void __iomem *)UNIPHIER_SSCC + 0x840;
206 break; 203 break;
207 default: 204 default:
208 base = (void __iomem *)UNIPHIER_SSCC + 0xc00; 205 base = (void __iomem *)UNIPHIER_SSCC + 0xc00;
209 break; 206 break;
210 } 207 }
211 208
212 writel(active_ways, base + 4 * cpu); 209 writel(active_ways, base + 4 * cpu);
213 } 210 }
214 211
215 static void uniphier_cache_endisable(int enable) 212 static void uniphier_cache_endisable(int enable)
216 { 213 {
217 u32 tmp; 214 u32 tmp;
218 215
219 tmp = readl(UNIPHIER_SSCC); 216 tmp = readl(UNIPHIER_SSCC);
220 if (enable) 217 if (enable)
221 tmp |= UNIPHIER_SSCC_ON; 218 tmp |= UNIPHIER_SSCC_ON;
222 else 219 else
223 tmp &= ~UNIPHIER_SSCC_ON; 220 tmp &= ~UNIPHIER_SSCC_ON;
224 writel(tmp, UNIPHIER_SSCC); 221 writel(tmp, UNIPHIER_SSCC);
225 } 222 }
226 223
227 void uniphier_cache_enable(void) 224 void uniphier_cache_enable(void)
228 { 225 {
229 uniphier_cache_endisable(1); 226 uniphier_cache_endisable(1);
230 } 227 }
231 228
232 void uniphier_cache_disable(void) 229 void uniphier_cache_disable(void)
233 { 230 {
234 uniphier_cache_endisable(0); 231 uniphier_cache_endisable(0);
235 } 232 }
236 233
237 #ifdef CONFIG_CACHE_UNIPHIER 234 #ifdef CONFIG_CACHE_UNIPHIER
238 void v7_outer_cache_flush_all(void) 235 void v7_outer_cache_flush_all(void)
239 { 236 {
240 uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH); 237 uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH);
241 } 238 }
242 239
243 void v7_outer_cache_inval_all(void) 240 void v7_outer_cache_inval_all(void)
244 { 241 {
245 uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_INV); 242 uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_INV);
246 } 243 }
247 244
248 void v7_outer_cache_flush_range(u32 start, u32 end) 245 void v7_outer_cache_flush_range(u32 start, u32 end)
249 { 246 {
250 uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_FLUSH); 247 uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_FLUSH);
251 } 248 }
252 249
253 void v7_outer_cache_inval_range(u32 start, u32 end) 250 void v7_outer_cache_inval_range(u32 start, u32 end)
254 { 251 {
255 if (start & (UNIPHIER_SSC_LINE_SIZE - 1)) { 252 if (start & (UNIPHIER_SSC_LINE_SIZE - 1)) {
256 start &= ~(UNIPHIER_SSC_LINE_SIZE - 1); 253 start &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
257 uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE, 0, 254 uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE, 0,
258 UNIPHIER_SSCOQM_CM_FLUSH); 255 UNIPHIER_SSCOQM_CM_FLUSH);
259 start += UNIPHIER_SSC_LINE_SIZE; 256 start += UNIPHIER_SSC_LINE_SIZE;
260 } 257 }
261 258
262 if (start >= end) { 259 if (start >= end) {
263 uniphier_cache_sync(); 260 uniphier_cache_sync();
264 return; 261 return;
265 } 262 }
266 263
267 if (end & (UNIPHIER_SSC_LINE_SIZE - 1)) { 264 if (end & (UNIPHIER_SSC_LINE_SIZE - 1)) {
268 end &= ~(UNIPHIER_SSC_LINE_SIZE - 1); 265 end &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
269 uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE, 0, 266 uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE, 0,
270 UNIPHIER_SSCOQM_CM_FLUSH); 267 UNIPHIER_SSCOQM_CM_FLUSH);
271 } 268 }
272 269
273 if (start >= end) { 270 if (start >= end) {
274 uniphier_cache_sync(); 271 uniphier_cache_sync();
275 return; 272 return;
276 } 273 }
277 274
278 uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_INV); 275 uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_INV);
279 } 276 }
280 277
281 void v7_outer_cache_enable(void) 278 void v7_outer_cache_enable(void)
282 { 279 {
283 uniphier_cache_set_active_ways(0, U32_MAX); /* activate all ways */ 280 uniphier_cache_set_active_ways(0, U32_MAX); /* activate all ways */
284 uniphier_cache_enable(); 281 uniphier_cache_enable();
285 } 282 }
286 283
287 void v7_outer_cache_disable(void) 284 void v7_outer_cache_disable(void)
288 { 285 {
289 uniphier_cache_disable(); 286 uniphier_cache_disable();
290 } 287 }
291 #endif 288 #endif
292 289
293 void enable_caches(void) 290 void enable_caches(void)
294 { 291 {
295 dcache_enable(); 292 dcache_enable();
296 } 293 }
297 294
arch/arm/mach-uniphier/arm32/debug_ll.S
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * On-chip UART initializaion for low-level debugging 2 * On-chip UART initializaion for low-level debugging
3 * 3 *
4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> 4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <linux/serial_reg.h> 9 #include <linux/serial_reg.h>
10 #include <linux/linkage.h> 10 #include <linux/linkage.h>
11 11
12 #include "../bcu/bcu-regs.h" 12 #include "../bcu/bcu-regs.h"
13 #include "../sc-regs.h" 13 #include "../sc-regs.h"
14 #include "../sg-regs.h" 14 #include "../sg-regs.h"
15 15
16 #if !defined(CONFIG_DEBUG_SEMIHOSTING) 16 #if !defined(CONFIG_DEBUG_SEMIHOSTING)
17 #include CONFIG_DEBUG_LL_INCLUDE 17 #include CONFIG_DEBUG_LL_INCLUDE
18 #endif 18 #endif
19 19
20 #define BAUDRATE 115200 20 #define BAUDRATE 115200
21 #define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d)) 21 #define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
22 22
23 ENTRY(debug_ll_init) 23 ENTRY(debug_ll_init)
24 ldr r0, =SG_REVISION 24 ldr r0, =SG_REVISION
25 ldr r1, [r0] 25 ldr r1, [r0]
26 and r1, r1, #SG_REVISION_TYPE_MASK 26 and r1, r1, #SG_REVISION_TYPE_MASK
27 mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT 27 mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
28 28
29 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
30 #define UNIPHIER_SLD3_UART_CLK 36864000
31 cmp r1, #0x25
32 bne sld3_end
33
34 sg_set_pinsel 64, 1, 4, 4, r0, r1 @ TXD0 -> TXD0
35
36 ldr r0, =BCSCR5
37 ldr r1, =0x24440000
38 str r1, [r0]
39
40 ldr r0, =SC_CLKCTRL
41 ldr r1, [r0]
42 orr r1, r1, #SC_CLKCTRL_CEN_PERI
43 str r1, [r0]
44
45 ldr r3, =DIV_ROUND(UNIPHIER_SLD3_UART_CLK, 16 * BAUDRATE)
46
47 b init_uart
48 sld3_end:
49 #endif
50 #if defined(CONFIG_ARCH_UNIPHIER_LD4) 29 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
51 #define UNIPHIER_LD4_UART_CLK 36864000 30 #define UNIPHIER_LD4_UART_CLK 36864000
52 cmp r1, #0x26 31 cmp r1, #0x26
53 bne ld4_end 32 bne ld4_end
54 33
55 ldr r0, =SG_IECTRL 34 ldr r0, =SG_IECTRL
56 ldr r1, [r0] 35 ldr r1, [r0]
57 orr r1, r1, #1 36 orr r1, r1, #1
58 str r1, [r0] 37 str r1, [r0]
59 38
60 sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0 39 sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
61 40
62 ldr r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE) 41 ldr r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE)
63 42
64 b init_uart 43 b init_uart
65 ld4_end: 44 ld4_end:
66 #endif 45 #endif
67 #if defined(CONFIG_ARCH_UNIPHIER_PRO4) 46 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
68 #define UNIPHIER_PRO4_UART_CLK 73728000 47 #define UNIPHIER_PRO4_UART_CLK 73728000
69 cmp r1, #0x28 48 cmp r1, #0x28
70 bne pro4_end 49 bne pro4_end
71 50
72 sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0 51 sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
73 52
74 ldr r0, =SG_LOADPINCTRL 53 ldr r0, =SG_LOADPINCTRL
75 mov r1, #1 54 mov r1, #1
76 str r1, [r0] 55 str r1, [r0]
77 56
78 ldr r0, =SC_CLKCTRL 57 ldr r0, =SC_CLKCTRL
79 ldr r1, [r0] 58 ldr r1, [r0]
80 orr r1, r1, #SC_CLKCTRL_CEN_PERI 59 orr r1, r1, #SC_CLKCTRL_CEN_PERI
81 str r1, [r0] 60 str r1, [r0]
82 61
83 ldr r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE) 62 ldr r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE)
84 63
85 b init_uart 64 b init_uart
86 pro4_end: 65 pro4_end:
87 #endif 66 #endif
88 #if defined(CONFIG_ARCH_UNIPHIER_SLD8) 67 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
89 #define UNIPHIER_SLD8_UART_CLK 80000000 68 #define UNIPHIER_SLD8_UART_CLK 80000000
90 cmp r1, #0x29 69 cmp r1, #0x29
91 bne sld8_end 70 bne sld8_end
92 71
93 ldr r0, =SG_IECTRL 72 ldr r0, =SG_IECTRL
94 ldr r1, [r0] 73 ldr r1, [r0]
95 orr r1, r1, #1 74 orr r1, r1, #1
96 str r1, [r0] 75 str r1, [r0]
97 76
98 sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0 77 sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0
99 78
100 ldr r3, =DIV_ROUND(UNIPHIER_SLD8_UART_CLK, 16 * BAUDRATE) 79 ldr r3, =DIV_ROUND(UNIPHIER_SLD8_UART_CLK, 16 * BAUDRATE)
101 80
102 b init_uart 81 b init_uart
103 sld8_end: 82 sld8_end:
104 #endif 83 #endif
105 #if defined(CONFIG_ARCH_UNIPHIER_PRO5) 84 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
106 #define UNIPHIER_PRO5_UART_CLK 73728000 85 #define UNIPHIER_PRO5_UART_CLK 73728000
107 cmp r1, #0x2A 86 cmp r1, #0x2A
108 bne pro5_end 87 bne pro5_end
109 88
110 sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0 89 sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
111 sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1 90 sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1
112 sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2 91 sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
113 sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3 92 sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
114 93
115 ldr r0, =SG_LOADPINCTRL 94 ldr r0, =SG_LOADPINCTRL
116 mov r1, #1 95 mov r1, #1
117 str r1, [r0] 96 str r1, [r0]
118 97
119 ldr r0, =SC_CLKCTRL 98 ldr r0, =SC_CLKCTRL
120 ldr r1, [r0] 99 ldr r1, [r0]
121 orr r1, r1, #SC_CLKCTRL_CEN_PERI 100 orr r1, r1, #SC_CLKCTRL_CEN_PERI
122 str r1, [r0] 101 str r1, [r0]
123 102
124 ldr r3, =DIV_ROUND(UNIPHIER_PRO5_UART_CLK, 16 * BAUDRATE) 103 ldr r3, =DIV_ROUND(UNIPHIER_PRO5_UART_CLK, 16 * BAUDRATE)
125 104
126 b init_uart 105 b init_uart
127 pro5_end: 106 pro5_end:
128 #endif 107 #endif
129 #if defined(CONFIG_ARCH_UNIPHIER_PXS2) 108 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
130 #define UNIPHIER_PXS2_UART_CLK 88900000 109 #define UNIPHIER_PXS2_UART_CLK 88900000
131 cmp r1, #0x2E 110 cmp r1, #0x2E
132 bne pxs2_end 111 bne pxs2_end
133 112
134 ldr r0, =SG_IECTRL 113 ldr r0, =SG_IECTRL
135 ldr r1, [r0] 114 ldr r1, [r0]
136 orr r1, r1, #1 115 orr r1, r1, #1
137 str r1, [r0] 116 str r1, [r0]
138 117
139 sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0 118 sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0
140 sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1 119 sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1
141 sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2 120 sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2
142 sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3 121 sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3
143 122
144 ldr r0, =SC_CLKCTRL 123 ldr r0, =SC_CLKCTRL
145 ldr r1, [r0] 124 ldr r1, [r0]
146 orr r1, r1, #SC_CLKCTRL_CEN_PERI 125 orr r1, r1, #SC_CLKCTRL_CEN_PERI
147 str r1, [r0] 126 str r1, [r0]
148 127
149 ldr r3, =DIV_ROUND(UNIPHIER_PXS2_UART_CLK, 16 * BAUDRATE) 128 ldr r3, =DIV_ROUND(UNIPHIER_PXS2_UART_CLK, 16 * BAUDRATE)
150 129
151 b init_uart 130 b init_uart
152 pxs2_end: 131 pxs2_end:
153 #endif 132 #endif
154 #if defined(CONFIG_ARCH_UNIPHIER_LD6B) 133 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
155 #define UNIPHIER_LD6B_UART_CLK 88900000 134 #define UNIPHIER_LD6B_UART_CLK 88900000
156 cmp r1, #0x2F 135 cmp r1, #0x2F
157 bne ld6b_end 136 bne ld6b_end
158 137
159 ldr r0, =SG_IECTRL 138 ldr r0, =SG_IECTRL
160 ldr r1, [r0] 139 ldr r1, [r0]
161 orr r1, r1, #1 140 orr r1, r1, #1
162 str r1, [r0] 141 str r1, [r0]
163 142
164 sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0 143 sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0
165 sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1 144 sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1
166 sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2 145 sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2
167 146
168 ldr r0, =SC_CLKCTRL 147 ldr r0, =SC_CLKCTRL
169 ldr r1, [r0] 148 ldr r1, [r0]
170 orr r1, r1, #SC_CLKCTRL_CEN_PERI 149 orr r1, r1, #SC_CLKCTRL_CEN_PERI
171 str r1, [r0] 150 str r1, [r0]
172 151
173 ldr r3, =DIV_ROUND(UNIPHIER_LD6B_UART_CLK, 16 * BAUDRATE) 152 ldr r3, =DIV_ROUND(UNIPHIER_LD6B_UART_CLK, 16 * BAUDRATE)
174 153
175 b init_uart 154 b init_uart
176 ld6b_end: 155 ld6b_end:
177 #endif 156 #endif
178 mov pc, lr 157 mov pc, lr
179 158
180 init_uart: 159 init_uart:
181 addruart r0, r1, r2 160 addruart r0, r1, r2
182 mov r1, #UART_LCR_WLEN8 << 8 161 mov r1, #UART_LCR_WLEN8 << 8
183 str r1, [r0, #0x10] 162 str r1, [r0, #0x10]
184 str r3, [r0, #0x24] 163 str r3, [r0, #0x24]
185 164
186 mov pc, lr 165 mov pc, lr
187 ENDPROC(debug_ll_init) 166 ENDPROC(debug_ll_init)
188 167
arch/arm/mach-uniphier/arm32/lowlevel_init.S
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2012-2015 Panasonic Corporation 2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc. 3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <config.h> 9 #include <config.h>
10 #include <linux/linkage.h> 10 #include <linux/linkage.h>
11 #include <linux/sizes.h> 11 #include <linux/sizes.h>
12 #include <asm/system.h> 12 #include <asm/system.h>
13 13
14 ENTRY(lowlevel_init) 14 ENTRY(lowlevel_init)
15 mov r8, lr @ persevere link reg across call 15 mov r8, lr @ persevere link reg across call
16 16
17 /* 17 /*
18 * The UniPhier Boot ROM loads SPL code to the L2 cache. 18 * The UniPhier Boot ROM loads SPL code to the L2 cache.
19 * But CPUs can only do instruction fetch now because start.S has 19 * But CPUs can only do instruction fetch now because start.S has
20 * cleared C and M bits. 20 * cleared C and M bits.
21 * First we need to turn on MMU and Dcache again to get back 21 * First we need to turn on MMU and Dcache again to get back
22 * data access to L2. 22 * data access to L2.
23 */ 23 */
24 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) 24 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
25 orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache 25 orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
26 mcr p15, 0, r0, c1, c0, 0 26 mcr p15, 0, r0, c1, c0, 0
27 27
28 bl setup_init_ram @ RAM area for stack and page table 28 bl setup_init_ram @ RAM area for stack and page table
29 29
30 /* 30 /*
31 * Now we are using the page table embedded in the Boot ROM. 31 * Now we are using the page table embedded in the Boot ROM.
32 * It is not handy since it is not a straight mapped table for sLD3. 32 * What we need to do next is to create a page table and switch
33 * Also, the access to the external bus is prohibited. What we need 33 * over to it.
34 * to do next is to create a page table and switch over to it.
35 */ 34 */
36 bl create_page_table 35 bl create_page_table
37 bl __v7_flush_dcache_all 36 bl __v7_flush_dcache_all
38 37
39 /* Disable MMU and Dcache before switching Page Table */ 38 /* Disable MMU and Dcache before switching Page Table */
40 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) 39 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
41 bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache 40 bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
42 mcr p15, 0, r0, c1, c0, 0 41 mcr p15, 0, r0, c1, c0, 0
43 42
44 bl enable_mmu 43 bl enable_mmu
45 44
46 #ifdef CONFIG_DEBUG_LL 45 #ifdef CONFIG_DEBUG_LL
47 bl debug_ll_init 46 bl debug_ll_init
48 #endif 47 #endif
49 48
50 mov lr, r8 @ restore link 49 mov lr, r8 @ restore link
51 mov pc, lr @ back to my caller 50 mov pc, lr @ back to my caller
52 ENDPROC(lowlevel_init) 51 ENDPROC(lowlevel_init)
53 52
54 ENTRY(enable_mmu) 53 ENTRY(enable_mmu)
55 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register) 54 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
56 bic r0, r0, #0x37 55 bic r0, r0, #0x37
57 orr r0, r0, #0x20 @ disable TTBR1 56 orr r0, r0, #0x20 @ disable TTBR1
58 mcr p15, 0, r0, c2, c0, 2 57 mcr p15, 0, r0, c2, c0, 2
59 58
60 orr r0, r12, #0x8 @ Outer Cacheability for table walks: WBWA 59 orr r0, r12, #0x8 @ Outer Cacheability for table walks: WBWA
61 mcr p15, 0, r0, c2, c0, 0 @ TTBR0 60 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
62 61
63 mov r0, #0 62 mov r0, #0
64 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 63 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
65 64
66 mov r0, #-1 @ manager for all domains (No permission check) 65 mov r0, #-1 @ manager for all domains (No permission check)
67 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register) 66 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
68 67
69 dsb 68 dsb
70 isb 69 isb
71 /* 70 /*
72 * MMU on: 71 * MMU on:
73 * TLBs was already invalidated in "../start.S" 72 * TLBs was already invalidated in "../start.S"
74 * So, we don't need to invalidate it here. 73 * So, we don't need to invalidate it here.
75 */ 74 */
76 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) 75 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
77 orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable 76 orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
78 mcr p15, 0, r0, c1, c0, 0 77 mcr p15, 0, r0, c1, c0, 0
79 78
80 mov pc, lr 79 mov pc, lr
81 ENDPROC(enable_mmu) 80 ENDPROC(enable_mmu)
82 81
83 /* 82 /*
84 * For PH1-Pro4 or older SoCs, the size of WAY is 32KB. 83 * For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
85 * It is large enough for tmp RAM. 84 * It is large enough for tmp RAM.
86 */ 85 */
87 #define BOOT_RAM_SIZE (SZ_32K) 86 #define BOOT_RAM_SIZE (SZ_32K)
88 #define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE)) 87 #define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
89 #define BOOT_RAM_WAYS (0x00000100) @ way 8 88 #define BOOT_RAM_WAYS (0x00000100) @ way 8
90 89
91 #define SSCO_BASE 0x506c0000 90 #define SSCO_BASE 0x506c0000
92 #define SSCOPE 0x244 91 #define SSCOPE 0x244
93 #define SSCOQM 0x248 92 #define SSCOQM 0x248
94 #define SSCOQAD 0x24c 93 #define SSCOQAD 0x24c
95 #define SSCOQSZ 0x250 94 #define SSCOQSZ 0x250
96 #define SSCOQWN 0x258 95 #define SSCOQWN 0x258
97 #define SSCOPPQSEF 0x25c 96 #define SSCOPPQSEF 0x25c
98 #define SSCOLPQS 0x260 97 #define SSCOLPQS 0x260
99 98
100 ENTRY(setup_init_ram) 99 ENTRY(setup_init_ram)
101 ldr r1, = SSCO_BASE 100 ldr r1, = SSCO_BASE
102 mrc p15, 0, r0, c2, c0, 0 @ TTBR0 101 mrc p15, 0, r0, c2, c0, 0 @ TTBR0
103 ldr r0, [r0, #0x400] @ entry for virtual address 0x100***** 102 ldr r0, [r0, #0x400] @ entry for virtual address 0x100*****
104 bfc r0, #0, #20 103 bfc r0, #0, #20
105 cmp r0, #0x50000000 @ is sLD3 page table? 104 cmp r0, #0x50000000 @ is sLD3 page table?
106 biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5******* to 0x1******* 105 biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5******* to 0x1*******
107 106
108 /* Touch to zero for the boot way */ 107 /* Touch to zero for the boot way */
109 0: ldr r0, = 0x00408006 @ touch to zero with address range 108 0: ldr r0, = 0x00408006 @ touch to zero with address range
110 str r0, [r1, #SSCOQM] 109 str r0, [r1, #SSCOQM]
111 ldr r0, = BOOT_RAM_BASE 110 ldr r0, = BOOT_RAM_BASE
112 str r0, [r1, #SSCOQAD] 111 str r0, [r1, #SSCOQAD]
113 ldr r0, = BOOT_RAM_SIZE 112 ldr r0, = BOOT_RAM_SIZE
114 str r0, [r1, #SSCOQSZ] 113 str r0, [r1, #SSCOQSZ]
115 ldr r0, = BOOT_RAM_WAYS 114 ldr r0, = BOOT_RAM_WAYS
116 str r0, [r1, #SSCOQWN] 115 str r0, [r1, #SSCOQWN]
117 ldr r0, [r1, #SSCOPPQSEF] 116 ldr r0, [r1, #SSCOPPQSEF]
118 cmp r0, #0 @ check if the command is successfully set 117 cmp r0, #0 @ check if the command is successfully set
119 bne 0b @ try again if an error occurs 118 bne 0b @ try again if an error occurs
120 119
121 1: ldr r0, [r1, #SSCOLPQS] 120 1: ldr r0, [r1, #SSCOLPQS]
122 cmp r0, #0x4 121 cmp r0, #0x4
123 bne 1b @ wait until the operation is completed 122 bne 1b @ wait until the operation is completed
124 str r0, [r1, #SSCOLPQS] @ clear the complete notification flag 123 str r0, [r1, #SSCOLPQS] @ clear the complete notification flag
125 124
126 mov pc, lr 125 mov pc, lr
127 ENDPROC(setup_init_ram) 126 ENDPROC(setup_init_ram)
128 127
129 #define DEVICE 0x00002002 /* Non-shareable Device */ 128 #define DEVICE 0x00002002 /* Non-shareable Device */
130 #define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */ 129 #define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
131 130
132 ENTRY(create_page_table) 131 ENTRY(create_page_table)
133 ldr r0, = DEVICE 132 ldr r0, = DEVICE
134 ldr r1, = BOOT_RAM_BASE 133 ldr r1, = BOOT_RAM_BASE
135 mov r12, r1 @ r12 is preserved during D-cache flush 134 mov r12, r1 @ r12 is preserved during D-cache flush
136 0: str r0, [r1], #4 @ specify all the sections as Device 135 0: str r0, [r1], #4 @ specify all the sections as Device
137 adds r0, r0, #0x00100000 136 adds r0, r0, #0x00100000
138 bcc 0b 137 bcc 0b
139 138
140 ldr r0, = NORMAL 139 ldr r0, = NORMAL
141 str r0, [r12] @ mark the first section as Normal 140 str r0, [r12] @ mark the first section as Normal
142 add r0, r0, #0x00100000 141 add r0, r0, #0x00100000
143 str r0, [r12, #4] @ mark the second section as Normal 142 str r0, [r12, #4] @ mark the second section as Normal
144 mov pc, lr 143 mov pc, lr
145 ENDPROC(create_page_table) 144 ENDPROC(create_page_table)
146 145
arch/arm/mach-uniphier/arm32/psci.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2016 Socionext Inc. 2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <linux/bitops.h> 9 #include <linux/bitops.h>
10 #include <linux/io.h> 10 #include <linux/io.h>
11 #include <linux/kernel.h> 11 #include <linux/kernel.h>
12 #include <linux/psci.h> 12 #include <linux/psci.h>
13 #include <linux/sizes.h> 13 #include <linux/sizes.h>
14 #include <asm/processor.h> 14 #include <asm/processor.h>
15 #include <asm/psci.h> 15 #include <asm/psci.h>
16 #include <asm/secure.h> 16 #include <asm/secure.h>
17 17
18 #include "../debug.h" 18 #include "../debug.h"
19 #include "../soc-info.h" 19 #include "../soc-info.h"
20 #include "arm-mpcore.h" 20 #include "arm-mpcore.h"
21 #include "cache-uniphier.h" 21 #include "cache-uniphier.h"
22 22
23 #define UNIPHIER_SMPCTRL_ROM_RSV2 0x59801208 23 #define UNIPHIER_SMPCTRL_ROM_RSV2 0x59801208
24 24
25 void uniphier_smp_trampoline(void); 25 void uniphier_smp_trampoline(void);
26 void uniphier_smp_trampoline_end(void); 26 void uniphier_smp_trampoline_end(void);
27 u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS]; 27 u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS];
28 28
29 static int uniphier_get_nr_cpus(void) 29 static int uniphier_get_nr_cpus(void)
30 { 30 {
31 switch (uniphier_get_soc_id()) { 31 switch (uniphier_get_soc_id()) {
32 case UNIPHIER_SLD3_ID:
33 case UNIPHIER_PRO4_ID: 32 case UNIPHIER_PRO4_ID:
34 case UNIPHIER_PRO5_ID: 33 case UNIPHIER_PRO5_ID:
35 return 2; 34 return 2;
36 case UNIPHIER_PXS2_ID: 35 case UNIPHIER_PXS2_ID:
37 case UNIPHIER_LD6B_ID: 36 case UNIPHIER_LD6B_ID:
38 return 4; 37 return 4;
39 default: 38 default:
40 return 1; 39 return 1;
41 } 40 }
42 } 41 }
43 42
44 static void uniphier_smp_kick_all_cpus(void) 43 static void uniphier_smp_kick_all_cpus(void)
45 { 44 {
46 const u32 target_ways = BIT(0); 45 const u32 target_ways = BIT(0);
47 size_t trmp_size; 46 size_t trmp_size;
48 u32 trmp_src = (unsigned long)uniphier_smp_trampoline; 47 u32 trmp_src = (unsigned long)uniphier_smp_trampoline;
49 u32 trmp_src_end = (unsigned long)uniphier_smp_trampoline_end; 48 u32 trmp_src_end = (unsigned long)uniphier_smp_trampoline_end;
50 u32 trmp_dest, trmp_dest_end; 49 u32 trmp_dest, trmp_dest_end;
51 int nr_cpus, i; 50 int nr_cpus, i;
52 int timeout = 1000; 51 int timeout = 1000;
53 52
54 nr_cpus = uniphier_get_nr_cpus(); 53 nr_cpus = uniphier_get_nr_cpus();
55 if (nr_cpus == 1) 54 if (nr_cpus == 1)
56 return; 55 return;
57 56
58 for (i = 0; i < nr_cpus; i++) /* lock ways for all CPUs */ 57 for (i = 0; i < nr_cpus; i++) /* lock ways for all CPUs */
59 uniphier_cache_set_active_ways(i, 0); 58 uniphier_cache_set_active_ways(i, 0);
60 uniphier_cache_inv_way(target_ways); 59 uniphier_cache_inv_way(target_ways);
61 uniphier_cache_enable(); 60 uniphier_cache_enable();
62 61
63 /* copy trampoline code */ 62 /* copy trampoline code */
64 uniphier_cache_prefetch_range(trmp_src, trmp_src_end, target_ways); 63 uniphier_cache_prefetch_range(trmp_src, trmp_src_end, target_ways);
65 64
66 trmp_size = trmp_src_end - trmp_src; 65 trmp_size = trmp_src_end - trmp_src;
67 66
68 trmp_dest = trmp_src & (SZ_64K - 1); 67 trmp_dest = trmp_src & (SZ_64K - 1);
69 trmp_dest += SZ_1M - SZ_64K * 2; 68 trmp_dest += SZ_1M - SZ_64K * 2;
70 69
71 trmp_dest_end = trmp_dest + trmp_size; 70 trmp_dest_end = trmp_dest + trmp_size;
72 71
73 uniphier_cache_touch_range(trmp_dest, trmp_dest_end, target_ways); 72 uniphier_cache_touch_range(trmp_dest, trmp_dest_end, target_ways);
74 73
75 writel(trmp_dest, UNIPHIER_SMPCTRL_ROM_RSV2); 74 writel(trmp_dest, UNIPHIER_SMPCTRL_ROM_RSV2);
76 75
77 asm("dsb ishst\n" /* Ensure the write to ROM_RSV2 is visible */ 76 asm("dsb ishst\n" /* Ensure the write to ROM_RSV2 is visible */
78 "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ 77 "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
79 78
80 while (--timeout) { 79 while (--timeout) {
81 int all_booted = 1; 80 int all_booted = 1;
82 81
83 for (i = 1; i < nr_cpus; i++) 82 for (i = 1; i < nr_cpus; i++)
84 if (!uniphier_smp_booted[i]) 83 if (!uniphier_smp_booted[i])
85 all_booted = 0; 84 all_booted = 0;
86 if (all_booted) 85 if (all_booted)
87 break; 86 break;
88 udelay(1); 87 udelay(1);
89 88
90 /* barrier here because uniphier_smp_booted[] may be updated */ 89 /* barrier here because uniphier_smp_booted[] may be updated */
91 cpu_relax(); 90 cpu_relax();
92 } 91 }
93 92
94 if (!timeout) 93 if (!timeout)
95 printf("warning: some of secondary CPUs may not boot\n"); 94 printf("warning: some of secondary CPUs may not boot\n");
96 95
97 uniphier_cache_disable(); 96 uniphier_cache_disable();
98 } 97 }
99 98
100 void psci_board_init(void) 99 void psci_board_init(void)
101 { 100 {
102 unsigned long scu_base; 101 unsigned long scu_base;
103 u32 scu_ctrl, tmp; 102 u32 scu_ctrl, tmp;
104 103
105 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (scu_base)); 104 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (scu_base));
106 105
107 scu_ctrl = readl(scu_base + 0x30); 106 scu_ctrl = readl(scu_base + 0x30);
108 if (!(scu_ctrl & 1)) 107 if (!(scu_ctrl & 1))
109 writel(scu_ctrl | 0x1, scu_base + 0x30); 108 writel(scu_ctrl | 0x1, scu_base + 0x30);
110 109
111 scu_ctrl = readl(scu_base + SCU_CTRL); 110 scu_ctrl = readl(scu_base + SCU_CTRL);
112 scu_ctrl |= SCU_ENABLE | SCU_STANDBY_ENABLE; 111 scu_ctrl |= SCU_ENABLE | SCU_STANDBY_ENABLE;
113 writel(scu_ctrl, scu_base + SCU_CTRL); 112 writel(scu_ctrl, scu_base + SCU_CTRL);
114 113
115 tmp = readl(scu_base + SCU_SNSAC); 114 tmp = readl(scu_base + SCU_SNSAC);
116 tmp |= 0xfff; 115 tmp |= 0xfff;
117 writel(tmp, scu_base + SCU_SNSAC); 116 writel(tmp, scu_base + SCU_SNSAC);
118 117
119 uniphier_smp_kick_all_cpus(); 118 uniphier_smp_kick_all_cpus();
120 } 119 }
121 120
122 void psci_arch_init(void) 121 void psci_arch_init(void)
123 { 122 {
124 u32 actlr; 123 u32 actlr;
125 124
126 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr)); 125 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
127 actlr |= 0x41; /* set SMP and FW bits */ 126 actlr |= 0x41; /* set SMP and FW bits */
128 asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr)); 127 asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
129 } 128 }
130 129
131 u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff; 130 u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff;
132 131
133 int __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point) 132 int __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point)
134 { 133 {
135 u32 cpu = cpuid & 0xff; 134 u32 cpu = cpuid & 0xff;
136 135
137 debug_puts("[U-Boot PSCI] psci_cpu_on: cpuid="); 136 debug_puts("[U-Boot PSCI] psci_cpu_on: cpuid=");
138 debug_puth(cpuid); 137 debug_puth(cpuid);
139 debug_puts(", entry_point="); 138 debug_puts(", entry_point=");
140 debug_puth(entry_point); 139 debug_puth(entry_point);
141 debug_puts("\n"); 140 debug_puts("\n");
142 141
143 psci_save_target_pc(cpu, entry_point); 142 psci_save_target_pc(cpu, entry_point);
144 143
145 /* We assume D-cache is off, so do not call flush_dcache() here */ 144 /* We assume D-cache is off, so do not call flush_dcache() here */
146 uniphier_psci_holding_pen_release = cpu; 145 uniphier_psci_holding_pen_release = cpu;
147 146
148 /* Send an event to wake up the secondary CPU. */ 147 /* Send an event to wake up the secondary CPU. */
149 asm("dsb ishst\n" 148 asm("dsb ishst\n"
150 "sev"); 149 "sev");
151 150
152 return PSCI_RET_SUCCESS; 151 return PSCI_RET_SUCCESS;
153 } 152 }
154 153
155 void __secure psci_system_reset(u32 function_id) 154 void __secure psci_system_reset(u32 function_id)
156 { 155 {
157 reset_cpu(0); 156 reset_cpu(0);
158 } 157 }
159 158
arch/arm/mach-uniphier/bcu/Makefile
Diff comments   View file @ 00aa453
1 # 1 #
2 # SPDX-License-Identifier: GPL-2.0+ 2 # SPDX-License-Identifier: GPL-2.0+
3 # 3 #
4 4
5 obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += bcu-sld3.o
6 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += bcu-ld4.o 5 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += bcu-ld4.o
7 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += bcu-ld4.o 6 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += bcu-ld4.o
8 7
arch/arm/mach-uniphier/bcu/bcu-sld3.c
View file @ 00aa453
1 /* File was deleted
2 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <linux/io.h>
10
11 #include "../init.h"
12 #include "bcu-regs.h"
13
14 #define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
15
16 void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd)
17 {
18 int shift;
19
20 writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
21 writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
22 writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
23 /*
24 * 0xe0000000-0xefffffff: Ex-bus
25 * 0xf0000000-0xfbffffff: ASM bus
26 * 0xfc000000-0xffffffff: OCM bus
27 */
28 writel(0x24440000, BCSCR5);
29
30 /* Specify DDR channel */
31 shift = bd->dram_ch[0].size / 0x04000000 * 4;
32 writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
33
34 shift -= 32;
35 writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
36
37 shift -= 32;
38 writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
39 }
40 1 /*
arch/arm/mach-uniphier/board_init.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2012-2015 Panasonic Corporation 2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc. 3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <common.h> 9 #include <common.h>
10 #include <libfdt.h> 10 #include <libfdt.h>
11 #include <linux/io.h> 11 #include <linux/io.h>
12 12
13 #include "init.h" 13 #include "init.h"
14 #include "micro-support-card.h" 14 #include "micro-support-card.h"
15 #include "sg-regs.h" 15 #include "sg-regs.h"
16 #include "soc-info.h" 16 #include "soc-info.h"
17 17
18 DECLARE_GLOBAL_DATA_PTR; 18 DECLARE_GLOBAL_DATA_PTR;
19 19
20 static void uniphier_setup_xirq(void) 20 static void uniphier_setup_xirq(void)
21 { 21 {
22 const void *fdt = gd->fdt_blob; 22 const void *fdt = gd->fdt_blob;
23 int soc_node, aidet_node; 23 int soc_node, aidet_node;
24 const fdt32_t *val; 24 const fdt32_t *val;
25 unsigned long aidet_base; 25 unsigned long aidet_base;
26 u32 tmp; 26 u32 tmp;
27 27
28 soc_node = fdt_path_offset(fdt, "/soc"); 28 soc_node = fdt_path_offset(fdt, "/soc");
29 if (soc_node < 0) 29 if (soc_node < 0)
30 return; 30 return;
31 31
32 aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5); 32 aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5);
33 if (aidet_node < 0) 33 if (aidet_node < 0)
34 return; 34 return;
35 35
36 val = fdt_getprop(fdt, aidet_node, "reg", NULL); 36 val = fdt_getprop(fdt, aidet_node, "reg", NULL);
37 if (!val) 37 if (!val)
38 return; 38 return;
39 39
40 aidet_base = fdt32_to_cpu(*val); 40 aidet_base = fdt32_to_cpu(*val);
41 41
42 tmp = readl(aidet_base + 8); /* AIDET DETCONFR2 */ 42 tmp = readl(aidet_base + 8); /* AIDET DETCONFR2 */
43 tmp |= 0x00ff0000; /* Set XIRQ0-7 low active */ 43 tmp |= 0x00ff0000; /* Set XIRQ0-7 low active */
44 writel(tmp, aidet_base + 8); 44 writel(tmp, aidet_base + 8);
45 45
46 tmp = readl(0x55000090); /* IRQCTL */ 46 tmp = readl(0x55000090); /* IRQCTL */
47 tmp |= 0x000000ff; 47 tmp |= 0x000000ff;
48 writel(tmp, 0x55000090); 48 writel(tmp, 0x55000090);
49 } 49 }
50 50
51 #ifdef CONFIG_ARCH_UNIPHIER_LD11 51 #ifdef CONFIG_ARCH_UNIPHIER_LD11
52 static void uniphier_ld11_misc_init(void) 52 static void uniphier_ld11_misc_init(void)
53 { 53 {
54 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ 54 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
55 sg_set_iectrl(149); 55 sg_set_iectrl(149);
56 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ 56 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
57 sg_set_iectrl(153); 57 sg_set_iectrl(153);
58 } 58 }
59 #endif 59 #endif
60 60
61 #ifdef CONFIG_ARCH_UNIPHIER_LD20 61 #ifdef CONFIG_ARCH_UNIPHIER_LD20
62 static void uniphier_ld20_misc_init(void) 62 static void uniphier_ld20_misc_init(void)
63 { 63 {
64 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ 64 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
65 sg_set_iectrl(149); 65 sg_set_iectrl(149);
66 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ 66 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
67 sg_set_iectrl(153); 67 sg_set_iectrl(153);
68 68
69 /* ES1 errata: increase VDD09 supply to suppress VBO noise */ 69 /* ES1 errata: increase VDD09 supply to suppress VBO noise */
70 if (uniphier_get_soc_revision() == 1) { 70 if (uniphier_get_soc_revision() == 1) {
71 writel(0x00000003, 0x6184e004); 71 writel(0x00000003, 0x6184e004);
72 writel(0x00000100, 0x6184e040); 72 writel(0x00000100, 0x6184e040);
73 writel(0x0000b500, 0x6184e024); 73 writel(0x0000b500, 0x6184e024);
74 writel(0x00000001, 0x6184e000); 74 writel(0x00000001, 0x6184e000);
75 } 75 }
76 } 76 }
77 #endif 77 #endif
78 78
79 struct uniphier_initdata { 79 struct uniphier_initdata {
80 unsigned int soc_id; 80 unsigned int soc_id;
81 bool nand_2cs; 81 bool nand_2cs;
82 void (*sbc_init)(void); 82 void (*sbc_init)(void);
83 void (*pll_init)(void); 83 void (*pll_init)(void);
84 void (*clk_init)(void); 84 void (*clk_init)(void);
85 void (*misc_init)(void); 85 void (*misc_init)(void);
86 }; 86 };
87 87
88 static const struct uniphier_initdata uniphier_initdata[] = { 88 static const struct uniphier_initdata uniphier_initdata[] = {
89 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
90 {
91 .soc_id = UNIPHIER_SLD3_ID,
92 .nand_2cs = true,
93 .sbc_init = uniphier_sbc_init_admulti,
94 .pll_init = uniphier_sld3_pll_init,
95 .clk_init = uniphier_ld4_clk_init,
96 },
97 #endif
98 #if defined(CONFIG_ARCH_UNIPHIER_LD4) 89 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
99 { 90 {
100 .soc_id = UNIPHIER_LD4_ID, 91 .soc_id = UNIPHIER_LD4_ID,
101 .nand_2cs = true, 92 .nand_2cs = true,
102 .sbc_init = uniphier_ld4_sbc_init, 93 .sbc_init = uniphier_ld4_sbc_init,
103 .pll_init = uniphier_ld4_pll_init, 94 .pll_init = uniphier_ld4_pll_init,
104 .clk_init = uniphier_ld4_clk_init, 95 .clk_init = uniphier_ld4_clk_init,
105 }, 96 },
106 #endif 97 #endif
107 #if defined(CONFIG_ARCH_UNIPHIER_PRO4) 98 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
108 { 99 {
109 .soc_id = UNIPHIER_PRO4_ID, 100 .soc_id = UNIPHIER_PRO4_ID,
110 .nand_2cs = false, 101 .nand_2cs = false,
111 .sbc_init = uniphier_sbc_init_savepin, 102 .sbc_init = uniphier_sbc_init_savepin,
112 .pll_init = uniphier_pro4_pll_init, 103 .pll_init = uniphier_pro4_pll_init,
113 .clk_init = uniphier_pro4_clk_init, 104 .clk_init = uniphier_pro4_clk_init,
114 }, 105 },
115 #endif 106 #endif
116 #if defined(CONFIG_ARCH_UNIPHIER_SLD8) 107 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
117 { 108 {
118 .soc_id = UNIPHIER_SLD8_ID, 109 .soc_id = UNIPHIER_SLD8_ID,
119 .nand_2cs = true, 110 .nand_2cs = true,
120 .sbc_init = uniphier_ld4_sbc_init, 111 .sbc_init = uniphier_ld4_sbc_init,
121 .pll_init = uniphier_ld4_pll_init, 112 .pll_init = uniphier_ld4_pll_init,
122 .clk_init = uniphier_ld4_clk_init, 113 .clk_init = uniphier_ld4_clk_init,
123 }, 114 },
124 #endif 115 #endif
125 #if defined(CONFIG_ARCH_UNIPHIER_PRO5) 116 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
126 { 117 {
127 .soc_id = UNIPHIER_PRO5_ID, 118 .soc_id = UNIPHIER_PRO5_ID,
128 .nand_2cs = true, 119 .nand_2cs = true,
129 .sbc_init = uniphier_sbc_init_savepin, 120 .sbc_init = uniphier_sbc_init_savepin,
130 .clk_init = uniphier_pro5_clk_init, 121 .clk_init = uniphier_pro5_clk_init,
131 }, 122 },
132 #endif 123 #endif
133 #if defined(CONFIG_ARCH_UNIPHIER_PXS2) 124 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
134 { 125 {
135 .soc_id = UNIPHIER_PXS2_ID, 126 .soc_id = UNIPHIER_PXS2_ID,
136 .nand_2cs = true, 127 .nand_2cs = true,
137 .sbc_init = uniphier_pxs2_sbc_init, 128 .sbc_init = uniphier_pxs2_sbc_init,
138 .clk_init = uniphier_pxs2_clk_init, 129 .clk_init = uniphier_pxs2_clk_init,
139 }, 130 },
140 #endif 131 #endif
141 #if defined(CONFIG_ARCH_UNIPHIER_LD6B) 132 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
142 { 133 {
143 .soc_id = UNIPHIER_LD6B_ID, 134 .soc_id = UNIPHIER_LD6B_ID,
144 .nand_2cs = true, 135 .nand_2cs = true,
145 .sbc_init = uniphier_pxs2_sbc_init, 136 .sbc_init = uniphier_pxs2_sbc_init,
146 .clk_init = uniphier_pxs2_clk_init, 137 .clk_init = uniphier_pxs2_clk_init,
147 }, 138 },
148 #endif 139 #endif
149 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 140 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
150 { 141 {
151 .soc_id = UNIPHIER_LD11_ID, 142 .soc_id = UNIPHIER_LD11_ID,
152 .nand_2cs = false, 143 .nand_2cs = false,
153 .sbc_init = uniphier_ld11_sbc_init, 144 .sbc_init = uniphier_ld11_sbc_init,
154 .pll_init = uniphier_ld11_pll_init, 145 .pll_init = uniphier_ld11_pll_init,
155 .clk_init = uniphier_ld11_clk_init, 146 .clk_init = uniphier_ld11_clk_init,
156 .misc_init = uniphier_ld11_misc_init, 147 .misc_init = uniphier_ld11_misc_init,
157 }, 148 },
158 #endif 149 #endif
159 #if defined(CONFIG_ARCH_UNIPHIER_LD20) 150 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
160 { 151 {
161 .soc_id = UNIPHIER_LD20_ID, 152 .soc_id = UNIPHIER_LD20_ID,
162 .nand_2cs = false, 153 .nand_2cs = false,
163 .sbc_init = uniphier_ld11_sbc_init, 154 .sbc_init = uniphier_ld11_sbc_init,
164 .pll_init = uniphier_ld20_pll_init, 155 .pll_init = uniphier_ld20_pll_init,
165 .clk_init = uniphier_ld20_clk_init, 156 .clk_init = uniphier_ld20_clk_init,
166 .misc_init = uniphier_ld20_misc_init, 157 .misc_init = uniphier_ld20_misc_init,
167 }, 158 },
168 #endif 159 #endif
169 #if defined(CONFIG_ARCH_UNIPHIER_PXS3) 160 #if defined(CONFIG_ARCH_UNIPHIER_PXS3)
170 { 161 {
171 .soc_id = UNIPHIER_PXS3_ID, 162 .soc_id = UNIPHIER_PXS3_ID,
172 .nand_2cs = false, 163 .nand_2cs = false,
173 .sbc_init = uniphier_pxs2_sbc_init, 164 .sbc_init = uniphier_pxs2_sbc_init,
174 .pll_init = uniphier_pxs3_pll_init, 165 .pll_init = uniphier_pxs3_pll_init,
175 .clk_init = uniphier_pxs3_clk_init, 166 .clk_init = uniphier_pxs3_clk_init,
176 }, 167 },
177 #endif 168 #endif
178 }; 169 };
179 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_initdata, uniphier_initdata) 170 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_initdata, uniphier_initdata)
180 171
181 int board_init(void) 172 int board_init(void)
182 { 173 {
183 const struct uniphier_initdata *initdata; 174 const struct uniphier_initdata *initdata;
184 int ret; 175 int ret;
185 176
186 led_puts("U0"); 177 led_puts("U0");
187 178
188 initdata = uniphier_get_initdata(); 179 initdata = uniphier_get_initdata();
189 if (!initdata) { 180 if (!initdata) {
190 pr_err("unsupported SoC\n"); 181 pr_err("unsupported SoC\n");
191 return -EINVAL; 182 return -EINVAL;
192 } 183 }
193 184
194 initdata->sbc_init(); 185 initdata->sbc_init();
195 186
196 support_card_init(); 187 support_card_init();
197 188
198 led_puts("U0"); 189 led_puts("U0");
199 190
200 if (IS_ENABLED(CONFIG_NAND_DENALI)) { 191 if (IS_ENABLED(CONFIG_NAND_DENALI)) {
201 ret = uniphier_pin_init(initdata->nand_2cs ? 192 ret = uniphier_pin_init(initdata->nand_2cs ?
202 "nand2cs_grp" : "nand_grp"); 193 "nand2cs_grp" : "nand_grp");
203 if (ret) 194 if (ret)
204 pr_err("failed to init NAND pins\n"); 195 pr_err("failed to init NAND pins\n");
205 } 196 }
206 197
207 led_puts("U1"); 198 led_puts("U1");
208 199
209 if (initdata->pll_init) 200 if (initdata->pll_init)
210 initdata->pll_init(); 201 initdata->pll_init();
211 202
212 led_puts("U2"); 203 led_puts("U2");
213 204
214 if (initdata->clk_init) 205 if (initdata->clk_init)
215 initdata->clk_init(); 206 initdata->clk_init();
216 207
217 led_puts("U3"); 208 led_puts("U3");
218 209
219 if (initdata->misc_init) 210 if (initdata->misc_init)
220 initdata->misc_init(); 211 initdata->misc_init();
221 212
222 led_puts("U4"); 213 led_puts("U4");
223 214
224 uniphier_setup_xirq(); 215 uniphier_setup_xirq();
225 216
226 led_puts("U5"); 217 led_puts("U5");
227 218
228 support_card_late_init(); 219 support_card_late_init();
229 220
230 led_puts("Uboo"); 221 led_puts("Uboo");
231 222
232 return 0; 223 return 0;
233 } 224 }
234 225
arch/arm/mach-uniphier/boards.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2015-2016 Socionext Inc. 2 * Copyright (C) 2015-2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <libfdt.h> 9 #include <libfdt.h>
10 #include <linux/kernel.h> 10 #include <linux/kernel.h>
11 11
12 #include "init.h" 12 #include "init.h"
13 13
14 DECLARE_GLOBAL_DATA_PTR; 14 DECLARE_GLOBAL_DATA_PTR;
15 15
16 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
17 static const struct uniphier_board_data uniphier_sld3_data = {
18 .dram_freq = 1600,
19 .dram_ch[0] = {
20 .size = 0x20000000,
21 .width = 32,
22 },
23 .dram_ch[1] = {
24 .size = 0x20000000,
25 .width = 16,
26 },
27 .dram_ch[2] = {
28 .size = 0x10000000,
29 .width = 16,
30 },
31 .flags = UNIPHIER_BD_DRAM_SPARSE,
32 };
33 #endif
34
35 #if defined(CONFIG_ARCH_UNIPHIER_LD4) 16 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
36 static const struct uniphier_board_data uniphier_ld4_data = { 17 static const struct uniphier_board_data uniphier_ld4_data = {
37 .dram_freq = 1600, 18 .dram_freq = 1600,
38 .dram_ch[0] = { 19 .dram_ch[0] = {
39 .size = 0x10000000, 20 .size = 0x10000000,
40 .width = 16, 21 .width = 16,
41 }, 22 },
42 .dram_ch[1] = { 23 .dram_ch[1] = {
43 .size = 0x10000000, 24 .size = 0x10000000,
44 .width = 16, 25 .width = 16,
45 }, 26 },
46 .flags = UNIPHIER_BD_DDR3PLUS, 27 .flags = UNIPHIER_BD_DDR3PLUS,
47 }; 28 };
48 #endif 29 #endif
49 30
50 #if defined(CONFIG_ARCH_UNIPHIER_PRO4) 31 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
51 /* 1GB RAM board */ 32 /* 1GB RAM board */
52 static const struct uniphier_board_data uniphier_pro4_data = { 33 static const struct uniphier_board_data uniphier_pro4_data = {
53 .dram_freq = 1600, 34 .dram_freq = 1600,
54 .dram_ch[0] = { 35 .dram_ch[0] = {
55 .size = 0x20000000, 36 .size = 0x20000000,
56 .width = 32, 37 .width = 32,
57 }, 38 },
58 .dram_ch[1] = { 39 .dram_ch[1] = {
59 .size = 0x20000000, 40 .size = 0x20000000,
60 .width = 32, 41 .width = 32,
61 }, 42 },
62 }; 43 };
63 44
64 /* 2GB RAM board */ 45 /* 2GB RAM board */
65 static const struct uniphier_board_data uniphier_pro4_2g_data = { 46 static const struct uniphier_board_data uniphier_pro4_2g_data = {
66 .dram_freq = 1600, 47 .dram_freq = 1600,
67 .dram_ch[0] = { 48 .dram_ch[0] = {
68 .size = 0x40000000, 49 .size = 0x40000000,
69 .width = 32, 50 .width = 32,
70 }, 51 },
71 .dram_ch[1] = { 52 .dram_ch[1] = {
72 .size = 0x40000000, 53 .size = 0x40000000,
73 .width = 32, 54 .width = 32,
74 }, 55 },
75 }; 56 };
76 #endif 57 #endif
77 58
78 #if defined(CONFIG_ARCH_UNIPHIER_SLD8) 59 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
79 static const struct uniphier_board_data uniphier_sld8_data = { 60 static const struct uniphier_board_data uniphier_sld8_data = {
80 .dram_freq = 1333, 61 .dram_freq = 1333,
81 .dram_ch[0] = { 62 .dram_ch[0] = {
82 .size = 0x10000000, 63 .size = 0x10000000,
83 .width = 16, 64 .width = 16,
84 }, 65 },
85 .dram_ch[1] = { 66 .dram_ch[1] = {
86 .size = 0x10000000, 67 .size = 0x10000000,
87 .width = 16, 68 .width = 16,
88 }, 69 },
89 .flags = UNIPHIER_BD_DDR3PLUS, 70 .flags = UNIPHIER_BD_DDR3PLUS,
90 }; 71 };
91 #endif 72 #endif
92 73
93 #if defined(CONFIG_ARCH_UNIPHIER_PRO5) 74 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
94 static const struct uniphier_board_data uniphier_pro5_data = { 75 static const struct uniphier_board_data uniphier_pro5_data = {
95 .dram_freq = 1866, 76 .dram_freq = 1866,
96 .dram_ch[0] = { 77 .dram_ch[0] = {
97 .size = 0x20000000, 78 .size = 0x20000000,
98 .width = 32, 79 .width = 32,
99 }, 80 },
100 .dram_ch[1] = { 81 .dram_ch[1] = {
101 .size = 0x20000000, 82 .size = 0x20000000,
102 .width = 32, 83 .width = 32,
103 }, 84 },
104 }; 85 };
105 #endif 86 #endif
106 87
107 #if defined(CONFIG_ARCH_UNIPHIER_PXS2) 88 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
108 static const struct uniphier_board_data uniphier_pxs2_data = { 89 static const struct uniphier_board_data uniphier_pxs2_data = {
109 .dram_freq = 2133, 90 .dram_freq = 2133,
110 .dram_ch[0] = { 91 .dram_ch[0] = {
111 .size = 0x40000000, 92 .size = 0x40000000,
112 .width = 32, 93 .width = 32,
113 }, 94 },
114 .dram_ch[1] = { 95 .dram_ch[1] = {
115 .size = 0x20000000, 96 .size = 0x20000000,
116 .width = 32, 97 .width = 32,
117 }, 98 },
118 .dram_ch[2] = { 99 .dram_ch[2] = {
119 .size = 0x20000000, 100 .size = 0x20000000,
120 .width = 16, 101 .width = 16,
121 }, 102 },
122 }; 103 };
123 #endif 104 #endif
124 105
125 #if defined(CONFIG_ARCH_UNIPHIER_LD6B) 106 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
126 static const struct uniphier_board_data uniphier_ld6b_data = { 107 static const struct uniphier_board_data uniphier_ld6b_data = {
127 .dram_freq = 1866, 108 .dram_freq = 1866,
128 .dram_ch[0] = { 109 .dram_ch[0] = {
129 .size = 0x40000000, 110 .size = 0x40000000,
130 .width = 32, 111 .width = 32,
131 }, 112 },
132 .dram_ch[1] = { 113 .dram_ch[1] = {
133 .size = 0x20000000, 114 .size = 0x20000000,
134 .width = 32, 115 .width = 32,
135 }, 116 },
136 .dram_ch[2] = { 117 .dram_ch[2] = {
137 .size = 0x20000000, 118 .size = 0x20000000,
138 .width = 16, 119 .width = 16,
139 }, 120 },
140 }; 121 };
141 #endif 122 #endif
142 123
143 struct uniphier_board_id { 124 struct uniphier_board_id {
144 const char *compatible; 125 const char *compatible;
145 const struct uniphier_board_data *param; 126 const struct uniphier_board_data *param;
146 }; 127 };
147 128
148 static const struct uniphier_board_id uniphier_boards[] = { 129 static const struct uniphier_board_id uniphier_boards[] = {
149 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
150 { "socionext,uniphier-sld3", &uniphier_sld3_data, },
151 #endif
152 #if defined(CONFIG_ARCH_UNIPHIER_LD4) 130 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
153 { "socionext,uniphier-ld4", &uniphier_ld4_data, }, 131 { "socionext,uniphier-ld4", &uniphier_ld4_data, },
154 #endif 132 #endif
155 #if defined(CONFIG_ARCH_UNIPHIER_PRO4) 133 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
156 { "socionext,uniphier-pro4-ace", &uniphier_pro4_2g_data, }, 134 { "socionext,uniphier-pro4-ace", &uniphier_pro4_2g_data, },
157 { "socionext,uniphier-pro4-sanji", &uniphier_pro4_2g_data, }, 135 { "socionext,uniphier-pro4-sanji", &uniphier_pro4_2g_data, },
158 { "socionext,uniphier-pro4", &uniphier_pro4_data, }, 136 { "socionext,uniphier-pro4", &uniphier_pro4_data, },
159 #endif 137 #endif
160 #if defined(CONFIG_ARCH_UNIPHIER_SLD8) 138 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
161 { "socionext,uniphier-sld8", &uniphier_sld8_data, }, 139 { "socionext,uniphier-sld8", &uniphier_sld8_data, },
162 #endif 140 #endif
163 #if defined(CONFIG_ARCH_UNIPHIER_PRO5) 141 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
164 { "socionext,uniphier-pro5", &uniphier_pro5_data, }, 142 { "socionext,uniphier-pro5", &uniphier_pro5_data, },
165 #endif 143 #endif
166 #if defined(CONFIG_ARCH_UNIPHIER_PXS2) 144 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
167 { "socionext,uniphier-pxs2", &uniphier_pxs2_data, }, 145 { "socionext,uniphier-pxs2", &uniphier_pxs2_data, },
168 #endif 146 #endif
169 #if defined(CONFIG_ARCH_UNIPHIER_LD6B) 147 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
170 { "socionext,uniphier-ld6b", &uniphier_ld6b_data, }, 148 { "socionext,uniphier-ld6b", &uniphier_ld6b_data, },
171 #endif 149 #endif
172 }; 150 };
173 151
174 const struct uniphier_board_data *uniphier_get_board_param(void) 152 const struct uniphier_board_data *uniphier_get_board_param(void)
175 { 153 {
176 int i; 154 int i;
177 155
178 for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) { 156 for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) {
179 if (!fdt_node_check_compatible(gd->fdt_blob, 0, 157 if (!fdt_node_check_compatible(gd->fdt_blob, 0,
180 uniphier_boards[i].compatible)) 158 uniphier_boards[i].compatible))
181 return uniphier_boards[i].param; 159 return uniphier_boards[i].param;
182 } 160 }
183 161
184 return NULL; 162 return NULL;
185 } 163 }
186 164
arch/arm/mach-uniphier/boot-device/Makefile
Diff comments   View file @ 00aa453
1 # 1 #
2 # SPDX-License-Identifier: GPL-2.0+ 2 # SPDX-License-Identifier: GPL-2.0+
3 # 3 #
4 4
5 obj-y += boot-device.o 5 obj-y += boot-device.o
6 6
7 obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += boot-device-sld3.o
8 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += boot-device-ld4.o 7 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += boot-device-ld4.o
9 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += boot-device-ld4.o 8 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += boot-device-ld4.o
10 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-device-ld4.o 9 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-device-ld4.o
11 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-device-pro5.o 10 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-device-pro5.o
12 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-device-pxs2.o 11 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-device-pxs2.o
13 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-device-pxs2.o 12 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-device-pxs2.o
14 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-device-ld11.o 13 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-device-ld11.o
15 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-device-ld11.o 14 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-device-ld11.o
16 obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += boot-device-pxs3.o 15 obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += boot-device-pxs3.o
17 16
arch/arm/mach-uniphier/boot-device/boot-device-sld3.c
View file @ 00aa453
1 /* File was deleted
2 * Copyright (C) 2014 Panasonic Corporation
3 * Copyright (C) 2015-2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <spl.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13
14 #include "boot-device.h"
15
16 const struct uniphier_boot_device uniphier_sld3_boot_device_table[] = {
17 {BOOT_DEVICE_NOR, "NOR (XECS0)"},
18 {BOOT_DEVICE_NONE, "External Master"},
19 {BOOT_DEVICE_NONE, "Reserved"},
20 {BOOT_DEVICE_NONE, "Reserved"},
21 {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"},
22 {BOOT_DEVICE_NONE, "Reserved"},
23 {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"},
24 {BOOT_DEVICE_NONE, "Reserved"},
25 {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"},
26 {BOOT_DEVICE_NONE, "Reserved"},
27 {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"},
28 {BOOT_DEVICE_NONE, "Reserved"},
29 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
30 {BOOT_DEVICE_NONE, "Reserved"},
31 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
32 {BOOT_DEVICE_NONE, "Reserved"},
33 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
34 {BOOT_DEVICE_NONE, "Reserved"},
35 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
36 {BOOT_DEVICE_NONE, "Reserved"},
37 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
38 {BOOT_DEVICE_NONE, "Reserved"},
39 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
40 {BOOT_DEVICE_NONE, "Reserved"},
41 {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
42 {BOOT_DEVICE_NONE, "Reserved"},
43 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
44 {BOOT_DEVICE_NONE, "Reserved"},
45 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
46 {BOOT_DEVICE_NONE, "Reserved"},
47 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
48 {BOOT_DEVICE_NONE, "Reserved"},
49 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
50 {BOOT_DEVICE_NONE, "Reserved"},
51 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
52 {BOOT_DEVICE_NONE, "Reserved"},
53 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
54 {BOOT_DEVICE_NONE, "Reserved"},
55 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
56 {BOOT_DEVICE_NONE, "Reserved"},
57 {BOOT_DEVICE_NONE, "Reserved"},
58 {BOOT_DEVICE_NONE, "Reserved"},
59 {BOOT_DEVICE_NONE, "Reserved"},
60 {BOOT_DEVICE_NONE, "Reserved"},
61 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
62 {BOOT_DEVICE_NONE, "Reserved"},
63 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
64 {BOOT_DEVICE_NONE, "Reserved"},
65 {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
66 {BOOT_DEVICE_NONE, "Reserved"},
67 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
68 {BOOT_DEVICE_NONE, "Reserved"},
69 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
70 {BOOT_DEVICE_NONE, "Reserved"},
71 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
72 {BOOT_DEVICE_NONE, "Reserved"},
73 {BOOT_DEVICE_NONE, "Reserved"},
74 {BOOT_DEVICE_NONE, "Reserved"},
75 {BOOT_DEVICE_NONE, "Reserved"},
76 {BOOT_DEVICE_NONE, "Reserved"},
77 {BOOT_DEVICE_NONE, "Reserved"},
78 {BOOT_DEVICE_NONE, "Reserved"},
79 {BOOT_DEVICE_NONE, "Reserved"},
80 {BOOT_DEVICE_NONE, "Reserved"},
81 };
82
83 const unsigned uniphier_sld3_boot_device_count =
84 ARRAY_SIZE(uniphier_sld3_boot_device_table);
85 1 /*
arch/arm/mach-uniphier/boot-device/boot-device.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2015-2017 Socionext Inc. 2 * Copyright (C) 2015-2017 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <spl.h> 9 #include <spl.h>
10 #include <linux/log2.h> 10 #include <linux/log2.h>
11 11
12 #include "../init.h" 12 #include "../init.h"
13 #include "../sbc/sbc-regs.h" 13 #include "../sbc/sbc-regs.h"
14 #include "../sg-regs.h" 14 #include "../sg-regs.h"
15 #include "../soc-info.h" 15 #include "../soc-info.h"
16 #include "boot-device.h" 16 #include "boot-device.h"
17 17
18 struct uniphier_boot_device_info { 18 struct uniphier_boot_device_info {
19 unsigned int soc_id; 19 unsigned int soc_id;
20 unsigned int boot_device_sel_shift; 20 unsigned int boot_device_sel_shift;
21 const struct uniphier_boot_device *boot_device_table; 21 const struct uniphier_boot_device *boot_device_table;
22 const unsigned int *boot_device_count; 22 const unsigned int *boot_device_count;
23 int (*boot_device_is_usb)(u32 pinmon); 23 int (*boot_device_is_usb)(u32 pinmon);
24 unsigned int (*boot_device_fixup)(unsigned int mode); 24 unsigned int (*boot_device_fixup)(unsigned int mode);
25 int have_internal_stm; 25 int have_internal_stm;
26 }; 26 };
27 27
28 static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { 28 static const struct uniphier_boot_device_info uniphier_boot_device_info[] = {
29 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
30 {
31 .soc_id = UNIPHIER_SLD3_ID,
32 .boot_device_sel_shift = 0,
33 .boot_device_table = uniphier_sld3_boot_device_table,
34 .boot_device_count = &uniphier_sld3_boot_device_count,
35 .have_internal_stm = 0,
36 },
37 #endif
38 #if defined(CONFIG_ARCH_UNIPHIER_LD4) 29 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
39 { 30 {
40 .soc_id = UNIPHIER_LD4_ID, 31 .soc_id = UNIPHIER_LD4_ID,
41 .boot_device_sel_shift = 1, 32 .boot_device_sel_shift = 1,
42 .boot_device_table = uniphier_ld4_boot_device_table, 33 .boot_device_table = uniphier_ld4_boot_device_table,
43 .boot_device_count = &uniphier_ld4_boot_device_count, 34 .boot_device_count = &uniphier_ld4_boot_device_count,
44 .have_internal_stm = 1, 35 .have_internal_stm = 1,
45 }, 36 },
46 #endif 37 #endif
47 #if defined(CONFIG_ARCH_UNIPHIER_PRO4) 38 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
48 { 39 {
49 .soc_id = UNIPHIER_PRO4_ID, 40 .soc_id = UNIPHIER_PRO4_ID,
50 .boot_device_sel_shift = 1, 41 .boot_device_sel_shift = 1,
51 .boot_device_table = uniphier_ld4_boot_device_table, 42 .boot_device_table = uniphier_ld4_boot_device_table,
52 .boot_device_count = &uniphier_ld4_boot_device_count, 43 .boot_device_count = &uniphier_ld4_boot_device_count,
53 .have_internal_stm = 0, 44 .have_internal_stm = 0,
54 }, 45 },
55 #endif 46 #endif
56 #if defined(CONFIG_ARCH_UNIPHIER_SLD8) 47 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
57 { 48 {
58 .soc_id = UNIPHIER_SLD8_ID, 49 .soc_id = UNIPHIER_SLD8_ID,
59 .boot_device_sel_shift = 1, 50 .boot_device_sel_shift = 1,
60 .boot_device_table = uniphier_ld4_boot_device_table, 51 .boot_device_table = uniphier_ld4_boot_device_table,
61 .boot_device_count = &uniphier_ld4_boot_device_count, 52 .boot_device_count = &uniphier_ld4_boot_device_count,
62 .have_internal_stm = 1, 53 .have_internal_stm = 1,
63 }, 54 },
64 #endif 55 #endif
65 #if defined(CONFIG_ARCH_UNIPHIER_PRO5) 56 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
66 { 57 {
67 .soc_id = UNIPHIER_PRO5_ID, 58 .soc_id = UNIPHIER_PRO5_ID,
68 .boot_device_sel_shift = 1, 59 .boot_device_sel_shift = 1,
69 .boot_device_table = uniphier_pro5_boot_device_table, 60 .boot_device_table = uniphier_pro5_boot_device_table,
70 .boot_device_count = &uniphier_pro5_boot_device_count, 61 .boot_device_count = &uniphier_pro5_boot_device_count,
71 .have_internal_stm = 0, 62 .have_internal_stm = 0,
72 }, 63 },
73 #endif 64 #endif
74 #if defined(CONFIG_ARCH_UNIPHIER_PXS2) 65 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
75 { 66 {
76 .soc_id = UNIPHIER_PXS2_ID, 67 .soc_id = UNIPHIER_PXS2_ID,
77 .boot_device_sel_shift = 1, 68 .boot_device_sel_shift = 1,
78 .boot_device_table = uniphier_pxs2_boot_device_table, 69 .boot_device_table = uniphier_pxs2_boot_device_table,
79 .boot_device_count = &uniphier_pxs2_boot_device_count, 70 .boot_device_count = &uniphier_pxs2_boot_device_count,
80 .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb, 71 .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb,
81 .boot_device_fixup = uniphier_pxs2_boot_device_fixup, 72 .boot_device_fixup = uniphier_pxs2_boot_device_fixup,
82 .have_internal_stm = 0, 73 .have_internal_stm = 0,
83 }, 74 },
84 #endif 75 #endif
85 #if defined(CONFIG_ARCH_UNIPHIER_LD6B) 76 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
86 { 77 {
87 .soc_id = UNIPHIER_LD6B_ID, 78 .soc_id = UNIPHIER_LD6B_ID,
88 .boot_device_sel_shift = 1, 79 .boot_device_sel_shift = 1,
89 .boot_device_table = uniphier_pxs2_boot_device_table, 80 .boot_device_table = uniphier_pxs2_boot_device_table,
90 .boot_device_count = &uniphier_pxs2_boot_device_count, 81 .boot_device_count = &uniphier_pxs2_boot_device_count,
91 .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb, 82 .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb,
92 .boot_device_fixup = uniphier_pxs2_boot_device_fixup, 83 .boot_device_fixup = uniphier_pxs2_boot_device_fixup,
93 .have_internal_stm = 1, /* STM on A-chip */ 84 .have_internal_stm = 1, /* STM on A-chip */
94 }, 85 },
95 #endif 86 #endif
96 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 87 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
97 { 88 {
98 .soc_id = UNIPHIER_LD11_ID, 89 .soc_id = UNIPHIER_LD11_ID,
99 .boot_device_sel_shift = 1, 90 .boot_device_sel_shift = 1,
100 .boot_device_table = uniphier_ld11_boot_device_table, 91 .boot_device_table = uniphier_ld11_boot_device_table,
101 .boot_device_count = &uniphier_ld11_boot_device_count, 92 .boot_device_count = &uniphier_ld11_boot_device_count,
102 .boot_device_is_usb = uniphier_ld11_boot_device_is_usb, 93 .boot_device_is_usb = uniphier_ld11_boot_device_is_usb,
103 .boot_device_fixup = uniphier_ld11_boot_device_fixup, 94 .boot_device_fixup = uniphier_ld11_boot_device_fixup,
104 .have_internal_stm = 1, 95 .have_internal_stm = 1,
105 }, 96 },
106 #endif 97 #endif
107 #if defined(CONFIG_ARCH_UNIPHIER_LD20) 98 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
108 { 99 {
109 .soc_id = UNIPHIER_LD20_ID, 100 .soc_id = UNIPHIER_LD20_ID,
110 .boot_device_sel_shift = 1, 101 .boot_device_sel_shift = 1,
111 .boot_device_table = uniphier_ld11_boot_device_table, 102 .boot_device_table = uniphier_ld11_boot_device_table,
112 .boot_device_count = &uniphier_ld11_boot_device_count, 103 .boot_device_count = &uniphier_ld11_boot_device_count,
113 .boot_device_is_usb = uniphier_ld20_boot_device_is_usb, 104 .boot_device_is_usb = uniphier_ld20_boot_device_is_usb,
114 .boot_device_fixup = uniphier_ld11_boot_device_fixup, 105 .boot_device_fixup = uniphier_ld11_boot_device_fixup,
115 .have_internal_stm = 1, 106 .have_internal_stm = 1,
116 }, 107 },
117 #endif 108 #endif
118 #if defined(CONFIG_ARCH_UNIPHIER_PXS3) 109 #if defined(CONFIG_ARCH_UNIPHIER_PXS3)
119 { 110 {
120 .soc_id = UNIPHIER_PXS3_ID, 111 .soc_id = UNIPHIER_PXS3_ID,
121 .boot_device_sel_shift = 1, 112 .boot_device_sel_shift = 1,
122 .boot_device_table = uniphier_pxs3_boot_device_table, 113 .boot_device_table = uniphier_pxs3_boot_device_table,
123 .boot_device_count = &uniphier_pxs3_boot_device_count, 114 .boot_device_count = &uniphier_pxs3_boot_device_count,
124 .boot_device_is_usb = uniphier_pxs3_boot_device_is_usb, 115 .boot_device_is_usb = uniphier_pxs3_boot_device_is_usb,
125 .have_internal_stm = 0, 116 .have_internal_stm = 0,
126 }, 117 },
127 #endif 118 #endif
128 }; 119 };
129 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_boot_device_info, 120 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_boot_device_info,
130 uniphier_boot_device_info) 121 uniphier_boot_device_info)
131 122
132 static unsigned int __uniphier_boot_device_raw( 123 static unsigned int __uniphier_boot_device_raw(
133 const struct uniphier_boot_device_info *info) 124 const struct uniphier_boot_device_info *info)
134 { 125 {
135 u32 pinmon; 126 u32 pinmon;
136 unsigned int boot_sel; 127 unsigned int boot_sel;
137 128
138 if (boot_is_swapped()) 129 if (boot_is_swapped())
139 return BOOT_DEVICE_NOR; 130 return BOOT_DEVICE_NOR;
140 131
141 pinmon = readl(SG_PINMON0); 132 pinmon = readl(SG_PINMON0);
142 133
143 if (info->boot_device_is_usb && info->boot_device_is_usb(pinmon)) 134 if (info->boot_device_is_usb && info->boot_device_is_usb(pinmon))
144 return BOOT_DEVICE_USB; 135 return BOOT_DEVICE_USB;
145 136
146 boot_sel = pinmon >> info->boot_device_sel_shift; 137 boot_sel = pinmon >> info->boot_device_sel_shift;
147 138
148 BUG_ON(!is_power_of_2(*info->boot_device_count)); 139 BUG_ON(!is_power_of_2(*info->boot_device_count));
149 boot_sel &= *info->boot_device_count - 1; 140 boot_sel &= *info->boot_device_count - 1;
150 141
151 return info->boot_device_table[boot_sel].boot_device; 142 return info->boot_device_table[boot_sel].boot_device;
152 } 143 }
153 144
154 unsigned int uniphier_boot_device_raw(void) 145 unsigned int uniphier_boot_device_raw(void)
155 { 146 {
156 const struct uniphier_boot_device_info *info; 147 const struct uniphier_boot_device_info *info;
157 148
158 info = uniphier_get_boot_device_info(); 149 info = uniphier_get_boot_device_info();
159 if (!info) { 150 if (!info) {
160 pr_err("unsupported SoC\n"); 151 pr_err("unsupported SoC\n");
161 return BOOT_DEVICE_NONE; 152 return BOOT_DEVICE_NONE;
162 } 153 }
163 154
164 return __uniphier_boot_device_raw(info); 155 return __uniphier_boot_device_raw(info);
165 } 156 }
166 157
167 u32 spl_boot_device(void) 158 u32 spl_boot_device(void)
168 { 159 {
169 const struct uniphier_boot_device_info *info; 160 const struct uniphier_boot_device_info *info;
170 u32 raw_mode; 161 u32 raw_mode;
171 162
172 info = uniphier_get_boot_device_info(); 163 info = uniphier_get_boot_device_info();
173 if (!info) { 164 if (!info) {
174 pr_err("unsupported SoC\n"); 165 pr_err("unsupported SoC\n");
175 return BOOT_DEVICE_NONE; 166 return BOOT_DEVICE_NONE;
176 } 167 }
177 168
178 raw_mode = __uniphier_boot_device_raw(info); 169 raw_mode = __uniphier_boot_device_raw(info);
179 170
180 return info->boot_device_fixup ? 171 return info->boot_device_fixup ?
181 info->boot_device_fixup(raw_mode) : raw_mode; 172 info->boot_device_fixup(raw_mode) : raw_mode;
182 } 173 }
183 174
184 int uniphier_have_internal_stm(void) 175 int uniphier_have_internal_stm(void)
185 { 176 {
186 const struct uniphier_boot_device_info *info; 177 const struct uniphier_boot_device_info *info;
187 178
188 info = uniphier_get_boot_device_info(); 179 info = uniphier_get_boot_device_info();
189 if (!info) { 180 if (!info) {
190 pr_err("unsupported SoC\n"); 181 pr_err("unsupported SoC\n");
191 return -ENOTSUPP; 182 return -ENOTSUPP;
192 } 183 }
193 184
194 return info->have_internal_stm; 185 return info->have_internal_stm;
195 } 186 }
196 187
197 int uniphier_boot_from_backend(void) 188 int uniphier_boot_from_backend(void)
198 { 189 {
199 return !!(readl(SG_PINMON0) & BIT(27)); 190 return !!(readl(SG_PINMON0) & BIT(27));
200 } 191 }
201 192
202 #ifndef CONFIG_SPL_BUILD 193 #ifndef CONFIG_SPL_BUILD
203 194
204 static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 195 static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
205 { 196 {
206 const struct uniphier_boot_device_info *info; 197 const struct uniphier_boot_device_info *info;
207 u32 pinmon; 198 u32 pinmon;
208 unsigned int boot_device_count, boot_sel; 199 unsigned int boot_device_count, boot_sel;
209 int i; 200 int i;
210 201
211 info = uniphier_get_boot_device_info(); 202 info = uniphier_get_boot_device_info();
212 if (!info) { 203 if (!info) {
213 pr_err("unsupported SoC\n"); 204 pr_err("unsupported SoC\n");
214 return CMD_RET_FAILURE; 205 return CMD_RET_FAILURE;
215 } 206 }
216 207
217 if (uniphier_have_internal_stm()) 208 if (uniphier_have_internal_stm())
218 printf("STB Micon: %s\n", 209 printf("STB Micon: %s\n",
219 uniphier_boot_from_backend() ? "OFF" : "ON"); 210 uniphier_boot_from_backend() ? "OFF" : "ON");
220 211
221 printf("Boot Swap: %s\n", boot_is_swapped() ? "ON" : "OFF"); 212 printf("Boot Swap: %s\n", boot_is_swapped() ? "ON" : "OFF");
222 213
223 pinmon = readl(SG_PINMON0); 214 pinmon = readl(SG_PINMON0);
224 215
225 if (info->boot_device_is_usb) 216 if (info->boot_device_is_usb)
226 printf("USB Boot: %s\n", 217 printf("USB Boot: %s\n",
227 info->boot_device_is_usb(pinmon) ? "ON" : "OFF"); 218 info->boot_device_is_usb(pinmon) ? "ON" : "OFF");
228 219
229 boot_device_count = *info->boot_device_count; 220 boot_device_count = *info->boot_device_count;
230 221
231 boot_sel = pinmon >> info->boot_device_sel_shift; 222 boot_sel = pinmon >> info->boot_device_sel_shift;
232 boot_sel &= boot_device_count - 1; 223 boot_sel &= boot_device_count - 1;
233 224
234 printf("\nBoot Mode Sel:\n"); 225 printf("\nBoot Mode Sel:\n");
235 for (i = 0; i < boot_device_count; i++) 226 for (i = 0; i < boot_device_count; i++)
236 printf(" %c %02x %s\n", i == boot_sel ? '*' : ' ', i, 227 printf(" %c %02x %s\n", i == boot_sel ? '*' : ' ', i,
237 info->boot_device_table[i].desc); 228 info->boot_device_table[i].desc);
238 229
239 return CMD_RET_SUCCESS; 230 return CMD_RET_SUCCESS;
240 } 231 }
241 232
242 U_BOOT_CMD( 233 U_BOOT_CMD(
243 pinmon, 1, 1, do_pinmon, 234 pinmon, 1, 1, do_pinmon,
244 "pin monitor", 235 "pin monitor",
245 "" 236 ""
246 ); 237 );
247 238
248 #endif /* !CONFIG_SPL_BUILD */ 239 #endif /* !CONFIG_SPL_BUILD */
249 240
arch/arm/mach-uniphier/boot-device/boot-device.h
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2017 Socionext Inc. 2 * Copyright (C) 2017 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef _UNIPHIER_BOOT_DEVICE_H_ 8 #ifndef _UNIPHIER_BOOT_DEVICE_H_
9 #define _UNIPHIER_BOOT_DEVICE_H_ 9 #define _UNIPHIER_BOOT_DEVICE_H_
10 10
11 struct uniphier_boot_device { 11 struct uniphier_boot_device {
12 unsigned int boot_device; 12 unsigned int boot_device;
13 const char *desc; 13 const char *desc;
14 }; 14 };
15 15
16 extern const struct uniphier_boot_device uniphier_sld3_boot_device_table[];
17 extern const struct uniphier_boot_device uniphier_ld4_boot_device_table[]; 16 extern const struct uniphier_boot_device uniphier_ld4_boot_device_table[];
18 extern const struct uniphier_boot_device uniphier_pro5_boot_device_table[]; 17 extern const struct uniphier_boot_device uniphier_pro5_boot_device_table[];
19 extern const struct uniphier_boot_device uniphier_pxs2_boot_device_table[]; 18 extern const struct uniphier_boot_device uniphier_pxs2_boot_device_table[];
20 extern const struct uniphier_boot_device uniphier_ld11_boot_device_table[]; 19 extern const struct uniphier_boot_device uniphier_ld11_boot_device_table[];
21 extern const struct uniphier_boot_device uniphier_pxs3_boot_device_table[]; 20 extern const struct uniphier_boot_device uniphier_pxs3_boot_device_table[];
22 21
23 extern const unsigned int uniphier_sld3_boot_device_count;
24 extern const unsigned int uniphier_ld4_boot_device_count; 22 extern const unsigned int uniphier_ld4_boot_device_count;
25 extern const unsigned int uniphier_pro5_boot_device_count; 23 extern const unsigned int uniphier_pro5_boot_device_count;
26 extern const unsigned int uniphier_pxs2_boot_device_count; 24 extern const unsigned int uniphier_pxs2_boot_device_count;
27 extern const unsigned int uniphier_ld11_boot_device_count; 25 extern const unsigned int uniphier_ld11_boot_device_count;
28 extern const unsigned int uniphier_pxs3_boot_device_count; 26 extern const unsigned int uniphier_pxs3_boot_device_count;
29 27
30 int uniphier_pxs2_boot_device_is_usb(u32 pinmon); 28 int uniphier_pxs2_boot_device_is_usb(u32 pinmon);
31 int uniphier_ld11_boot_device_is_usb(u32 pinmon); 29 int uniphier_ld11_boot_device_is_usb(u32 pinmon);
32 int uniphier_ld20_boot_device_is_usb(u32 pinmon); 30 int uniphier_ld20_boot_device_is_usb(u32 pinmon);
33 int uniphier_pxs3_boot_device_is_usb(u32 pinmon); 31 int uniphier_pxs3_boot_device_is_usb(u32 pinmon);
34 32
35 unsigned int uniphier_pxs2_boot_device_fixup(unsigned int mode); 33 unsigned int uniphier_pxs2_boot_device_fixup(unsigned int mode);
36 unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode); 34 unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode);
37 35
38 #endif /* _UNIPHIER_BOOT_DEVICE_H_ */ 36 #endif /* _UNIPHIER_BOOT_DEVICE_H_ */
39 37
arch/arm/mach-uniphier/clk/Makefile
Diff comments   View file @ 00aa453
1 # 1 #
2 # SPDX-License-Identifier: GPL-2.0+ 2 # SPDX-License-Identifier: GPL-2.0+
3 # 3 #
4 4
5 ifdef CONFIG_SPL_BUILD 5 ifdef CONFIG_SPL_BUILD
6 6
7 obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-early-sld3.o clk-dram-sld3.o dpll-sld3.o 7 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
8 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-sld3.o clk-dram-sld3.o dpll-ld4.o 8 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
9 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-sld3.o clk-dram-sld3.o dpll-pro4.o 9 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
10 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-sld3.o clk-dram-sld3.o dpll-sld8.o 10 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
11 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-sld3.o clk-dram-pro5.o dpll-pro5.o 11 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
12 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o 12 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
13 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o
14 13
15 else 14 else
16 15
17 obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o pll-sld3.o dpll-tail.o
18 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o 16 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o
19 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o 17 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
20 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o 18 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o
21 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o 19 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o
22 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o 20 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
23 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o 21 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
24 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o 22 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o
25 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o 23 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o
26 obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += clk-pxs3.o pll-pxs3.o 24 obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += clk-pxs3.o pll-pxs3.o
27 25
28 endif 26 endif
29 27
30 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o 28 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o
31 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o 29 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o
32 30
arch/arm/mach-uniphier/clk/clk-dram-ld4.c
Diff comments   View file @ 00aa453
File was created 1 /*
2 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Copyright (C) 2015-2017 Socionext Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <spl.h>
10 #include <linux/io.h>
11
12 #include "../init.h"
13 #include "../sc-regs.h"
14
15 void uniphier_ld4_dram_clk_init(void)
16 {
17 u32 tmp;
18
19 /* deassert reset */
20 tmp = readl(SC_RSTCTRL);
21 tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
22 writel(tmp, SC_RSTCTRL);
23 readl(SC_RSTCTRL); /* dummy read */
24
25 /* provide clocks */
26 tmp = readl(SC_CLKCTRL);
27 tmp |= SC_CLKCTRL_CEN_UMC;
28 writel(tmp, SC_CLKCTRL);
29 readl(SC_CLKCTRL); /* dummy read */
30 }
31
arch/arm/mach-uniphier/clk/clk-dram-sld3.c
View file @ 00aa453
1 /* File was deleted
2 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Copyright (C) 2015-2017 Socionext Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <spl.h>
10 #include <linux/io.h>
11
12 #include "../init.h"
13 #include "../sc-regs.h"
14
15 void uniphier_sld3_dram_clk_init(void)
16 {
17 u32 tmp;
18
19 /* deassert reset */
20 tmp = readl(SC_RSTCTRL);
21 tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
22 writel(tmp, SC_RSTCTRL);
23 readl(SC_RSTCTRL); /* dummy read */
24
25 /* provide clocks */
26 tmp = readl(SC_CLKCTRL);
27 tmp |= SC_CLKCTRL_CEN_UMC;
28 writel(tmp, SC_CLKCTRL);
29 readl(SC_CLKCTRL); /* dummy read */
30 }
31 1 /*
arch/arm/mach-uniphier/clk/clk-early-ld4.c
Diff comments   View file @ 00aa453
File was created 1 /*
2 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Copyright (C) 2015-2017 Socionext Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <spl.h>
10 #include <linux/io.h>
11
12 #include "../init.h"
13 #include "../sc-regs.h"
14
15 void uniphier_ld4_early_clk_init(void)
16 {
17 u32 tmp;
18
19 /* deassert reset */
20 if (spl_boot_device() != BOOT_DEVICE_NAND) {
21 tmp = readl(SC_RSTCTRL);
22 tmp &= ~SC_RSTCTRL_NRST_NAND;
23 writel(tmp, SC_RSTCTRL);
24 };
25
26 /* provide clocks */
27 tmp = readl(SC_CLKCTRL);
28 tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
29 writel(tmp, SC_CLKCTRL);
30 readl(SC_CLKCTRL); /* dummy read */
31 }
32
arch/arm/mach-uniphier/clk/clk-early-sld3.c
View file @ 00aa453
1 /* File was deleted
2 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Copyright (C) 2015-2017 Socionext Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <spl.h>
10 #include <linux/io.h>
11
12 #include "../init.h"
13 #include "../sc-regs.h"
14
15 void uniphier_sld3_early_clk_init(void)
16 {
17 u32 tmp;
18
19 /* deassert reset */
20 if (spl_boot_device() != BOOT_DEVICE_NAND) {
21 tmp = readl(SC_RSTCTRL);
22 tmp &= ~SC_RSTCTRL_NRST_NAND;
23 writel(tmp, SC_RSTCTRL);
24 };
25
26 /* provide clocks */
27 tmp = readl(SC_CLKCTRL);
28 tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
29 writel(tmp, SC_CLKCTRL);
30 readl(SC_CLKCTRL); /* dummy read */
31 }
32 1 /*
arch/arm/mach-uniphier/clk/dpll-sld3.c
View file @ 00aa453
1 /* File was deleted
2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include "../init.h"
8
9 int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd)
10 {
11 /* add pll init code here */
12 return 0;
13 }
14 1 /*
arch/arm/mach-uniphier/clk/pll-sld3.c
View file @ 00aa453
1 /* File was deleted
2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include "../init.h"
9 #include "pll.h"
10
11 void uniphier_sld3_pll_init(void)
12 {
13 uniphier_ld4_dpll_ssc_en();
14 }
15 1 /*
arch/arm/mach-uniphier/cpu-info.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2013-2014 Panasonic Corporation 2 * Copyright (C) 2013-2014 Panasonic Corporation
3 * Copyright (C) 2015-2017 Socionext Inc. 3 * Copyright (C) 2015-2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <common.h> 9 #include <common.h>
10 #include <linux/errno.h> 10 #include <linux/errno.h>
11 #include <linux/io.h> 11 #include <linux/io.h>
12 12
13 #include "soc-info.h" 13 #include "soc-info.h"
14 14
15 int print_cpuinfo(void) 15 int print_cpuinfo(void)
16 { 16 {
17 unsigned int id, model, rev, required_model = 1, required_rev = 1; 17 unsigned int id, model, rev, required_model = 1, required_rev = 1;
18 18
19 id = uniphier_get_soc_id(); 19 id = uniphier_get_soc_id();
20 model = uniphier_get_soc_model(); 20 model = uniphier_get_soc_model();
21 rev = uniphier_get_soc_revision(); 21 rev = uniphier_get_soc_revision();
22 22
23 puts("SoC: "); 23 puts("SoC: ");
24 24
25 switch (id) { 25 switch (id) {
26 case UNIPHIER_SLD3_ID:
27 puts("sLD3");
28 required_model = 2;
29 break;
30 case UNIPHIER_LD4_ID: 26 case UNIPHIER_LD4_ID:
31 puts("LD4"); 27 puts("LD4");
32 required_rev = 2; 28 required_rev = 2;
33 break; 29 break;
34 case UNIPHIER_PRO4_ID: 30 case UNIPHIER_PRO4_ID:
35 puts("Pro4"); 31 puts("Pro4");
36 break; 32 break;
37 case UNIPHIER_SLD8_ID: 33 case UNIPHIER_SLD8_ID:
38 puts("sLD8"); 34 puts("sLD8");
39 break; 35 break;
40 case UNIPHIER_PRO5_ID: 36 case UNIPHIER_PRO5_ID:
41 puts("Pro5"); 37 puts("Pro5");
42 break; 38 break;
43 case UNIPHIER_PXS2_ID: 39 case UNIPHIER_PXS2_ID:
44 puts("PXs2"); 40 puts("PXs2");
45 break; 41 break;
46 case UNIPHIER_LD6B_ID: 42 case UNIPHIER_LD6B_ID:
47 puts("LD6b"); 43 puts("LD6b");
48 break; 44 break;
49 case UNIPHIER_LD11_ID: 45 case UNIPHIER_LD11_ID:
50 puts("LD11"); 46 puts("LD11");
51 break; 47 break;
52 case UNIPHIER_LD20_ID: 48 case UNIPHIER_LD20_ID:
53 puts("LD20"); 49 puts("LD20");
54 break; 50 break;
55 case UNIPHIER_PXS3_ID: 51 case UNIPHIER_PXS3_ID:
56 puts("PXs3"); 52 puts("PXs3");
57 break; 53 break;
58 default: 54 default:
59 printf("Unknown Processor ID (0x%x)\n", id); 55 printf("Unknown Processor ID (0x%x)\n", id);
60 return -ENOTSUPP; 56 return -ENOTSUPP;
61 } 57 }
62 58
63 printf(" (model %d, revision %d)\n", model, rev); 59 printf(" (model %d, revision %d)\n", model, rev);
64 60
65 if (model < required_model) { 61 if (model < required_model) {
66 printf("Only model %d or newer is supported.\n", 62 printf("Only model %d or newer is supported.\n",
67 required_model); 63 required_model);
68 return -ENOTSUPP; 64 return -ENOTSUPP;
69 } else if (rev < required_rev) { 65 } else if (rev < required_rev) {
70 printf("Only revision %d or newer is supported.\n", 66 printf("Only revision %d or newer is supported.\n",
71 required_rev); 67 required_rev);
72 return -ENOTSUPP; 68 return -ENOTSUPP;
73 } 69 }
74 70
75 return 0; 71 return 0;
76 } 72 }
77 73
arch/arm/mach-uniphier/debug-uart/Makefile
Diff comments   View file @ 00aa453
1 # 1 #
2 # SPDX-License-Identifier: GPL-2.0+ 2 # SPDX-License-Identifier: GPL-2.0+
3 # 3 #
4 4
5 ifdef CONFIG_SPL_BUILD 5 ifdef CONFIG_SPL_BUILD
6 obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += debug-uart-sld3.o
7 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += debug-uart-ld4.o 6 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += debug-uart-ld4.o
8 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += debug-uart-pro4.o 7 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += debug-uart-pro4.o
9 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o 8 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o
10 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += debug-uart-pro5.o 9 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += debug-uart-pro5.o
11 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += debug-uart-pxs2.o 10 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += debug-uart-pxs2.o
12 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += debug-uart-ld6b.o 11 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += debug-uart-ld6b.o
13 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += debug-uart-ld20.o 12 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += debug-uart-ld20.o
14 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += debug-uart-ld20.o 13 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += debug-uart-ld20.o
15 endif 14 endif
16 15
17 obj-y += debug-uart.o 16 obj-y += debug-uart.o
18 17
arch/arm/mach-uniphier/debug-uart/debug-uart-sld3.c
View file @ 00aa453
1 /* File was deleted
2 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <config.h>
8 #include <linux/kernel.h>
9 #include <linux/io.h>
10
11 #include "../bcu/bcu-regs.h"
12 #include "../sc-regs.h"
13 #include "../sg-regs.h"
14 #include "debug-uart.h"
15
16 #define UNIPHIER_SLD3_UART_CLK 36864000
17
18 unsigned int uniphier_sld3_debug_uart_init(void)
19 {
20 u32 tmp;
21
22 sg_set_pinsel(64, 1, 4, 4); /* TXD0 -> TXD0 */
23
24 writel(0x24440000, BCSCR5);
25
26 tmp = readl(SC_CLKCTRL);
27 tmp |= SC_CLKCTRL_CEN_PERI;
28 writel(tmp, SC_CLKCTRL);
29
30 return DIV_ROUND_CLOSEST(UNIPHIER_SLD3_UART_CLK, 16 * CONFIG_BAUDRATE);
31 }
32 1 /*
arch/arm/mach-uniphier/debug-uart/debug-uart.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> 2 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <debug_uart.h> 8 #include <debug_uart.h>
9 #include <linux/io.h> 9 #include <linux/io.h>
10 #include <linux/serial_reg.h> 10 #include <linux/serial_reg.h>
11 11
12 #include "../soc-info.h" 12 #include "../soc-info.h"
13 #include "debug-uart.h" 13 #include "debug-uart.h"
14 14
15 #define UNIPHIER_UART_TX 0x00 15 #define UNIPHIER_UART_TX 0x00
16 #define UNIPHIER_UART_LCR_MCR 0x10 16 #define UNIPHIER_UART_LCR_MCR 0x10
17 #define UNIPHIER_UART_LSR 0x14 17 #define UNIPHIER_UART_LSR 0x14
18 #define UNIPHIER_UART_LDR 0x24 18 #define UNIPHIER_UART_LDR 0x24
19 19
20 static void _debug_uart_putc(int c) 20 static void _debug_uart_putc(int c)
21 { 21 {
22 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; 22 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
23 23
24 while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE)) 24 while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE))
25 ; 25 ;
26 26
27 writel(c, base + UNIPHIER_UART_TX); 27 writel(c, base + UNIPHIER_UART_TX);
28 } 28 }
29 29
30 void _debug_uart_init(void) 30 void _debug_uart_init(void)
31 { 31 {
32 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; 32 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
33 unsigned int divisor; 33 unsigned int divisor;
34 34
35 switch (uniphier_get_soc_id()) { 35 switch (uniphier_get_soc_id()) {
36 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
37 case UNIPHIER_SLD3_ID:
38 divisor = uniphier_sld3_debug_uart_init();
39 break;
40 #endif
41 #if defined(CONFIG_ARCH_UNIPHIER_LD4) 36 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
42 case UNIPHIER_LD4_ID: 37 case UNIPHIER_LD4_ID:
43 divisor = uniphier_ld4_debug_uart_init(); 38 divisor = uniphier_ld4_debug_uart_init();
44 break; 39 break;
45 #endif 40 #endif
46 #if defined(CONFIG_ARCH_UNIPHIER_PRO4) 41 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
47 case UNIPHIER_PRO4_ID: 42 case UNIPHIER_PRO4_ID:
48 divisor = uniphier_pro4_debug_uart_init(); 43 divisor = uniphier_pro4_debug_uart_init();
49 break; 44 break;
50 #endif 45 #endif
51 #if defined(CONFIG_ARCH_UNIPHIER_SLD8) 46 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
52 case UNIPHIER_SLD8_ID: 47 case UNIPHIER_SLD8_ID:
53 divisor = uniphier_sld8_debug_uart_init(); 48 divisor = uniphier_sld8_debug_uart_init();
54 break; 49 break;
55 #endif 50 #endif
56 #if defined(CONFIG_ARCH_UNIPHIER_PRO5) 51 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
57 case UNIPHIER_PRO5_ID: 52 case UNIPHIER_PRO5_ID:
58 divisor = uniphier_pro5_debug_uart_init(); 53 divisor = uniphier_pro5_debug_uart_init();
59 break; 54 break;
60 #endif 55 #endif
61 #if defined(CONFIG_ARCH_UNIPHIER_PXS2) 56 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
62 case UNIPHIER_PXS2_ID: 57 case UNIPHIER_PXS2_ID:
63 divisor = uniphier_pxs2_debug_uart_init(); 58 divisor = uniphier_pxs2_debug_uart_init();
64 break; 59 break;
65 #endif 60 #endif
66 #if defined(CONFIG_ARCH_UNIPHIER_LD6B) 61 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
67 case UNIPHIER_LD6B_ID: 62 case UNIPHIER_LD6B_ID:
68 divisor = uniphier_ld6b_debug_uart_init(); 63 divisor = uniphier_ld6b_debug_uart_init();
69 break; 64 break;
70 #endif 65 #endif
71 #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) 66 #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
72 case UNIPHIER_LD11_ID: 67 case UNIPHIER_LD11_ID:
73 case UNIPHIER_LD20_ID: 68 case UNIPHIER_LD20_ID:
74 divisor = uniphier_ld20_debug_uart_init(); 69 divisor = uniphier_ld20_debug_uart_init();
75 break; 70 break;
76 #endif 71 #endif
77 default: 72 default:
78 return; 73 return;
79 } 74 }
80 75
81 writel(UART_LCR_WLEN8 << 8, base + UNIPHIER_UART_LCR_MCR); 76 writel(UART_LCR_WLEN8 << 8, base + UNIPHIER_UART_LCR_MCR);
82 77
83 writel(divisor, base + UNIPHIER_UART_LDR); 78 writel(divisor, base + UNIPHIER_UART_LDR);
84 } 79 }
85 DEBUG_UART_FUNCS 80 DEBUG_UART_FUNCS
86 81
arch/arm/mach-uniphier/debug-uart/debug-uart.h
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> 2 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef _MACH_DEBUG_UART_H 7 #ifndef _MACH_DEBUG_UART_H
8 #define _MACH_DEBUG_UART_H 8 #define _MACH_DEBUG_UART_H
9 9
10 unsigned int uniphier_sld3_debug_uart_init(void);
11 unsigned int uniphier_ld4_debug_uart_init(void); 10 unsigned int uniphier_ld4_debug_uart_init(void);
12 unsigned int uniphier_pro4_debug_uart_init(void); 11 unsigned int uniphier_pro4_debug_uart_init(void);
13 unsigned int uniphier_sld8_debug_uart_init(void); 12 unsigned int uniphier_sld8_debug_uart_init(void);
14 unsigned int uniphier_pro5_debug_uart_init(void); 13 unsigned int uniphier_pro5_debug_uart_init(void);
15 unsigned int uniphier_pxs2_debug_uart_init(void); 14 unsigned int uniphier_pxs2_debug_uart_init(void);
16 unsigned int uniphier_ld6b_debug_uart_init(void); 15 unsigned int uniphier_ld6b_debug_uart_init(void);
17 unsigned int uniphier_ld11_debug_uart_init(void); 16 unsigned int uniphier_ld11_debug_uart_init(void);
18 unsigned int uniphier_ld20_debug_uart_init(void); 17 unsigned int uniphier_ld20_debug_uart_init(void);
19 18
20 #endif /* _MACH_DEBUG_UART_H */ 19 #endif /* _MACH_DEBUG_UART_H */
21 20
arch/arm/mach-uniphier/dram/Makefile
Diff comments   View file @ 00aa453
1 # 1 #
2 # SPDX-License-Identifier: GPL-2.0+ 2 # SPDX-License-Identifier: GPL-2.0+
3 # 3 #
4 4
5 ifdef CONFIG_SPL_BUILD 5 ifdef CONFIG_SPL_BUILD
6 6
7 obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += umc-sld3.o
8 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \ 7 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \
9 ddrphy-training.o ddrphy-ld4.o 8 ddrphy-training.o ddrphy-ld4.o
10 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += umc-pro4.o \ 9 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += umc-pro4.o \
11 ddrphy-training.o ddrphy-ld4.o 10 ddrphy-training.o ddrphy-ld4.o
12 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \ 11 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \
13 ddrphy-training.o ddrphy-ld4.o 12 ddrphy-training.o ddrphy-ld4.o
14 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += umc-pro5.o 13 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += umc-pro5.o
15 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o 14 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
16 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o 15 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
17 16
18 else 17 else
19 18
20 obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o 19 obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
21 obj-$(CONFIG_CMD_DDRMPHY_DUMP) += cmd_ddrmphy.o 20 obj-$(CONFIG_CMD_DDRMPHY_DUMP) += cmd_ddrmphy.o
22 21
23 endif 22 endif
24 23
arch/arm/mach-uniphier/dram/umc-sld3.c
View file @ 00aa453
1 #include "../init.h" File was deleted
2
3 int uniphier_sld3_umc_init(const struct uniphier_board_data *bd)
4 {
5 return 0;
6 }
7 1 #include "../init.h"
arch/arm/mach-uniphier/dram_init.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2012-2015 Panasonic Corporation 2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2017 Socionext Inc. 3 * Copyright (C) 2015-2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <common.h> 9 #include <common.h>
10 #include <fdt_support.h> 10 #include <fdt_support.h>
11 #include <fdtdec.h> 11 #include <fdtdec.h>
12 #include <linux/errno.h> 12 #include <linux/errno.h>
13 #include <linux/sizes.h> 13 #include <linux/sizes.h>
14 14
15 #include "sg-regs.h" 15 #include "sg-regs.h"
16 #include "soc-info.h" 16 #include "soc-info.h"
17 17
18 #define pr_warn(fmt, args...) printf(fmt, ##args) 18 #define pr_warn(fmt, args...) printf(fmt, ##args)
19 #define pr_err(fmt, args...) printf(fmt, ##args) 19 #define pr_err(fmt, args...) printf(fmt, ##args)
20 20
21 DECLARE_GLOBAL_DATA_PTR; 21 DECLARE_GLOBAL_DATA_PTR;
22 22
23 struct uniphier_memif_data { 23 struct uniphier_memif_data {
24 unsigned int soc_id; 24 unsigned int soc_id;
25 unsigned long sparse_ch1_base; 25 unsigned long sparse_ch1_base;
26 int have_ch2; 26 int have_ch2;
27 }; 27 };
28 28
29 static const struct uniphier_memif_data uniphier_memif_data[] = { 29 static const struct uniphier_memif_data uniphier_memif_data[] = {
30 { 30 {
31 .soc_id = UNIPHIER_SLD3_ID,
32 .sparse_ch1_base = 0xc0000000,
33 /*
34 * In fact, SLD3 has DRAM ch2, but the memory regions for ch1
35 * and ch2 overlap, and host cannot get access to them at the
36 * same time. Hide the ch2 from U-Boot.
37 */
38 },
39 {
40 .soc_id = UNIPHIER_LD4_ID, 31 .soc_id = UNIPHIER_LD4_ID,
41 .sparse_ch1_base = 0xc0000000, 32 .sparse_ch1_base = 0xc0000000,
42 }, 33 },
43 { 34 {
44 .soc_id = UNIPHIER_PRO4_ID, 35 .soc_id = UNIPHIER_PRO4_ID,
45 .sparse_ch1_base = 0xa0000000, 36 .sparse_ch1_base = 0xa0000000,
46 }, 37 },
47 { 38 {
48 .soc_id = UNIPHIER_SLD8_ID, 39 .soc_id = UNIPHIER_SLD8_ID,
49 .sparse_ch1_base = 0xc0000000, 40 .sparse_ch1_base = 0xc0000000,
50 }, 41 },
51 { 42 {
52 .soc_id = UNIPHIER_PRO5_ID, 43 .soc_id = UNIPHIER_PRO5_ID,
53 .sparse_ch1_base = 0xc0000000, 44 .sparse_ch1_base = 0xc0000000,
54 }, 45 },
55 { 46 {
56 .soc_id = UNIPHIER_PXS2_ID, 47 .soc_id = UNIPHIER_PXS2_ID,
57 .sparse_ch1_base = 0xc0000000, 48 .sparse_ch1_base = 0xc0000000,
58 .have_ch2 = 1, 49 .have_ch2 = 1,
59 }, 50 },
60 { 51 {
61 .soc_id = UNIPHIER_LD6B_ID, 52 .soc_id = UNIPHIER_LD6B_ID,
62 .sparse_ch1_base = 0xc0000000, 53 .sparse_ch1_base = 0xc0000000,
63 .have_ch2 = 1, 54 .have_ch2 = 1,
64 }, 55 },
65 { 56 {
66 .soc_id = UNIPHIER_LD11_ID, 57 .soc_id = UNIPHIER_LD11_ID,
67 .sparse_ch1_base = 0xc0000000, 58 .sparse_ch1_base = 0xc0000000,
68 }, 59 },
69 { 60 {
70 .soc_id = UNIPHIER_LD20_ID, 61 .soc_id = UNIPHIER_LD20_ID,
71 .sparse_ch1_base = 0xc0000000, 62 .sparse_ch1_base = 0xc0000000,
72 .have_ch2 = 1, 63 .have_ch2 = 1,
73 }, 64 },
74 { 65 {
75 .soc_id = UNIPHIER_PXS3_ID, 66 .soc_id = UNIPHIER_PXS3_ID,
76 .sparse_ch1_base = 0xc0000000, 67 .sparse_ch1_base = 0xc0000000,
77 .have_ch2 = 1, 68 .have_ch2 = 1,
78 }, 69 },
79 }; 70 };
80 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data) 71 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data)
81 72
82 struct uniphier_dram_map { 73 struct uniphier_dram_map {
83 unsigned long base; 74 unsigned long base;
84 unsigned long size; 75 unsigned long size;
85 }; 76 };
86 77
87 static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) 78 static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map)
88 { 79 {
89 const struct uniphier_memif_data *data; 80 const struct uniphier_memif_data *data;
90 unsigned long size; 81 unsigned long size;
91 u32 val; 82 u32 val;
92 83
93 data = uniphier_get_memif_data(); 84 data = uniphier_get_memif_data();
94 if (!data) { 85 if (!data) {
95 pr_err("unsupported SoC\n"); 86 pr_err("unsupported SoC\n");
96 return -EINVAL; 87 return -EINVAL;
97 } 88 }
98 89
99 val = readl(SG_MEMCONF); 90 val = readl(SG_MEMCONF);
100 91
101 /* set up ch0 */ 92 /* set up ch0 */
102 dram_map[0].base = CONFIG_SYS_SDRAM_BASE; 93 dram_map[0].base = CONFIG_SYS_SDRAM_BASE;
103 94
104 switch (val & SG_MEMCONF_CH0_SZ_MASK) { 95 switch (val & SG_MEMCONF_CH0_SZ_MASK) {
105 case SG_MEMCONF_CH0_SZ_64M: 96 case SG_MEMCONF_CH0_SZ_64M:
106 size = SZ_64M; 97 size = SZ_64M;
107 break; 98 break;
108 case SG_MEMCONF_CH0_SZ_128M: 99 case SG_MEMCONF_CH0_SZ_128M:
109 size = SZ_128M; 100 size = SZ_128M;
110 break; 101 break;
111 case SG_MEMCONF_CH0_SZ_256M: 102 case SG_MEMCONF_CH0_SZ_256M:
112 size = SZ_256M; 103 size = SZ_256M;
113 break; 104 break;
114 case SG_MEMCONF_CH0_SZ_512M: 105 case SG_MEMCONF_CH0_SZ_512M:
115 size = SZ_512M; 106 size = SZ_512M;
116 break; 107 break;
117 case SG_MEMCONF_CH0_SZ_1G: 108 case SG_MEMCONF_CH0_SZ_1G:
118 size = SZ_1G; 109 size = SZ_1G;
119 break; 110 break;
120 default: 111 default:
121 pr_err("error: invalid value is set to MEMCONF ch0 size\n"); 112 pr_err("error: invalid value is set to MEMCONF ch0 size\n");
122 return -EINVAL; 113 return -EINVAL;
123 } 114 }
124 115
125 if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2) 116 if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2)
126 size *= 2; 117 size *= 2;
127 118
128 dram_map[0].size = size; 119 dram_map[0].size = size;
129 120
130 /* set up ch1 */ 121 /* set up ch1 */
131 dram_map[1].base = dram_map[0].base + size; 122 dram_map[1].base = dram_map[0].base + size;
132 123
133 if (val & SG_MEMCONF_SPARSEMEM) { 124 if (val & SG_MEMCONF_SPARSEMEM) {
134 if (dram_map[1].base > data->sparse_ch1_base) { 125 if (dram_map[1].base > data->sparse_ch1_base) {
135 pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n"); 126 pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
136 pr_warn("Only ch0 is available\n"); 127 pr_warn("Only ch0 is available\n");
137 dram_map[1].base = 0; 128 dram_map[1].base = 0;
138 return 0; 129 return 0;
139 } 130 }
140 131
141 dram_map[1].base = data->sparse_ch1_base; 132 dram_map[1].base = data->sparse_ch1_base;
142 } 133 }
143 134
144 switch (val & SG_MEMCONF_CH1_SZ_MASK) { 135 switch (val & SG_MEMCONF_CH1_SZ_MASK) {
145 case SG_MEMCONF_CH1_SZ_64M: 136 case SG_MEMCONF_CH1_SZ_64M:
146 size = SZ_64M; 137 size = SZ_64M;
147 break; 138 break;
148 case SG_MEMCONF_CH1_SZ_128M: 139 case SG_MEMCONF_CH1_SZ_128M:
149 size = SZ_128M; 140 size = SZ_128M;
150 break; 141 break;
151 case SG_MEMCONF_CH1_SZ_256M: 142 case SG_MEMCONF_CH1_SZ_256M:
152 size = SZ_256M; 143 size = SZ_256M;
153 break; 144 break;
154 case SG_MEMCONF_CH1_SZ_512M: 145 case SG_MEMCONF_CH1_SZ_512M:
155 size = SZ_512M; 146 size = SZ_512M;
156 break; 147 break;
157 case SG_MEMCONF_CH1_SZ_1G: 148 case SG_MEMCONF_CH1_SZ_1G:
158 size = SZ_1G; 149 size = SZ_1G;
159 break; 150 break;
160 default: 151 default:
161 pr_err("error: invalid value is set to MEMCONF ch1 size\n"); 152 pr_err("error: invalid value is set to MEMCONF ch1 size\n");
162 return -EINVAL; 153 return -EINVAL;
163 } 154 }
164 155
165 if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2) 156 if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2)
166 size *= 2; 157 size *= 2;
167 158
168 dram_map[1].size = size; 159 dram_map[1].size = size;
169 160
170 if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE) 161 if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE)
171 return 0; 162 return 0;
172 163
173 /* set up ch2 */ 164 /* set up ch2 */
174 dram_map[2].base = dram_map[1].base + size; 165 dram_map[2].base = dram_map[1].base + size;
175 166
176 switch (val & SG_MEMCONF_CH2_SZ_MASK) { 167 switch (val & SG_MEMCONF_CH2_SZ_MASK) {
177 case SG_MEMCONF_CH2_SZ_64M: 168 case SG_MEMCONF_CH2_SZ_64M:
178 size = SZ_64M; 169 size = SZ_64M;
179 break; 170 break;
180 case SG_MEMCONF_CH2_SZ_128M: 171 case SG_MEMCONF_CH2_SZ_128M:
181 size = SZ_128M; 172 size = SZ_128M;
182 break; 173 break;
183 case SG_MEMCONF_CH2_SZ_256M: 174 case SG_MEMCONF_CH2_SZ_256M:
184 size = SZ_256M; 175 size = SZ_256M;
185 break; 176 break;
186 case SG_MEMCONF_CH2_SZ_512M: 177 case SG_MEMCONF_CH2_SZ_512M:
187 size = SZ_512M; 178 size = SZ_512M;
188 break; 179 break;
189 case SG_MEMCONF_CH2_SZ_1G: 180 case SG_MEMCONF_CH2_SZ_1G:
190 size = SZ_1G; 181 size = SZ_1G;
191 break; 182 break;
192 default: 183 default:
193 pr_err("error: invalid value is set to MEMCONF ch2 size\n"); 184 pr_err("error: invalid value is set to MEMCONF ch2 size\n");
194 return -EINVAL; 185 return -EINVAL;
195 } 186 }
196 187
197 if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2) 188 if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2)
198 size *= 2; 189 size *= 2;
199 190
200 dram_map[2].size = size; 191 dram_map[2].size = size;
201 192
202 return 0; 193 return 0;
203 } 194 }
204 195
205 int dram_init(void) 196 int dram_init(void)
206 { 197 {
207 struct uniphier_dram_map dram_map[3] = {}; 198 struct uniphier_dram_map dram_map[3] = {};
208 int ret, i; 199 int ret, i;
209 200
210 gd->ram_size = 0; 201 gd->ram_size = 0;
211 202
212 ret = uniphier_memconf_decode(dram_map); 203 ret = uniphier_memconf_decode(dram_map);
213 if (ret) 204 if (ret)
214 return ret; 205 return ret;
215 206
216 for (i = 0; i < ARRAY_SIZE(dram_map); i++) { 207 for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
217 208
218 if (!dram_map[i].size) 209 if (!dram_map[i].size)
219 break; 210 break;
220 211
221 /* 212 /*
222 * U-Boot relocates itself to the tail of the memory region, 213 * U-Boot relocates itself to the tail of the memory region,
223 * but it does not expect sparse memory. We use the first 214 * but it does not expect sparse memory. We use the first
224 * contiguous chunk here. 215 * contiguous chunk here.
225 */ 216 */
226 if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size < 217 if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size <
227 dram_map[i].base) 218 dram_map[i].base)
228 break; 219 break;
229 220
230 gd->ram_size += dram_map[i].size; 221 gd->ram_size += dram_map[i].size;
231 } 222 }
232 223
233 return 0; 224 return 0;
234 } 225 }
235 226
236 int dram_init_banksize(void) 227 int dram_init_banksize(void)
237 { 228 {
238 struct uniphier_dram_map dram_map[3] = {}; 229 struct uniphier_dram_map dram_map[3] = {};
239 int i; 230 int i;
240 231
241 uniphier_memconf_decode(dram_map); 232 uniphier_memconf_decode(dram_map);
242 233
243 for (i = 0; i < ARRAY_SIZE(dram_map); i++) { 234 for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
244 if (i >= ARRAY_SIZE(gd->bd->bi_dram)) 235 if (i >= ARRAY_SIZE(gd->bd->bi_dram))
245 break; 236 break;
246 237
247 gd->bd->bi_dram[i].start = dram_map[i].base; 238 gd->bd->bi_dram[i].start = dram_map[i].base;
248 gd->bd->bi_dram[i].size = dram_map[i].size; 239 gd->bd->bi_dram[i].size = dram_map[i].size;
249 } 240 }
250 241
251 return 0; 242 return 0;
252 } 243 }
253 244
254 #ifdef CONFIG_OF_BOARD_SETUP 245 #ifdef CONFIG_OF_BOARD_SETUP
255 /* 246 /*
256 * The DRAM PHY requires 64 byte scratch area in each DRAM channel 247 * The DRAM PHY requires 64 byte scratch area in each DRAM channel
257 * for its dynamic PHY training feature. 248 * for its dynamic PHY training feature.
258 */ 249 */
259 int ft_board_setup(void *fdt, bd_t *bd) 250 int ft_board_setup(void *fdt, bd_t *bd)
260 { 251 {
261 unsigned long rsv_addr; 252 unsigned long rsv_addr;
262 const unsigned long rsv_size = 64; 253 const unsigned long rsv_size = 64;
263 int i, ret; 254 int i, ret;
264 255
265 if (uniphier_get_soc_id() != UNIPHIER_LD20_ID) 256 if (uniphier_get_soc_id() != UNIPHIER_LD20_ID)
266 return 0; 257 return 0;
267 258
268 for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { 259 for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
269 if (!gd->bd->bi_dram[i].size) 260 if (!gd->bd->bi_dram[i].size)
270 continue; 261 continue;
271 262
272 rsv_addr = gd->bd->bi_dram[i].start + gd->bd->bi_dram[i].size; 263 rsv_addr = gd->bd->bi_dram[i].start + gd->bd->bi_dram[i].size;
273 rsv_addr -= rsv_size; 264 rsv_addr -= rsv_size;
274 265
275 ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size); 266 ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
276 if (ret) 267 if (ret)
277 return -ENOSPC; 268 return -ENOSPC;
278 269
279 printf(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n", 270 printf(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n",
280 rsv_addr, rsv_size); 271 rsv_addr, rsv_size);
281 } 272 }
282 273
283 return 0; 274 return 0;
284 } 275 }
285 #endif 276 #endif
286 277
arch/arm/mach-uniphier/init.h
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2015-2016 Socionext Inc. 2 * Copyright (C) 2015-2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef __MACH_INIT_H 8 #ifndef __MACH_INIT_H
9 #define __MACH_INIT_H 9 #define __MACH_INIT_H
10 10
11 #include <linux/types.h> 11 #include <linux/types.h>
12 12
13 #define UNIPHIER_MAX_NR_DRAM_CH 3 13 #define UNIPHIER_MAX_NR_DRAM_CH 3
14 14
15 struct uniphier_dram_ch { 15 struct uniphier_dram_ch {
16 unsigned long size; 16 unsigned long size;
17 unsigned int width; 17 unsigned int width;
18 }; 18 };
19 19
20 struct uniphier_board_data { 20 struct uniphier_board_data {
21 unsigned int dram_freq; 21 unsigned int dram_freq;
22 struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH]; 22 struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
23 unsigned int flags; 23 unsigned int flags;
24 24
25 #define UNIPHIER_BD_DRAM_SPARSE BIT(9) 25 #define UNIPHIER_BD_DRAM_SPARSE BIT(9)
26 #define UNIPHIER_BD_DDR3PLUS BIT(8) 26 #define UNIPHIER_BD_DDR3PLUS BIT(8)
27 }; 27 };
28 28
29 const struct uniphier_board_data *uniphier_get_board_param(void); 29 const struct uniphier_board_data *uniphier_get_board_param(void);
30 30
31 int uniphier_sld3_init(const struct uniphier_board_data *bd);
32 int uniphier_ld4_init(const struct uniphier_board_data *bd); 31 int uniphier_ld4_init(const struct uniphier_board_data *bd);
33 int uniphier_pro4_init(const struct uniphier_board_data *bd); 32 int uniphier_pro4_init(const struct uniphier_board_data *bd);
34 int uniphier_sld8_init(const struct uniphier_board_data *bd); 33 int uniphier_sld8_init(const struct uniphier_board_data *bd);
35 int uniphier_pro5_init(const struct uniphier_board_data *bd); 34 int uniphier_pro5_init(const struct uniphier_board_data *bd);
36 int uniphier_pxs2_init(const struct uniphier_board_data *bd); 35 int uniphier_pxs2_init(const struct uniphier_board_data *bd);
37 36
38 #if defined(CONFIG_MICRO_SUPPORT_CARD) 37 #if defined(CONFIG_MICRO_SUPPORT_CARD)
39 void uniphier_sbc_init_admulti(void); 38 void uniphier_sbc_init_admulti(void);
40 void uniphier_sbc_init_savepin(void); 39 void uniphier_sbc_init_savepin(void);
41 void uniphier_ld4_sbc_init(void); 40 void uniphier_ld4_sbc_init(void);
42 void uniphier_pxs2_sbc_init(void); 41 void uniphier_pxs2_sbc_init(void);
43 void uniphier_ld11_sbc_init(void); 42 void uniphier_ld11_sbc_init(void);
44 #else 43 #else
45 static inline void uniphier_sbc_init_admulti(void) 44 static inline void uniphier_sbc_init_admulti(void)
46 { 45 {
47 } 46 }
48 47
49 static inline void uniphier_sbc_init_savepin(void) 48 static inline void uniphier_sbc_init_savepin(void)
50 { 49 {
51 } 50 }
52 51
53 static inline void uniphier_ld4_sbc_init(void) 52 static inline void uniphier_ld4_sbc_init(void)
54 { 53 {
55 } 54 }
56 55
57 static inline void uniphier_pxs2_sbc_init(void) 56 static inline void uniphier_pxs2_sbc_init(void)
58 { 57 {
59 } 58 }
60 59
61 static inline void uniphier_ld11_sbc_init(void) 60 static inline void uniphier_ld11_sbc_init(void)
62 { 61 {
63 } 62 }
64 #endif 63 #endif
65 64
66 void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd);
67 void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd); 65 void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd);
68 66
69 int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd); 67 int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd);
70 int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd);
71 int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd); 68 int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd);
72 69
73 int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd);
74 int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd); 70 int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd);
75 int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd); 71 int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd);
76 int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd); 72 int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd);
77 int uniphier_pro5_dpll_init(const struct uniphier_board_data *bd); 73 int uniphier_pro5_dpll_init(const struct uniphier_board_data *bd);
78 int uniphier_pxs2_dpll_init(const struct uniphier_board_data *bd); 74 int uniphier_pxs2_dpll_init(const struct uniphier_board_data *bd);
79 75
80 void uniphier_sld3_early_clk_init(void); 76 void uniphier_ld4_early_clk_init(void);
81 77
82 void uniphier_sld3_dram_clk_init(void); 78 void uniphier_ld4_dram_clk_init(void);
83 void uniphier_pro5_dram_clk_init(void); 79 void uniphier_pro5_dram_clk_init(void);
84 void uniphier_pxs2_dram_clk_init(void); 80 void uniphier_pxs2_dram_clk_init(void);
85 81
86 int uniphier_sld3_umc_init(const struct uniphier_board_data *bd);
87 int uniphier_ld4_umc_init(const struct uniphier_board_data *bd); 82 int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
88 int uniphier_pro4_umc_init(const struct uniphier_board_data *bd); 83 int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
89 int uniphier_sld8_umc_init(const struct uniphier_board_data *bd); 84 int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
90 int uniphier_pro5_umc_init(const struct uniphier_board_data *bd); 85 int uniphier_pro5_umc_init(const struct uniphier_board_data *bd);
91 int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd); 86 int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
92 87
93 void uniphier_sld3_pll_init(void);
94 void uniphier_ld4_pll_init(void); 88 void uniphier_ld4_pll_init(void);
95 void uniphier_pro4_pll_init(void); 89 void uniphier_pro4_pll_init(void);
96 void uniphier_ld11_pll_init(void); 90 void uniphier_ld11_pll_init(void);
97 void uniphier_ld20_pll_init(void); 91 void uniphier_ld20_pll_init(void);
98 void uniphier_pxs3_pll_init(void); 92 void uniphier_pxs3_pll_init(void);
99 93
100 void uniphier_ld4_clk_init(void); 94 void uniphier_ld4_clk_init(void);
101 void uniphier_pro4_clk_init(void); 95 void uniphier_pro4_clk_init(void);
102 void uniphier_pro5_clk_init(void); 96 void uniphier_pro5_clk_init(void);
103 void uniphier_pxs2_clk_init(void); 97 void uniphier_pxs2_clk_init(void);
104 void uniphier_ld11_clk_init(void); 98 void uniphier_ld11_clk_init(void);
105 void uniphier_ld20_clk_init(void); 99 void uniphier_ld20_clk_init(void);
106 void uniphier_pxs3_clk_init(void); 100 void uniphier_pxs3_clk_init(void);
107 101
108 unsigned int uniphier_boot_device_raw(void); 102 unsigned int uniphier_boot_device_raw(void);
109 int uniphier_have_internal_stm(void); 103 int uniphier_have_internal_stm(void);
110 int uniphier_boot_from_backend(void); 104 int uniphier_boot_from_backend(void);
111 int uniphier_pin_init(const char *pinconfig_name); 105 int uniphier_pin_init(const char *pinconfig_name);
112 106
113 #undef pr_warn 107 #undef pr_warn
114 #define pr_warn(fmt, args...) printf(fmt, ##args) 108 #define pr_warn(fmt, args...) printf(fmt, ##args)
115 #undef pr_err 109 #undef pr_err
116 #define pr_err(fmt, args...) printf(fmt, ##args) 110 #define pr_err(fmt, args...) printf(fmt, ##args)
117 111
118 #endif /* __MACH_INIT_H */ 112 #endif /* __MACH_INIT_H */
119 113
arch/arm/mach-uniphier/memconf.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2011-2015 Panasonic Corporation 2 * Copyright (C) 2011-2015 Panasonic Corporation
3 * Copyright (C) 2016 Socionext Inc. 3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <common.h> 9 #include <common.h>
10 #include <linux/errno.h> 10 #include <linux/errno.h>
11 #include <linux/io.h> 11 #include <linux/io.h>
12 #include <linux/sizes.h> 12 #include <linux/sizes.h>
13 13
14 #include "sg-regs.h" 14 #include "sg-regs.h"
15 #include "init.h" 15 #include "init.h"
16 16
17 static int __uniphier_memconf_init(const struct uniphier_board_data *bd, 17 static int __uniphier_memconf_init(const struct uniphier_board_data *bd,
18 int have_ch2, int have_ch2_disable_bit) 18 int have_ch2)
19 { 19 {
20 u32 val = 0; 20 u32 val = 0;
21 unsigned long size_per_word; 21 unsigned long size_per_word;
22 22
23 /* set up ch0 */ 23 /* set up ch0 */
24 switch (bd->dram_ch[0].width) { 24 switch (bd->dram_ch[0].width) {
25 case 16: 25 case 16:
26 val |= SG_MEMCONF_CH0_NUM_1; 26 val |= SG_MEMCONF_CH0_NUM_1;
27 size_per_word = bd->dram_ch[0].size; 27 size_per_word = bd->dram_ch[0].size;
28 break; 28 break;
29 case 32: 29 case 32:
30 val |= SG_MEMCONF_CH0_NUM_2; 30 val |= SG_MEMCONF_CH0_NUM_2;
31 size_per_word = bd->dram_ch[0].size >> 1; 31 size_per_word = bd->dram_ch[0].size >> 1;
32 break; 32 break;
33 default: 33 default:
34 pr_err("error: unsupported DRAM ch0 width\n"); 34 pr_err("error: unsupported DRAM ch0 width\n");
35 return -EINVAL; 35 return -EINVAL;
36 } 36 }
37 37
38 switch (size_per_word) { 38 switch (size_per_word) {
39 case SZ_64M: 39 case SZ_64M:
40 val |= SG_MEMCONF_CH0_SZ_64M; 40 val |= SG_MEMCONF_CH0_SZ_64M;
41 break; 41 break;
42 case SZ_128M: 42 case SZ_128M:
43 val |= SG_MEMCONF_CH0_SZ_128M; 43 val |= SG_MEMCONF_CH0_SZ_128M;
44 break; 44 break;
45 case SZ_256M: 45 case SZ_256M:
46 val |= SG_MEMCONF_CH0_SZ_256M; 46 val |= SG_MEMCONF_CH0_SZ_256M;
47 break; 47 break;
48 case SZ_512M: 48 case SZ_512M:
49 val |= SG_MEMCONF_CH0_SZ_512M; 49 val |= SG_MEMCONF_CH0_SZ_512M;
50 break; 50 break;
51 case SZ_1G: 51 case SZ_1G:
52 val |= SG_MEMCONF_CH0_SZ_1G; 52 val |= SG_MEMCONF_CH0_SZ_1G;
53 break; 53 break;
54 default: 54 default:
55 pr_err("error: unsupported DRAM ch0 size\n"); 55 pr_err("error: unsupported DRAM ch0 size\n");
56 return -EINVAL; 56 return -EINVAL;
57 } 57 }
58 58
59 /* set up ch1 */ 59 /* set up ch1 */
60 switch (bd->dram_ch[1].width) { 60 switch (bd->dram_ch[1].width) {
61 case 16: 61 case 16:
62 val |= SG_MEMCONF_CH1_NUM_1; 62 val |= SG_MEMCONF_CH1_NUM_1;
63 size_per_word = bd->dram_ch[1].size; 63 size_per_word = bd->dram_ch[1].size;
64 break; 64 break;
65 case 32: 65 case 32:
66 val |= SG_MEMCONF_CH1_NUM_2; 66 val |= SG_MEMCONF_CH1_NUM_2;
67 size_per_word = bd->dram_ch[1].size >> 1; 67 size_per_word = bd->dram_ch[1].size >> 1;
68 break; 68 break;
69 default: 69 default:
70 pr_err("error: unsupported DRAM ch1 width\n"); 70 pr_err("error: unsupported DRAM ch1 width\n");
71 return -EINVAL; 71 return -EINVAL;
72 } 72 }
73 73
74 switch (size_per_word) { 74 switch (size_per_word) {
75 case SZ_64M: 75 case SZ_64M:
76 val |= SG_MEMCONF_CH1_SZ_64M; 76 val |= SG_MEMCONF_CH1_SZ_64M;
77 break; 77 break;
78 case SZ_128M: 78 case SZ_128M:
79 val |= SG_MEMCONF_CH1_SZ_128M; 79 val |= SG_MEMCONF_CH1_SZ_128M;
80 break; 80 break;
81 case SZ_256M: 81 case SZ_256M:
82 val |= SG_MEMCONF_CH1_SZ_256M; 82 val |= SG_MEMCONF_CH1_SZ_256M;
83 break; 83 break;
84 case SZ_512M: 84 case SZ_512M:
85 val |= SG_MEMCONF_CH1_SZ_512M; 85 val |= SG_MEMCONF_CH1_SZ_512M;
86 break; 86 break;
87 case SZ_1G: 87 case SZ_1G:
88 val |= SG_MEMCONF_CH1_SZ_1G; 88 val |= SG_MEMCONF_CH1_SZ_1G;
89 break; 89 break;
90 default: 90 default:
91 pr_err("error: unsupported DRAM ch1 size\n"); 91 pr_err("error: unsupported DRAM ch1 size\n");
92 return -EINVAL; 92 return -EINVAL;
93 } 93 }
94 94
95 /* is sparse mem? */ 95 /* is sparse mem? */
96 if (bd->flags & UNIPHIER_BD_DRAM_SPARSE) 96 if (bd->flags & UNIPHIER_BD_DRAM_SPARSE)
97 val |= SG_MEMCONF_SPARSEMEM; 97 val |= SG_MEMCONF_SPARSEMEM;
98 98
99 if (!have_ch2) 99 if (!have_ch2)
100 goto out; 100 goto out;
101 101
102 if (!bd->dram_ch[2].size) { 102 if (!bd->dram_ch[2].size) {
103 if (have_ch2_disable_bit) 103 val |= SG_MEMCONF_CH2_DISABLE;
104 val |= SG_MEMCONF_CH2_DISABLE;
105 goto out; 104 goto out;
106 } 105 }
107 106
108 /* set up ch2 */ 107 /* set up ch2 */
109 switch (bd->dram_ch[2].width) { 108 switch (bd->dram_ch[2].width) {
110 case 16: 109 case 16:
111 val |= SG_MEMCONF_CH2_NUM_1; 110 val |= SG_MEMCONF_CH2_NUM_1;
112 size_per_word = bd->dram_ch[2].size; 111 size_per_word = bd->dram_ch[2].size;
113 break; 112 break;
114 case 32: 113 case 32:
115 val |= SG_MEMCONF_CH2_NUM_2; 114 val |= SG_MEMCONF_CH2_NUM_2;
116 size_per_word = bd->dram_ch[2].size >> 1; 115 size_per_word = bd->dram_ch[2].size >> 1;
117 break; 116 break;
118 default: 117 default:
119 pr_err("error: unsupported DRAM ch2 width\n"); 118 pr_err("error: unsupported DRAM ch2 width\n");
120 return -EINVAL; 119 return -EINVAL;
121 } 120 }
122 121
123 switch (size_per_word) { 122 switch (size_per_word) {
124 case SZ_64M: 123 case SZ_64M:
125 val |= SG_MEMCONF_CH2_SZ_64M; 124 val |= SG_MEMCONF_CH2_SZ_64M;
126 break; 125 break;
127 case SZ_128M: 126 case SZ_128M:
128 val |= SG_MEMCONF_CH2_SZ_128M; 127 val |= SG_MEMCONF_CH2_SZ_128M;
129 break; 128 break;
130 case SZ_256M: 129 case SZ_256M:
131 val |= SG_MEMCONF_CH2_SZ_256M; 130 val |= SG_MEMCONF_CH2_SZ_256M;
132 break; 131 break;
133 case SZ_512M: 132 case SZ_512M:
134 val |= SG_MEMCONF_CH2_SZ_512M; 133 val |= SG_MEMCONF_CH2_SZ_512M;
135 break; 134 break;
136 case SZ_1G: 135 case SZ_1G:
137 val |= SG_MEMCONF_CH2_SZ_1G; 136 val |= SG_MEMCONF_CH2_SZ_1G;
138 break; 137 break;
139 default: 138 default:
140 pr_err("error: unsupported DRAM ch2 size\n"); 139 pr_err("error: unsupported DRAM ch2 size\n");
141 return -EINVAL; 140 return -EINVAL;
142 } 141 }
143 142
144 out: 143 out:
145 writel(val, SG_MEMCONF); 144 writel(val, SG_MEMCONF);
146 145
147 return 0; 146 return 0;
148 } 147 }
149 148
150 int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd) 149 int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd)
151 { 150 {
152 return __uniphier_memconf_init(bd, 0, 0); 151 return __uniphier_memconf_init(bd, 0);
153 } 152 }
154 153
155 int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd)
156 {
157 return __uniphier_memconf_init(bd, 1, 0);
158 }
159
160 int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd) 154 int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd)
161 { 155 {
162 return __uniphier_memconf_init(bd, 1, 1); 156 return __uniphier_memconf_init(bd, 1);
163 } 157 }
164 158
arch/arm/mach-uniphier/mmc-boot-mode.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2016 Socionext Inc. 2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <mmc.h> 9 #include <mmc.h>
10 #include <spl.h> 10 #include <spl.h>
11 11
12 u32 spl_boot_mode(const u32 boot_device) 12 u32 spl_boot_mode(const u32 boot_device)
13 { 13 {
14 struct mmc *mmc; 14 struct mmc *mmc;
15 15
16 /* 16 /*
17 * work around a bug in the Boot ROM of PH1-sLD3, LD4, Pro4, and sLD8: 17 * work around a bug in the Boot ROM of LD4, Pro4, and sLD8:
18 * 18 *
19 * The boot ROM in these SoCs breaks the PARTITION_CONFIG [179] of 19 * The boot ROM in these SoCs breaks the PARTITION_CONFIG [179] of
20 * Extended CSD register; when switching to the Boot Partition 1, the 20 * Extended CSD register; when switching to the Boot Partition 1, the
21 * Boot ROM should issue the SWITCH command (CMD6) with Set Bits for 21 * Boot ROM should issue the SWITCH command (CMD6) with Set Bits for
22 * the Access Bits, but in fact it uses Write Byte for the Access Bits. 22 * the Access Bits, but in fact it uses Write Byte for the Access Bits.
23 * As a result, the BOOT_PARTITION_ENABLE field of the PARTITION_CONFIG 23 * As a result, the BOOT_PARTITION_ENABLE field of the PARTITION_CONFIG
24 * is lost. This bug was fixed for PH1-Pro5 and later SoCs. 24 * is lost. This bug was fixed for PH1-Pro5 and later SoCs.
25 * 25 *
26 * Fixup mmc->part_config here because it is used to determine the 26 * Fixup mmc->part_config here because it is used to determine the
27 * partition which the U-Boot image is read from. 27 * partition which the U-Boot image is read from.
28 */ 28 */
29 mmc = find_mmc_device(0); 29 mmc = find_mmc_device(0);
30 mmc->part_config &= ~EXT_CSD_BOOT_PART_NUM(PART_ACCESS_MASK); 30 mmc->part_config &= ~EXT_CSD_BOOT_PART_NUM(PART_ACCESS_MASK);
31 mmc->part_config |= EXT_CSD_BOOT_PARTITION_ENABLE; 31 mmc->part_config |= EXT_CSD_BOOT_PARTITION_ENABLE;
32 32
33 return MMCSD_MODE_EMMCBOOT; 33 return MMCSD_MODE_EMMCBOOT;
34 } 34 }
35 35
arch/arm/mach-uniphier/sc-regs.h
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * UniPhier SC (System Control) block registers 2 * UniPhier SC (System Control) block registers
3 * 3 *
4 * Copyright (C) 2011-2015 Panasonic Corporation 4 * Copyright (C) 2011-2015 Panasonic Corporation
5 * Copyright (C) 2015-2016 Socionext Inc. 5 * Copyright (C) 2015-2016 Socionext Inc.
6 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #ifndef ARCH_SC_REGS_H 11 #ifndef ARCH_SC_REGS_H
12 #define ARCH_SC_REGS_H 12 #define ARCH_SC_REGS_H
13 13
14 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
15 #define SC_BASE_ADDR 0xf1840000
16 #else
17 #define SC_BASE_ADDR 0x61840000 14 #define SC_BASE_ADDR 0x61840000
18 #endif
19 15
20 #define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110) 16 #define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110)
21 #define SC_DPLLOSCCTRL_DPLLST (0x1 << 1) 17 #define SC_DPLLOSCCTRL_DPLLST (0x1 << 1)
22 #define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0) 18 #define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0)
23 19
24 #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) 20 #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
25 #define SC_DPLLCTRL_SSC_EN (0x1 << 31) 21 #define SC_DPLLCTRL_SSC_EN (0x1 << 31)
26 #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) 22 #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
27 #define SC_DPLLCTRL_SSC_RATE (0x1 << 15) 23 #define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
28 24
29 #define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204) 25 #define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
30 #define SC_DPLLCTRL2_NRSTDS (0x1 << 28) 26 #define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
31 27
32 #define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208) 28 #define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
33 #define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31) 29 #define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
34 #define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31) 30 #define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
35 31
36 #define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210) 32 #define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
37 33
38 #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270) 34 #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
39 #define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274) 35 #define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
40 #define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278) 36 #define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
41 37
42 #define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290) 38 #define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
43 #define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294) 39 #define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
44 #define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298) 40 #define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
45 41
46 #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) 42 #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
47 #define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */ 43 #define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */
48 #define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */ 44 #define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */
49 #define SC_RSTCTRL_NRST_ETHER (0x1 << 12) 45 #define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
50 #define SC_RSTCTRL_NRST_STDMAC (0x1 << 10) 46 #define SC_RSTCTRL_NRST_STDMAC (0x1 << 10)
51 #define SC_RSTCTRL_NRST_GIO (0x1 << 6) 47 #define SC_RSTCTRL_NRST_GIO (0x1 << 6)
52 /* Pro4 or older */ 48 /* Pro4 or older */
53 #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) 49 #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
54 #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) 50 #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
55 #define SC_RSTCTRL_NRST_NAND (0x1 << 2) 51 #define SC_RSTCTRL_NRST_NAND (0x1 << 2)
56 52
57 #define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004) 53 #define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
58 #define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */ 54 #define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */
59 #define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */ 55 #define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */
60 56
61 #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) 57 #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
62 58
63 /* Pro5 or newer */ 59 /* Pro5 or newer */
64 #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) 60 #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
65 #define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */ 61 #define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */
66 #define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */ 62 #define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */
67 #define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */ 63 #define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */
68 #define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */ 64 #define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */
69 #define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */ 65 #define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */
70 #define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */ 66 #define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */
71 #define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */ 67 #define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */
72 68
73 #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) 69 #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
74 70
75 #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) 71 #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
76 72
77 #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) 73 #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
78 #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ 74 #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
79 #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */ 75 #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
80 #define SC_CLKCTRL_CEN_ETHER (0x1 << 12) 76 #define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
81 #define SC_CLKCTRL_CEN_MIO (0x1 << 11) 77 #define SC_CLKCTRL_CEN_MIO (0x1 << 11)
82 #define SC_CLKCTRL_CEN_STDMAC (0x1 << 10) 78 #define SC_CLKCTRL_CEN_STDMAC (0x1 << 10)
83 #define SC_CLKCTRL_CEN_GIO (0x1 << 6) 79 #define SC_CLKCTRL_CEN_GIO (0x1 << 6)
84 /* Pro4 or older */ 80 /* Pro4 or older */
85 #define SC_CLKCTRL_CEN_UMC (0x1 << 4) 81 #define SC_CLKCTRL_CEN_UMC (0x1 << 4)
86 #define SC_CLKCTRL_CEN_NAND (0x1 << 2) 82 #define SC_CLKCTRL_CEN_NAND (0x1 << 2)
87 #define SC_CLKCTRL_CEN_SBC (0x1 << 1) 83 #define SC_CLKCTRL_CEN_SBC (0x1 << 1)
88 #define SC_CLKCTRL_CEN_PERI (0x1 << 0) 84 #define SC_CLKCTRL_CEN_PERI (0x1 << 0)
89 85
90 /* Pro5 or newer */ 86 /* Pro5 or newer */
91 #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) 87 #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
92 #define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */ 88 #define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */
93 #define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */ 89 #define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */
94 #define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */ 90 #define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */
95 #define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */ 91 #define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */
96 92
97 /* System reset control register */ 93 /* System reset control register */
98 #define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000) 94 #define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
99 #define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010) 95 #define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
100 #define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014) 96 #define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)
101 97
102 #endif /* ARCH_SC_REGS_H */ 98 #endif /* ARCH_SC_REGS_H */
103 99
arch/arm/mach-uniphier/soc-info.h
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2017 Socionext Inc. 2 * Copyright (C) 2017 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef __UNIPHIER_SOC_INFO_H__ 8 #ifndef __UNIPHIER_SOC_INFO_H__
9 #define __UNIPHIER_SOC_INFO_H__ 9 #define __UNIPHIER_SOC_INFO_H__
10 10
11 #include <linux/kernel.h> 11 #include <linux/kernel.h>
12 #include <linux/stddef.h> 12 #include <linux/stddef.h>
13 13
14 #define UNIPHIER_SLD3_ID 0x25
15 #define UNIPHIER_LD4_ID 0x26 14 #define UNIPHIER_LD4_ID 0x26
16 #define UNIPHIER_PRO4_ID 0x28 15 #define UNIPHIER_PRO4_ID 0x28
17 #define UNIPHIER_SLD8_ID 0x29 16 #define UNIPHIER_SLD8_ID 0x29
18 #define UNIPHIER_PRO5_ID 0x2a 17 #define UNIPHIER_PRO5_ID 0x2a
19 #define UNIPHIER_PXS2_ID 0x2e 18 #define UNIPHIER_PXS2_ID 0x2e
20 #define UNIPHIER_LD6B_ID 0x2f 19 #define UNIPHIER_LD6B_ID 0x2f
21 #define UNIPHIER_LD11_ID 0x31 20 #define UNIPHIER_LD11_ID 0x31
22 #define UNIPHIER_LD20_ID 0x32 21 #define UNIPHIER_LD20_ID 0x32
23 #define UNIPHIER_PXS3_ID 0x35 22 #define UNIPHIER_PXS3_ID 0x35
24 23
25 unsigned int uniphier_get_soc_id(void); 24 unsigned int uniphier_get_soc_id(void);
26 unsigned int uniphier_get_soc_model(void); 25 unsigned int uniphier_get_soc_model(void);
27 unsigned int uniphier_get_soc_revision(void); 26 unsigned int uniphier_get_soc_revision(void);
28 27
29 #define UNIPHIER_DEFINE_SOCDATA_FUNC(__func_name, __table) \ 28 #define UNIPHIER_DEFINE_SOCDATA_FUNC(__func_name, __table) \
30 static typeof(&__table[0]) __func_name(void) \ 29 static typeof(&__table[0]) __func_name(void) \
31 { \ 30 { \
32 unsigned int soc_id; \ 31 unsigned int soc_id; \
33 int i; \ 32 int i; \
34 \ 33 \
35 soc_id = uniphier_get_soc_id(); \ 34 soc_id = uniphier_get_soc_id(); \
36 for (i = 0; i < ARRAY_SIZE(__table); i++) { \ 35 for (i = 0; i < ARRAY_SIZE(__table); i++) { \
37 if (__table[i].soc_id == soc_id) \ 36 if (__table[i].soc_id == soc_id) \
38 return &__table[i]; \ 37 return &__table[i]; \
39 } \ 38 } \
40 \ 39 \
41 return NULL; \ 40 return NULL; \
42 } 41 }
43 42
44 #endif /* __UNIPHIER_SOC_INFO_H__ */ 43 #endif /* __UNIPHIER_SOC_INFO_H__ */
45 44
arch/arm/mach-uniphier/spl_board_init.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2015-2016 Socionext Inc. 2 * Copyright (C) 2015-2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <debug_uart.h> 9 #include <debug_uart.h>
10 #include <spl.h> 10 #include <spl.h>
11 11
12 #include "init.h" 12 #include "init.h"
13 #include "micro-support-card.h" 13 #include "micro-support-card.h"
14 #include "soc-info.h" 14 #include "soc-info.h"
15 15
16 struct uniphier_spl_initdata { 16 struct uniphier_spl_initdata {
17 unsigned int soc_id; 17 unsigned int soc_id;
18 void (*bcu_init)(const struct uniphier_board_data *bd); 18 void (*bcu_init)(const struct uniphier_board_data *bd);
19 void (*early_clk_init)(void); 19 void (*early_clk_init)(void);
20 int (*dpll_init)(const struct uniphier_board_data *bd); 20 int (*dpll_init)(const struct uniphier_board_data *bd);
21 int (*memconf_init)(const struct uniphier_board_data *bd); 21 int (*memconf_init)(const struct uniphier_board_data *bd);
22 void (*dram_clk_init)(void); 22 void (*dram_clk_init)(void);
23 int (*umc_init)(const struct uniphier_board_data *bd); 23 int (*umc_init)(const struct uniphier_board_data *bd);
24 }; 24 };
25 25
26 static const struct uniphier_spl_initdata uniphier_spl_initdata[] = { 26 static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
27 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
28 {
29 .soc_id = UNIPHIER_SLD3_ID,
30 .bcu_init = uniphier_sld3_bcu_init,
31 .early_clk_init = uniphier_sld3_early_clk_init,
32 .dpll_init = uniphier_sld3_dpll_init,
33 .memconf_init = uniphier_memconf_3ch_no_disbit_init,
34 .dram_clk_init = uniphier_sld3_dram_clk_init,
35 .umc_init = uniphier_sld3_umc_init,
36 },
37 #endif
38 #if defined(CONFIG_ARCH_UNIPHIER_LD4) 27 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
39 { 28 {
40 .soc_id = UNIPHIER_LD4_ID, 29 .soc_id = UNIPHIER_LD4_ID,
41 .bcu_init = uniphier_ld4_bcu_init, 30 .bcu_init = uniphier_ld4_bcu_init,
42 .early_clk_init = uniphier_sld3_early_clk_init, 31 .early_clk_init = uniphier_ld4_early_clk_init,
43 .dpll_init = uniphier_ld4_dpll_init, 32 .dpll_init = uniphier_ld4_dpll_init,
44 .memconf_init = uniphier_memconf_2ch_init, 33 .memconf_init = uniphier_memconf_2ch_init,
45 .dram_clk_init = uniphier_sld3_dram_clk_init, 34 .dram_clk_init = uniphier_ld4_dram_clk_init,
46 .umc_init = uniphier_ld4_umc_init, 35 .umc_init = uniphier_ld4_umc_init,
47 }, 36 },
48 #endif 37 #endif
49 #if defined(CONFIG_ARCH_UNIPHIER_PRO4) 38 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
50 { 39 {
51 .soc_id = UNIPHIER_PRO4_ID, 40 .soc_id = UNIPHIER_PRO4_ID,
52 .early_clk_init = uniphier_sld3_early_clk_init, 41 .early_clk_init = uniphier_ld4_early_clk_init,
53 .dpll_init = uniphier_pro4_dpll_init, 42 .dpll_init = uniphier_pro4_dpll_init,
54 .memconf_init = uniphier_memconf_2ch_init, 43 .memconf_init = uniphier_memconf_2ch_init,
55 .dram_clk_init = uniphier_sld3_dram_clk_init, 44 .dram_clk_init = uniphier_ld4_dram_clk_init,
56 .umc_init = uniphier_pro4_umc_init, 45 .umc_init = uniphier_pro4_umc_init,
57 }, 46 },
58 #endif 47 #endif
59 #if defined(CONFIG_ARCH_UNIPHIER_SLD8) 48 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
60 { 49 {
61 .soc_id = UNIPHIER_SLD8_ID, 50 .soc_id = UNIPHIER_SLD8_ID,
62 .bcu_init = uniphier_ld4_bcu_init, 51 .bcu_init = uniphier_ld4_bcu_init,
63 .early_clk_init = uniphier_sld3_early_clk_init, 52 .early_clk_init = uniphier_ld4_early_clk_init,
64 .dpll_init = uniphier_sld8_dpll_init, 53 .dpll_init = uniphier_sld8_dpll_init,
65 .memconf_init = uniphier_memconf_2ch_init, 54 .memconf_init = uniphier_memconf_2ch_init,
66 .dram_clk_init = uniphier_sld3_dram_clk_init, 55 .dram_clk_init = uniphier_ld4_dram_clk_init,
67 .umc_init = uniphier_sld8_umc_init, 56 .umc_init = uniphier_sld8_umc_init,
68 }, 57 },
69 #endif 58 #endif
70 #if defined(CONFIG_ARCH_UNIPHIER_PRO5) 59 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
71 { 60 {
72 .soc_id = UNIPHIER_PRO5_ID, 61 .soc_id = UNIPHIER_PRO5_ID,
73 .early_clk_init = uniphier_sld3_early_clk_init, 62 .early_clk_init = uniphier_ld4_early_clk_init,
74 .dpll_init = uniphier_pro5_dpll_init, 63 .dpll_init = uniphier_pro5_dpll_init,
75 .memconf_init = uniphier_memconf_2ch_init, 64 .memconf_init = uniphier_memconf_2ch_init,
76 .dram_clk_init = uniphier_pro5_dram_clk_init, 65 .dram_clk_init = uniphier_pro5_dram_clk_init,
77 .umc_init = uniphier_pro5_umc_init, 66 .umc_init = uniphier_pro5_umc_init,
78 }, 67 },
79 #endif 68 #endif
80 #if defined(CONFIG_ARCH_UNIPHIER_PXS2) 69 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
81 { 70 {
82 .soc_id = UNIPHIER_PXS2_ID, 71 .soc_id = UNIPHIER_PXS2_ID,
83 .early_clk_init = uniphier_sld3_early_clk_init, 72 .early_clk_init = uniphier_ld4_early_clk_init,
84 .dpll_init = uniphier_pxs2_dpll_init, 73 .dpll_init = uniphier_pxs2_dpll_init,
85 .memconf_init = uniphier_memconf_3ch_init, 74 .memconf_init = uniphier_memconf_3ch_init,
86 .dram_clk_init = uniphier_pxs2_dram_clk_init, 75 .dram_clk_init = uniphier_pxs2_dram_clk_init,
87 .umc_init = uniphier_pxs2_umc_init, 76 .umc_init = uniphier_pxs2_umc_init,
88 }, 77 },
89 #endif 78 #endif
90 #if defined(CONFIG_ARCH_UNIPHIER_LD6B) 79 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
91 { 80 {
92 .soc_id = UNIPHIER_LD6B_ID, 81 .soc_id = UNIPHIER_LD6B_ID,
93 .early_clk_init = uniphier_sld3_early_clk_init, 82 .early_clk_init = uniphier_ld4_early_clk_init,
94 .dpll_init = uniphier_pxs2_dpll_init, 83 .dpll_init = uniphier_pxs2_dpll_init,
95 .memconf_init = uniphier_memconf_3ch_init, 84 .memconf_init = uniphier_memconf_3ch_init,
96 .dram_clk_init = uniphier_pxs2_dram_clk_init, 85 .dram_clk_init = uniphier_pxs2_dram_clk_init,
97 .umc_init = uniphier_pxs2_umc_init, 86 .umc_init = uniphier_pxs2_umc_init,
98 }, 87 },
99 #endif 88 #endif
100 }; 89 };
101 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_spl_initdata, uniphier_spl_initdata) 90 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_spl_initdata, uniphier_spl_initdata)
102 91
103 void spl_board_init(void) 92 void spl_board_init(void)
104 { 93 {
105 const struct uniphier_board_data *bd; 94 const struct uniphier_board_data *bd;
106 const struct uniphier_spl_initdata *initdata; 95 const struct uniphier_spl_initdata *initdata;
107 int ret; 96 int ret;
108 97
109 #ifdef CONFIG_DEBUG_UART 98 #ifdef CONFIG_DEBUG_UART
110 debug_uart_init(); 99 debug_uart_init();
111 #endif 100 #endif
112 101
113 bd = uniphier_get_board_param(); 102 bd = uniphier_get_board_param();
114 if (!bd) 103 if (!bd)
115 hang(); 104 hang();
116 105
117 initdata = uniphier_get_spl_initdata(); 106 initdata = uniphier_get_spl_initdata();
118 if (!initdata) 107 if (!initdata)
119 hang(); 108 hang();
120 109
121 if (initdata->bcu_init) 110 if (initdata->bcu_init)
122 initdata->bcu_init(bd); 111 initdata->bcu_init(bd);
123 112
124 initdata->early_clk_init(); 113 initdata->early_clk_init();
125 114
126 #ifdef CONFIG_SPL_SERIAL_SUPPORT 115 #ifdef CONFIG_SPL_SERIAL_SUPPORT
127 preloader_console_init(); 116 preloader_console_init();
128 #endif 117 #endif
129 118
130 ret = initdata->dpll_init(bd); 119 ret = initdata->dpll_init(bd);
131 if (ret) { 120 if (ret) {
132 pr_err("failed to init DPLL\n"); 121 pr_err("failed to init DPLL\n");
133 hang(); 122 hang();
134 } 123 }
135 124
136 ret = initdata->memconf_init(bd); 125 ret = initdata->memconf_init(bd);
137 if (ret) { 126 if (ret) {
138 pr_err("failed to init MEMCONF\n"); 127 pr_err("failed to init MEMCONF\n");
139 hang(); 128 hang();
140 } 129 }
141 130
142 initdata->dram_clk_init(); 131 initdata->dram_clk_init();
143 132
144 ret = initdata->umc_init(bd); 133 ret = initdata->umc_init(bd);
145 if (ret) { 134 if (ret) {
146 pr_err("failed to init DRAM\n"); 135 pr_err("failed to init DRAM\n");
147 hang(); 136 hang();
148 } 137 }
149 } 138 }
150 139
configs/uniphier_sld3_defconfig
View file @ 00aa453
1 CONFIG_ARM=y File was deleted
2 CONFIG_ARCH_UNIPHIER=y
3 CONFIG_SYS_TEXT_BASE=0x84000000
4 CONFIG_SYS_MALLOC_F_LEN=0x2000
5 CONFIG_SPL_MMC_SUPPORT=y
6 CONFIG_SPL_SERIAL_SUPPORT=y
7 CONFIG_SPL_NAND_SUPPORT=y
8 CONFIG_ARCH_UNIPHIER_SLD3=y
9 CONFIG_MICRO_SUPPORT_CARD=y
10 CONFIG_DEFAULT_DEVICE_TREE="uniphier-sld3-ref"
11 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
12 CONFIG_SPL=y
13 CONFIG_SPL_NOR_SUPPORT=y
14 CONFIG_HUSH_PARSER=y
15 CONFIG_CMD_CONFIG=y
16 CONFIG_CMD_BOOTZ=y
17 # CONFIG_CMD_XIMG is not set
18 # CONFIG_CMD_ENV_EXISTS is not set
19 # CONFIG_CMD_FPGA is not set
20 CONFIG_CMD_GPIO=y
21 CONFIG_CMD_GPT=y
22 CONFIG_CMD_I2C=y
23 CONFIG_CMD_MMC=y
24 CONFIG_CMD_USB=y
25 CONFIG_CMD_TFTPPUT=y
26 CONFIG_CMD_PING=y
27 CONFIG_CMD_CACHE=y
28 CONFIG_CMD_TIME=y
29 # CONFIG_CMD_MISC is not set
30 CONFIG_CMD_FAT=y
31 CONFIG_CMD_FS_GENERIC=y
32 # CONFIG_SPL_DOS_PARTITION is not set
33 # CONFIG_SPL_EFI_PARTITION is not set
34 CONFIG_NET_RANDOM_ETHADDR=y
35 CONFIG_GPIO_UNIPHIER=y
36 CONFIG_MISC=y
37 CONFIG_I2C_EEPROM=y
38 CONFIG_MMC_UNIPHIER=y
39 CONFIG_NAND_DENALI=y
40 CONFIG_SYS_NAND_DENALI_64BIT=y
41 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
42 CONFIG_SPL_NAND_DENALI=y
43 CONFIG_USB=y
44 CONFIG_USB_EHCI_HCD=y
45 CONFIG_USB_EHCI_GENERIC=y
46 CONFIG_USB_STORAGE=y
47 1 CONFIG_ARM=y
1 U-Boot for UniPhier SoC family 1 U-Boot for UniPhier SoC family
2 ============================== 2 ==============================
3 3
4 4
5 Recommended toolchains 5 Recommended toolchains
6 ---------------------- 6 ----------------------
7 7
8 The UniPhier platform is well tested with Linaro toolchains. 8 The UniPhier platform is well tested with Linaro toolchains.
9 You can download pre-built toolchains from: 9 You can download pre-built toolchains from:
10 10
11 http://www.linaro.org/downloads/ 11 http://www.linaro.org/downloads/
12 12
13 13
14 Compile the source 14 Compile the source
15 ------------------ 15 ------------------
16 16
17 The source can be configured and built with the following commands: 17 The source can be configured and built with the following commands:
18 18
19 $ make <defconfig> 19 $ make <defconfig>
20 $ make CROSS_COMPILE=<toolchain-prefix> DEVICE_TREE=<device-tree> 20 $ make CROSS_COMPILE=<toolchain-prefix> DEVICE_TREE=<device-tree>
21 21
22 The recommended <toolchain-prefix> is `arm-linux-gnueabihf-` for 32bit SoCs, 22 The recommended <toolchain-prefix> is `arm-linux-gnueabihf-` for 32bit SoCs,
23 `aarch64-linux-gnu-` for 64bit SoCs, but you may wish to change it to use your 23 `aarch64-linux-gnu-` for 64bit SoCs, but you may wish to change it to use your
24 favorite compiler. 24 favorite compiler.
25 25
26 The following tables show <defconfig> and <device-tree> for each board. 26 The following tables show <defconfig> and <device-tree> for each board.
27 27
28 32bit SoC boards: 28 32bit SoC boards:
29 29
30 Board | <defconfig> | <device-tree> 30 Board | <defconfig> | <device-tree>
31 ---------------|------------------------------|------------------------------ 31 ---------------|------------------------------|------------------------------
32 sLD3 reference | uniphier_sld3_defconfig | uniphier-sld3-ref (default)
33 LD4 reference | uniphier_ld4_sld8_defconfig | uniphier-ld4-ref (default) 32 LD4 reference | uniphier_ld4_sld8_defconfig | uniphier-ld4-ref (default)
34 sld8 reference | uniphier_ld4_sld8_defconfig | uniphier-sld8-def 33 sld8 reference | uniphier_ld4_sld8_defconfig | uniphier-sld8-def
35 Pro4 reference | uniphier_pro4_defconfig | uniphier-pro4-ref (default) 34 Pro4 reference | uniphier_pro4_defconfig | uniphier-pro4-ref (default)
36 Pro4 Ace | uniphier_pro4_defconfig | uniphier-pro4-ace 35 Pro4 Ace | uniphier_pro4_defconfig | uniphier-pro4-ace
37 Pro4 Sanji | uniphier_pro4_defconfig | uniphier-pro4-sanji 36 Pro4 Sanji | uniphier_pro4_defconfig | uniphier-pro4-sanji
38 Pro5 4KBOX | uniphier_pxs2_ld6b_defconfig | uniphier-pro5-4kbox 37 Pro5 4KBOX | uniphier_pxs2_ld6b_defconfig | uniphier-pro5-4kbox
39 PXs2 Gentil | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-gentil 38 PXs2 Gentil | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-gentil
40 PXs2 Vodka | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-vodka (default) 39 PXs2 Vodka | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-vodka (default)
41 LD6b reference | uniphier_pxs2_ld6b_defconfig | uniphier-ld6b-ref 40 LD6b reference | uniphier_pxs2_ld6b_defconfig | uniphier-ld6b-ref
42 41
43 64bit SoC boards: 42 64bit SoC boards:
44 43
45 Board | <defconfig> | <device-tree> 44 Board | <defconfig> | <device-tree>
46 ---------------|-----------------------|---------------------------- 45 ---------------|-----------------------|----------------------------
47 LD11 reference | uniphier_v8_defconfig | uniphier-ld11-ref 46 LD11 reference | uniphier_v8_defconfig | uniphier-ld11-ref
48 LD11 Global | uniphier_v8_defconfig | uniphier-ld11-global 47 LD11 Global | uniphier_v8_defconfig | uniphier-ld11-global
49 LD20 reference | uniphier_v8_defconfig | uniphier-ld20-ref (default) 48 LD20 reference | uniphier_v8_defconfig | uniphier-ld20-ref (default)
50 LD20 Global | uniphier_v8_defconfig | uniphier-ld20-global 49 LD20 Global | uniphier_v8_defconfig | uniphier-ld20-global
51 50
52 For example, to compile the source for PXs2 Vodka board, run the following: 51 For example, to compile the source for PXs2 Vodka board, run the following:
53 52
54 $ make uniphier_pxs2_ld6b_defconfig 53 $ make uniphier_pxs2_ld6b_defconfig
55 $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-vodka 54 $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-vodka
56 55
57 The device tree marked as (default) can be omitted. `uniphier-pxs2-vodka` is 56 The device tree marked as (default) can be omitted. `uniphier-pxs2-vodka` is
58 the default device tree for the configuration `uniphier_pxs2_ld6b_defconfig`, 57 the default device tree for the configuration `uniphier_pxs2_ld6b_defconfig`,
59 so the following gives the same result. 58 so the following gives the same result.
60 59
61 $ make uniphier_pxs2_ld6b_defconfig 60 $ make uniphier_pxs2_ld6b_defconfig
62 $ make CROSS_COMPILE=arm-linux-gnueabihf- 61 $ make CROSS_COMPILE=arm-linux-gnueabihf-
63 62
64 63
65 Booting 32bit SoC boards 64 Booting 32bit SoC boards
66 ------------------------ 65 ------------------------
67 66
68 The build command will generate the following: 67 The build command will generate the following:
69 - u-boot.bin 68 - u-boot.bin
70 - spl/u-boot.bin 69 - spl/u-boot.bin
71 70
72 U-Boot can boot UniPhier 32bit SoC boards by itself. Flash the generated images 71 U-Boot can boot UniPhier 32bit SoC boards by itself. Flash the generated images
73 to the storage device (NAND or eMMC) on your board. 72 to the storage device (NAND or eMMC) on your board.
74 73
75 - spl/u-boot-spl.bin at the offset address 0x00000000 74 - spl/u-boot-spl.bin at the offset address 0x00000000
76 - u-boot.bin at the offset address 0x00020000 75 - u-boot.bin at the offset address 0x00020000
77 76
78 The `u-boot-with-spl.bin` is the concatenation of the two (with appropriate 77 The `u-boot-with-spl.bin` is the concatenation of the two (with appropriate
79 padding), so you can also do: 78 padding), so you can also do:
80 79
81 - u-boot-with-spl.bin at the offset address 0x00000000 80 - u-boot-with-spl.bin at the offset address 0x00000000
82 81
83 If a TFTP server is available, the images can be easily updated. 82 If a TFTP server is available, the images can be easily updated.
84 Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory, 83 Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory,
85 and run the following command at the U-Boot command line: 84 and run the following command at the U-Boot command line:
86 85
87 To update the images in NAND: 86 To update the images in NAND:
88 87
89 => run nandupdate 88 => run nandupdate
90 89
91 To update the images in eMMC: 90 To update the images in eMMC:
92 91
93 => run emmcupdate 92 => run emmcupdate
94 93
95 94
96 Booting 64bit SoC boards 95 Booting 64bit SoC boards
97 ------------------------ 96 ------------------------
98 97
99 The build command will generate the following: 98 The build command will generate the following:
100 - u-boot.bin 99 - u-boot.bin
101 100
102 However, U-Boot is not the first stage loader for UniPhier 64bit SoC boards. 101 However, U-Boot is not the first stage loader for UniPhier 64bit SoC boards.
103 U-Boot serves as a non-secure boot loader loaded by [ARM Trusted Firmware], 102 U-Boot serves as a non-secure boot loader loaded by [ARM Trusted Firmware],
104 so you need to provide the `u-boot.bin` to the build command of ARM Trusted 103 so you need to provide the `u-boot.bin` to the build command of ARM Trusted
105 Firmware. 104 Firmware.
106 105
107 [ARM Trusted Firmware]: https://github.com/ARM-software/arm-trusted-firmware 106 [ARM Trusted Firmware]: https://github.com/ARM-software/arm-trusted-firmware
108 107
109 108
110 UniPhier specific commands 109 UniPhier specific commands
111 -------------------------- 110 --------------------------
112 111
113 - pinmon (enabled by CONFIG_CMD_PINMON) 112 - pinmon (enabled by CONFIG_CMD_PINMON)
114 shows the boot mode pins that has been latched at the power-on reset 113 shows the boot mode pins that has been latched at the power-on reset
115 114
116 - ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP) 115 - ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP)
117 shows the DDR PHY parameters set by the PHY training 116 shows the DDR PHY parameters set by the PHY training
118 117
119 - ddrmphy (enabled by CONFIG_CMD_DDRMPHY_DUMP) 118 - ddrmphy (enabled by CONFIG_CMD_DDRMPHY_DUMP)
120 shows the DDR Multi PHY parameters set by the PHY training 119 shows the DDR Multi PHY parameters set by the PHY training
121 120
122 121
123 Supported devices 122 Supported devices
124 ----------------- 123 -----------------
125 124
126 - UART (on-chip) 125 - UART (on-chip)
127 - NAND 126 - NAND
128 - SD/eMMC 127 - SD/eMMC
129 - USB 2.0 (EHCI) 128 - USB 2.0 (EHCI)
130 - USB 3.0 (xHCI) 129 - USB 3.0 (xHCI)
131 - GPIO 130 - GPIO
132 - LAN (on-board SMSC9118) 131 - LAN (on-board SMSC9118)
133 - I2C 132 - I2C
134 - EEPROM (connected to the on-board I2C bus) 133 - EEPROM (connected to the on-board I2C bus)
135 - Support card (SRAM, NOR flash, some peripherals) 134 - Support card (SRAM, NOR flash, some peripherals)
136 135
137 136
138 Micro Support Card 137 Micro Support Card
139 ------------------ 138 ------------------
140 139
141 The recommended bit switch settings are as follows: 140 The recommended bit switch settings are as follows:
142 141
143 SW2 OFF(1)/ON(0) Description 142 SW2 OFF(1)/ON(0) Description
144 ------------------------------------------ 143 ------------------------------------------
145 bit 1 <---- BKSZ[0] 144 bit 1 <---- BKSZ[0]
146 bit 2 ----> BKSZ[1] 145 bit 2 ----> BKSZ[1]
147 bit 3 <---- SoC Bus Width 16/32 146 bit 3 <---- SoC Bus Width 16/32
148 bit 4 <---- SERIAL_SEL[0] 147 bit 4 <---- SERIAL_SEL[0]
149 bit 5 ----> SERIAL_SEL[1] 148 bit 5 ----> SERIAL_SEL[1]
150 bit 6 ----> BOOTSWAP_EN 149 bit 6 ----> BOOTSWAP_EN
151 bit 7 <---- CS1/CS5 150 bit 7 <---- CS1/CS5
152 bit 8 <---- SOC_SERIAL_DISABLE 151 bit 8 <---- SOC_SERIAL_DISABLE
153 152
154 SW8 OFF(1)/ON(0) Description 153 SW8 OFF(1)/ON(0) Description
155 ------------------------------------------ 154 ------------------------------------------
156 bit 1 <---- CS1_SPLIT 155 bit 1 <---- CS1_SPLIT
157 bit 2 <---- CASE9_ON 156 bit 2 <---- CASE9_ON
158 bit 3 <---- CASE10_ON 157 bit 3 <---- CASE10_ON
159 bit 4 Don't Care Reserve 158 bit 4 Don't Care Reserve
160 bit 5 Don't Care Reserve 159 bit 5 Don't Care Reserve
161 bit 6 Don't Care Reserve 160 bit 6 Don't Care Reserve
162 bit 7 ----> BURST_EN 161 bit 7 ----> BURST_EN
163 bit 8 ----> FLASHBUS32_16 162 bit 8 ----> FLASHBUS32_16
164 163
165 The BKSZ[1:0] specifies the address range of memory slot and peripherals 164 The BKSZ[1:0] specifies the address range of memory slot and peripherals
166 as follows: 165 as follows:
167 166
168 BKSZ Description RAM slot Peripherals 167 BKSZ Description RAM slot Peripherals
169 -------------------------------------------------------------------- 168 --------------------------------------------------------------------
170 0b00 15MB RAM / 1MB Peri 00000000-00efffff 00f00000-00ffffff 169 0b00 15MB RAM / 1MB Peri 00000000-00efffff 00f00000-00ffffff
171 0b01 31MB RAM / 1MB Peri 00000000-01efffff 01f00000-01ffffff 170 0b01 31MB RAM / 1MB Peri 00000000-01efffff 01f00000-01ffffff
172 0b10 64MB RAM / 1MB Peri 00000000-03efffff 03f00000-03ffffff 171 0b10 64MB RAM / 1MB Peri 00000000-03efffff 03f00000-03ffffff
173 0b11 127MB RAM / 1MB Peri 00000000-07efffff 07f00000-07ffffff 172 0b11 127MB RAM / 1MB Peri 00000000-07efffff 07f00000-07ffffff
174 173
175 Set BSKZ[1:0] to 0b01 for U-Boot. 174 Set BSKZ[1:0] to 0b01 for U-Boot.
176 This mode is the most handy because EA[24] is always supported by the save pin 175 This mode is the most handy because EA[24] is always supported by the save pin
177 mode of the system bus. On the other hand, EA[25] is not supported for some 176 mode of the system bus. On the other hand, EA[25] is not supported for some
178 newer SoCs. Even if it is, EA[25] is not connected on most of the boards. 177 newer SoCs. Even if it is, EA[25] is not connected on most of the boards.
179 178
180 -- 179 --
181 Masahiro Yamada <yamada.masahiro@socionext.com> 180 Masahiro Yamada <yamada.masahiro@socionext.com>
182 Jul. 2017 181 Jul. 2017
183 182
drivers/clk/uniphier/clk-uniphier-core.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2016 Socionext Inc. 2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <clk-uclass.h> 9 #include <clk-uclass.h>
10 #include <dm.h> 10 #include <dm.h>
11 #include <linux/bitops.h> 11 #include <linux/bitops.h>
12 #include <linux/io.h> 12 #include <linux/io.h>
13 #include <linux/sizes.h> 13 #include <linux/sizes.h>
14 14
15 #include "clk-uniphier.h" 15 #include "clk-uniphier.h"
16 16
17 /** 17 /**
18 * struct uniphier_clk_priv - private data for UniPhier clock driver 18 * struct uniphier_clk_priv - private data for UniPhier clock driver
19 * 19 *
20 * @base: base address of the clock provider 20 * @base: base address of the clock provider
21 * @data: SoC specific data 21 * @data: SoC specific data
22 */ 22 */
23 struct uniphier_clk_priv { 23 struct uniphier_clk_priv {
24 void __iomem *base; 24 void __iomem *base;
25 const struct uniphier_clk_data *data; 25 const struct uniphier_clk_data *data;
26 }; 26 };
27 27
28 static int uniphier_clk_enable(struct clk *clk) 28 static int uniphier_clk_enable(struct clk *clk)
29 { 29 {
30 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); 30 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
31 unsigned long id = clk->id; 31 unsigned long id = clk->id;
32 const struct uniphier_clk_gate_data *p; 32 const struct uniphier_clk_gate_data *p;
33 33
34 for (p = priv->data->gate; p->id != UNIPHIER_CLK_ID_END; p++) { 34 for (p = priv->data->gate; p->id != UNIPHIER_CLK_ID_END; p++) {
35 u32 val; 35 u32 val;
36 36
37 if (p->id != id) 37 if (p->id != id)
38 continue; 38 continue;
39 39
40 val = readl(priv->base + p->reg); 40 val = readl(priv->base + p->reg);
41 val |= BIT(p->bit); 41 val |= BIT(p->bit);
42 writel(val, priv->base + p->reg); 42 writel(val, priv->base + p->reg);
43 43
44 return 0; 44 return 0;
45 } 45 }
46 46
47 dev_err(priv->dev, "clk_id=%lu was not handled\n", id); 47 dev_err(priv->dev, "clk_id=%lu was not handled\n", id);
48 return -EINVAL; 48 return -EINVAL;
49 } 49 }
50 50
51 static const struct uniphier_clk_mux_data * 51 static const struct uniphier_clk_mux_data *
52 uniphier_clk_get_mux_data(struct uniphier_clk_priv *priv, unsigned long id) 52 uniphier_clk_get_mux_data(struct uniphier_clk_priv *priv, unsigned long id)
53 { 53 {
54 const struct uniphier_clk_mux_data *p; 54 const struct uniphier_clk_mux_data *p;
55 55
56 for (p = priv->data->mux; p->id != UNIPHIER_CLK_ID_END; p++) { 56 for (p = priv->data->mux; p->id != UNIPHIER_CLK_ID_END; p++) {
57 if (p->id == id) 57 if (p->id == id)
58 return p; 58 return p;
59 } 59 }
60 60
61 return NULL; 61 return NULL;
62 } 62 }
63 63
64 static ulong uniphier_clk_get_rate(struct clk *clk) 64 static ulong uniphier_clk_get_rate(struct clk *clk)
65 { 65 {
66 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); 66 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
67 const struct uniphier_clk_mux_data *mux; 67 const struct uniphier_clk_mux_data *mux;
68 u32 val; 68 u32 val;
69 int i; 69 int i;
70 70
71 mux = uniphier_clk_get_mux_data(priv, clk->id); 71 mux = uniphier_clk_get_mux_data(priv, clk->id);
72 if (!mux) 72 if (!mux)
73 return 0; 73 return 0;
74 74
75 if (!mux->nr_muxs) /* fixed-rate */ 75 if (!mux->nr_muxs) /* fixed-rate */
76 return mux->rates[0]; 76 return mux->rates[0];
77 77
78 val = readl(priv->base + mux->reg); 78 val = readl(priv->base + mux->reg);
79 79
80 for (i = 0; i < mux->nr_muxs; i++) 80 for (i = 0; i < mux->nr_muxs; i++)
81 if ((mux->masks[i] & val) == mux->vals[i]) 81 if ((mux->masks[i] & val) == mux->vals[i])
82 return mux->rates[i]; 82 return mux->rates[i];
83 83
84 return -EINVAL; 84 return -EINVAL;
85 } 85 }
86 86
87 static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate) 87 static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
88 { 88 {
89 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); 89 struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
90 const struct uniphier_clk_mux_data *mux; 90 const struct uniphier_clk_mux_data *mux;
91 u32 val; 91 u32 val;
92 int i, best_rate_id = -1; 92 int i, best_rate_id = -1;
93 ulong best_rate = 0; 93 ulong best_rate = 0;
94 94
95 mux = uniphier_clk_get_mux_data(priv, clk->id); 95 mux = uniphier_clk_get_mux_data(priv, clk->id);
96 if (!mux) 96 if (!mux)
97 return 0; 97 return 0;
98 98
99 if (!mux->nr_muxs) /* fixed-rate */ 99 if (!mux->nr_muxs) /* fixed-rate */
100 return mux->rates[0]; 100 return mux->rates[0];
101 101
102 /* first, decide the best match rate */ 102 /* first, decide the best match rate */
103 for (i = 0; i < mux->nr_muxs; i++) { 103 for (i = 0; i < mux->nr_muxs; i++) {
104 if (mux->rates[i] > best_rate && mux->rates[i] <= rate) { 104 if (mux->rates[i] > best_rate && mux->rates[i] <= rate) {
105 best_rate = mux->rates[i]; 105 best_rate = mux->rates[i];
106 best_rate_id = i; 106 best_rate_id = i;
107 } 107 }
108 } 108 }
109 109
110 if (best_rate_id < 0) 110 if (best_rate_id < 0)
111 return -EINVAL; 111 return -EINVAL;
112 112
113 val = readl(priv->base + mux->reg); 113 val = readl(priv->base + mux->reg);
114 val &= ~mux->masks[best_rate_id]; 114 val &= ~mux->masks[best_rate_id];
115 val |= mux->vals[best_rate_id]; 115 val |= mux->vals[best_rate_id];
116 writel(val, priv->base + mux->reg); 116 writel(val, priv->base + mux->reg);
117 117
118 debug("%s: requested rate = %lu, set rate = %lu\n", __func__, 118 debug("%s: requested rate = %lu, set rate = %lu\n", __func__,
119 rate, best_rate); 119 rate, best_rate);
120 120
121 return best_rate; 121 return best_rate;
122 } 122 }
123 123
124 static const struct clk_ops uniphier_clk_ops = { 124 static const struct clk_ops uniphier_clk_ops = {
125 .enable = uniphier_clk_enable, 125 .enable = uniphier_clk_enable,
126 .get_rate = uniphier_clk_get_rate, 126 .get_rate = uniphier_clk_get_rate,
127 .set_rate = uniphier_clk_set_rate, 127 .set_rate = uniphier_clk_set_rate,
128 }; 128 };
129 129
130 static int uniphier_clk_probe(struct udevice *dev) 130 static int uniphier_clk_probe(struct udevice *dev)
131 { 131 {
132 struct uniphier_clk_priv *priv = dev_get_priv(dev); 132 struct uniphier_clk_priv *priv = dev_get_priv(dev);
133 fdt_addr_t addr; 133 fdt_addr_t addr;
134 134
135 addr = devfdt_get_addr(dev->parent); 135 addr = devfdt_get_addr(dev->parent);
136 if (addr == FDT_ADDR_T_NONE) 136 if (addr == FDT_ADDR_T_NONE)
137 return -EINVAL; 137 return -EINVAL;
138 138
139 priv->base = devm_ioremap(dev, addr, SZ_4K); 139 priv->base = devm_ioremap(dev, addr, SZ_4K);
140 if (!priv->base) 140 if (!priv->base)
141 return -ENOMEM; 141 return -ENOMEM;
142 142
143 priv->data = (void *)dev_get_driver_data(dev); 143 priv->data = (void *)dev_get_driver_data(dev);
144 144
145 return 0; 145 return 0;
146 } 146 }
147 147
148 static const struct udevice_id uniphier_clk_match[] = { 148 static const struct udevice_id uniphier_clk_match[] = {
149 { 149 {
150 .compatible = "socionext,uniphier-sld3-mio-clock",
151 .data = (ulong)&uniphier_mio_clk_data,
152 },
153 {
154 .compatible = "socionext,uniphier-ld4-mio-clock", 150 .compatible = "socionext,uniphier-ld4-mio-clock",
155 .data = (ulong)&uniphier_mio_clk_data, 151 .data = (ulong)&uniphier_mio_clk_data,
156 }, 152 },
157 { 153 {
158 .compatible = "socionext,uniphier-pro4-mio-clock", 154 .compatible = "socionext,uniphier-pro4-mio-clock",
159 .data = (ulong)&uniphier_mio_clk_data, 155 .data = (ulong)&uniphier_mio_clk_data,
160 }, 156 },
161 { 157 {
162 .compatible = "socionext,uniphier-sld8-mio-clock", 158 .compatible = "socionext,uniphier-sld8-mio-clock",
163 .data = (ulong)&uniphier_mio_clk_data, 159 .data = (ulong)&uniphier_mio_clk_data,
164 }, 160 },
165 { 161 {
166 .compatible = "socionext,uniphier-pro5-sd-clock", 162 .compatible = "socionext,uniphier-pro5-sd-clock",
167 .data = (ulong)&uniphier_mio_clk_data, 163 .data = (ulong)&uniphier_mio_clk_data,
168 }, 164 },
169 { 165 {
170 .compatible = "socionext,uniphier-pxs2-sd-clock", 166 .compatible = "socionext,uniphier-pxs2-sd-clock",
171 .data = (ulong)&uniphier_mio_clk_data, 167 .data = (ulong)&uniphier_mio_clk_data,
172 }, 168 },
173 { 169 {
174 .compatible = "socionext,uniphier-ld11-mio-clock", 170 .compatible = "socionext,uniphier-ld11-mio-clock",
175 .data = (ulong)&uniphier_mio_clk_data, 171 .data = (ulong)&uniphier_mio_clk_data,
176 }, 172 },
177 { 173 {
178 .compatible = "socionext,uniphier-ld20-sd-clock", 174 .compatible = "socionext,uniphier-ld20-sd-clock",
179 .data = (ulong)&uniphier_mio_clk_data, 175 .data = (ulong)&uniphier_mio_clk_data,
180 }, 176 },
181 { /* sentinel */ } 177 { /* sentinel */ }
182 }; 178 };
183 179
184 U_BOOT_DRIVER(uniphier_clk) = { 180 U_BOOT_DRIVER(uniphier_clk) = {
185 .name = "uniphier-clk", 181 .name = "uniphier-clk",
186 .id = UCLASS_CLK, 182 .id = UCLASS_CLK,
187 .of_match = uniphier_clk_match, 183 .of_match = uniphier_clk_match,
188 .probe = uniphier_clk_probe, 184 .probe = uniphier_clk_probe,
189 .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv), 185 .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
190 .ops = &uniphier_clk_ops, 186 .ops = &uniphier_clk_ops,
191 }; 187 };
192 188
drivers/clk/uniphier/clk-uniphier-mio.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2016 Socionext Inc. 2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include "clk-uniphier.h" 8 #include "clk-uniphier.h"
9 9
10 #define UNIPHIER_MIO_CLK_SD_GATE(id, ch) \ 10 #define UNIPHIER_MIO_CLK_SD_GATE(id, ch) \
11 UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 8) 11 UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 8)
12 12
13 #define UNIPHIER_MIO_CLK_USB2(id, ch) \ 13 #define UNIPHIER_MIO_CLK_USB2(id, ch) \
14 UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 28) 14 UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 28)
15 15
16 #define UNIPHIER_MIO_CLK_USB2_PHY(id, ch) \ 16 #define UNIPHIER_MIO_CLK_USB2_PHY(id, ch) \
17 UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 29) 17 UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 29)
18 18
19 #define UNIPHIER_MIO_CLK_DMAC(id) \ 19 #define UNIPHIER_MIO_CLK_DMAC(id) \
20 UNIPHIER_CLK_GATE((id), 0x20, 25) 20 UNIPHIER_CLK_GATE((id), 0x20, 25)
21 21
22 #define UNIPHIER_MIO_CLK_SD_MUX(_id, ch) \ 22 #define UNIPHIER_MIO_CLK_SD_MUX(_id, ch) \
23 { \ 23 { \
24 .id = (_id), \ 24 .id = (_id), \
25 .nr_muxs = 8, \ 25 .nr_muxs = 8, \
26 .reg = 0x30 + 0x200 * (ch), \ 26 .reg = 0x30 + 0x200 * (ch), \
27 .masks = { \ 27 .masks = { \
28 0x00031000, \ 28 0x00031000, \
29 0x00031000, \ 29 0x00031000, \
30 0x00031000, \ 30 0x00031000, \
31 0x00031000, \ 31 0x00031000, \
32 0x00001300, \ 32 0x00001300, \
33 0x00001300, \ 33 0x00001300, \
34 0x00001300, \ 34 0x00001300, \
35 0x00001300, \ 35 0x00001300, \
36 }, \ 36 }, \
37 .vals = { \ 37 .vals = { \
38 0x00000000, \ 38 0x00000000, \
39 0x00010000, \ 39 0x00010000, \
40 0x00020000, \ 40 0x00020000, \
41 0x00030000, \ 41 0x00030000, \
42 0x00001000, \ 42 0x00001000, \
43 0x00001100, \ 43 0x00001100, \
44 0x00001200, \ 44 0x00001200, \
45 0x00001300, \ 45 0x00001300, \
46 }, \ 46 }, \
47 .rates = { \ 47 .rates = { \
48 44444444, \ 48 44444444, \
49 33333333, \ 49 33333333, \
50 50000000, \ 50 50000000, \
51 66666666, \ 51 66666666, \
52 100000000, \ 52 100000000, \
53 40000000, \ 53 40000000, \
54 25000000, \ 54 25000000, \
55 22222222, \ 55 22222222, \
56 }, \ 56 }, \
57 } 57 }
58 58
59 static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = { 59 static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
60 UNIPHIER_MIO_CLK_SD_GATE(0, 0), 60 UNIPHIER_MIO_CLK_SD_GATE(0, 0),
61 UNIPHIER_MIO_CLK_SD_GATE(1, 1), 61 UNIPHIER_MIO_CLK_SD_GATE(1, 1),
62 UNIPHIER_MIO_CLK_SD_GATE(2, 2), /* for PH1-Pro4 only */ 62 UNIPHIER_MIO_CLK_SD_GATE(2, 2), /* for PH1-Pro4 only */
63 UNIPHIER_MIO_CLK_DMAC(7), 63 UNIPHIER_MIO_CLK_DMAC(7),
64 UNIPHIER_MIO_CLK_USB2(8, 0), 64 UNIPHIER_MIO_CLK_USB2(8, 0),
65 UNIPHIER_MIO_CLK_USB2(9, 1), 65 UNIPHIER_MIO_CLK_USB2(9, 1),
66 UNIPHIER_MIO_CLK_USB2(10, 2), 66 UNIPHIER_MIO_CLK_USB2(10, 2),
67 UNIPHIER_MIO_CLK_USB2(11, 3), /* for PH1-sLD3 only */
68 UNIPHIER_MIO_CLK_USB2_PHY(12, 0), 67 UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
69 UNIPHIER_MIO_CLK_USB2_PHY(13, 1), 68 UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
70 UNIPHIER_MIO_CLK_USB2_PHY(14, 2), 69 UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
71 UNIPHIER_MIO_CLK_USB2_PHY(15, 3), /* for PH1-sLD3 only */
72 UNIPHIER_CLK_END 70 UNIPHIER_CLK_END
73 }; 71 };
74 72
75 static const struct uniphier_clk_mux_data uniphier_mio_clk_mux[] = { 73 static const struct uniphier_clk_mux_data uniphier_mio_clk_mux[] = {
76 UNIPHIER_MIO_CLK_SD_MUX(0, 0), 74 UNIPHIER_MIO_CLK_SD_MUX(0, 0),
77 UNIPHIER_MIO_CLK_SD_MUX(1, 1), 75 UNIPHIER_MIO_CLK_SD_MUX(1, 1),
78 UNIPHIER_MIO_CLK_SD_MUX(2, 2), /* for PH1-Pro4 only */ 76 UNIPHIER_MIO_CLK_SD_MUX(2, 2), /* for PH1-Pro4 only */
79 UNIPHIER_CLK_END 77 UNIPHIER_CLK_END
80 }; 78 };
81 79
82 const struct uniphier_clk_data uniphier_mio_clk_data = { 80 const struct uniphier_clk_data uniphier_mio_clk_data = {
83 .gate = uniphier_mio_clk_gate, 81 .gate = uniphier_mio_clk_gate,
84 .mux = uniphier_mio_clk_mux, 82 .mux = uniphier_mio_clk_mux,
85 }; 83 };
86 84
drivers/pinctrl/uniphier/Kconfig
Diff comments   View file @ 00aa453
1 if ARCH_UNIPHIER 1 if ARCH_UNIPHIER
2 2
3 config PINCTRL_UNIPHIER 3 config PINCTRL_UNIPHIER
4 bool 4 bool
5 5
6 config PINCTRL_UNIPHIER_SLD3
7 bool "UniPhier sLD3 SoC pinctrl driver"
8 depends on ARCH_UNIPHIER_SLD3
9 default y
10 select PINCTRL_UNIPHIER
11
12 config PINCTRL_UNIPHIER_LD4 6 config PINCTRL_UNIPHIER_LD4
13 bool "UniPhier LD4 SoC pinctrl driver" 7 bool "UniPhier LD4 SoC pinctrl driver"
14 depends on ARCH_UNIPHIER_LD4 8 depends on ARCH_UNIPHIER_LD4
15 default y 9 default y
16 select PINCTRL_UNIPHIER 10 select PINCTRL_UNIPHIER
17 11
18 config PINCTRL_UNIPHIER_PRO4 12 config PINCTRL_UNIPHIER_PRO4
19 bool "UniPhier Pro4 SoC pinctrl driver" 13 bool "UniPhier Pro4 SoC pinctrl driver"
20 depends on ARCH_UNIPHIER_PRO4 14 depends on ARCH_UNIPHIER_PRO4
21 default y 15 default y
22 select PINCTRL_UNIPHIER 16 select PINCTRL_UNIPHIER
23 17
24 config PINCTRL_UNIPHIER_SLD8 18 config PINCTRL_UNIPHIER_SLD8
25 bool "UniPhier sLD8 SoC pinctrl driver" 19 bool "UniPhier sLD8 SoC pinctrl driver"
26 depends on ARCH_UNIPHIER_SLD8 20 depends on ARCH_UNIPHIER_SLD8
27 default y 21 default y
28 select PINCTRL_UNIPHIER 22 select PINCTRL_UNIPHIER
29 23
30 config PINCTRL_UNIPHIER_PRO5 24 config PINCTRL_UNIPHIER_PRO5
31 bool "UniPhier Pro5 SoC pinctrl driver" 25 bool "UniPhier Pro5 SoC pinctrl driver"
32 depends on ARCH_UNIPHIER_PRO5 26 depends on ARCH_UNIPHIER_PRO5
33 default y 27 default y
34 select PINCTRL_UNIPHIER 28 select PINCTRL_UNIPHIER
35 29
36 config PINCTRL_UNIPHIER_PXS2 30 config PINCTRL_UNIPHIER_PXS2
37 bool "UniPhier PXs2 SoC pinctrl driver" 31 bool "UniPhier PXs2 SoC pinctrl driver"
38 depends on ARCH_UNIPHIER_PXS2 32 depends on ARCH_UNIPHIER_PXS2
39 default y 33 default y
40 select PINCTRL_UNIPHIER 34 select PINCTRL_UNIPHIER
41 35
42 config PINCTRL_UNIPHIER_LD6B 36 config PINCTRL_UNIPHIER_LD6B
43 bool "UniPhier LD6b SoC pinctrl driver" 37 bool "UniPhier LD6b SoC pinctrl driver"
44 depends on ARCH_UNIPHIER_LD6B 38 depends on ARCH_UNIPHIER_LD6B
45 default y 39 default y
46 select PINCTRL_UNIPHIER 40 select PINCTRL_UNIPHIER
47 41
48 config PINCTRL_UNIPHIER_LD11 42 config PINCTRL_UNIPHIER_LD11
49 bool "UniPhier LD11 SoC pinctrl driver" 43 bool "UniPhier LD11 SoC pinctrl driver"
50 depends on ARCH_UNIPHIER_LD11 44 depends on ARCH_UNIPHIER_LD11
51 default y 45 default y
52 select PINCTRL_UNIPHIER 46 select PINCTRL_UNIPHIER
53 47
54 config PINCTRL_UNIPHIER_LD20 48 config PINCTRL_UNIPHIER_LD20
55 bool "UniPhier LD20 SoC pinctrl driver" 49 bool "UniPhier LD20 SoC pinctrl driver"
56 depends on ARCH_UNIPHIER_LD20 50 depends on ARCH_UNIPHIER_LD20
57 default y 51 default y
58 select PINCTRL_UNIPHIER 52 select PINCTRL_UNIPHIER
59 53
60 config PINCTRL_UNIPHIER_PXS3 54 config PINCTRL_UNIPHIER_PXS3
61 bool "UniPhier PXs3 SoC pinctrl driver" 55 bool "UniPhier PXs3 SoC pinctrl driver"
62 depends on ARCH_UNIPHIER_PXS3 56 depends on ARCH_UNIPHIER_PXS3
63 default y 57 default y
64 select PINCTRL_UNIPHIER 58 select PINCTRL_UNIPHIER
65 59
66 endif 60 endif
67 61
drivers/pinctrl/uniphier/Makefile
Diff comments   View file @ 00aa453
1 # 1 #
2 # SPDX-License-Identifier: GPL-2.0+ 2 # SPDX-License-Identifier: GPL-2.0+
3 # 3 #
4 4
5 obj-y += pinctrl-uniphier-core.o 5 obj-y += pinctrl-uniphier-core.o
6 6
7 obj-$(CONFIG_PINCTRL_UNIPHIER_SLD3) += pinctrl-uniphier-sld3.o
8 obj-$(CONFIG_PINCTRL_UNIPHIER_LD4) += pinctrl-uniphier-ld4.o 7 obj-$(CONFIG_PINCTRL_UNIPHIER_LD4) += pinctrl-uniphier-ld4.o
9 obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4) += pinctrl-uniphier-pro4.o 8 obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4) += pinctrl-uniphier-pro4.o
10 obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8) += pinctrl-uniphier-sld8.o 9 obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8) += pinctrl-uniphier-sld8.o
11 obj-$(CONFIG_PINCTRL_UNIPHIER_PRO5) += pinctrl-uniphier-pro5.o 10 obj-$(CONFIG_PINCTRL_UNIPHIER_PRO5) += pinctrl-uniphier-pro5.o
12 obj-$(CONFIG_PINCTRL_UNIPHIER_PXS2) += pinctrl-uniphier-pxs2.o 11 obj-$(CONFIG_PINCTRL_UNIPHIER_PXS2) += pinctrl-uniphier-pxs2.o
13 obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B) += pinctrl-uniphier-ld6b.o 12 obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B) += pinctrl-uniphier-ld6b.o
14 obj-$(CONFIG_PINCTRL_UNIPHIER_LD11) += pinctrl-uniphier-ld11.o 13 obj-$(CONFIG_PINCTRL_UNIPHIER_LD11) += pinctrl-uniphier-ld11.o
15 obj-$(CONFIG_PINCTRL_UNIPHIER_LD20) += pinctrl-uniphier-ld20.o 14 obj-$(CONFIG_PINCTRL_UNIPHIER_LD20) += pinctrl-uniphier-ld20.o
16 obj-$(CONFIG_PINCTRL_UNIPHIER_PXS3) += pinctrl-uniphier-pxs3.o 15 obj-$(CONFIG_PINCTRL_UNIPHIER_PXS3) += pinctrl-uniphier-pxs3.o
17 16
drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c
View file @ 00aa453
1 /* File was deleted
2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <dm/pinctrl.h>
11
12 #include "pinctrl-uniphier.h"
13
14 static const unsigned emmc_pins[] = {55, 56, 60};
15 static const int emmc_muxvals[] = {1, 1, 1};
16 static const unsigned emmc_dat8_pins[] = {57};
17 static const int emmc_dat8_muxvals[] = {1};
18 static const unsigned ether_mii_pins[] = {35, 107, 108, 109, 110, 111, 112,
19 113};
20 static const int ether_mii_muxvals[] = {1, 2, 2, 2, 2, 2, 2, 2};
21 static const unsigned ether_rmii_pins[] = {35};
22 static const int ether_rmii_muxvals[] = {1};
23 static const unsigned i2c0_pins[] = {36};
24 static const int i2c0_muxvals[] = {0};
25 static const unsigned nand_pins[] = {38, 39, 40, 58, 59};
26 static const int nand_muxvals[] = {1, 1, 1, 1, 1};
27 static const unsigned nand_cs1_pins[] = {41};
28 static const int nand_cs1_muxvals[] = {1};
29 static const unsigned sd_pins[] = {42, 43, 44, 45};
30 static const int sd_muxvals[] = {1, 1, 1, 1};
31 static const unsigned system_bus_pins[] = {46, 50, 51, 53, 54, 73, 74, 75, 76,
32 77, 78, 79, 80, 88, 89, 91, 92, 99};
33 static const int system_bus_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
34 1, 1, 1, 1, 1};
35 static const unsigned system_bus_cs0_pins[] = {93};
36 static const int system_bus_cs0_muxvals[] = {1};
37 static const unsigned system_bus_cs1_pins[] = {94};
38 static const int system_bus_cs1_muxvals[] = {1};
39 static const unsigned system_bus_cs2_pins[] = {95};
40 static const int system_bus_cs2_muxvals[] = {1};
41 static const unsigned system_bus_cs3_pins[] = {96};
42 static const int system_bus_cs3_muxvals[] = {1};
43 static const unsigned system_bus_cs4_pins[] = {81};
44 static const int system_bus_cs4_muxvals[] = {1};
45 static const unsigned system_bus_cs5_pins[] = {82};
46 static const int system_bus_cs5_muxvals[] = {1};
47 static const unsigned uart0_pins[] = {63, 64};
48 static const int uart0_muxvals[] = {0, 1};
49 static const unsigned uart1_pins[] = {65, 66};
50 static const int uart1_muxvals[] = {0, 1};
51 static const unsigned uart2_pins[] = {96, 102};
52 static const int uart2_muxvals[] = {2, 2};
53 static const unsigned usb0_pins[] = {13, 14};
54 static const int usb0_muxvals[] = {0, 1};
55 static const unsigned usb1_pins[] = {15, 16};
56 static const int usb1_muxvals[] = {0, 1};
57 static const unsigned usb2_pins[] = {17, 18};
58 static const int usb2_muxvals[] = {0, 1};
59 static const unsigned usb3_pins[] = {19, 20};
60 static const int usb3_muxvals[] = {0, 1};
61
62 static const struct uniphier_pinctrl_group uniphier_sld3_groups[] = {
63 UNIPHIER_PINCTRL_GROUP_SPL(emmc),
64 UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
65 UNIPHIER_PINCTRL_GROUP(ether_mii),
66 UNIPHIER_PINCTRL_GROUP(ether_rmii),
67 UNIPHIER_PINCTRL_GROUP(i2c0),
68 UNIPHIER_PINCTRL_GROUP(nand),
69 UNIPHIER_PINCTRL_GROUP(nand_cs1),
70 UNIPHIER_PINCTRL_GROUP(sd),
71 UNIPHIER_PINCTRL_GROUP(system_bus),
72 UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
73 UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
74 UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
75 UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
76 UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
77 UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
78 UNIPHIER_PINCTRL_GROUP_SPL(uart0),
79 UNIPHIER_PINCTRL_GROUP_SPL(uart1),
80 UNIPHIER_PINCTRL_GROUP_SPL(uart2),
81 UNIPHIER_PINCTRL_GROUP(usb0),
82 UNIPHIER_PINCTRL_GROUP(usb1),
83 UNIPHIER_PINCTRL_GROUP(usb2),
84 UNIPHIER_PINCTRL_GROUP(usb3)
85 };
86
87 static const char * const uniphier_sld3_functions[] = {
88 UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
89 UNIPHIER_PINMUX_FUNCTION(ether_mii),
90 UNIPHIER_PINMUX_FUNCTION(ether_rmii),
91 UNIPHIER_PINMUX_FUNCTION(i2c0),
92 UNIPHIER_PINMUX_FUNCTION(nand),
93 UNIPHIER_PINMUX_FUNCTION(sd),
94 UNIPHIER_PINMUX_FUNCTION(system_bus),
95 UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
96 UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
97 UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
98 UNIPHIER_PINMUX_FUNCTION(usb0),
99 UNIPHIER_PINMUX_FUNCTION(usb1),
100 UNIPHIER_PINMUX_FUNCTION(usb2),
101 UNIPHIER_PINMUX_FUNCTION(usb3),
102 };
103
104 static struct uniphier_pinctrl_socdata uniphier_sld3_pinctrl_socdata = {
105 .groups = uniphier_sld3_groups,
106 .groups_count = ARRAY_SIZE(uniphier_sld3_groups),
107 .functions = uniphier_sld3_functions,
108 .functions_count = ARRAY_SIZE(uniphier_sld3_functions),
109 .caps = UNIPHIER_PINCTRL_CAPS_MUX_4BIT,
110 };
111
112 static int uniphier_sld3_pinctrl_probe(struct udevice *dev)
113 {
114 return uniphier_pinctrl_probe(dev, &uniphier_sld3_pinctrl_socdata);
115 }
116
117 static const struct udevice_id uniphier_sld3_pinctrl_match[] = {
118 { .compatible = "socionext,uniphier-sld3-pinctrl" },
119 { /* sentinel */ }
120 };
121
122 U_BOOT_DRIVER(uniphier_sld3_pinctrl) = {
123 .name = "uniphier-sld3-pinctrl",
124 .id = UCLASS_PINCTRL,
125 .of_match = of_match_ptr(uniphier_sld3_pinctrl_match),
126 .probe = uniphier_sld3_pinctrl_probe,
127 .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
128 .ops = &uniphier_pinctrl_ops,
129 };
130 1 /*
drivers/reset/reset-uniphier.c
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2016 Socionext Inc. 2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <dm.h> 9 #include <dm.h>
10 #include <reset-uclass.h> 10 #include <reset-uclass.h>
11 #include <linux/bitops.h> 11 #include <linux/bitops.h>
12 #include <linux/io.h> 12 #include <linux/io.h>
13 #include <linux/sizes.h> 13 #include <linux/sizes.h>
14 14
15 struct uniphier_reset_data { 15 struct uniphier_reset_data {
16 unsigned int id; 16 unsigned int id;
17 unsigned int reg; 17 unsigned int reg;
18 unsigned int bit; 18 unsigned int bit;
19 unsigned int flags; 19 unsigned int flags;
20 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0) 20 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
21 }; 21 };
22 22
23 #define UNIPHIER_RESET_ID_END (unsigned int)(-1) 23 #define UNIPHIER_RESET_ID_END (unsigned int)(-1)
24 24
25 #define UNIPHIER_RESET_END \ 25 #define UNIPHIER_RESET_END \
26 { .id = UNIPHIER_RESET_ID_END } 26 { .id = UNIPHIER_RESET_ID_END }
27 27
28 #define UNIPHIER_RESET(_id, _reg, _bit) \ 28 #define UNIPHIER_RESET(_id, _reg, _bit) \
29 { \ 29 { \
30 .id = (_id), \ 30 .id = (_id), \
31 .reg = (_reg), \ 31 .reg = (_reg), \
32 .bit = (_bit), \ 32 .bit = (_bit), \
33 } 33 }
34 34
35 #define UNIPHIER_RESETX(_id, _reg, _bit) \ 35 #define UNIPHIER_RESETX(_id, _reg, _bit) \
36 { \ 36 { \
37 .id = (_id), \ 37 .id = (_id), \
38 .reg = (_reg), \ 38 .reg = (_reg), \
39 .bit = (_bit), \ 39 .bit = (_bit), \
40 .flags = UNIPHIER_RESET_ACTIVE_LOW, \ 40 .flags = UNIPHIER_RESET_ACTIVE_LOW, \
41 } 41 }
42 42
43 /* System reset data */ 43 /* System reset data */
44 #define UNIPHIER_SLD3_SYS_RESET_STDMAC(id) \ 44 #define UNIPHIER_SLD3_SYS_RESET_STDMAC(id) \
45 UNIPHIER_RESETX((id), 0x2000, 10) 45 UNIPHIER_RESETX((id), 0x2000, 10)
46 46
47 #define UNIPHIER_LD11_SYS_RESET_STDMAC(id) \ 47 #define UNIPHIER_LD11_SYS_RESET_STDMAC(id) \
48 UNIPHIER_RESETX((id), 0x200c, 8) 48 UNIPHIER_RESETX((id), 0x200c, 8)
49 49
50 #define UNIPHIER_PRO4_SYS_RESET_GIO(id) \ 50 #define UNIPHIER_PRO4_SYS_RESET_GIO(id) \
51 UNIPHIER_RESETX((id), 0x2000, 6) 51 UNIPHIER_RESETX((id), 0x2000, 6)
52 52
53 #define UNIPHIER_LD20_SYS_RESET_GIO(id) \ 53 #define UNIPHIER_LD20_SYS_RESET_GIO(id) \
54 UNIPHIER_RESETX((id), 0x200c, 5) 54 UNIPHIER_RESETX((id), 0x200c, 5)
55 55
56 #define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \ 56 #define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \
57 UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17) 57 UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17)
58 58
59 static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = { 59 static const struct uniphier_reset_data uniphier_ld4_sys_reset_data[] = {
60 UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */ 60 UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */
61 UNIPHIER_RESET_END, 61 UNIPHIER_RESET_END,
62 }; 62 };
63 63
64 static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { 64 static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
65 UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */ 65 UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */
66 UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */ 66 UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */
67 UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), 67 UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
68 UNIPHIER_PRO4_SYS_RESET_USB3(15, 1), 68 UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
69 UNIPHIER_RESET_END, 69 UNIPHIER_RESET_END,
70 }; 70 };
71 71
72 static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { 72 static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
73 UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */ 73 UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */
74 UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */ 74 UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */
75 UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), 75 UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
76 UNIPHIER_PRO4_SYS_RESET_USB3(15, 1), 76 UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
77 UNIPHIER_RESET_END, 77 UNIPHIER_RESET_END,
78 }; 78 };
79 79
80 static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { 80 static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
81 UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */ 81 UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */
82 UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), 82 UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
83 UNIPHIER_PRO4_SYS_RESET_USB3(15, 1), 83 UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
84 UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */ 84 UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
85 UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */ 85 UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
86 UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */ 86 UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
87 UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */ 87 UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
88 UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */ 88 UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */
89 UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */ 89 UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */
90 UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */ 90 UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */
91 UNIPHIER_RESET_END, 91 UNIPHIER_RESET_END,
92 }; 92 };
93 93
94 static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = { 94 static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
95 UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */ 95 UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */
96 UNIPHIER_RESET_END, 96 UNIPHIER_RESET_END,
97 }; 97 };
98 98
99 static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { 99 static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
100 UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */ 100 UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */
101 UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */ 101 UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */
102 UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */ 102 UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
103 UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */ 103 UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
104 UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */ 104 UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
105 UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */ 105 UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */
106 UNIPHIER_RESET_END, 106 UNIPHIER_RESET_END,
107 }; 107 };
108 108
109 /* Media I/O reset data */ 109 /* Media I/O reset data */
110 #define UNIPHIER_MIO_RESET_SD(id, ch) \ 110 #define UNIPHIER_MIO_RESET_SD(id, ch) \
111 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0) 111 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
112 112
113 #define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \ 113 #define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \
114 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26) 114 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26)
115 115
116 #define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \ 116 #define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \
117 UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0) 117 UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0)
118 118
119 #define UNIPHIER_MIO_RESET_USB2(id, ch) \ 119 #define UNIPHIER_MIO_RESET_USB2(id, ch) \
120 UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0) 120 UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0)
121 121
122 #define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \ 122 #define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \
123 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24) 123 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)
124 124
125 #define UNIPHIER_MIO_RESET_DMAC(id) \ 125 #define UNIPHIER_MIO_RESET_DMAC(id) \
126 UNIPHIER_RESETX((id), 0x110, 17) 126 UNIPHIER_RESETX((id), 0x110, 17)
127 127
128 static const struct uniphier_reset_data uniphier_mio_reset_data[] = { 128 static const struct uniphier_reset_data uniphier_mio_reset_data[] = {
129 UNIPHIER_MIO_RESET_SD(0, 0), 129 UNIPHIER_MIO_RESET_SD(0, 0),
130 UNIPHIER_MIO_RESET_SD(1, 1), 130 UNIPHIER_MIO_RESET_SD(1, 1),
131 UNIPHIER_MIO_RESET_SD(2, 2), 131 UNIPHIER_MIO_RESET_SD(2, 2),
132 UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0), 132 UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0),
133 UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1), 133 UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1),
134 UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2), 134 UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2),
135 UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1), 135 UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
136 UNIPHIER_MIO_RESET_DMAC(7), 136 UNIPHIER_MIO_RESET_DMAC(7),
137 UNIPHIER_MIO_RESET_USB2(8, 0), 137 UNIPHIER_MIO_RESET_USB2(8, 0),
138 UNIPHIER_MIO_RESET_USB2(9, 1), 138 UNIPHIER_MIO_RESET_USB2(9, 1),
139 UNIPHIER_MIO_RESET_USB2(10, 2), 139 UNIPHIER_MIO_RESET_USB2(10, 2),
140 UNIPHIER_MIO_RESET_USB2(11, 3), 140 UNIPHIER_MIO_RESET_USB2(11, 3),
141 UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0), 141 UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0),
142 UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1), 142 UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1),
143 UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2), 143 UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2),
144 UNIPHIER_MIO_RESET_USB2_BRIDGE(15, 3), 144 UNIPHIER_MIO_RESET_USB2_BRIDGE(15, 3),
145 UNIPHIER_RESET_END, 145 UNIPHIER_RESET_END,
146 }; 146 };
147 147
148 /* Peripheral reset data */ 148 /* Peripheral reset data */
149 #define UNIPHIER_PERI_RESET_UART(id, ch) \ 149 #define UNIPHIER_PERI_RESET_UART(id, ch) \
150 UNIPHIER_RESETX((id), 0x114, 19 + (ch)) 150 UNIPHIER_RESETX((id), 0x114, 19 + (ch))
151 151
152 #define UNIPHIER_PERI_RESET_I2C(id, ch) \ 152 #define UNIPHIER_PERI_RESET_I2C(id, ch) \
153 UNIPHIER_RESETX((id), 0x114, 5 + (ch)) 153 UNIPHIER_RESETX((id), 0x114, 5 + (ch))
154 154
155 #define UNIPHIER_PERI_RESET_FI2C(id, ch) \ 155 #define UNIPHIER_PERI_RESET_FI2C(id, ch) \
156 UNIPHIER_RESETX((id), 0x114, 24 + (ch)) 156 UNIPHIER_RESETX((id), 0x114, 24 + (ch))
157 157
158 static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { 158 static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
159 UNIPHIER_PERI_RESET_UART(0, 0), 159 UNIPHIER_PERI_RESET_UART(0, 0),
160 UNIPHIER_PERI_RESET_UART(1, 1), 160 UNIPHIER_PERI_RESET_UART(1, 1),
161 UNIPHIER_PERI_RESET_UART(2, 2), 161 UNIPHIER_PERI_RESET_UART(2, 2),
162 UNIPHIER_PERI_RESET_UART(3, 3), 162 UNIPHIER_PERI_RESET_UART(3, 3),
163 UNIPHIER_PERI_RESET_I2C(4, 0), 163 UNIPHIER_PERI_RESET_I2C(4, 0),
164 UNIPHIER_PERI_RESET_I2C(5, 1), 164 UNIPHIER_PERI_RESET_I2C(5, 1),
165 UNIPHIER_PERI_RESET_I2C(6, 2), 165 UNIPHIER_PERI_RESET_I2C(6, 2),
166 UNIPHIER_PERI_RESET_I2C(7, 3), 166 UNIPHIER_PERI_RESET_I2C(7, 3),
167 UNIPHIER_PERI_RESET_I2C(8, 4), 167 UNIPHIER_PERI_RESET_I2C(8, 4),
168 UNIPHIER_RESET_END, 168 UNIPHIER_RESET_END,
169 }; 169 };
170 170
171 static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = { 171 static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
172 UNIPHIER_PERI_RESET_UART(0, 0), 172 UNIPHIER_PERI_RESET_UART(0, 0),
173 UNIPHIER_PERI_RESET_UART(1, 1), 173 UNIPHIER_PERI_RESET_UART(1, 1),
174 UNIPHIER_PERI_RESET_UART(2, 2), 174 UNIPHIER_PERI_RESET_UART(2, 2),
175 UNIPHIER_PERI_RESET_UART(3, 3), 175 UNIPHIER_PERI_RESET_UART(3, 3),
176 UNIPHIER_PERI_RESET_FI2C(4, 0), 176 UNIPHIER_PERI_RESET_FI2C(4, 0),
177 UNIPHIER_PERI_RESET_FI2C(5, 1), 177 UNIPHIER_PERI_RESET_FI2C(5, 1),
178 UNIPHIER_PERI_RESET_FI2C(6, 2), 178 UNIPHIER_PERI_RESET_FI2C(6, 2),
179 UNIPHIER_PERI_RESET_FI2C(7, 3), 179 UNIPHIER_PERI_RESET_FI2C(7, 3),
180 UNIPHIER_PERI_RESET_FI2C(8, 4), 180 UNIPHIER_PERI_RESET_FI2C(8, 4),
181 UNIPHIER_PERI_RESET_FI2C(9, 5), 181 UNIPHIER_PERI_RESET_FI2C(9, 5),
182 UNIPHIER_PERI_RESET_FI2C(10, 6), 182 UNIPHIER_PERI_RESET_FI2C(10, 6),
183 UNIPHIER_RESET_END, 183 UNIPHIER_RESET_END,
184 }; 184 };
185 185
186 /* core implementaton */ 186 /* core implementaton */
187 struct uniphier_reset_priv { 187 struct uniphier_reset_priv {
188 void __iomem *base; 188 void __iomem *base;
189 const struct uniphier_reset_data *data; 189 const struct uniphier_reset_data *data;
190 }; 190 };
191 191
192 static int uniphier_reset_request(struct reset_ctl *reset_ctl) 192 static int uniphier_reset_request(struct reset_ctl *reset_ctl)
193 { 193 {
194 return 0; 194 return 0;
195 } 195 }
196 196
197 static int uniphier_reset_free(struct reset_ctl *reset_ctl) 197 static int uniphier_reset_free(struct reset_ctl *reset_ctl)
198 { 198 {
199 return 0; 199 return 0;
200 } 200 }
201 201
202 static int uniphier_reset_update(struct reset_ctl *reset_ctl, int assert) 202 static int uniphier_reset_update(struct reset_ctl *reset_ctl, int assert)
203 { 203 {
204 struct uniphier_reset_priv *priv = dev_get_priv(reset_ctl->dev); 204 struct uniphier_reset_priv *priv = dev_get_priv(reset_ctl->dev);
205 unsigned long id = reset_ctl->id; 205 unsigned long id = reset_ctl->id;
206 const struct uniphier_reset_data *p; 206 const struct uniphier_reset_data *p;
207 207
208 for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) { 208 for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
209 u32 mask, val; 209 u32 mask, val;
210 210
211 if (p->id != id) 211 if (p->id != id)
212 continue; 212 continue;
213 213
214 val = readl(priv->base + p->reg); 214 val = readl(priv->base + p->reg);
215 215
216 if (p->flags & UNIPHIER_RESET_ACTIVE_LOW) 216 if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
217 assert = !assert; 217 assert = !assert;
218 218
219 mask = BIT(p->bit); 219 mask = BIT(p->bit);
220 220
221 if (assert) 221 if (assert)
222 val |= mask; 222 val |= mask;
223 else 223 else
224 val &= ~mask; 224 val &= ~mask;
225 225
226 writel(val, priv->base + p->reg); 226 writel(val, priv->base + p->reg);
227 227
228 return 0; 228 return 0;
229 } 229 }
230 230
231 dev_err(priv->dev, "reset_id=%lu was not handled\n", id); 231 dev_err(priv->dev, "reset_id=%lu was not handled\n", id);
232 return -EINVAL; 232 return -EINVAL;
233 } 233 }
234 234
235 static int uniphier_reset_assert(struct reset_ctl *reset_ctl) 235 static int uniphier_reset_assert(struct reset_ctl *reset_ctl)
236 { 236 {
237 return uniphier_reset_update(reset_ctl, 1); 237 return uniphier_reset_update(reset_ctl, 1);
238 } 238 }
239 239
240 static int uniphier_reset_deassert(struct reset_ctl *reset_ctl) 240 static int uniphier_reset_deassert(struct reset_ctl *reset_ctl)
241 { 241 {
242 return uniphier_reset_update(reset_ctl, 0); 242 return uniphier_reset_update(reset_ctl, 0);
243 } 243 }
244 244
245 static const struct reset_ops uniphier_reset_ops = { 245 static const struct reset_ops uniphier_reset_ops = {
246 .request = uniphier_reset_request, 246 .request = uniphier_reset_request,
247 .free = uniphier_reset_free, 247 .free = uniphier_reset_free,
248 .rst_assert = uniphier_reset_assert, 248 .rst_assert = uniphier_reset_assert,
249 .rst_deassert = uniphier_reset_deassert, 249 .rst_deassert = uniphier_reset_deassert,
250 }; 250 };
251 251
252 static int uniphier_reset_probe(struct udevice *dev) 252 static int uniphier_reset_probe(struct udevice *dev)
253 { 253 {
254 struct uniphier_reset_priv *priv = dev_get_priv(dev); 254 struct uniphier_reset_priv *priv = dev_get_priv(dev);
255 fdt_addr_t addr; 255 fdt_addr_t addr;
256 256
257 addr = devfdt_get_addr(dev->parent); 257 addr = devfdt_get_addr(dev->parent);
258 if (addr == FDT_ADDR_T_NONE) 258 if (addr == FDT_ADDR_T_NONE)
259 return -EINVAL; 259 return -EINVAL;
260 260
261 priv->base = devm_ioremap(dev, addr, SZ_4K); 261 priv->base = devm_ioremap(dev, addr, SZ_4K);
262 if (!priv->base) 262 if (!priv->base)
263 return -ENOMEM; 263 return -ENOMEM;
264 264
265 priv->data = (void *)dev_get_driver_data(dev); 265 priv->data = (void *)dev_get_driver_data(dev);
266 266
267 return 0; 267 return 0;
268 } 268 }
269 269
270 static const struct udevice_id uniphier_reset_match[] = { 270 static const struct udevice_id uniphier_reset_match[] = {
271 /* System reset */ 271 /* System reset */
272 { 272 {
273 .compatible = "socionext,uniphier-sld3-reset",
274 .data = (ulong)uniphier_sld3_sys_reset_data,
275 },
276 {
277 .compatible = "socionext,uniphier-ld4-reset", 273 .compatible = "socionext,uniphier-ld4-reset",
278 .data = (ulong)uniphier_sld3_sys_reset_data, 274 .data = (ulong)uniphier_ld4_sys_reset_data,
279 }, 275 },
280 { 276 {
281 .compatible = "socionext,uniphier-pro4-reset", 277 .compatible = "socionext,uniphier-pro4-reset",
282 .data = (ulong)uniphier_pro4_sys_reset_data, 278 .data = (ulong)uniphier_pro4_sys_reset_data,
283 }, 279 },
284 { 280 {
285 .compatible = "socionext,uniphier-sld8-reset", 281 .compatible = "socionext,uniphier-sld8-reset",
286 .data = (ulong)uniphier_sld3_sys_reset_data, 282 .data = (ulong)uniphier_ld4_sys_reset_data,
287 }, 283 },
288 { 284 {
289 .compatible = "socionext,uniphier-pro5-reset", 285 .compatible = "socionext,uniphier-pro5-reset",
290 .data = (ulong)uniphier_pro5_sys_reset_data, 286 .data = (ulong)uniphier_pro5_sys_reset_data,
291 }, 287 },
292 { 288 {
293 .compatible = "socionext,uniphier-pxs2-reset", 289 .compatible = "socionext,uniphier-pxs2-reset",
294 .data = (ulong)uniphier_pxs2_sys_reset_data, 290 .data = (ulong)uniphier_pxs2_sys_reset_data,
295 }, 291 },
296 { 292 {
297 .compatible = "socionext,uniphier-ld11-reset", 293 .compatible = "socionext,uniphier-ld11-reset",
298 .data = (ulong)uniphier_ld11_sys_reset_data, 294 .data = (ulong)uniphier_ld11_sys_reset_data,
299 }, 295 },
300 { 296 {
301 .compatible = "socionext,uniphier-ld20-reset", 297 .compatible = "socionext,uniphier-ld20-reset",
302 .data = (ulong)uniphier_ld20_sys_reset_data, 298 .data = (ulong)uniphier_ld20_sys_reset_data,
303 }, 299 },
304 /* Media I/O reset */ 300 /* Media I/O reset */
305 {
306 .compatible = "socionext,uniphier-sld3-mio-clock",
307 .data = (ulong)uniphier_mio_reset_data,
308 },
309 { 301 {
310 .compatible = "socionext,uniphier-ld4-mio-reset", 302 .compatible = "socionext,uniphier-ld4-mio-reset",
311 .data = (ulong)uniphier_mio_reset_data, 303 .data = (ulong)uniphier_mio_reset_data,
312 }, 304 },
313 { 305 {
314 .compatible = "socionext,uniphier-pro4-mio-reset", 306 .compatible = "socionext,uniphier-pro4-mio-reset",
315 .data = (ulong)uniphier_mio_reset_data, 307 .data = (ulong)uniphier_mio_reset_data,
316 }, 308 },
317 { 309 {
318 .compatible = "socionext,uniphier-sld8-mio-reset", 310 .compatible = "socionext,uniphier-sld8-mio-reset",
319 .data = (ulong)uniphier_mio_reset_data, 311 .data = (ulong)uniphier_mio_reset_data,
320 }, 312 },
321 { 313 {
322 .compatible = "socionext,uniphier-pro5-mio-reset", 314 .compatible = "socionext,uniphier-pro5-mio-reset",
323 .data = (ulong)uniphier_mio_reset_data, 315 .data = (ulong)uniphier_mio_reset_data,
324 }, 316 },
325 { 317 {
326 .compatible = "socionext,uniphier-pxs2-mio-reset", 318 .compatible = "socionext,uniphier-pxs2-mio-reset",
327 .data = (ulong)uniphier_mio_reset_data, 319 .data = (ulong)uniphier_mio_reset_data,
328 }, 320 },
329 { 321 {
330 .compatible = "socionext,uniphier-ld11-mio-reset", 322 .compatible = "socionext,uniphier-ld11-mio-reset",
331 .data = (ulong)uniphier_mio_reset_data, 323 .data = (ulong)uniphier_mio_reset_data,
332 }, 324 },
333 { 325 {
334 .compatible = "socionext,uniphier-ld20-mio-reset", 326 .compatible = "socionext,uniphier-ld20-mio-reset",
335 .data = (ulong)uniphier_mio_reset_data, 327 .data = (ulong)uniphier_mio_reset_data,
336 }, 328 },
337 /* Peripheral reset */ 329 /* Peripheral reset */
338 { 330 {
339 .compatible = "socionext,uniphier-ld4-peri-reset", 331 .compatible = "socionext,uniphier-ld4-peri-reset",
340 .data = (ulong)uniphier_ld4_peri_reset_data, 332 .data = (ulong)uniphier_ld4_peri_reset_data,
341 }, 333 },
342 { 334 {
343 .compatible = "socionext,uniphier-pro4-peri-reset", 335 .compatible = "socionext,uniphier-pro4-peri-reset",
344 .data = (ulong)uniphier_pro4_peri_reset_data, 336 .data = (ulong)uniphier_pro4_peri_reset_data,
345 }, 337 },
346 { 338 {
347 .compatible = "socionext,uniphier-sld8-peri-reset", 339 .compatible = "socionext,uniphier-sld8-peri-reset",
348 .data = (ulong)uniphier_ld4_peri_reset_data, 340 .data = (ulong)uniphier_ld4_peri_reset_data,
349 }, 341 },
350 { 342 {
351 .compatible = "socionext,uniphier-pro5-peri-reset", 343 .compatible = "socionext,uniphier-pro5-peri-reset",
352 .data = (ulong)uniphier_pro4_peri_reset_data, 344 .data = (ulong)uniphier_pro4_peri_reset_data,
353 }, 345 },
354 { 346 {
355 .compatible = "socionext,uniphier-pxs2-peri-reset", 347 .compatible = "socionext,uniphier-pxs2-peri-reset",
356 .data = (ulong)uniphier_pro4_peri_reset_data, 348 .data = (ulong)uniphier_pro4_peri_reset_data,
357 }, 349 },
358 { 350 {
359 .compatible = "socionext,uniphier-ld11-peri-reset", 351 .compatible = "socionext,uniphier-ld11-peri-reset",
360 .data = (ulong)uniphier_pro4_peri_reset_data, 352 .data = (ulong)uniphier_pro4_peri_reset_data,
361 }, 353 },
362 { 354 {
363 .compatible = "socionext,uniphier-ld20-peri-reset", 355 .compatible = "socionext,uniphier-ld20-peri-reset",
364 .data = (ulong)uniphier_pro4_peri_reset_data, 356 .data = (ulong)uniphier_pro4_peri_reset_data,
365 }, 357 },
366 { /* sentinel */ } 358 { /* sentinel */ }
367 }; 359 };
368 360
369 U_BOOT_DRIVER(uniphier_reset) = { 361 U_BOOT_DRIVER(uniphier_reset) = {
370 .name = "uniphier-reset", 362 .name = "uniphier-reset",
371 .id = UCLASS_RESET, 363 .id = UCLASS_RESET,
372 .of_match = uniphier_reset_match, 364 .of_match = uniphier_reset_match,
373 .probe = uniphier_reset_probe, 365 .probe = uniphier_reset_probe,
374 .priv_auto_alloc_size = sizeof(struct uniphier_reset_priv), 366 .priv_auto_alloc_size = sizeof(struct uniphier_reset_priv),
375 .ops = &uniphier_reset_ops, 367 .ops = &uniphier_reset_ops,
376 }; 368 };
377 369
include/configs/uniphier.h
Diff comments   View file @ 00aa453
1 /* 1 /*
2 * Copyright (C) 2012-2015 Panasonic Corporation 2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc. 3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 /* U-Boot - Common settings for UniPhier Family */ 9 /* U-Boot - Common settings for UniPhier Family */
10 10
11 #ifndef __CONFIG_UNIPHIER_COMMON_H__ 11 #ifndef __CONFIG_UNIPHIER_COMMON_H__
12 #define __CONFIG_UNIPHIER_COMMON_H__ 12 #define __CONFIG_UNIPHIER_COMMON_H__
13 13
14 #define CONFIG_ARMV7_PSCI_1_0 14 #define CONFIG_ARMV7_PSCI_1_0
15 15
16 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 16 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
17 17
18 /*----------------------------------------------------------------------- 18 /*-----------------------------------------------------------------------
19 * MMU and Cache Setting 19 * MMU and Cache Setting
20 *----------------------------------------------------------------------*/ 20 *----------------------------------------------------------------------*/
21 21
22 /* Comment out the following to enable L1 cache */ 22 /* Comment out the following to enable L1 cache */
23 /* #define CONFIG_SYS_ICACHE_OFF */ 23 /* #define CONFIG_SYS_ICACHE_OFF */
24 /* #define CONFIG_SYS_DCACHE_OFF */ 24 /* #define CONFIG_SYS_DCACHE_OFF */
25 25
26 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 26 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
27 27
28 #define CONFIG_TIMESTAMP 28 #define CONFIG_TIMESTAMP
29 29
30 /* FLASH related */ 30 /* FLASH related */
31 #define CONFIG_MTD_DEVICE 31 #define CONFIG_MTD_DEVICE
32 32
33 #define CONFIG_SMC911X_32_BIT 33 #define CONFIG_SMC911X_32_BIT
34 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ 34 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */
35 #define CONFIG_SMC911X_BASE 0 35 #define CONFIG_SMC911X_BASE 0
36 36
37 #ifdef CONFIG_MICRO_SUPPORT_CARD 37 #ifdef CONFIG_MICRO_SUPPORT_CARD
38 #define CONFIG_SMC911X 38 #define CONFIG_SMC911X
39 #endif 39 #endif
40 40
41 #define CONFIG_FLASH_CFI_DRIVER 41 #define CONFIG_FLASH_CFI_DRIVER
42 #define CONFIG_SYS_FLASH_CFI 42 #define CONFIG_SYS_FLASH_CFI
43 43
44 #define CONFIG_SYS_MAX_FLASH_SECT 256 44 #define CONFIG_SYS_MAX_FLASH_SECT 256
45 #define CONFIG_SYS_MONITOR_BASE 0 45 #define CONFIG_SYS_MONITOR_BASE 0
46 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ 46 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */
47 #define CONFIG_SYS_FLASH_BASE 0 47 #define CONFIG_SYS_FLASH_BASE 0
48 48
49 /* 49 /*
50 * flash_toggle does not work for our support card. 50 * flash_toggle does not work for our support card.
51 * We need to use flash_status_poll. 51 * We need to use flash_status_poll.
52 */ 52 */
53 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 53 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
54 54
55 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 55 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
56 56
57 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 57 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
58 58
59 /* serial console configuration */ 59 /* serial console configuration */
60 60
61 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 61 #define CONFIG_SYS_LONGHELP /* undef to save memory */
62 62
63 #define CONFIG_CMDLINE_EDITING /* add command line history */ 63 #define CONFIG_CMDLINE_EDITING /* add command line history */
64 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 64 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
65 /* Print Buffer Size */ 65 /* Print Buffer Size */
66 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 66 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
67 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 67 #define CONFIG_SYS_MAXARGS 16 /* max number of command */
68 /* Boot Argument Buffer Size */ 68 /* Boot Argument Buffer Size */
69 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 69 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
70 70
71 #define CONFIG_CONS_INDEX 1 71 #define CONFIG_CONS_INDEX 1
72 72
73 #define CONFIG_ENV_OFFSET 0x100000 73 #define CONFIG_ENV_OFFSET 0x100000
74 #define CONFIG_ENV_SIZE 0x2000 74 #define CONFIG_ENV_SIZE 0x2000
75 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ 75 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
76 76
77 #define CONFIG_SYS_MMC_ENV_DEV 0 77 #define CONFIG_SYS_MMC_ENV_DEV 0
78 #define CONFIG_SYS_MMC_ENV_PART 1 78 #define CONFIG_SYS_MMC_ENV_PART 1
79 79
80 #if !defined(CONFIG_ARM64) 80 #if !defined(CONFIG_ARM64)
81 /* Time clock 1MHz */ 81 /* Time clock 1MHz */
82 #define CONFIG_SYS_TIMER_RATE 1000000 82 #define CONFIG_SYS_TIMER_RATE 1000000
83 #endif 83 #endif
84 84
85 #define CONFIG_SYS_MAX_NAND_DEVICE 1 85 #define CONFIG_SYS_MAX_NAND_DEVICE 1
86 #define CONFIG_SYS_NAND_MAX_CHIPS 2 86 #define CONFIG_SYS_NAND_MAX_CHIPS 2
87 #define CONFIG_SYS_NAND_ONFI_DETECTION 87 #define CONFIG_SYS_NAND_ONFI_DETECTION
88 88
89 #define CONFIG_NAND_DENALI_ECC_SIZE 1024 89 #define CONFIG_NAND_DENALI_ECC_SIZE 1024
90 90
91 #ifdef CONFIG_ARCH_UNIPHIER_SLD3
92 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
93 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
94 #else
95 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 91 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000
96 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 92 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000
97 #endif
98 93
99 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 94 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
100 95
101 #define CONFIG_SYS_NAND_USE_FLASH_BBT 96 #define CONFIG_SYS_NAND_USE_FLASH_BBT
102 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 97 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
103 98
104 /* SD/MMC */ 99 /* SD/MMC */
105 #define CONFIG_SUPPORT_EMMC_BOOT 100 #define CONFIG_SUPPORT_EMMC_BOOT
106 101
107 /* memtest works on */ 102 /* memtest works on */
108 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 103 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
109 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) 104 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
110 105
111 /* 106 /*
112 * Network Configuration 107 * Network Configuration
113 */ 108 */
114 #define CONFIG_SERVERIP 192.168.11.1 109 #define CONFIG_SERVERIP 192.168.11.1
115 #define CONFIG_IPADDR 192.168.11.10 110 #define CONFIG_IPADDR 192.168.11.10
116 #define CONFIG_GATEWAYIP 192.168.11.1 111 #define CONFIG_GATEWAYIP 192.168.11.1
117 #define CONFIG_NETMASK 255.255.255.0 112 #define CONFIG_NETMASK 255.255.255.0
118 113
119 #define CONFIG_LOADADDR 0x84000000 114 #define CONFIG_LOADADDR 0x84000000
120 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 115 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
121 116
122 #define CONFIG_CMDLINE_EDITING /* add command line history */ 117 #define CONFIG_CMDLINE_EDITING /* add command line history */
123 118
124 #if defined(CONFIG_ARM64) 119 #if defined(CONFIG_ARM64)
125 /* ARM Trusted Firmware */ 120 /* ARM Trusted Firmware */
126 #define BOOT_IMAGES \ 121 #define BOOT_IMAGES \
127 "second_image=unph_bl.bin\0" \ 122 "second_image=unph_bl.bin\0" \
128 "third_image=fip.bin\0" 123 "third_image=fip.bin\0"
129 #else 124 #else
130 #define BOOT_IMAGES \ 125 #define BOOT_IMAGES \
131 "second_image=u-boot-spl.bin\0" \ 126 "second_image=u-boot-spl.bin\0" \
132 "third_image=u-boot.bin\0" 127 "third_image=u-boot.bin\0"
133 #endif 128 #endif
134 129
135 #define CONFIG_BOOTCOMMAND "run $bootmode" 130 #define CONFIG_BOOTCOMMAND "run $bootmode"
136 131
137 #define CONFIG_ROOTPATH "/nfs/root/path" 132 #define CONFIG_ROOTPATH "/nfs/root/path"
138 #define CONFIG_NFSBOOTCOMMAND \ 133 #define CONFIG_NFSBOOTCOMMAND \
139 "setenv bootargs $bootargs root=/dev/nfs rw " \ 134 "setenv bootargs $bootargs root=/dev/nfs rw " \
140 "nfsroot=$serverip:$rootpath " \ 135 "nfsroot=$serverip:$rootpath " \
141 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ 136 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
142 "run __nfsboot" 137 "run __nfsboot"
143 138
144 #ifdef CONFIG_FIT 139 #ifdef CONFIG_FIT
145 #define CONFIG_BOOTFILE "fitImage" 140 #define CONFIG_BOOTFILE "fitImage"
146 #define LINUXBOOT_ENV_SETTINGS \ 141 #define LINUXBOOT_ENV_SETTINGS \
147 "fit_addr=0x00100000\0" \ 142 "fit_addr=0x00100000\0" \
148 "fit_addr_r=0x84100000\0" \ 143 "fit_addr_r=0x84100000\0" \
149 "fit_size=0x00f00000\0" \ 144 "fit_size=0x00f00000\0" \
150 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ 145 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
151 "bootm $fit_addr\0" \ 146 "bootm $fit_addr\0" \
152 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ 147 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
153 "bootm $fit_addr_r\0" \ 148 "bootm $fit_addr_r\0" \
154 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ 149 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \
155 "bootm $fit_addr_r\0" \ 150 "bootm $fit_addr_r\0" \
156 "__nfsboot=run tftpboot\0" 151 "__nfsboot=run tftpboot\0"
157 #else 152 #else
158 #ifdef CONFIG_ARM64 153 #ifdef CONFIG_ARM64
159 #define CONFIG_BOOTFILE "Image.gz" 154 #define CONFIG_BOOTFILE "Image.gz"
160 #define LINUXBOOT_CMD "booti" 155 #define LINUXBOOT_CMD "booti"
161 #define KERNEL_ADDR_LOAD "kernel_addr_load=0x84200000\0" 156 #define KERNEL_ADDR_LOAD "kernel_addr_load=0x84200000\0"
162 #define KERNEL_ADDR_R "kernel_addr_r=0x82080000\0" 157 #define KERNEL_ADDR_R "kernel_addr_r=0x82080000\0"
163 #else 158 #else
164 #define CONFIG_BOOTFILE "zImage" 159 #define CONFIG_BOOTFILE "zImage"
165 #define LINUXBOOT_CMD "bootz" 160 #define LINUXBOOT_CMD "bootz"
166 #define KERNEL_ADDR_LOAD "kernel_addr_load=0x80208000\0" 161 #define KERNEL_ADDR_LOAD "kernel_addr_load=0x80208000\0"
167 #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" 162 #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0"
168 #endif 163 #endif
169 #define LINUXBOOT_ENV_SETTINGS \ 164 #define LINUXBOOT_ENV_SETTINGS \
170 "fdt_addr=0x00100000\0" \ 165 "fdt_addr=0x00100000\0" \
171 "fdt_addr_r=0x84100000\0" \ 166 "fdt_addr_r=0x84100000\0" \
172 "fdt_size=0x00008000\0" \ 167 "fdt_size=0x00008000\0" \
173 "kernel_addr=0x00200000\0" \ 168 "kernel_addr=0x00200000\0" \
174 KERNEL_ADDR_LOAD \ 169 KERNEL_ADDR_LOAD \
175 KERNEL_ADDR_R \ 170 KERNEL_ADDR_R \
176 "kernel_size=0x00800000\0" \ 171 "kernel_size=0x00800000\0" \
177 "ramdisk_addr=0x00a00000\0" \ 172 "ramdisk_addr=0x00a00000\0" \
178 "ramdisk_addr_r=0x84a00000\0" \ 173 "ramdisk_addr_r=0x84a00000\0" \
179 "ramdisk_size=0x00600000\0" \ 174 "ramdisk_size=0x00600000\0" \
180 "ramdisk_file=rootfs.cpio.uboot\0" \ 175 "ramdisk_file=rootfs.cpio.uboot\0" \
181 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \ 176 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \
182 "if test $kernel_addr_load = $kernel_addr_r; then " \ 177 "if test $kernel_addr_load = $kernel_addr_r; then " \
183 "true; " \ 178 "true; " \
184 "else " \ 179 "else " \
185 "unzip $kernel_addr_load $kernel_addr_r; " \ 180 "unzip $kernel_addr_load $kernel_addr_r; " \
186 "fi && " \ 181 "fi && " \
187 LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ 182 LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
188 "norboot=setexpr kernel_addr_nor $nor_base + $kernel_addr && " \ 183 "norboot=setexpr kernel_addr_nor $nor_base + $kernel_addr && " \
189 "setexpr kernel_size_div4 $kernel_size / 4 && " \ 184 "setexpr kernel_size_div4 $kernel_size / 4 && " \
190 "cp $kernel_addr_nor $kernel_addr_load $kernel_size_div4 && " \ 185 "cp $kernel_addr_nor $kernel_addr_load $kernel_size_div4 && " \
191 "setexpr ramdisk_addr_nor $nor_base + $ramdisk_addr && " \ 186 "setexpr ramdisk_addr_nor $nor_base + $ramdisk_addr && " \
192 "setexpr ramdisk_size_div4 $ramdisk_size / 4 && " \ 187 "setexpr ramdisk_size_div4 $ramdisk_size / 4 && " \
193 "cp $ramdisk_addr_nor $ramdisk_addr_r $ramdisk_size_div4 && " \ 188 "cp $ramdisk_addr_nor $ramdisk_addr_r $ramdisk_size_div4 && " \
194 "setexpr fdt_addr_nor $nor_base + $fdt_addr && " \ 189 "setexpr fdt_addr_nor $nor_base + $fdt_addr && " \
195 "setexpr fdt_size_div4 $fdt_size / 4 && " \ 190 "setexpr fdt_size_div4 $fdt_size / 4 && " \
196 "cp $fdt_addr_nor $fdt_addr_r $fdt_size_div4 && " \ 191 "cp $fdt_addr_nor $fdt_addr_r $fdt_size_div4 && " \
197 "run boot_common\0" \ 192 "run boot_common\0" \
198 "nandboot=nand read $kernel_addr_load $kernel_addr $kernel_size && " \ 193 "nandboot=nand read $kernel_addr_load $kernel_addr $kernel_size && " \
199 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ 194 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
200 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ 195 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
201 "run boot_common\0" \ 196 "run boot_common\0" \
202 "tftpboot=tftpboot $kernel_addr_load $bootfile && " \ 197 "tftpboot=tftpboot $kernel_addr_load $bootfile && " \
203 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ 198 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \
204 "tftpboot $fdt_addr_r $fdt_file &&" \ 199 "tftpboot $fdt_addr_r $fdt_file &&" \
205 "run boot_common\0" \ 200 "run boot_common\0" \
206 "__nfsboot=tftpboot $kernel_addr_load $bootfile && " \ 201 "__nfsboot=tftpboot $kernel_addr_load $bootfile && " \
207 "tftpboot $fdt_addr_r $fdt_file &&" \ 202 "tftpboot $fdt_addr_r $fdt_file &&" \
208 "setenv ramdisk_addr_r - &&" \ 203 "setenv ramdisk_addr_r - &&" \
209 "run boot_common\0" 204 "run boot_common\0"
210 #endif 205 #endif
211 206
212 #define CONFIG_EXTRA_ENV_SETTINGS \ 207 #define CONFIG_EXTRA_ENV_SETTINGS \
213 "netdev=eth0\0" \ 208 "netdev=eth0\0" \
214 "verify=n\0" \ 209 "verify=n\0" \
215 "initrd_high=0xffffffffffffffff\0" \ 210 "initrd_high=0xffffffffffffffff\0" \
216 "nor_base=0x42000000\0" \ 211 "nor_base=0x42000000\0" \
217 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ 212 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
218 "tftpboot $tmp_addr $second_image && " \ 213 "tftpboot $tmp_addr $second_image && " \
219 "setexpr tmp_addr $nor_base + 0x70000 && " \ 214 "setexpr tmp_addr $nor_base + 0x70000 && " \
220 "tftpboot $tmp_addr $third_image\0" \ 215 "tftpboot $tmp_addr $third_image\0" \
221 "emmcupdate=mmcsetn &&" \ 216 "emmcupdate=mmcsetn &&" \
222 "mmc partconf $mmc_first_dev 0 1 1 &&" \ 217 "mmc partconf $mmc_first_dev 0 1 1 &&" \
223 "tftpboot $second_image && " \ 218 "tftpboot $second_image && " \
224 "mmc write $loadaddr 0 100 && " \ 219 "mmc write $loadaddr 0 100 && " \
225 "tftpboot $third_image && " \ 220 "tftpboot $third_image && " \
226 "mmc write $loadaddr 100 700\0" \ 221 "mmc write $loadaddr 100 700\0" \
227 "nandupdate=nand erase 0 0x00100000 &&" \ 222 "nandupdate=nand erase 0 0x00100000 &&" \
228 "tftpboot $second_image && " \ 223 "tftpboot $second_image && " \
229 "nand write $loadaddr 0 0x00020000 && " \ 224 "nand write $loadaddr 0 0x00020000 && " \
230 "tftpboot $third_image && " \ 225 "tftpboot $third_image && " \
231 "nand write $loadaddr 0x00020000 0x000e0000\0" \ 226 "nand write $loadaddr 0x00020000 0x000e0000\0" \
232 "usbupdate=usb start &&" \ 227 "usbupdate=usb start &&" \
233 "tftpboot $second_image && " \ 228 "tftpboot $second_image && " \
234 "usb write $loadaddr 0 100 && " \ 229 "usb write $loadaddr 0 100 && " \
235 "tftpboot $third_image && " \ 230 "tftpboot $third_image && " \
236 "usb write $loadaddr 100 700\0" \ 231 "usb write $loadaddr 100 700\0" \
237 BOOT_IMAGES \ 232 BOOT_IMAGES \
238 LINUXBOOT_ENV_SETTINGS 233 LINUXBOOT_ENV_SETTINGS
239 234
240 #define CONFIG_SYS_BOOTMAPSZ 0x20000000 235 #define CONFIG_SYS_BOOTMAPSZ 0x20000000
241 236
242 #define CONFIG_SYS_SDRAM_BASE 0x80000000 237 #define CONFIG_SYS_SDRAM_BASE 0x80000000
243 #define CONFIG_NR_DRAM_BANKS 3 238 #define CONFIG_NR_DRAM_BANKS 3
244 /* for LD20; the last 64 byte is used for dynamic DDR PHY training */ 239 /* for LD20; the last 64 byte is used for dynamic DDR PHY training */
245 #define CONFIG_SYS_MEM_TOP_HIDE 64 240 #define CONFIG_SYS_MEM_TOP_HIDE 64
246 241
247 #define CONFIG_PANIC_HANG 242 #define CONFIG_PANIC_HANG
248 243
249 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) 244 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
250 245
251 /* only for SPL */ 246 /* only for SPL */
252 #if defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ 247 #if defined(CONFIG_ARCH_UNIPHIER_LD4) || \
253 defined(CONFIG_ARCH_UNIPHIER_LD4) || \
254 defined(CONFIG_ARCH_UNIPHIER_SLD8) 248 defined(CONFIG_ARCH_UNIPHIER_SLD8)
255 #define CONFIG_SPL_TEXT_BASE 0x00040000 249 #define CONFIG_SPL_TEXT_BASE 0x00040000
256 #else 250 #else
257 #define CONFIG_SPL_TEXT_BASE 0x00100000 251 #define CONFIG_SPL_TEXT_BASE 0x00100000
258 #endif 252 #endif
259 253
260 #define CONFIG_SPL_STACK (0x00100000) 254 #define CONFIG_SPL_STACK (0x00100000)
261 255
262 #define CONFIG_SPL_FRAMEWORK 256 #define CONFIG_SPL_FRAMEWORK
263 257
264 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 258 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
265 259
266 /* subtract sizeof(struct image_header) */ 260 /* subtract sizeof(struct image_header) */
267 #define CONFIG_SYS_UBOOT_BASE (0x70000 - 0x40) 261 #define CONFIG_SYS_UBOOT_BASE (0x70000 - 0x40)
268 262
269 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 263 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
270 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 264 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000
271 #define CONFIG_SPL_MAX_SIZE 0x10000 265 #define CONFIG_SPL_MAX_SIZE 0x10000
272 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 266 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000
273 267
274 #define CONFIG_SPL_PAD_TO 0x20000 268 #define CONFIG_SPL_PAD_TO 0x20000
275 269
276 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ 270 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */
277 271