Eric Lee / smarc-uboot

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Commit 00aa453ebf56fc3a2bd5b684467bc912ba59c4d6

Authored by Masahiro Yamada
1 parent 213fcabdfd
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ARM: uniphier: remove sLD3 SoC support 

This SoC is too old.  It is difficult to maintain any longer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Showing 46 changed files with 89 additions and 1164 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ 00aa453
... ... @@ -119,8 +119,6 @@
119 119 uniphier-pxs2-vodka.dtb
120 120 dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \
121 121 uniphier-pxs3-ref.dtb
122   -dtb-$(CONFIG_ARCH_UNIPHIER_SLD3) += \
123   - uniphier-sld3-ref.dtb
124 122 dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
125 123 uniphier-sld8-ref.dtb
126 124  
arch/arm/dts/uniphier-sld3-ref.dts
View file @ 00aa453
1   -/*
2   - * Device Tree Source for UniPhier sLD3 Reference Board
3   - *
4   - * Copyright (C) 2015-2016 Socionext Inc.
5   - * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6   - *
7   - * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8   - */
9   -
10   -/dts-v1/;
11   -/include/ "uniphier-sld3.dtsi"
12   -/include/ "uniphier-ref-daughter.dtsi"
13   -/include/ "uniphier-support-card.dtsi"
14   -
15   -/ {
16   - model = "UniPhier sLD3 Reference Board";
17   - compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3";
18   -
19   - chosen {
20   - stdout-path = "serial0:115200n8";
21   - };
22   -
23   - aliases {
24   - serial0 = &serial0;
25   - serial1 = &serial1;
26   - serial2 = &serial2;
27   - i2c0 = &i2c0;
28   - i2c1 = &i2c1;
29   - i2c2 = &i2c2;
30   - i2c3 = &i2c3;
31   - i2c4 = &i2c4;
32   - };
33   -
34   - memory@8000000 {
35   - device_type = "memory";
36   - reg = <0x80000000 0x20000000
37   - 0xc0000000 0x20000000>;
38   - };
39   -};
40   -
41   -&ethsc {
42   - interrupts = <0 49 4>;
43   -};
44   -
45   -&serial0 {
46   - status = "okay";
47   -};
48   -
49   -&serial1 {
50   - status = "okay";
51   -};
52   -
53   -&serial2 {
54   - status = "okay";
55   -};
56   -
57   -&i2c0 {
58   - status = "okay";
59   -};
60   -
61   -&emmc {
62   - status = "okay";
63   -};
64   -
65   -&sd {
66   - status = "okay";
67   -};
68   -
69   -&usb0 {
70   - status = "okay";
71   -};
72   -
73   -&usb1 {
74   - status = "okay";
75   -};
76   -
77   -&usb2 {
78   - status = "okay";
79   -};
80   -
81   -&usb3 {
82   - status = "okay";
83   -};
84   -
85   -/* for U-Boot only */
86   -&serial0 {
87   - u-boot,dm-pre-reloc;
88   -};
89   -
90   -&emmc {
91   - u-boot,dm-pre-reloc;
92   -};
93   -
94   -&pinctrl_uart0 {
95   - u-boot,dm-pre-reloc;
96   -};
97   -
98   -&pinctrl_emmc {
99   - u-boot,dm-pre-reloc;
100   -};
arch/arm/dts/uniphier-sld3.dtsi
View file @ 00aa453
1   -/*
2   - * Device Tree Source for UniPhier sLD3 SoC
3   - *
4   - * Copyright (C) 2015-2016 Socionext Inc.
5   - * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6   - *
7   - * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8   - */
9   -
10   -/ {
11   - compatible = "socionext,uniphier-sld3";
12   - #address-cells = <1>;
13   - #size-cells = <1>;
14   -
15   - cpus {
16   - #address-cells = <1>;
17   - #size-cells = <0>;
18   -
19   - cpu@0 {
20   - device_type = "cpu";
21   - compatible = "arm,cortex-a9";
22   - reg = <0>;
23   - enable-method = "psci";
24   - next-level-cache = <&l2>;
25   - };
26   -
27   - cpu@1 {
28   - device_type = "cpu";
29   - compatible = "arm,cortex-a9";
30   - reg = <1>;
31   - enable-method = "psci";
32   - next-level-cache = <&l2>;
33   - };
34   - };
35   -
36   - psci {
37   - compatible = "arm,psci-0.2";
38   - method = "smc";
39   - };
40   -
41   - clocks {
42   - refclk: ref {
43   - #clock-cells = <0>;
44   - compatible = "fixed-clock";
45   - clock-frequency = <24576000>;
46   - };
47   -
48   - arm_timer_clk: arm_timer_clk {
49   - #clock-cells = <0>;
50   - compatible = "fixed-clock";
51   - clock-frequency = <50000000>;
52   - };
53   - };
54   -
55   - soc {
56   - compatible = "simple-bus";
57   - #address-cells = <1>;
58   - #size-cells = <1>;
59   - ranges;
60   - interrupt-parent = <&intc>;
61   - u-boot,dm-pre-reloc;
62   -
63   - timer@20000200 {
64   - compatible = "arm,cortex-a9-global-timer";
65   - reg = <0x20000200 0x20>;
66   - interrupts = <1 11 0x304>;
67   - clocks = <&arm_timer_clk>;
68   - };
69   -
70   - timer@20000600 {
71   - compatible = "arm,cortex-a9-twd-timer";
72   - reg = <0x20000600 0x20>;
73   - interrupts = <1 13 0x304>;
74   - clocks = <&arm_timer_clk>;
75   - };
76   -
77   - intc: interrupt-controller@20001000 {
78   - compatible = "arm,cortex-a9-gic";
79   - #interrupt-cells = <3>;
80   - interrupt-controller;
81   - reg = <0x20001000 0x1000>,
82   - <0x20000100 0x100>;
83   - };
84   -
85   - l2: l2-cache@500c0000 {
86   - compatible = "socionext,uniphier-system-cache";
87   - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
88   - <0x506c0000 0x400>;
89   - interrupts = <0 174 4>, <0 175 4>;
90   - cache-unified;
91   - cache-size = <(512 * 1024)>;
92   - cache-sets = <256>;
93   - cache-line-size = <128>;
94   - cache-level = <2>;
95   - };
96   -
97   - serial0: serial@54006800 {
98   - compatible = "socionext,uniphier-uart";
99   - status = "disabled";
100   - reg = <0x54006800 0x40>;
101   - interrupts = <0 33 4>;
102   - pinctrl-names = "default";
103   - pinctrl-0 = <&pinctrl_uart0>;
104   - clocks = <&sys_clk 0>;
105   - clock-frequency = <36864000>;
106   - };
107   -
108   - serial1: serial@54006900 {
109   - compatible = "socionext,uniphier-uart";
110   - status = "disabled";
111   - reg = <0x54006900 0x40>;
112   - interrupts = <0 35 4>;
113   - pinctrl-names = "default";
114   - pinctrl-0 = <&pinctrl_uart1>;
115   - clocks = <&sys_clk 0>;
116   - clock-frequency = <36864000>;
117   - };
118   -
119   - serial2: serial@54006a00 {
120   - compatible = "socionext,uniphier-uart";
121   - status = "disabled";
122   - reg = <0x54006a00 0x40>;
123   - interrupts = <0 37 4>;
124   - pinctrl-names = "default";
125   - pinctrl-0 = <&pinctrl_uart2>;
126   - clocks = <&sys_clk 0>;
127   - clock-frequency = <36864000>;
128   - };
129   -
130   - port0x: gpio@55000008 {
131   - compatible = "socionext,uniphier-gpio";
132   - reg = <0x55000008 0x8>;
133   - gpio-controller;
134   - #gpio-cells = <2>;
135   - };
136   -
137   - port1x: gpio@55000010 {
138   - compatible = "socionext,uniphier-gpio";
139   - reg = <0x55000010 0x8>;
140   - gpio-controller;
141   - #gpio-cells = <2>;
142   - };
143   -
144   - port2x: gpio@55000018 {
145   - compatible = "socionext,uniphier-gpio";
146   - reg = <0x55000018 0x8>;
147   - gpio-controller;
148   - #gpio-cells = <2>;
149   - };
150   -
151   - port3x: gpio@55000020 {
152   - compatible = "socionext,uniphier-gpio";
153   - reg = <0x55000020 0x8>;
154   - gpio-controller;
155   - #gpio-cells = <2>;
156   - };
157   -
158   - port4: gpio@55000028 {
159   - compatible = "socionext,uniphier-gpio";
160   - reg = <0x55000028 0x8>;
161   - gpio-controller;
162   - #gpio-cells = <2>;
163   - };
164   -
165   - port5x: gpio@55000030 {
166   - compatible = "socionext,uniphier-gpio";
167   - reg = <0x55000030 0x8>;
168   - gpio-controller;
169   - #gpio-cells = <2>;
170   - };
171   -
172   - port6x: gpio@55000038 {
173   - compatible = "socionext,uniphier-gpio";
174   - reg = <0x55000038 0x8>;
175   - gpio-controller;
176   - #gpio-cells = <2>;
177   - };
178   -
179   - port7x: gpio@55000040 {
180   - compatible = "socionext,uniphier-gpio";
181   - reg = <0x55000040 0x8>;
182   - gpio-controller;
183   - #gpio-cells = <2>;
184   - };
185   -
186   - port8x: gpio@55000048 {
187   - compatible = "socionext,uniphier-gpio";
188   - reg = <0x55000048 0x8>;
189   - gpio-controller;
190   - #gpio-cells = <2>;
191   - };
192   -
193   - port9x: gpio@55000050 {
194   - compatible = "socionext,uniphier-gpio";
195   - reg = <0x55000050 0x8>;
196   - gpio-controller;
197   - #gpio-cells = <2>;
198   - };
199   -
200   - port10x: gpio@55000058 {
201   - compatible = "socionext,uniphier-gpio";
202   - reg = <0x55000058 0x8>;
203   - gpio-controller;
204   - #gpio-cells = <2>;
205   - };
206   -
207   - port11x: gpio@55000060 {
208   - compatible = "socionext,uniphier-gpio";
209   - reg = <0x55000060 0x8>;
210   - gpio-controller;
211   - #gpio-cells = <2>;
212   - };
213   -
214   - port12x: gpio@55000068 {
215   - compatible = "socionext,uniphier-gpio";
216   - reg = <0x55000068 0x8>;
217   - gpio-controller;
218   - #gpio-cells = <2>;
219   - };
220   -
221   - port13x: gpio@55000070 {
222   - compatible = "socionext,uniphier-gpio";
223   - reg = <0x55000070 0x8>;
224   - gpio-controller;
225   - #gpio-cells = <2>;
226   - };
227   -
228   - port14x: gpio@55000078 {
229   - compatible = "socionext,uniphier-gpio";
230   - reg = <0x55000078 0x8>;
231   - gpio-controller;
232   - #gpio-cells = <2>;
233   - };
234   -
235   - port16x: gpio@55000088 {
236   - compatible = "socionext,uniphier-gpio";
237   - reg = <0x55000088 0x8>;
238   - gpio-controller;
239   - #gpio-cells = <2>;
240   - };
241   -
242   - i2c0: i2c@58400000 {
243   - compatible = "socionext,uniphier-i2c";
244   - status = "disabled";
245   - reg = <0x58400000 0x40>;
246   - #address-cells = <1>;
247   - #size-cells = <0>;
248   - interrupts = <0 41 1>;
249   - pinctrl-names = "default";
250   - pinctrl-0 = <&pinctrl_i2c0>;
251   - clocks = <&sys_clk 1>;
252   - clock-frequency = <100000>;
253   - };
254   -
255   - i2c1: i2c@58480000 {
256   - compatible = "socionext,uniphier-i2c";
257   - status = "disabled";
258   - reg = <0x58480000 0x40>;
259   - #address-cells = <1>;
260   - #size-cells = <0>;
261   - interrupts = <0 42 1>;
262   - clocks = <&sys_clk 1>;
263   - clock-frequency = <100000>;
264   - };
265   -
266   - i2c2: i2c@58500000 {
267   - compatible = "socionext,uniphier-i2c";
268   - status = "disabled";
269   - reg = <0x58500000 0x40>;
270   - #address-cells = <1>;
271   - #size-cells = <0>;
272   - interrupts = <0 43 1>;
273   - clocks = <&sys_clk 1>;
274   - clock-frequency = <100000>;
275   - };
276   -
277   - i2c3: i2c@58580000 {
278   - compatible = "socionext,uniphier-i2c";
279   - status = "disabled";
280   - reg = <0x58580000 0x40>;
281   - #address-cells = <1>;
282   - #size-cells = <0>;
283   - interrupts = <0 44 1>;
284   - clocks = <&sys_clk 1>;
285   - clock-frequency = <100000>;
286   - };
287   -
288   - /* chip-internal connection for DMD */
289   - i2c4: i2c@58600000 {
290   - compatible = "socionext,uniphier-i2c";
291   - reg = <0x58600000 0x40>;
292   - #address-cells = <1>;
293   - #size-cells = <0>;
294   - interrupts = <0 45 1>;
295   - clocks = <&sys_clk 1>;
296   - clock-frequency = <400000>;
297   - };
298   -
299   - system_bus: system-bus@58c00000 {
300   - compatible = "socionext,uniphier-system-bus";
301   - status = "disabled";
302   - reg = <0x58c00000 0x400>;
303   - #address-cells = <2>;
304   - #size-cells = <1>;
305   - };
306   -
307   - smpctrl@59801000 {
308   - compatible = "socionext,uniphier-smpctrl";
309   - reg = <0x59801000 0x400>;
310   - };
311   -
312   - mioctrl@59810000 {
313   - compatible = "socionext,uniphier-sld3-mioctrl",
314   - "simple-mfd", "syscon";
315   - reg = <0x59810000 0x800>;
316   - u-boot,dm-pre-reloc;
317   -
318   - mio_clk: clock {
319   - compatible = "socionext,uniphier-sld3-mio-clock";
320   - #clock-cells = <1>;
321   - u-boot,dm-pre-reloc;
322   - };
323   -
324   - mio_rst: reset {
325   - compatible = "socionext,uniphier-sld3-mio-reset";
326   - #reset-cells = <1>;
327   - };
328   - };
329   -
330   - emmc: sdhc@5a400000 {
331   - compatible = "socionext,uniphier-sdhc";
332   - status = "disabled";
333   - reg = <0x5a400000 0x200>;
334   - interrupts = <0 78 4>;
335   - pinctrl-names = "default", "1.8v";
336   - pinctrl-0 = <&pinctrl_emmc>;
337   - pinctrl-1 = <&pinctrl_emmc_1v8>;
338   - clocks = <&mio_clk 1>;
339   - reset-names = "host", "bridge";
340   - resets = <&mio_rst 1>, <&mio_rst 4>;
341   - bus-width = <8>;
342   - non-removable;
343   - cap-mmc-highspeed;
344   - cap-mmc-hw-reset;
345   - };
346   -
347   - sd: sdhc@5a500000 {
348   - compatible = "socionext,uniphier-sdhc";
349   - status = "disabled";
350   - reg = <0x5a500000 0x200>;
351   - interrupts = <0 76 4>;
352   - pinctrl-names = "default", "1.8v";
353   - pinctrl-0 = <&pinctrl_sd>;
354   - pinctrl-1 = <&pinctrl_sd_1v8>;
355   - clocks = <&mio_clk 0>;
356   - reset-names = "host", "bridge";
357   - resets = <&mio_rst 0>, <&mio_rst 3>;
358   - bus-width = <4>;
359   - cap-sd-highspeed;
360   - sd-uhs-sdr12;
361   - sd-uhs-sdr25;
362   - sd-uhs-sdr50;
363   - };
364   -
365   - usb0: usb@5a800100 {
366   - compatible = "socionext,uniphier-ehci", "generic-ehci";
367   - status = "disabled";
368   - reg = <0x5a800100 0x100>;
369   - interrupts = <0 80 4>;
370   - pinctrl-names = "default";
371   - pinctrl-0 = <&pinctrl_usb0>;
372   - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
373   - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
374   - <&mio_rst 12>;
375   - };
376   -
377   - usb1: usb@5a810100 {
378   - compatible = "socionext,uniphier-ehci", "generic-ehci";
379   - status = "disabled";
380   - reg = <0x5a810100 0x100>;
381   - interrupts = <0 81 4>;
382   - pinctrl-names = "default";
383   - pinctrl-0 = <&pinctrl_usb1>;
384   - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
385   - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
386   - <&mio_rst 13>;
387   - };
388   -
389   - usb2: usb@5a820100 {
390   - compatible = "socionext,uniphier-ehci", "generic-ehci";
391   - status = "disabled";
392   - reg = <0x5a820100 0x100>;
393   - interrupts = <0 82 4>;
394   - pinctrl-names = "default";
395   - pinctrl-0 = <&pinctrl_usb2>;
396   - clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
397   - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
398   - <&mio_rst 14>;
399   - };
400   -
401   - usb3: usb@5a830100 {
402   - compatible = "socionext,uniphier-ehci", "generic-ehci";
403   - status = "disabled";
404   - reg = <0x5a830100 0x100>;
405   - interrupts = <0 83 4>;
406   - pinctrl-names = "default";
407   - pinctrl-0 = <&pinctrl_usb3>;
408   - clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
409   - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
410   - <&mio_rst 15>;
411   - };
412   -
413   - soc-glue@5f800000 {
414   - compatible = "socionext,uniphier-sld3-soc-glue",
415   - "simple-mfd", "syscon";
416   - reg = <0x5f800000 0x2000>;
417   - u-boot,dm-pre-reloc;
418   -
419   - pinctrl: pinctrl {
420   - compatible = "socionext,uniphier-sld3-pinctrl";
421   - u-boot,dm-pre-reloc;
422   - };
423   - };
424   -
425   - aidet@f1830000 {
426   - compatible = "simple-mfd", "syscon";
427   - reg = <0xf1830000 0x200>;
428   - };
429   -
430   - sysctrl@f1840000 {
431   - compatible = "socionext,uniphier-sld3-sysctrl",
432   - "simple-mfd", "syscon";
433   - reg = <0xf1840000 0x10000>;
434   -
435   - sys_clk: clock {
436   - compatible = "socionext,uniphier-sld3-clock";
437   - #clock-cells = <1>;
438   - };
439   -
440   - sys_rst: reset {
441   - compatible = "socionext,uniphier-sld3-reset";
442   - #reset-cells = <1>;
443   - };
444   - };
445   -
446   - nand: nand@f8000000 {
447   - compatible = "socionext,uniphier-denali-nand-v5a";
448   - status = "disabled";
449   - reg-names = "nand_data", "denali_reg";
450   - reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
451   - interrupts = <0 65 4>;
452   - clocks = <&sys_clk 2>;
453   - nand-ecc-strength = <8>;
454   - };
455   - };
456   -};
457   -
458   -/include/ "uniphier-pinctrl.dtsi"
arch/arm/mach-uniphier/Kconfig
Diff comments   View file @ 00aa453
... ... @@ -15,10 +15,6 @@
15 15 prompt "UniPhier SoC select"
16 16 default ARCH_UNIPHIER_PRO4
17 17  
18   -config ARCH_UNIPHIER_SLD3
19   - bool "UniPhier sLD3 SoC"
20   - select ARCH_UNIPHIER_32BIT
21   -
22 18 config ARCH_UNIPHIER_LD4_SLD8
23 19 bool "UniPhier LD4/sLD8 SoCs"
24 20 select ARCH_UNIPHIER_32BIT
arch/arm/mach-uniphier/arm32/cache-uniphier.c
Diff comments   View file @ 00aa453
... ... @@ -197,9 +197,6 @@
197 197 void __iomem *base = (void __iomem *)UNIPHIER_SSCC + 0xc00;
198 198  
199 199 switch (readl(UNIPHIER_SSCID)) { /* revision */
200   - case 0x11: /* sLD3 */
201   - base = (void __iomem *)UNIPHIER_SSCC + 0x870;
202   - break;
203 200 case 0x12: /* LD4 */
204 201 case 0x16: /* sld8 */
205 202 base = (void __iomem *)UNIPHIER_SSCC + 0x840;
arch/arm/mach-uniphier/arm32/debug_ll.S
Diff comments   View file @ 00aa453
... ... @@ -26,27 +26,6 @@
26 26 and r1, r1, #SG_REVISION_TYPE_MASK
27 27 mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
28 28  
29   -#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
30   -#define UNIPHIER_SLD3_UART_CLK 36864000
31   - cmp r1, #0x25
32   - bne sld3_end
33   -
34   - sg_set_pinsel 64, 1, 4, 4, r0, r1 @ TXD0 -> TXD0
35   -
36   - ldr r0, =BCSCR5
37   - ldr r1, =0x24440000
38   - str r1, [r0]
39   -
40   - ldr r0, =SC_CLKCTRL
41   - ldr r1, [r0]
42   - orr r1, r1, #SC_CLKCTRL_CEN_PERI
43   - str r1, [r0]
44   -
45   - ldr r3, =DIV_ROUND(UNIPHIER_SLD3_UART_CLK, 16 * BAUDRATE)
46   -
47   - b init_uart
48   -sld3_end:
49   -#endif
50 29 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
51 30 #define UNIPHIER_LD4_UART_CLK 36864000
52 31 cmp r1, #0x26
arch/arm/mach-uniphier/arm32/lowlevel_init.S
Diff comments   View file @ 00aa453
... ... @@ -29,9 +29,8 @@
29 29  
30 30 /*
31 31 * Now we are using the page table embedded in the Boot ROM.
32   - * It is not handy since it is not a straight mapped table for sLD3.
33   - * Also, the access to the external bus is prohibited. What we need
34   - * to do next is to create a page table and switch over to it.
  32 + * What we need to do next is to create a page table and switch
  33 + * over to it.
35 34 */
36 35 bl create_page_table
37 36 bl __v7_flush_dcache_all
arch/arm/mach-uniphier/arm32/psci.c
Diff comments   View file @ 00aa453
... ... @@ -29,7 +29,6 @@
29 29 static int uniphier_get_nr_cpus(void)
30 30 {
31 31 switch (uniphier_get_soc_id()) {
32   - case UNIPHIER_SLD3_ID:
33 32 case UNIPHIER_PRO4_ID:
34 33 case UNIPHIER_PRO5_ID:
35 34 return 2;
arch/arm/mach-uniphier/bcu/Makefile
Diff comments   View file @ 00aa453
... ... @@ -2,7 +2,6 @@
2 2 # SPDX-License-Identifier: GPL-2.0+
3 3 #
4 4  
5   -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += bcu-sld3.o
6 5 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += bcu-ld4.o
7 6 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += bcu-ld4.o
arch/arm/mach-uniphier/bcu/bcu-sld3.c
View file @ 00aa453
1   -/*
2   - * Copyright (C) 2011-2014 Panasonic Corporation
3   - * Copyright (C) 2015-2016 Socionext Inc.
4   - * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#include <linux/io.h>
10   -
11   -#include "../init.h"
12   -#include "bcu-regs.h"
13   -
14   -#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
15   -
16   -void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd)
17   -{
18   - int shift;
19   -
20   - writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
21   - writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
22   - writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
23   - /*
24   - * 0xe0000000-0xefffffff: Ex-bus
25   - * 0xf0000000-0xfbffffff: ASM bus
26   - * 0xfc000000-0xffffffff: OCM bus
27   - */
28   - writel(0x24440000, BCSCR5);
29   -
30   - /* Specify DDR channel */
31   - shift = bd->dram_ch[0].size / 0x04000000 * 4;
32   - writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
33   -
34   - shift -= 32;
35   - writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
36   -
37   - shift -= 32;
38   - writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
39   -}
arch/arm/mach-uniphier/board_init.c
Diff comments   View file @ 00aa453
... ... @@ -86,15 +86,6 @@
86 86 };
87 87  
88 88 static const struct uniphier_initdata uniphier_initdata[] = {
89   -#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
90   - {
91   - .soc_id = UNIPHIER_SLD3_ID,
92   - .nand_2cs = true,
93   - .sbc_init = uniphier_sbc_init_admulti,
94   - .pll_init = uniphier_sld3_pll_init,
95   - .clk_init = uniphier_ld4_clk_init,
96   - },
97   -#endif
98 89 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
99 90 {
100 91 .soc_id = UNIPHIER_LD4_ID,
arch/arm/mach-uniphier/boards.c
Diff comments   View file @ 00aa453
... ... @@ -13,25 +13,6 @@
13 13  
14 14 DECLARE_GLOBAL_DATA_PTR;
15 15  
16   -#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
17   -static const struct uniphier_board_data uniphier_sld3_data = {
18   - .dram_freq = 1600,
19   - .dram_ch[0] = {
20   - .size = 0x20000000,
21   - .width = 32,
22   - },
23   - .dram_ch[1] = {
24   - .size = 0x20000000,
25   - .width = 16,
26   - },
27   - .dram_ch[2] = {
28   - .size = 0x10000000,
29   - .width = 16,
30   - },
31   - .flags = UNIPHIER_BD_DRAM_SPARSE,
32   -};
33   -#endif
34   -
35 16 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
36 17 static const struct uniphier_board_data uniphier_ld4_data = {
37 18 .dram_freq = 1600,
... ... @@ -146,9 +127,6 @@
146 127 };
147 128  
148 129 static const struct uniphier_board_id uniphier_boards[] = {
149   -#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
150   - { "socionext,uniphier-sld3", &uniphier_sld3_data, },
151   -#endif
152 130 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
153 131 { "socionext,uniphier-ld4", &uniphier_ld4_data, },
154 132 #endif
arch/arm/mach-uniphier/boot-device/Makefile
Diff comments   View file @ 00aa453
... ... @@ -4,7 +4,6 @@
4 4  
5 5 obj-y += boot-device.o
6 6  
7   -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += boot-device-sld3.o
8 7 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += boot-device-ld4.o
9 8 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += boot-device-ld4.o
10 9 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-device-ld4.o
arch/arm/mach-uniphier/boot-device/boot-device-sld3.c
View file @ 00aa453
1   -/*
2   - * Copyright (C) 2014 Panasonic Corporation
3   - * Copyright (C) 2015-2017 Socionext Inc.
4   - * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#include <common.h>
10   -#include <spl.h>
11   -#include <linux/io.h>
12   -#include <linux/kernel.h>
13   -
14   -#include "boot-device.h"
15   -
16   -const struct uniphier_boot_device uniphier_sld3_boot_device_table[] = {
17   - {BOOT_DEVICE_NOR, "NOR (XECS0)"},
18   - {BOOT_DEVICE_NONE, "External Master"},
19   - {BOOT_DEVICE_NONE, "Reserved"},
20   - {BOOT_DEVICE_NONE, "Reserved"},
21   - {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"},
22   - {BOOT_DEVICE_NONE, "Reserved"},
23   - {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"},
24   - {BOOT_DEVICE_NONE, "Reserved"},
25   - {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"},
26   - {BOOT_DEVICE_NONE, "Reserved"},
27   - {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"},
28   - {BOOT_DEVICE_NONE, "Reserved"},
29   - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
30   - {BOOT_DEVICE_NONE, "Reserved"},
31   - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
32   - {BOOT_DEVICE_NONE, "Reserved"},
33   - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
34   - {BOOT_DEVICE_NONE, "Reserved"},
35   - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
36   - {BOOT_DEVICE_NONE, "Reserved"},
37   - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
38   - {BOOT_DEVICE_NONE, "Reserved"},
39   - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
40   - {BOOT_DEVICE_NONE, "Reserved"},
41   - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
42   - {BOOT_DEVICE_NONE, "Reserved"},
43   - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
44   - {BOOT_DEVICE_NONE, "Reserved"},
45   - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
46   - {BOOT_DEVICE_NONE, "Reserved"},
47   - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
48   - {BOOT_DEVICE_NONE, "Reserved"},
49   - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
50   - {BOOT_DEVICE_NONE, "Reserved"},
51   - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
52   - {BOOT_DEVICE_NONE, "Reserved"},
53   - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
54   - {BOOT_DEVICE_NONE, "Reserved"},
55   - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
56   - {BOOT_DEVICE_NONE, "Reserved"},
57   - {BOOT_DEVICE_NONE, "Reserved"},
58   - {BOOT_DEVICE_NONE, "Reserved"},
59   - {BOOT_DEVICE_NONE, "Reserved"},
60   - {BOOT_DEVICE_NONE, "Reserved"},
61   - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
62   - {BOOT_DEVICE_NONE, "Reserved"},
63   - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
64   - {BOOT_DEVICE_NONE, "Reserved"},
65   - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
66   - {BOOT_DEVICE_NONE, "Reserved"},
67   - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
68   - {BOOT_DEVICE_NONE, "Reserved"},
69   - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
70   - {BOOT_DEVICE_NONE, "Reserved"},
71   - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
72   - {BOOT_DEVICE_NONE, "Reserved"},
73   - {BOOT_DEVICE_NONE, "Reserved"},
74   - {BOOT_DEVICE_NONE, "Reserved"},
75   - {BOOT_DEVICE_NONE, "Reserved"},
76   - {BOOT_DEVICE_NONE, "Reserved"},
77   - {BOOT_DEVICE_NONE, "Reserved"},
78   - {BOOT_DEVICE_NONE, "Reserved"},
79   - {BOOT_DEVICE_NONE, "Reserved"},
80   - {BOOT_DEVICE_NONE, "Reserved"},
81   -};
82   -
83   -const unsigned uniphier_sld3_boot_device_count =
84   - ARRAY_SIZE(uniphier_sld3_boot_device_table);
arch/arm/mach-uniphier/boot-device/boot-device.c
Diff comments   View file @ 00aa453
... ... @@ -26,15 +26,6 @@
26 26 };
27 27  
28 28 static const struct uniphier_boot_device_info uniphier_boot_device_info[] = {
29   -#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
30   - {
31   - .soc_id = UNIPHIER_SLD3_ID,
32   - .boot_device_sel_shift = 0,
33   - .boot_device_table = uniphier_sld3_boot_device_table,
34   - .boot_device_count = &uniphier_sld3_boot_device_count,
35   - .have_internal_stm = 0,
36   - },
37   -#endif
38 29 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
39 30 {
40 31 .soc_id = UNIPHIER_LD4_ID,
arch/arm/mach-uniphier/boot-device/boot-device.h
Diff comments   View file @ 00aa453
... ... @@ -13,14 +13,12 @@
13 13 const char *desc;
14 14 };
15 15  
16   -extern const struct uniphier_boot_device uniphier_sld3_boot_device_table[];
17 16 extern const struct uniphier_boot_device uniphier_ld4_boot_device_table[];
18 17 extern const struct uniphier_boot_device uniphier_pro5_boot_device_table[];
19 18 extern const struct uniphier_boot_device uniphier_pxs2_boot_device_table[];
20 19 extern const struct uniphier_boot_device uniphier_ld11_boot_device_table[];
21 20 extern const struct uniphier_boot_device uniphier_pxs3_boot_device_table[];
22 21  
23   -extern const unsigned int uniphier_sld3_boot_device_count;
24 22 extern const unsigned int uniphier_ld4_boot_device_count;
25 23 extern const unsigned int uniphier_pro5_boot_device_count;
26 24 extern const unsigned int uniphier_pxs2_boot_device_count;
arch/arm/mach-uniphier/clk/Makefile
Diff comments   View file @ 00aa453
... ... @@ -4,17 +4,15 @@
4 4  
5 5 ifdef CONFIG_SPL_BUILD
6 6  
7   -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-early-sld3.o clk-dram-sld3.o dpll-sld3.o
8   -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-sld3.o clk-dram-sld3.o dpll-ld4.o
9   -obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-sld3.o clk-dram-sld3.o dpll-pro4.o
10   -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-sld3.o clk-dram-sld3.o dpll-sld8.o
11   -obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-sld3.o clk-dram-pro5.o dpll-pro5.o
12   -obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o
13   -obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o
  7 +obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
  8 +obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
  9 +obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
  10 +obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
  11 +obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
  12 +obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
14 13  
15 14 else
16 15  
17   -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o pll-sld3.o dpll-tail.o
18 16 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o
19 17 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
20 18 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o
arch/arm/mach-uniphier/clk/clk-dram-ld4.c
Diff comments   View file @ 00aa453
  1 +/*
  2 + * Copyright (C) 2011-2014 Panasonic Corporation
  3 + * Copyright (C) 2015-2017 Socionext Inc.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <spl.h>
  10 +#include <linux/io.h>
  11 +
  12 +#include "../init.h"
  13 +#include "../sc-regs.h"
  14 +
  15 +void uniphier_ld4_dram_clk_init(void)
  16 +{
  17 + u32 tmp;
  18 +
  19 + /* deassert reset */
  20 + tmp = readl(SC_RSTCTRL);
  21 + tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
  22 + writel(tmp, SC_RSTCTRL);
  23 + readl(SC_RSTCTRL); /* dummy read */
  24 +
  25 + /* provide clocks */
  26 + tmp = readl(SC_CLKCTRL);
  27 + tmp |= SC_CLKCTRL_CEN_UMC;
  28 + writel(tmp, SC_CLKCTRL);
  29 + readl(SC_CLKCTRL); /* dummy read */
  30 +}
arch/arm/mach-uniphier/clk/clk-dram-sld3.c
View file @ 00aa453
1   -/*
2   - * Copyright (C) 2011-2014 Panasonic Corporation
3   - * Copyright (C) 2015-2017 Socionext Inc.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <spl.h>
10   -#include <linux/io.h>
11   -
12   -#include "../init.h"
13   -#include "../sc-regs.h"
14   -
15   -void uniphier_sld3_dram_clk_init(void)
16   -{
17   - u32 tmp;
18   -
19   - /* deassert reset */
20   - tmp = readl(SC_RSTCTRL);
21   - tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
22   - writel(tmp, SC_RSTCTRL);
23   - readl(SC_RSTCTRL); /* dummy read */
24   -
25   - /* provide clocks */
26   - tmp = readl(SC_CLKCTRL);
27   - tmp |= SC_CLKCTRL_CEN_UMC;
28   - writel(tmp, SC_CLKCTRL);
29   - readl(SC_CLKCTRL); /* dummy read */
30   -}
arch/arm/mach-uniphier/clk/clk-early-ld4.c
Diff comments   View file @ 00aa453
  1 +/*
  2 + * Copyright (C) 2011-2014 Panasonic Corporation
  3 + * Copyright (C) 2015-2017 Socionext Inc.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <spl.h>
  10 +#include <linux/io.h>
  11 +
  12 +#include "../init.h"
  13 +#include "../sc-regs.h"
  14 +
  15 +void uniphier_ld4_early_clk_init(void)
  16 +{
  17 + u32 tmp;
  18 +
  19 + /* deassert reset */
  20 + if (spl_boot_device() != BOOT_DEVICE_NAND) {
  21 + tmp = readl(SC_RSTCTRL);
  22 + tmp &= ~SC_RSTCTRL_NRST_NAND;
  23 + writel(tmp, SC_RSTCTRL);
  24 + };
  25 +
  26 + /* provide clocks */
  27 + tmp = readl(SC_CLKCTRL);
  28 + tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
  29 + writel(tmp, SC_CLKCTRL);
  30 + readl(SC_CLKCTRL); /* dummy read */
  31 +}
arch/arm/mach-uniphier/clk/clk-early-sld3.c
View file @ 00aa453
1   -/*
2   - * Copyright (C) 2011-2014 Panasonic Corporation
3   - * Copyright (C) 2015-2017 Socionext Inc.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <spl.h>
10   -#include <linux/io.h>
11   -
12   -#include "../init.h"
13   -#include "../sc-regs.h"
14   -
15   -void uniphier_sld3_early_clk_init(void)
16   -{
17   - u32 tmp;
18   -
19   - /* deassert reset */
20   - if (spl_boot_device() != BOOT_DEVICE_NAND) {
21   - tmp = readl(SC_RSTCTRL);
22   - tmp &= ~SC_RSTCTRL_NRST_NAND;
23   - writel(tmp, SC_RSTCTRL);
24   - };
25   -
26   - /* provide clocks */
27   - tmp = readl(SC_CLKCTRL);
28   - tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
29   - writel(tmp, SC_CLKCTRL);
30   - readl(SC_CLKCTRL); /* dummy read */
31   -}
arch/arm/mach-uniphier/clk/dpll-sld3.c
View file @ 00aa453
1   -/*
2   - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include "../init.h"
8   -
9   -int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd)
10   -{
11   - /* add pll init code here */
12   - return 0;
13   -}
arch/arm/mach-uniphier/clk/pll-sld3.c
View file @ 00aa453
1   -/*
2   - * Copyright (C) 2016 Socionext Inc.
3   - * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include "../init.h"
9   -#include "pll.h"
10   -
11   -void uniphier_sld3_pll_init(void)
12   -{
13   - uniphier_ld4_dpll_ssc_en();
14   -}
arch/arm/mach-uniphier/cpu-info.c
Diff comments   View file @ 00aa453
... ... @@ -23,10 +23,6 @@
23 23 puts("SoC: ");
24 24  
25 25 switch (id) {
26   - case UNIPHIER_SLD3_ID:
27   - puts("sLD3");
28   - required_model = 2;
29   - break;
30 26 case UNIPHIER_LD4_ID:
31 27 puts("LD4");
32 28 required_rev = 2;
arch/arm/mach-uniphier/debug-uart/Makefile
Diff comments   View file @ 00aa453
... ... @@ -3,7 +3,6 @@
3 3 #
4 4  
5 5 ifdef CONFIG_SPL_BUILD
6   -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += debug-uart-sld3.o
7 6 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += debug-uart-ld4.o
8 7 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += debug-uart-pro4.o
9 8 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o
arch/arm/mach-uniphier/debug-uart/debug-uart-sld3.c
View file @ 00aa453
1   -/*
2   - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <config.h>
8   -#include <linux/kernel.h>
9   -#include <linux/io.h>
10   -
11   -#include "../bcu/bcu-regs.h"
12   -#include "../sc-regs.h"
13   -#include "../sg-regs.h"
14   -#include "debug-uart.h"
15   -
16   -#define UNIPHIER_SLD3_UART_CLK 36864000
17   -
18   -unsigned int uniphier_sld3_debug_uart_init(void)
19   -{
20   - u32 tmp;
21   -
22   - sg_set_pinsel(64, 1, 4, 4); /* TXD0 -> TXD0 */
23   -
24   - writel(0x24440000, BCSCR5);
25   -
26   - tmp = readl(SC_CLKCTRL);
27   - tmp |= SC_CLKCTRL_CEN_PERI;
28   - writel(tmp, SC_CLKCTRL);
29   -
30   - return DIV_ROUND_CLOSEST(UNIPHIER_SLD3_UART_CLK, 16 * CONFIG_BAUDRATE);
31   -}
arch/arm/mach-uniphier/debug-uart/debug-uart.c
Diff comments   View file @ 00aa453
... ... @@ -33,11 +33,6 @@
33 33 unsigned int divisor;
34 34  
35 35 switch (uniphier_get_soc_id()) {
36   -#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
37   - case UNIPHIER_SLD3_ID:
38   - divisor = uniphier_sld3_debug_uart_init();
39   - break;
40   -#endif
41 36 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
42 37 case UNIPHIER_LD4_ID:
43 38 divisor = uniphier_ld4_debug_uart_init();
arch/arm/mach-uniphier/debug-uart/debug-uart.h
Diff comments   View file @ 00aa453
... ... @@ -7,7 +7,6 @@
7 7 #ifndef _MACH_DEBUG_UART_H
8 8 #define _MACH_DEBUG_UART_H
9 9  
10   -unsigned int uniphier_sld3_debug_uart_init(void);
11 10 unsigned int uniphier_ld4_debug_uart_init(void);
12 11 unsigned int uniphier_pro4_debug_uart_init(void);
13 12 unsigned int uniphier_sld8_debug_uart_init(void);
arch/arm/mach-uniphier/dram/Makefile
Diff comments   View file @ 00aa453
... ... @@ -4,7 +4,6 @@
4 4  
5 5 ifdef CONFIG_SPL_BUILD
6 6  
7   -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += umc-sld3.o
8 7 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \
9 8 ddrphy-training.o ddrphy-ld4.o
10 9 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += umc-pro4.o \
arch/arm/mach-uniphier/dram/umc-sld3.c
View file @ 00aa453
1   -#include "../init.h"
2   -
3   -int uniphier_sld3_umc_init(const struct uniphier_board_data *bd)
4   -{
5   - return 0;
6   -}
arch/arm/mach-uniphier/dram_init.c
Diff comments   View file @ 00aa453
... ... @@ -28,15 +28,6 @@
28 28  
29 29 static const struct uniphier_memif_data uniphier_memif_data[] = {
30 30 {
31   - .soc_id = UNIPHIER_SLD3_ID,
32   - .sparse_ch1_base = 0xc0000000,
33   - /*
34   - * In fact, SLD3 has DRAM ch2, but the memory regions for ch1
35   - * and ch2 overlap, and host cannot get access to them at the
36   - * same time. Hide the ch2 from U-Boot.
37   - */
38   - },
39   - {
40 31 .soc_id = UNIPHIER_LD4_ID,
41 32 .sparse_ch1_base = 0xc0000000,
42 33 },
arch/arm/mach-uniphier/init.h
Diff comments   View file @ 00aa453
... ... @@ -28,7 +28,6 @@
28 28  
29 29 const struct uniphier_board_data *uniphier_get_board_param(void);
30 30  
31   -int uniphier_sld3_init(const struct uniphier_board_data *bd);
32 31 int uniphier_ld4_init(const struct uniphier_board_data *bd);
33 32 int uniphier_pro4_init(const struct uniphier_board_data *bd);
34 33 int uniphier_sld8_init(const struct uniphier_board_data *bd);
35 34  
36 35  
37 36  
38 37  
39 38  
40 39  
... ... @@ -63,34 +62,29 @@
63 62 }
64 63 #endif
65 64  
66   -void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd);
67 65 void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd);
68 66  
69 67 int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd);
70   -int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd);
71 68 int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd);
72 69  
73   -int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd);
74 70 int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd);
75 71 int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd);
76 72 int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd);
77 73 int uniphier_pro5_dpll_init(const struct uniphier_board_data *bd);
78 74 int uniphier_pxs2_dpll_init(const struct uniphier_board_data *bd);
79 75  
80   -void uniphier_sld3_early_clk_init(void);
  76 +void uniphier_ld4_early_clk_init(void);
81 77  
82   -void uniphier_sld3_dram_clk_init(void);
  78 +void uniphier_ld4_dram_clk_init(void);
83 79 void uniphier_pro5_dram_clk_init(void);
84 80 void uniphier_pxs2_dram_clk_init(void);
85 81  
86   -int uniphier_sld3_umc_init(const struct uniphier_board_data *bd);
87 82 int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
88 83 int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
89 84 int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
90 85 int uniphier_pro5_umc_init(const struct uniphier_board_data *bd);
91 86 int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
92 87  
93   -void uniphier_sld3_pll_init(void);
94 88 void uniphier_ld4_pll_init(void);
95 89 void uniphier_pro4_pll_init(void);
96 90 void uniphier_ld11_pll_init(void);
arch/arm/mach-uniphier/memconf.c
Diff comments   View file @ 00aa453
... ... @@ -15,7 +15,7 @@
15 15 #include "init.h"
16 16  
17 17 static int __uniphier_memconf_init(const struct uniphier_board_data *bd,
18   - int have_ch2, int have_ch2_disable_bit)
  18 + int have_ch2)
19 19 {
20 20 u32 val = 0;
21 21 unsigned long size_per_word;
... ... @@ -100,8 +100,7 @@
100 100 goto out;
101 101  
102 102 if (!bd->dram_ch[2].size) {
103   - if (have_ch2_disable_bit)
104   - val |= SG_MEMCONF_CH2_DISABLE;
  103 + val |= SG_MEMCONF_CH2_DISABLE;
105 104 goto out;
106 105 }
107 106  
108 107  
109 108  
... ... @@ -149,16 +148,11 @@
149 148  
150 149 int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd)
151 150 {
152   - return __uniphier_memconf_init(bd, 0, 0);
  151 + return __uniphier_memconf_init(bd, 0);
153 152 }
154 153  
155   -int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd)
156   -{
157   - return __uniphier_memconf_init(bd, 1, 0);
158   -}
159   -
160 154 int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd)
161 155 {
162   - return __uniphier_memconf_init(bd, 1, 1);
  156 + return __uniphier_memconf_init(bd, 1);
163 157 }
arch/arm/mach-uniphier/mmc-boot-mode.c
Diff comments   View file @ 00aa453
... ... @@ -14,7 +14,7 @@
14 14 struct mmc *mmc;
15 15  
16 16 /*
17   - * work around a bug in the Boot ROM of PH1-sLD3, LD4, Pro4, and sLD8:
  17 + * work around a bug in the Boot ROM of LD4, Pro4, and sLD8:
18 18 *
19 19 * The boot ROM in these SoCs breaks the PARTITION_CONFIG [179] of
20 20 * Extended CSD register; when switching to the Boot Partition 1, the
arch/arm/mach-uniphier/sc-regs.h
Diff comments   View file @ 00aa453
... ... @@ -11,11 +11,7 @@
11 11 #ifndef ARCH_SC_REGS_H
12 12 #define ARCH_SC_REGS_H
13 13  
14   -#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
15   -#define SC_BASE_ADDR 0xf1840000
16   -#else
17 14 #define SC_BASE_ADDR 0x61840000
18   -#endif
19 15  
20 16 #define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110)
21 17 #define SC_DPLLOSCCTRL_DPLLST (0x1 << 1)
arch/arm/mach-uniphier/soc-info.h
Diff comments   View file @ 00aa453
... ... @@ -11,7 +11,6 @@
11 11 #include <linux/kernel.h>
12 12 #include <linux/stddef.h>
13 13  
14   -#define UNIPHIER_SLD3_ID 0x25
15 14 #define UNIPHIER_LD4_ID 0x26
16 15 #define UNIPHIER_PRO4_ID 0x28
17 16 #define UNIPHIER_SLD8_ID 0x29
arch/arm/mach-uniphier/spl_board_init.c
Diff comments   View file @ 00aa453
... ... @@ -24,35 +24,24 @@
24 24 };
25 25  
26 26 static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
27   -#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
28   - {
29   - .soc_id = UNIPHIER_SLD3_ID,
30   - .bcu_init = uniphier_sld3_bcu_init,
31   - .early_clk_init = uniphier_sld3_early_clk_init,
32   - .dpll_init = uniphier_sld3_dpll_init,
33   - .memconf_init = uniphier_memconf_3ch_no_disbit_init,
34   - .dram_clk_init = uniphier_sld3_dram_clk_init,
35   - .umc_init = uniphier_sld3_umc_init,
36   - },
37   -#endif
38 27 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
39 28 {
40 29 .soc_id = UNIPHIER_LD4_ID,
41 30 .bcu_init = uniphier_ld4_bcu_init,
42   - .early_clk_init = uniphier_sld3_early_clk_init,
  31 + .early_clk_init = uniphier_ld4_early_clk_init,
43 32 .dpll_init = uniphier_ld4_dpll_init,
44 33 .memconf_init = uniphier_memconf_2ch_init,
45   - .dram_clk_init = uniphier_sld3_dram_clk_init,
  34 + .dram_clk_init = uniphier_ld4_dram_clk_init,
46 35 .umc_init = uniphier_ld4_umc_init,
47 36 },
48 37 #endif
49 38 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
50 39 {
51 40 .soc_id = UNIPHIER_PRO4_ID,
52   - .early_clk_init = uniphier_sld3_early_clk_init,
  41 + .early_clk_init = uniphier_ld4_early_clk_init,
53 42 .dpll_init = uniphier_pro4_dpll_init,
54 43 .memconf_init = uniphier_memconf_2ch_init,
55   - .dram_clk_init = uniphier_sld3_dram_clk_init,
  44 + .dram_clk_init = uniphier_ld4_dram_clk_init,
56 45 .umc_init = uniphier_pro4_umc_init,
57 46 },
58 47 #endif
59 48  
60 49  
... ... @@ -60,17 +49,17 @@
60 49 {
61 50 .soc_id = UNIPHIER_SLD8_ID,
62 51 .bcu_init = uniphier_ld4_bcu_init,
63   - .early_clk_init = uniphier_sld3_early_clk_init,
  52 + .early_clk_init = uniphier_ld4_early_clk_init,
64 53 .dpll_init = uniphier_sld8_dpll_init,
65 54 .memconf_init = uniphier_memconf_2ch_init,
66   - .dram_clk_init = uniphier_sld3_dram_clk_init,
  55 + .dram_clk_init = uniphier_ld4_dram_clk_init,
67 56 .umc_init = uniphier_sld8_umc_init,
68 57 },
69 58 #endif
70 59 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
71 60 {
72 61 .soc_id = UNIPHIER_PRO5_ID,
73   - .early_clk_init = uniphier_sld3_early_clk_init,
  62 + .early_clk_init = uniphier_ld4_early_clk_init,
74 63 .dpll_init = uniphier_pro5_dpll_init,
75 64 .memconf_init = uniphier_memconf_2ch_init,
76 65 .dram_clk_init = uniphier_pro5_dram_clk_init,
... ... @@ -80,7 +69,7 @@
80 69 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
81 70 {
82 71 .soc_id = UNIPHIER_PXS2_ID,
83   - .early_clk_init = uniphier_sld3_early_clk_init,
  72 + .early_clk_init = uniphier_ld4_early_clk_init,
84 73 .dpll_init = uniphier_pxs2_dpll_init,
85 74 .memconf_init = uniphier_memconf_3ch_init,
86 75 .dram_clk_init = uniphier_pxs2_dram_clk_init,
... ... @@ -90,7 +79,7 @@
90 79 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
91 80 {
92 81 .soc_id = UNIPHIER_LD6B_ID,
93   - .early_clk_init = uniphier_sld3_early_clk_init,
  82 + .early_clk_init = uniphier_ld4_early_clk_init,
94 83 .dpll_init = uniphier_pxs2_dpll_init,
95 84 .memconf_init = uniphier_memconf_3ch_init,
96 85 .dram_clk_init = uniphier_pxs2_dram_clk_init,
configs/uniphier_sld3_defconfig
View file @ 00aa453
1   -CONFIG_ARM=y
2   -CONFIG_ARCH_UNIPHIER=y
3   -CONFIG_SYS_TEXT_BASE=0x84000000
4   -CONFIG_SYS_MALLOC_F_LEN=0x2000
5   -CONFIG_SPL_MMC_SUPPORT=y
6   -CONFIG_SPL_SERIAL_SUPPORT=y
7   -CONFIG_SPL_NAND_SUPPORT=y
8   -CONFIG_ARCH_UNIPHIER_SLD3=y
9   -CONFIG_MICRO_SUPPORT_CARD=y
10   -CONFIG_DEFAULT_DEVICE_TREE="uniphier-sld3-ref"
11   -# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
12   -CONFIG_SPL=y
13   -CONFIG_SPL_NOR_SUPPORT=y
14   -CONFIG_HUSH_PARSER=y
15   -CONFIG_CMD_CONFIG=y
16   -CONFIG_CMD_BOOTZ=y
17   -# CONFIG_CMD_XIMG is not set
18   -# CONFIG_CMD_ENV_EXISTS is not set
19   -# CONFIG_CMD_FPGA is not set
20   -CONFIG_CMD_GPIO=y
21   -CONFIG_CMD_GPT=y
22   -CONFIG_CMD_I2C=y
23   -CONFIG_CMD_MMC=y
24   -CONFIG_CMD_USB=y
25   -CONFIG_CMD_TFTPPUT=y
26   -CONFIG_CMD_PING=y
27   -CONFIG_CMD_CACHE=y
28   -CONFIG_CMD_TIME=y
29   -# CONFIG_CMD_MISC is not set
30   -CONFIG_CMD_FAT=y
31   -CONFIG_CMD_FS_GENERIC=y
32   -# CONFIG_SPL_DOS_PARTITION is not set
33   -# CONFIG_SPL_EFI_PARTITION is not set
34   -CONFIG_NET_RANDOM_ETHADDR=y
35   -CONFIG_GPIO_UNIPHIER=y
36   -CONFIG_MISC=y
37   -CONFIG_I2C_EEPROM=y
38   -CONFIG_MMC_UNIPHIER=y
39   -CONFIG_NAND_DENALI=y
40   -CONFIG_SYS_NAND_DENALI_64BIT=y
41   -CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
42   -CONFIG_SPL_NAND_DENALI=y
43   -CONFIG_USB=y
44   -CONFIG_USB_EHCI_HCD=y
45   -CONFIG_USB_EHCI_GENERIC=y
46   -CONFIG_USB_STORAGE=y
... ... @@ -29,7 +29,6 @@
29 29  
30 30 Board | <defconfig> | <device-tree>
31 31 ---------------|------------------------------|------------------------------
32   -sLD3 reference | uniphier_sld3_defconfig | uniphier-sld3-ref (default)
33 32 LD4 reference | uniphier_ld4_sld8_defconfig | uniphier-ld4-ref (default)
34 33 sld8 reference | uniphier_ld4_sld8_defconfig | uniphier-sld8-def
35 34 Pro4 reference | uniphier_pro4_defconfig | uniphier-pro4-ref (default)
drivers/clk/uniphier/clk-uniphier-core.c
Diff comments   View file @ 00aa453
... ... @@ -147,10 +147,6 @@
147 147  
148 148 static const struct udevice_id uniphier_clk_match[] = {
149 149 {
150   - .compatible = "socionext,uniphier-sld3-mio-clock",
151   - .data = (ulong)&uniphier_mio_clk_data,
152   - },
153   - {
154 150 .compatible = "socionext,uniphier-ld4-mio-clock",
155 151 .data = (ulong)&uniphier_mio_clk_data,
156 152 },
drivers/clk/uniphier/clk-uniphier-mio.c
Diff comments   View file @ 00aa453
... ... @@ -64,11 +64,9 @@
64 64 UNIPHIER_MIO_CLK_USB2(8, 0),
65 65 UNIPHIER_MIO_CLK_USB2(9, 1),
66 66 UNIPHIER_MIO_CLK_USB2(10, 2),
67   - UNIPHIER_MIO_CLK_USB2(11, 3), /* for PH1-sLD3 only */
68 67 UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
69 68 UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
70 69 UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
71   - UNIPHIER_MIO_CLK_USB2_PHY(15, 3), /* for PH1-sLD3 only */
72 70 UNIPHIER_CLK_END
73 71 };
74 72  
drivers/pinctrl/uniphier/Kconfig
Diff comments   View file @ 00aa453
... ... @@ -3,12 +3,6 @@
3 3 config PINCTRL_UNIPHIER
4 4 bool
5 5  
6   -config PINCTRL_UNIPHIER_SLD3
7   - bool "UniPhier sLD3 SoC pinctrl driver"
8   - depends on ARCH_UNIPHIER_SLD3
9   - default y
10   - select PINCTRL_UNIPHIER
11   -
12 6 config PINCTRL_UNIPHIER_LD4
13 7 bool "UniPhier LD4 SoC pinctrl driver"
14 8 depends on ARCH_UNIPHIER_LD4
drivers/pinctrl/uniphier/Makefile
Diff comments   View file @ 00aa453
... ... @@ -4,7 +4,6 @@
4 4  
5 5 obj-y += pinctrl-uniphier-core.o
6 6  
7   -obj-$(CONFIG_PINCTRL_UNIPHIER_SLD3) += pinctrl-uniphier-sld3.o
8 7 obj-$(CONFIG_PINCTRL_UNIPHIER_LD4) += pinctrl-uniphier-ld4.o
9 8 obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4) += pinctrl-uniphier-pro4.o
10 9 obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8) += pinctrl-uniphier-sld8.o
drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c
View file @ 00aa453
1   -/*
2   - * Copyright (C) 2016 Socionext Inc.
3   - * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <dm.h>
10   -#include <dm/pinctrl.h>
11   -
12   -#include "pinctrl-uniphier.h"
13   -
14   -static const unsigned emmc_pins[] = {55, 56, 60};
15   -static const int emmc_muxvals[] = {1, 1, 1};
16   -static const unsigned emmc_dat8_pins[] = {57};
17   -static const int emmc_dat8_muxvals[] = {1};
18   -static const unsigned ether_mii_pins[] = {35, 107, 108, 109, 110, 111, 112,
19   - 113};
20   -static const int ether_mii_muxvals[] = {1, 2, 2, 2, 2, 2, 2, 2};
21   -static const unsigned ether_rmii_pins[] = {35};
22   -static const int ether_rmii_muxvals[] = {1};
23   -static const unsigned i2c0_pins[] = {36};
24   -static const int i2c0_muxvals[] = {0};
25   -static const unsigned nand_pins[] = {38, 39, 40, 58, 59};
26   -static const int nand_muxvals[] = {1, 1, 1, 1, 1};
27   -static const unsigned nand_cs1_pins[] = {41};
28   -static const int nand_cs1_muxvals[] = {1};
29   -static const unsigned sd_pins[] = {42, 43, 44, 45};
30   -static const int sd_muxvals[] = {1, 1, 1, 1};
31   -static const unsigned system_bus_pins[] = {46, 50, 51, 53, 54, 73, 74, 75, 76,
32   - 77, 78, 79, 80, 88, 89, 91, 92, 99};
33   -static const int system_bus_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
34   - 1, 1, 1, 1, 1};
35   -static const unsigned system_bus_cs0_pins[] = {93};
36   -static const int system_bus_cs0_muxvals[] = {1};
37   -static const unsigned system_bus_cs1_pins[] = {94};
38   -static const int system_bus_cs1_muxvals[] = {1};
39   -static const unsigned system_bus_cs2_pins[] = {95};
40   -static const int system_bus_cs2_muxvals[] = {1};
41   -static const unsigned system_bus_cs3_pins[] = {96};
42   -static const int system_bus_cs3_muxvals[] = {1};
43   -static const unsigned system_bus_cs4_pins[] = {81};
44   -static const int system_bus_cs4_muxvals[] = {1};
45   -static const unsigned system_bus_cs5_pins[] = {82};
46   -static const int system_bus_cs5_muxvals[] = {1};
47   -static const unsigned uart0_pins[] = {63, 64};
48   -static const int uart0_muxvals[] = {0, 1};
49   -static const unsigned uart1_pins[] = {65, 66};
50   -static const int uart1_muxvals[] = {0, 1};
51   -static const unsigned uart2_pins[] = {96, 102};
52   -static const int uart2_muxvals[] = {2, 2};
53   -static const unsigned usb0_pins[] = {13, 14};
54   -static const int usb0_muxvals[] = {0, 1};
55   -static const unsigned usb1_pins[] = {15, 16};
56   -static const int usb1_muxvals[] = {0, 1};
57   -static const unsigned usb2_pins[] = {17, 18};
58   -static const int usb2_muxvals[] = {0, 1};
59   -static const unsigned usb3_pins[] = {19, 20};
60   -static const int usb3_muxvals[] = {0, 1};
61   -
62   -static const struct uniphier_pinctrl_group uniphier_sld3_groups[] = {
63   - UNIPHIER_PINCTRL_GROUP_SPL(emmc),
64   - UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
65   - UNIPHIER_PINCTRL_GROUP(ether_mii),
66   - UNIPHIER_PINCTRL_GROUP(ether_rmii),
67   - UNIPHIER_PINCTRL_GROUP(i2c0),
68   - UNIPHIER_PINCTRL_GROUP(nand),
69   - UNIPHIER_PINCTRL_GROUP(nand_cs1),
70   - UNIPHIER_PINCTRL_GROUP(sd),
71   - UNIPHIER_PINCTRL_GROUP(system_bus),
72   - UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
73   - UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
74   - UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
75   - UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
76   - UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
77   - UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
78   - UNIPHIER_PINCTRL_GROUP_SPL(uart0),
79   - UNIPHIER_PINCTRL_GROUP_SPL(uart1),
80   - UNIPHIER_PINCTRL_GROUP_SPL(uart2),
81   - UNIPHIER_PINCTRL_GROUP(usb0),
82   - UNIPHIER_PINCTRL_GROUP(usb1),
83   - UNIPHIER_PINCTRL_GROUP(usb2),
84   - UNIPHIER_PINCTRL_GROUP(usb3)
85   -};
86   -
87   -static const char * const uniphier_sld3_functions[] = {
88   - UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
89   - UNIPHIER_PINMUX_FUNCTION(ether_mii),
90   - UNIPHIER_PINMUX_FUNCTION(ether_rmii),
91   - UNIPHIER_PINMUX_FUNCTION(i2c0),
92   - UNIPHIER_PINMUX_FUNCTION(nand),
93   - UNIPHIER_PINMUX_FUNCTION(sd),
94   - UNIPHIER_PINMUX_FUNCTION(system_bus),
95   - UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
96   - UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
97   - UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
98   - UNIPHIER_PINMUX_FUNCTION(usb0),
99   - UNIPHIER_PINMUX_FUNCTION(usb1),
100   - UNIPHIER_PINMUX_FUNCTION(usb2),
101   - UNIPHIER_PINMUX_FUNCTION(usb3),
102   -};
103   -
104   -static struct uniphier_pinctrl_socdata uniphier_sld3_pinctrl_socdata = {
105   - .groups = uniphier_sld3_groups,
106   - .groups_count = ARRAY_SIZE(uniphier_sld3_groups),
107   - .functions = uniphier_sld3_functions,
108   - .functions_count = ARRAY_SIZE(uniphier_sld3_functions),
109   - .caps = UNIPHIER_PINCTRL_CAPS_MUX_4BIT,
110   -};
111   -
112   -static int uniphier_sld3_pinctrl_probe(struct udevice *dev)
113   -{
114   - return uniphier_pinctrl_probe(dev, &uniphier_sld3_pinctrl_socdata);
115   -}
116   -
117   -static const struct udevice_id uniphier_sld3_pinctrl_match[] = {
118   - { .compatible = "socionext,uniphier-sld3-pinctrl" },
119   - { /* sentinel */ }
120   -};
121   -
122   -U_BOOT_DRIVER(uniphier_sld3_pinctrl) = {
123   - .name = "uniphier-sld3-pinctrl",
124   - .id = UCLASS_PINCTRL,
125   - .of_match = of_match_ptr(uniphier_sld3_pinctrl_match),
126   - .probe = uniphier_sld3_pinctrl_probe,
127   - .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
128   - .ops = &uniphier_pinctrl_ops,
129   -};
drivers/reset/reset-uniphier.c
Diff comments   View file @ 00aa453
... ... @@ -56,7 +56,7 @@
56 56 #define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \
57 57 UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17)
58 58  
59   -static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
  59 +static const struct uniphier_reset_data uniphier_ld4_sys_reset_data[] = {
60 60 UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */
61 61 UNIPHIER_RESET_END,
62 62 };
63 63  
... ... @@ -270,12 +270,8 @@
270 270 static const struct udevice_id uniphier_reset_match[] = {
271 271 /* System reset */
272 272 {
273   - .compatible = "socionext,uniphier-sld3-reset",
274   - .data = (ulong)uniphier_sld3_sys_reset_data,
275   - },
276   - {
277 273 .compatible = "socionext,uniphier-ld4-reset",
278   - .data = (ulong)uniphier_sld3_sys_reset_data,
  274 + .data = (ulong)uniphier_ld4_sys_reset_data,
279 275 },
280 276 {
281 277 .compatible = "socionext,uniphier-pro4-reset",
... ... @@ -283,7 +279,7 @@
283 279 },
284 280 {
285 281 .compatible = "socionext,uniphier-sld8-reset",
286   - .data = (ulong)uniphier_sld3_sys_reset_data,
  282 + .data = (ulong)uniphier_ld4_sys_reset_data,
287 283 },
288 284 {
289 285 .compatible = "socionext,uniphier-pro5-reset",
... ... @@ -302,10 +298,6 @@
302 298 .data = (ulong)uniphier_ld20_sys_reset_data,
303 299 },
304 300 /* Media I/O reset */
305   - {
306   - .compatible = "socionext,uniphier-sld3-mio-clock",
307   - .data = (ulong)uniphier_mio_reset_data,
308   - },
309 301 {
310 302 .compatible = "socionext,uniphier-ld4-mio-reset",
311 303 .data = (ulong)uniphier_mio_reset_data,
include/configs/uniphier.h
Diff comments   View file @ 00aa453
... ... @@ -88,13 +88,8 @@
88 88  
89 89 #define CONFIG_NAND_DENALI_ECC_SIZE 1024
90 90  
91   -#ifdef CONFIG_ARCH_UNIPHIER_SLD3
92   -#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
93   -#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
94   -#else
95 91 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000
96 92 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000
97   -#endif
98 93  
99 94 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
100 95  
... ... @@ -249,8 +244,7 @@
249 244 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
250 245  
251 246 /* only for SPL */
252   -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
253   - defined(CONFIG_ARCH_UNIPHIER_LD4) || \
  247 +#if defined(CONFIG_ARCH_UNIPHIER_LD4) || \
254 248 defined(CONFIG_ARCH_UNIPHIER_SLD8)
255 249 #define CONFIG_SPL_TEXT_BASE 0x00040000
256 250 #else