Eric Lee / smarc-uboot

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Commit 00aff7bbc3f22616d34bd8c0150a6c3045d06ec5

Authored by Simon Glass
Committed by Tom Rini
1 parent 93d66ee566
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

powerpc: Drop configs/manroland 

This is not used in U-Boot. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 2 changed files with 0 additions and 311 deletions Side-by-side Diff

include/configs/manroland/common.h
View file @ 00aff7b
1   -/*
2   - * (C) Copyright 2009
3   - * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#ifndef __MANROLAND_COMMON_H
9   -#define __MANROLAND_COMMON_H
10   -
11   -/*
12   - * High Level Configuration Options
13   - * (easy to change)
14   - */
15   -
16   -#define CONFIG_BOARD_EARLY_INIT_R
17   -
18   -/*
19   - * Command line configuration.
20   - */
21   -#define CONFIG_CMD_DATE
22   -#define CONFIG_CMD_EEPROM
23   -#define CONFIG_CMD_DTT
24   -#define CONFIG_CMD_IDE
25   -
26   -/*
27   - * 8-symbol LED display (can be accessed with 'display' command)
28   - */
29   -#define CONFIG_PDSP188x
30   -
31   -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
32   -
33   -/*
34   - * Autobooting
35   - */
36   -
37   -#define CONFIG_PREBOOT "echo;" \
38   - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
39   - "echo"
40   -
41   -#undef CONFIG_BOOTARGS
42   -
43   -#define CONFIG_EXTRA_ENV_SETTINGS \
44   - "netdev=eth0\0" \
45   - "nfsargs=setenv bootargs root=/dev/nfs rw " \
46   - "nfsroot=${serverip}:${rootpath}\0" \
47   - "ramargs=setenv bootargs root=/dev/ram rw\0" \
48   - "addwdt=setenv bootargs ${bootargs} wdt=off\0" \
49   - "logval=4\0" \
50   - "addlog=setenv bootargs ${bootargs} loglevel=${logval}\0" \
51   - "addip=setenv bootargs ${bootargs} " \
52   - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
53   - ":${hostname}:${netdev}:off panic=1\0" \
54   - "kernel_addr=ff810000\0" \
55   - "fdt_addr="__stringify(CONFIG_SYS_FLASH_BASE)"\0" \
56   - "flash_nfs=run nfsargs addip addcon addwdt addlog;" \
57   - "bootm ${kernel_addr} - ${fdt_addr}\0" \
58   - "rootpath=/opt/eldk/ppc_82xx\0" \
59   - "kernel_addr_r=300000\0" \
60   - "fdt_addr_r=200000\0" \
61   - "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \
62   - __stringify(CONFIG_HOSTNAME) ".dtb\0" \
63   - "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
64   - "load_fdt=tftp ${fdt_addr_r} ${fdt_file};\0" \
65   - "load_kernel=tftp ${kernel_addr_r} ${kernel_file};\0" \
66   - "addcon=setenv bootargs ${bootargs} console=ttyPSC0,${baudrate}\0"\
67   - "net_nfs=run load_fdt load_kernel; " \
68   - "run nfsargs addip addcon addwdt addlog;" \
69   - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
70   - "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin \0" \
71   - "u-boot_addr_r=200000\0" \
72   - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
73   - "update=protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize};"\
74   - "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize};"\
75   - "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_TEXT_BASE) \
76   - " ${filesize};" \
77   - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize}\0"\
78   - ""
79   -
80   -#define CONFIG_BOOTCOMMAND "run net_nfs"
81   -
82   -#define CONFIG_MISC_INIT_R 1
83   -
84   -/*
85   - * Miscellaneous configurable options
86   - */
87   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
88   -#if defined(CONFIG_CMD_KGDB)
89   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
90   -#else
91   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
92   -#endif
93   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
94   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
95   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
96   -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
97   -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
98   -
99   -/* Enable an alternate, more extensive memory test */
100   -#define CONFIG_SYS_ALT_MEMTEST
101   -
102   -/*
103   - * Enable loopw command.
104   - */
105   -
106   -#endif /* __MANROLAND_COMMON_H */
include/configs/manroland/mpc5200-common.h
View file @ 00aff7b
1   -/*
2   - * (C) Copyright 2009
3   - * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#ifndef __MANROLAND_MPC52XX__COMMON_H
9   -#define __MANROLAND_MPC52XX__COMMON_H
10   -
11   -/*
12   - * High Level Configuration Options
13   - * (easy to change)
14   - */
15   -#define CONFIG_MPC5200 1 /* MPC5200 CPU */
16   -
17   -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
18   -
19   -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
20   -
21   -/*
22   - * Serial console configuration
23   - */
24   -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
25   -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200,\
26   - 230400 }
27   -
28   -#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
29   -# define CONFIG_SYS_LOWBOOT 1
30   -#endif
31   -
32   -/*
33   - * IPB Bus clocking configuration.
34   - */
35   -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
36   -
37   -/*
38   - * I2C configuration
39   - */
40   -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
41   -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
42   -
43   -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
44   -#define CONFIG_SYS_I2C_SLAVE 0x7F
45   -
46   -/*
47   - * EEPROM configuration
48   - */
49   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
50   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
51   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
52   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
53   -
54   -/*
55   - * RTC configuration
56   - */
57   -#define CONFIG_RTC_PCF8563
58   -#define CONFIG_SYS_I2C_RTC_ADDR 0x51
59   -
60   -/* I2C SYSMON (LM75) */
61   -#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
62   -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
63   -#define CONFIG_SYS_DTT_MAX_TEMP 70
64   -#define CONFIG_SYS_DTT_LOW_TEMP -30
65   -#define CONFIG_SYS_DTT_HYSTERESIS 3
66   -
67   -/*
68   - * Flash configuration
69   - */
70   -#define CONFIG_SYS_FLASH_BASE 0xFF800000
71   -
72   -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
73   -
74   -#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
75   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
76   - (= chip selects) */
77   -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout [ms]*/
78   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout [ms]*/
79   -
80   -#define CONFIG_FLASH_CFI_DRIVER
81   -#define CONFIG_SYS_FLASH_CFI
82   -#define CONFIG_SYS_FLASH_EMPTY_INFO
83   -#define CONFIG_SYS_FLASH_CFI_AMD_RESET
84   -
85   -/*
86   - * Environment settings
87   - */
88   -#define CONFIG_ENV_IS_IN_FLASH 1
89   -#define CONFIG_ENV_SIZE 0x4000
90   -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
91   -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
92   -
93   -/*
94   - * Memory map
95   - */
96   -#define CONFIG_SYS_MBAR 0xF0000000
97   -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
98   -
99   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
100   - GENERATED_GBL_DATA_SIZE)
101   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
102   -
103   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
104   -#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */
105   -#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */
106   -
107   -/* Settings for XLB = 132 MHz */
108   -#define SDRAM_DDR 1
109   -#define SDRAM_MODE 0x018D0000
110   -#define SDRAM_EMODE 0x40090000
111   -#define SDRAM_CONTROL 0x714f0f00
112   -#define SDRAM_CONFIG1 0x73722930
113   -#define SDRAM_CONFIG2 0x47770000
114   -#define SDRAM_TAPDELAY 0x10000000
115   -
116   -/* Use ON-Chip SRAM until RAM will be available */
117   -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
118   -#ifdef CONFIG_POST
119   -/* preserve space for the post_word at end of on-chip SRAM */
120   -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
121   -#else
122   -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
123   -#endif
124   -
125   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
126   -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
127   -# define CONFIG_SYS_RAMBOOT 1
128   -#endif
129   -
130   -#define CONFIG_SYS_MONITOR_LEN (192 << 10)
131   -#define CONFIG_SYS_MALLOC_LEN (512 << 10)
132   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
133   -
134   -/*
135   - * Ethernet configuration
136   - */
137   -#define CONFIG_MPC5xxx_FEC 1
138   -#define CONFIG_MPC5xxx_FEC_MII100
139   -#define CONFIG_PHY_ADDR 0x00
140   -#define CONFIG_MII 1
141   -
142   -/*use Hardware WDT */
143   -#define CONFIG_HW_WATCHDOG
144   -
145   -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
146   -#if defined(CONFIG_CMD_KGDB)
147   -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
148   -#endif
149   -
150   -/*
151   - * Various low-level settings
152   - */
153   -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
154   -#define CONFIG_SYS_HID0_FINAL HID0_ICE
155   -
156   -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
157   -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
158   -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
159   -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
160   -
161   -/* 8Mbit SRAM @0x80100000 */
162   -#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
163   -
164   -#define CONFIG_SYS_CS_BURST 0x00000000
165   -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
166   -
167   -/*-----------------------------------------------------------------------
168   - * IDE/ATA stuff Supports IDE harddisk
169   - *-----------------------------------------------------------------------
170   - */
171   -
172   -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
173   -
174   -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
175   -#undef CONFIG_IDE_LED /* LED for ide not supported */
176   -
177   -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
178   -
179   -#define CONFIG_IDE_PREINIT 1
180   -
181   -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
182   -
183   -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
184   -
185   -/* Offset for data I/O */
186   -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
187   -
188   -/* Offset for normal register accesses */
189   -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
190   -
191   -/* Offset for alternate registers */
192   -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
193   -
194   -/* Interval between registers */
195   -#define CONFIG_SYS_ATA_STRIDE 4
196   -
197   -#define CONFIG_ATAPI 1
198   -
199   -#define OF_CPU "PowerPC,5200@0"
200   -#define OF_SOC "soc5200@f0000000"
201   -#define OF_TBCLK (bd->bi_busfreq / 4)
202   -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
203   -#define CONFIG_OF_IDE_FIXUP
204   -
205   -#endif /* __MANROLAND_MPC52XX__COMMON_H */