Eric Lee / smarc-uboot

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Commit 00c60f9131b513af9fc85d0cf1b6a6148d754a90

Authored by Wolfgang Denk
1 parent b264bcf2b9
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Minor Coding Style Cleanup. 

Signed-off-by: Wolfgang Denk <wd@denx.de>

Showing 2 changed files with 27 additions and 30 deletions Side-by-side Diff

board/freescale/p1010rdb/README
Diff comments   View file @ 00c60f9
... ... @@ -146,7 +146,6 @@
146 146 3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
147 147  
148 148  
149   -
150 149 Build and burn u-boot to SPI flash
151 150 ==================================
152 151 1. Build u-boot-spi.bin image
... ... @@ -166,7 +165,6 @@
166 165 3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
167 166  
168 167  
169   -
170 168 CPLD POR setting registers
171 169 ==========================
172 170 1. Set POR switch selection register (addr 0xFFB00011) to 0.
... ... @@ -195,7 +193,6 @@
195 193 => mw.b ffb00016 3
196 194 => mw.b ffb00017 f
197 195 => reset
198   -
199 196  
200 197  
201 198 Boot Linux from network using TFTP on P1010RDB
... ... @@ -26,15 +26,15 @@
26 26 ----------------------------------------------
27 27  
28 28 NOR boot
29   - !defined(CONFIG_SYS_RAMBOOT)
  29 + !defined(CONFIG_SYS_RAMBOOT)
30 30 NOR boot Secure
31   - !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
  31 + !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
32 32 RAMBOOT(SD, SPI & NAND boot)
33   - defined(CONFIG_SYS_RAMBOOT)
  33 + defined(CONFIG_SYS_RAMBOOT)
34 34 RAMBOOT Secure (SD, SPI & NAND)
35   - defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
  35 + defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
36 36 NAND SPL BOOT
37   - defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)
  37 + defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)
38 38  
39 39  
40 40 TLB Entries during u-boot execution
41 41  
42 42  
43 43  
44 44  
45 45  
46 46  
47 47  
... ... @@ -45,44 +45,44 @@
45 45 A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
46 46  
47 47 1) TLB entry to overcome e500 v1/v2 debug restriction
48   - Location : Label "_start_e500"
  48 + Location : Label "_start_e500"
49 49 TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
50 50 EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
51 51 Properties : 256K, AS0, I, IPROT
52 52  
53 53 2) TLB entry for working in AS1
54   - Location : Label "create_init_ram_area"
  54 + Location : Label "create_init_ram_area"
55 55 TLB Entry : 15
56 56 EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
57 57 Properties : 1M, AS1, I, G, IPROT
58 58  
59 59 3) TLB entry for the stack during AS1
60   - Location : Lable "create_init_ram_area"
  60 + Location : Lable "create_init_ram_area"
61 61 TLB Entry : 14
62 62 EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
63 63 Properties : 16K, AS1, IPROT
64 64  
65 65 4) TLB entry for CCSRBAR during AS1 execution
66   - Location : cpu_init_early_f
  66 + Location : cpu_init_early_f
67 67 TLB Entry : 13
68 68 EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
69 69 Properties : 1M, AS1, I, G
70 70  
71 71 5) Invalidate unproctected TLB Entries
72   - Location : cpu_init_early_f
  72 + Location : cpu_init_early_f
73 73 Invalidated: 13
74 74  
75 75 6) Create TLB entries as per boards/freescale/<board>/tlb.c
76   - Location : cpu_init_early_f --> init_tlbs()
  76 + Location : cpu_init_early_f --> init_tlbs()
77 77 Properties : ..., AS0, ...
78 78 Please note It can overwrites previous TLB Entries.
79 79  
80 80 7) Disable TLB Entries of AS1
81   - Location : cpu_init_f --> disable_tlb()
82   - Disable : 15, 14
  81 + Location : cpu_init_f --> disable_tlb()
  82 + Disable : 15, 14
83 83  
84 84 8) Update Flash's TLB entry
85   - Location : Board_init_r
  85 + Location : Board_init_r
86 86 TLB entry : Search from TLB entries
87 87 EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
88 88 Properties : Board specific size, AS0, I, G, IPROT
... ... @@ -91,7 +91,7 @@
91 91 B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
92 92  
93 93 1) TLB entry to overcome e500 v1/v2 debug restriction
94   - Location : Label "_start_e500"
  94 + Location : Label "_start_e500"
95 95 TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
96 96 #if defined(CONFIG_SECURE_BOOT)
97 97 EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
... ... @@ -102,7 +102,7 @@
102 102 #endif
103 103  
104 104 2) TLB entry for working in AS1
105   - Location : Label "create_init_ram_area"
  105 + Location : Label "create_init_ram_area"
106 106 TLB Entry : 15
107 107 #if defined(CONFIG_SECURE_BOOT)
108 108 EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
109 109  
110 110  
111 111  
112 112  
113 113  
114 114  
115 115  
116 116  
117 117  
... ... @@ -113,54 +113,54 @@
113 113 #endif
114 114  
115 115 3) TLB entry for the stack during AS1
116   - Location : Lable "create_init_ram_area"
  116 + Location : Lable "create_init_ram_area"
117 117 TLB Entry : 14
118 118 EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
119 119 Properties : 16K, AS1, IPROT
120 120  
121 121 4) TLB entry for CCSRBAR during AS1 execution
122   - Location : cpu_init_early_f
  122 + Location : cpu_init_early_f
123 123 TLB Entry : 13
124 124 EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
125 125 Properties : 1M, AS1, I, G
126 126  
127 127 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
128   - Location : cpu_init_early_f
  128 + Location : cpu_init_early_f
129 129 TLB Entry : 9
130 130 EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR
131 131 Properties : 1M, AS1, I
132 132  
133 133 6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr
134   - Location : cpu_init_early_f --> setup_ifc
  134 + Location : cpu_init_early_f --> setup_ifc
135 135 TLB Entry : Get Flash TLB
136 136 EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
137 137 Properties : 4M, AS1, I, G, IPROT
138 138  
139 139 7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction
140   - Location : cpu_init_early_f --> setup_ifc
  140 + Location : cpu_init_early_f --> setup_ifc
141 141 TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
142 142 EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
143 143 Properties : 4M, AS0, I, G, IPROT
144 144  
145 145 8) Invalidate unproctected TLB Entries
146   - Location : cpu_init_early_f
  146 + Location : cpu_init_early_f
147 147 Invalidated: 13, 9
148 148  
149 149 9) Create TLB entries as per boards/freescale/<board>/tlb.c
150   - Location : cpu_init_early_f --> init_tlbs()
  150 + Location : cpu_init_early_f --> init_tlbs()
151 151 Properties : ..., AS0, ...
152 152 Note: It can overwrites previous TLB Entries
153 153  
154 154 10) Disable TLB Entries of AS1
155   - Location : cpu_init_f --> disable_tlb()
156   - Disable : 15, 14
  155 + Location : cpu_init_f --> disable_tlb()
  156 + Disable : 15, 14
157 157  
158 158 11) Create DDR's TLB entriy
159   - Location : Board_init_f -> init_func_ram -> initdram
  159 + Location : Board_init_f -> init_func_ram -> initdram
160 160 TLB entry : Search free TLB entry
161 161  
162 162 12) Update Flash's TLB entry
163   - Location : Board_init_r
  163 + Location : Board_init_r
164 164 TLB entry : Search from TLB entries
165 165 EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
166 166 Properties : Board specific size, AS0, I, G, IPROT