Commit 00f792e0df9ae942427e44595a0f4379582accee
i2c, fsl_i2c: switch to new multibus/multiadapter support
- added to fsl_i2c driver new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@wwwdotorg.org>
Showing 100 changed files with 645 additions and 694 deletions Side-by-side Diff
- README
- arch/m68k/cpu/mcf5227x/cpu_init.c
- arch/m68k/cpu/mcf5227x/speed.c
- arch/m68k/cpu/mcf523x/cpu_init.c
- arch/m68k/cpu/mcf523x/speed.c
- arch/m68k/cpu/mcf52x2/cpu_init.c
- arch/m68k/cpu/mcf52x2/speed.c
- arch/m68k/cpu/mcf532x/cpu_init.c
- arch/m68k/cpu/mcf532x/speed.c
- arch/m68k/cpu/mcf5445x/cpu_init.c
- arch/m68k/cpu/mcf5445x/speed.c
- arch/m68k/cpu/mcf547x_8x/cpu_init.c
- arch/m68k/cpu/mcf547x_8x/speed.c
- arch/m68k/include/asm/global_data.h
- board/esd/vme8349/vme8349.c
- board/freescale/m52277evb/README
- board/freescale/m53017evb/README
- board/freescale/m5373evb/README
- board/freescale/m54455evb/README
- board/freescale/m547xevb/README
- board/freescale/mpc8349itx/mpc8349itx.c
- board/freescale/mpc8349itx/pci.c
- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
- board/keymile/common/ivm.c
- board/keymile/km83xx/km83xx.c
- drivers/i2c/Makefile
- drivers/i2c/fsl_i2c.c
- include/configs/B4860QDS.h
- include/configs/BSC9131RDB.h
- include/configs/BSC9132QDS.h
- include/configs/HWW1U1A.h
- include/configs/M5208EVBE.h
- include/configs/M52277EVB.h
- include/configs/M5235EVB.h
- include/configs/M5253DEMO.h
- include/configs/M5271EVB.h
- include/configs/M5275EVB.h
- include/configs/M53017EVB.h
- include/configs/M5329EVB.h
- include/configs/M5373EVB.h
- include/configs/M54418TWR.h
- include/configs/M54451EVB.h
- include/configs/M54455EVB.h
- include/configs/M5475EVB.h
- include/configs/M5485EVB.h
- include/configs/MERGERBOX.h
- include/configs/MPC8308RDB.h
- include/configs/MPC8313ERDB.h
- include/configs/MPC8315ERDB.h
- include/configs/MPC8323ERDB.h
- include/configs/MPC832XEMDS.h
- include/configs/MPC8349EMDS.h
- include/configs/MPC8349ITX.h
- include/configs/MPC8360EMDS.h
- include/configs/MPC8360ERDK.h
- include/configs/MPC837XEMDS.h
- include/configs/MPC837XERDB.h
- include/configs/MPC8536DS.h
- include/configs/MPC8540ADS.h
- include/configs/MPC8541CDS.h
- include/configs/MPC8544DS.h
- include/configs/MPC8548CDS.h
- include/configs/MPC8555CDS.h
- include/configs/MPC8560ADS.h
- include/configs/MPC8568MDS.h
- include/configs/MPC8569MDS.h
- include/configs/MPC8572DS.h
- include/configs/MPC8610HPCD.h
- include/configs/MPC8641HPCN.h
- include/configs/MVBLM7.h
- include/configs/P1010RDB.h
- include/configs/P1022DS.h
- include/configs/P1023RDB.h
- include/configs/P1023RDS.h
- include/configs/P1_P2_RDB.h
- include/configs/P2020COME.h
- include/configs/P2020DS.h
- include/configs/P2041RDB.h
- include/configs/SIMPC8313.h
- include/configs/TQM834x.h
- include/configs/astro_mcf5373l.h
- include/configs/controlcenterd.h
- include/configs/corenet_ds.h
- include/configs/eb_cpu5282.h
- include/configs/km/km83xx-common.h
- include/configs/mpc8308_p1m.h
- include/configs/mpq101.h
- include/configs/p1_p2_rdb_pc.h
- include/configs/sbc8349.h
- include/configs/sbc8548.h
- include/configs/sbc8641d.h
- include/configs/socrates.h
- include/configs/stxgp3.h
- include/configs/stxssa.h
- include/configs/t4qds.h
- include/configs/vme8349.h
- include/configs/xpedite517x.h
- include/configs/xpedite520x.h
- include/configs/xpedite537x.h
- include/configs/xpedite550x.h
... | ... | @@ -1968,6 +1968,18 @@ |
1968 | 1968 | CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4 |
1969 | 1969 | for defining speed and slave address |
1970 | 1970 | |
1971 | + - drivers/i2c/fsl_i2c.c: | |
1972 | + - activate i2c driver with CONFIG_SYS_I2C_FSL | |
1973 | + define CONFIG_SYS_FSL_I2C_OFFSET for setting the register | |
1974 | + offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and | |
1975 | + CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first | |
1976 | + bus. | |
1977 | + - If your board supports a second fsl i2c bus, define | |
1978 | + CONFIG_SYS_FSL_I2C2_OFFSET for the register offset | |
1979 | + CONFIG_SYS_FSL_I2C2_SPEED for the speed and | |
1980 | + CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the | |
1981 | + second bus. | |
1982 | + | |
1971 | 1983 | additional defines: |
1972 | 1984 | |
1973 | 1985 | CONFIG_SYS_NUM_I2C_BUSES |
... | ... | @@ -2212,11 +2224,6 @@ |
2212 | 2224 | If defined, specifies the I2C address of the DTT device. |
2213 | 2225 | If not defined, then U-Boot uses predefined value for |
2214 | 2226 | specified DTT device. |
2215 | - | |
2216 | - CONFIG_FSL_I2C | |
2217 | - | |
2218 | - Define this option if you want to use Freescale's I2C driver in | |
2219 | - drivers/i2c/fsl_i2c.c. | |
2220 | 2227 | |
2221 | 2228 | CONFIG_I2C_MUX |
2222 | 2229 |
... | ... | @@ -115,7 +115,7 @@ |
115 | 115 | out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK); |
116 | 116 | #endif |
117 | 117 | |
118 | -#ifdef CONFIG_FSL_I2C | |
118 | +#ifdef CONFIG_SYS_I2C_FSL | |
119 | 119 | CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; |
120 | 120 | CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; |
121 | 121 | #endif |
... | ... | @@ -228,7 +228,7 @@ |
228 | 228 | /* FlexBus Chipselect */ |
229 | 229 | init_fbcs(); |
230 | 230 | |
231 | -#ifdef CONFIG_FSL_I2C | |
231 | +#ifdef CONFIG_SYS_I2C_FSL | |
232 | 232 | CONFIG_SYS_I2C_PINMUX_REG = |
233 | 233 | CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR; |
234 | 234 | CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; |
... | ... | @@ -498,7 +498,7 @@ |
498 | 498 | init_fbcs(); |
499 | 499 | #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ |
500 | 500 | |
501 | -#ifdef CONFIG_FSL_I2C | |
501 | +#ifdef CONFIG_SYS_I2C_FSL | |
502 | 502 | CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; |
503 | 503 | CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; |
504 | 504 | #endif |
... | ... | @@ -90,9 +90,9 @@ |
90 | 90 | gd->bus_clk = gd->cpu_clk; |
91 | 91 | #endif |
92 | 92 | |
93 | -#ifdef CONFIG_FSL_I2C | |
93 | +#ifdef CONFIG_SYS_I2C_FSL | |
94 | 94 | gd->arch.i2c1_clk = gd->bus_clk; |
95 | -#ifdef CONFIG_SYS_I2C2_OFFSET | |
95 | +#ifdef CONFIG_SYS_I2C2_FSL_OFFSET | |
96 | 96 | gd->arch.i2c2_clk = gd->bus_clk; |
97 | 97 | #endif |
98 | 98 | #endif |
... | ... | @@ -98,7 +98,7 @@ |
98 | 98 | out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); |
99 | 99 | #endif |
100 | 100 | |
101 | -#ifdef CONFIG_FSL_I2C | |
101 | +#ifdef CONFIG_SYS_I2C_FSL | |
102 | 102 | out_8(&gpio->par_feci2c, |
103 | 103 | GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL); |
104 | 104 | #endif |
... | ... | @@ -292,7 +292,7 @@ |
292 | 292 | out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); |
293 | 293 | #endif |
294 | 294 | |
295 | -#ifdef CONFIG_FSL_I2C | |
295 | +#ifdef CONFIG_SYS_I2C_FSL | |
296 | 296 | out_8(&gpio->par_feci2c, |
297 | 297 | GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); |
298 | 298 | #endif |
... | ... | @@ -212,7 +212,7 @@ |
212 | 212 | GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | |
213 | 213 | GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS); |
214 | 214 | |
215 | -#ifdef CONFIG_FSL_I2C | |
215 | +#ifdef CONFIG_SYS_FSL_I2C | |
216 | 216 | out_be16(&gpio->par_feci2c, |
217 | 217 | GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); |
218 | 218 | #endif |
... | ... | @@ -273,7 +273,7 @@ |
273 | 273 | #endif |
274 | 274 | } |
275 | 275 | |
276 | -#ifdef CONFIG_FSL_I2C | |
276 | +#ifdef CONFIG_SYS_I2C_FSL | |
277 | 277 | gd->arch.i2c1_clk = gd->bus_clk; |
278 | 278 | #endif |
279 | 279 | } |
... | ... | @@ -289,7 +289,7 @@ |
289 | 289 | setup_5445x_clocks(); |
290 | 290 | #endif |
291 | 291 | |
292 | -#ifdef CONFIG_FSL_I2C | |
292 | +#ifdef CONFIG_SYS_FSL_I2C | |
293 | 293 | gd->arch.i2c1_clk = gd->bus_clk; |
294 | 294 | #endif |
295 | 295 |
... | ... | @@ -186,11 +186,11 @@ |
186 | 186 | |
187 | 187 | int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len) |
188 | 188 | { |
189 | - int old_bus = I2C_GET_BUS(); | |
189 | + int old_bus = i2c_get_bus_num(); | |
190 | 190 | unsigned int l, sum; |
191 | 191 | int valid = 0; |
192 | 192 | |
193 | - I2C_SET_BUS(0); | |
193 | + i2c_set_bus_num(0); | |
194 | 194 | |
195 | 195 | if (i2c_read(chip, addr, alen, buffer, len) == 0) |
196 | 196 | if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) { |
... | ... | @@ -215,7 +215,7 @@ |
215 | 215 | buffer[63] = sum; |
216 | 216 | } |
217 | 217 | |
218 | - I2C_SET_BUS(old_bus); | |
218 | + i2c_set_bus_num(old_bus); | |
219 | 219 | |
220 | 220 | return 0; |
221 | 221 | } |
... | ... | @@ -82,7 +82,7 @@ |
82 | 82 | CONFIG_MCFTMR -- define to use DMA timer |
83 | 83 | CONFIG_MCFPIT -- define to use PIT timer |
84 | 84 | |
85 | -CONFIG_FSL_I2C -- define to use FSL common I2C driver | |
85 | +CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver | |
86 | 86 | CONFIG_HARD_I2C -- define for I2C hardware support |
87 | 87 | CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged |
88 | 88 | CONFIG_SYS_I2C_SPEED -- define for I2C speed |
... | ... | @@ -90,7 +90,7 @@ |
90 | 90 | CONFIG_MCFTMR -- define to use DMA timer |
91 | 91 | CONFIG_MCFPIT -- define to use PIT timer |
92 | 92 | |
93 | -CONFIG_FSL_I2C -- define to use FSL common I2C driver | |
93 | +CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver | |
94 | 94 | CONFIG_HARD_I2C -- define for I2C hardware support |
95 | 95 | CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged |
96 | 96 | CONFIG_SYS_I2C_SPEED -- define for I2C speed |
... | ... | @@ -89,7 +89,7 @@ |
89 | 89 | CONFIG_MCFTMR -- define to use DMA timer |
90 | 90 | CONFIG_MCFPIT -- define to use PIT timer |
91 | 91 | |
92 | -CONFIG_FSL_I2C -- define to use FSL common I2C driver | |
92 | +CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver | |
93 | 93 | CONFIG_HARD_I2C -- define for I2C hardware support |
94 | 94 | CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged |
95 | 95 | CONFIG_SYS_I2C_SPEED -- define for I2C speed |
... | ... | @@ -112,7 +112,7 @@ |
112 | 112 | CONFIG_MCFTMR -- define to use DMA timer |
113 | 113 | CONFIG_MCFPIT -- define to use PIT timer |
114 | 114 | |
115 | -CONFIG_FSL_I2C -- define to use FSL common I2C driver | |
115 | +CONFIG_SYS_FSL_I2C -- define to use FSL common I2C driver | |
116 | 116 | CONFIG_HARD_I2C -- define for I2C hardware support |
117 | 117 | CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged |
118 | 118 | CONFIG_SYS_I2C_SPEED -- define for I2C speed |
... | ... | @@ -97,7 +97,7 @@ |
97 | 97 | |
98 | 98 | CONFIG_SLTTMR -- define to use SLT timer |
99 | 99 | |
100 | -CONFIG_FSL_I2C -- define to use FSL common I2C driver | |
100 | +CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver | |
101 | 101 | CONFIG_HARD_I2C -- define for I2C hardware support |
102 | 102 | CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged |
103 | 103 | CONFIG_SYS_I2C_SPEED -- define for I2C speed |
... | ... | @@ -248,7 +248,7 @@ |
248 | 248 | in_8(&cpld_data->pcba_rev) & 0x0F); |
249 | 249 | |
250 | 250 | /* Initialize i2c early for rom_loc and flash bank information */ |
251 | - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); | |
251 | + i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); | |
252 | 252 | |
253 | 253 | if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || |
254 | 254 | i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || |
... | ... | @@ -314,29 +314,13 @@ |
314 | 314 | |
315 | 315 | int ivm_read_eeprom(void) |
316 | 316 | { |
317 | -#if defined(CONFIG_I2C_MUX) | |
318 | - I2C_MUX_DEVICE *dev = NULL; | |
319 | -#endif | |
320 | 317 | uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; |
321 | 318 | char *buf; |
322 | 319 | unsigned long dev_addr = CONFIG_SYS_IVM_EEPROM_ADR; |
323 | 320 | int ret; |
324 | 321 | |
325 | -#if defined(CONFIG_SYS_I2C) | |
326 | 322 | buf = getenv("EEprom_ivm"); |
327 | 323 | i2c_set_bus_num(buf ? (int)simple_strtol(buf, NULL, 10) : 0); |
328 | -#else | |
329 | -#if defined(CONFIG_I2C_MUX) | |
330 | - /* First init the Bus, select the Bus */ | |
331 | - buf = (unsigned char *) getenv("EEprom_ivm"); | |
332 | - if (buf != NULL) | |
333 | - dev = i2c_mux_ident_muxstring(buf); | |
334 | - if (dev == NULL) { | |
335 | - printf("Error couldnt add Bus for IVM\n"); | |
336 | - return -1; | |
337 | - } | |
338 | - i2c_set_bus_num(dev->busid); | |
339 | -#endif | |
340 | 324 | /* add deblocking here */ |
341 | 325 | i2c_make_abort(); |
342 | 326 |
... | ... | @@ -95,19 +95,6 @@ |
95 | 95 | {0, 0, 0, 0, QE_IOP_TAB_END}, |
96 | 96 | }; |
97 | 97 | |
98 | -static int board_init_i2c_busses(void) | |
99 | -{ | |
100 | - I2C_MUX_DEVICE *dev = NULL; | |
101 | - uchar *dtt_bus = (uchar *)"pca9547:70:a"; | |
102 | - | |
103 | - /* Set up the Bus for the DTTs */ | |
104 | - dev = i2c_mux_ident_muxstring(dtt_bus); | |
105 | - if (dev == NULL) | |
106 | - printf("Error couldn't add Bus for DTT\n"); | |
107 | - | |
108 | - return 0; | |
109 | -} | |
110 | - | |
111 | 98 | #if defined(CONFIG_SUVD3) |
112 | 99 | const uint upma_table[] = { |
113 | 100 | 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */ |
... | ... | @@ -206,8 +193,6 @@ |
206 | 193 | |
207 | 194 | int misc_init_r(void) |
208 | 195 | { |
209 | - /* add board specific i2c busses */ | |
210 | - board_init_i2c_busses(); | |
211 | 196 | return 0; |
212 | 197 | } |
213 | 198 |
... | ... | @@ -28,7 +28,6 @@ |
28 | 28 | COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o |
29 | 29 | COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o |
30 | 30 | COBJS-$(CONFIG_DW_I2C) += designware_i2c.o |
31 | -COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o | |
32 | 31 | COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o |
33 | 32 | COBJS-$(CONFIG_I2C_MV) += mv_i2c.o |
34 | 33 | COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o |
... | ... | @@ -46,6 +45,7 @@ |
46 | 45 | COBJS-$(CONFIG_SH_I2C) += sh_i2c.o |
47 | 46 | COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o |
48 | 47 | COBJS-$(CONFIG_SYS_I2C) += i2c_core.o |
48 | +COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o | |
49 | 49 | COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o |
50 | 50 | COBJS-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o |
51 | 51 |
1 | 1 | /* |
2 | 2 | * Copyright 2006,2009 Freescale Semiconductor, Inc. |
3 | 3 | * |
4 | + * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
5 | + * Changes for multibus/multiadapter I2C support. | |
6 | + * | |
4 | 7 | * This program is free software; you can redistribute it and/or |
5 | 8 | * modify it under the terms of the GNU General Public License |
6 | 9 | * Version 2 as published by the Free Software Foundation. |
7 | 10 | |
... | ... | @@ -17,12 +20,8 @@ |
17 | 20 | */ |
18 | 21 | |
19 | 22 | #include <common.h> |
20 | - | |
21 | -#ifdef CONFIG_HARD_I2C | |
22 | - | |
23 | 23 | #include <command.h> |
24 | 24 | #include <i2c.h> /* Functional interface */ |
25 | - | |
26 | 25 | #include <asm/io.h> |
27 | 26 | #include <asm/fsl_i2c.h> /* HW definitions */ |
28 | 27 | |
29 | 28 | |
... | ... | @@ -47,25 +46,10 @@ |
47 | 46 | |
48 | 47 | DECLARE_GLOBAL_DATA_PTR; |
49 | 48 | |
50 | -/* Initialize the bus pointer to whatever one the SPD EEPROM is on. | |
51 | - * Default is bus 0. This is necessary because the DDR initialization | |
52 | - * runs from ROM, and we can't switch buses because we can't modify | |
53 | - * the global variables. | |
54 | - */ | |
55 | -#ifndef CONFIG_SYS_SPD_BUS_NUM | |
56 | -#define CONFIG_SYS_SPD_BUS_NUM 0 | |
57 | -#endif | |
58 | -static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM; | |
59 | -#if defined(CONFIG_I2C_MUX) | |
60 | -static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0; | |
61 | -#endif | |
62 | - | |
63 | -static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED}; | |
64 | - | |
65 | 49 | static const struct fsl_i2c *i2c_dev[2] = { |
66 | - (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET), | |
67 | -#ifdef CONFIG_SYS_I2C2_OFFSET | |
68 | - (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET) | |
50 | + (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET), | |
51 | +#ifdef CONFIG_SYS_FSL_I2C2_OFFSET | |
52 | + (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET) | |
69 | 53 | #endif |
70 | 54 | }; |
71 | 55 | |
72 | 56 | |
... | ... | @@ -222,12 +206,9 @@ |
222 | 206 | return gd->arch.i2c1_clk; /* I2C1 clock */ |
223 | 207 | } |
224 | 208 | |
225 | -void | |
226 | -i2c_init(int speed, int slaveadd) | |
209 | +static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) | |
227 | 210 | { |
228 | 211 | const struct fsl_i2c *dev; |
229 | - unsigned int temp; | |
230 | - int bus_num, i; | |
231 | 212 | |
232 | 213 | #ifdef CONFIG_SYS_I2C_INIT_BOARD |
233 | 214 | /* Call board specific i2c bus reset routine before accessing the |
234 | 215 | |
... | ... | @@ -236,23 +217,14 @@ |
236 | 217 | */ |
237 | 218 | i2c_init_board(); |
238 | 219 | #endif |
239 | -#ifdef CONFIG_SYS_I2C2_OFFSET | |
240 | - bus_num = 2; | |
241 | -#else | |
242 | - bus_num = 1; | |
243 | -#endif | |
244 | - for (i = 0; i < bus_num; i++) { | |
245 | - dev = i2c_dev[i]; | |
220 | + dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; | |
246 | 221 | |
247 | - writeb(0, &dev->cr); /* stop I2C controller */ | |
248 | - udelay(5); /* let it shutdown in peace */ | |
249 | - temp = set_i2c_bus_speed(dev, get_i2c_clock(i), speed); | |
250 | - if (gd->flags & GD_FLG_RELOC) | |
251 | - i2c_bus_speed[i] = temp; | |
252 | - writeb(slaveadd << 1, &dev->adr);/* write slave address */ | |
253 | - writeb(0x0, &dev->sr); /* clear status register */ | |
254 | - writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ | |
255 | - } | |
222 | + writeb(0, &dev->cr); /* stop I2C controller */ | |
223 | + udelay(5); /* let it shutdown in peace */ | |
224 | + set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed); | |
225 | + writeb(slaveadd << 1, &dev->adr);/* write slave address */ | |
226 | + writeb(0x0, &dev->sr); /* clear status register */ | |
227 | + writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ | |
256 | 228 | |
257 | 229 | #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT |
258 | 230 | /* Call board specific i2c bus reset routine AFTER the bus has been |
259 | 231 | |
260 | 232 | |
... | ... | @@ -265,12 +237,13 @@ |
265 | 237 | } |
266 | 238 | |
267 | 239 | static int |
268 | -i2c_wait4bus(void) | |
240 | +i2c_wait4bus(struct i2c_adapter *adap) | |
269 | 241 | { |
242 | + struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; | |
270 | 243 | unsigned long long timeval = get_ticks(); |
271 | 244 | const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); |
272 | 245 | |
273 | - while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { | |
246 | + while (readb(&dev->sr) & I2C_SR_MBB) { | |
274 | 247 | if ((get_ticks() - timeval) > timeout) |
275 | 248 | return -1; |
276 | 249 | } |
277 | 250 | |
278 | 251 | |
279 | 252 | |
280 | 253 | |
... | ... | @@ -279,20 +252,21 @@ |
279 | 252 | } |
280 | 253 | |
281 | 254 | static __inline__ int |
282 | -i2c_wait(int write) | |
255 | +i2c_wait(struct i2c_adapter *adap, int write) | |
283 | 256 | { |
284 | 257 | u32 csr; |
285 | 258 | unsigned long long timeval = get_ticks(); |
286 | 259 | const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT); |
260 | + struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; | |
287 | 261 | |
288 | 262 | do { |
289 | - csr = readb(&i2c_dev[i2c_bus_num]->sr); | |
263 | + csr = readb(&dev->sr); | |
290 | 264 | if (!(csr & I2C_SR_MIF)) |
291 | 265 | continue; |
292 | 266 | /* Read again to allow register to stabilise */ |
293 | - csr = readb(&i2c_dev[i2c_bus_num]->sr); | |
267 | + csr = readb(&dev->sr); | |
294 | 268 | |
295 | - writeb(0x0, &i2c_dev[i2c_bus_num]->sr); | |
269 | + writeb(0x0, &dev->sr); | |
296 | 270 | |
297 | 271 | if (csr & I2C_SR_MAL) { |
298 | 272 | debug("i2c_wait: MAL\n"); |
299 | 273 | |
300 | 274 | |
301 | 275 | |
302 | 276 | |
303 | 277 | |
304 | 278 | |
305 | 279 | |
306 | 280 | |
... | ... | @@ -317,29 +291,32 @@ |
317 | 291 | } |
318 | 292 | |
319 | 293 | static __inline__ int |
320 | -i2c_write_addr (u8 dev, u8 dir, int rsta) | |
294 | +i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta) | |
321 | 295 | { |
296 | + struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; | |
297 | + | |
322 | 298 | writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX |
323 | 299 | | (rsta ? I2C_CR_RSTA : 0), |
324 | - &i2c_dev[i2c_bus_num]->cr); | |
300 | + &device->cr); | |
325 | 301 | |
326 | - writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); | |
302 | + writeb((dev << 1) | dir, &device->dr); | |
327 | 303 | |
328 | - if (i2c_wait(I2C_WRITE_BIT) < 0) | |
304 | + if (i2c_wait(adap, I2C_WRITE_BIT) < 0) | |
329 | 305 | return 0; |
330 | 306 | |
331 | 307 | return 1; |
332 | 308 | } |
333 | 309 | |
334 | 310 | static __inline__ int |
335 | -__i2c_write(u8 *data, int length) | |
311 | +__i2c_write(struct i2c_adapter *adap, u8 *data, int length) | |
336 | 312 | { |
313 | + struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; | |
337 | 314 | int i; |
338 | 315 | |
339 | 316 | for (i = 0; i < length; i++) { |
340 | - writeb(data[i], &i2c_dev[i2c_bus_num]->dr); | |
317 | + writeb(data[i], &dev->dr); | |
341 | 318 | |
342 | - if (i2c_wait(I2C_WRITE_BIT) < 0) | |
319 | + if (i2c_wait(adap, I2C_WRITE_BIT) < 0) | |
343 | 320 | break; |
344 | 321 | } |
345 | 322 | |
346 | 323 | |
347 | 324 | |
348 | 325 | |
349 | 326 | |
350 | 327 | |
351 | 328 | |
352 | 329 | |
353 | 330 | |
354 | 331 | |
355 | 332 | |
356 | 333 | |
357 | 334 | |
358 | 335 | |
359 | 336 | |
... | ... | @@ -347,57 +324,60 @@ |
347 | 324 | } |
348 | 325 | |
349 | 326 | static __inline__ int |
350 | -__i2c_read(u8 *data, int length) | |
327 | +__i2c_read(struct i2c_adapter *adap, u8 *data, int length) | |
351 | 328 | { |
329 | + struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; | |
352 | 330 | int i; |
353 | 331 | |
354 | 332 | writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), |
355 | - &i2c_dev[i2c_bus_num]->cr); | |
333 | + &dev->cr); | |
356 | 334 | |
357 | 335 | /* dummy read */ |
358 | - readb(&i2c_dev[i2c_bus_num]->dr); | |
336 | + readb(&dev->dr); | |
359 | 337 | |
360 | 338 | for (i = 0; i < length; i++) { |
361 | - if (i2c_wait(I2C_READ_BIT) < 0) | |
339 | + if (i2c_wait(adap, I2C_READ_BIT) < 0) | |
362 | 340 | break; |
363 | 341 | |
364 | 342 | /* Generate ack on last next to last byte */ |
365 | 343 | if (i == length - 2) |
366 | 344 | writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, |
367 | - &i2c_dev[i2c_bus_num]->cr); | |
345 | + &dev->cr); | |
368 | 346 | |
369 | 347 | /* Do not generate stop on last byte */ |
370 | 348 | if (i == length - 1) |
371 | 349 | writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, |
372 | - &i2c_dev[i2c_bus_num]->cr); | |
350 | + &dev->cr); | |
373 | 351 | |
374 | - data[i] = readb(&i2c_dev[i2c_bus_num]->dr); | |
352 | + data[i] = readb(&dev->dr); | |
375 | 353 | } |
376 | 354 | |
377 | 355 | return i; |
378 | 356 | } |
379 | 357 | |
380 | -int | |
381 | -i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) | |
358 | +static int | |
359 | +fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data, | |
360 | + int length) | |
382 | 361 | { |
362 | + struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; | |
383 | 363 | int i = -1; /* signal error */ |
384 | 364 | u8 *a = (u8*)&addr; |
385 | 365 | |
386 | - if (i2c_wait4bus() < 0) | |
366 | + if (i2c_wait4bus(adap) < 0) | |
387 | 367 | return -1; |
388 | 368 | |
389 | 369 | if ((!length || alen > 0) |
390 | - && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 | |
391 | - && __i2c_write(&a[4 - alen], alen) == alen) | |
370 | + && i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 | |
371 | + && __i2c_write(adap, &a[4 - alen], alen) == alen) | |
392 | 372 | i = 0; /* No error so far */ |
393 | 373 | |
394 | 374 | if (length && |
395 | - i2c_write_addr(dev, I2C_READ_BIT, alen ? 1 : 0) != 0) | |
396 | - i = __i2c_read(data, length); | |
375 | + i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0) | |
376 | + i = __i2c_read(adap, data, length); | |
397 | 377 | |
398 | - writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); | |
378 | + writeb(I2C_CR_MEN, &device->cr); | |
399 | 379 | |
400 | - if (i2c_wait4bus()) /* Wait until STOP */ | |
380 | + if (i2c_wait4bus(adap)) /* Wait until STOP */ | |
401 | 381 | debug("i2c_read: wait4bus timed out\n"); |
402 | 382 | |
403 | 383 | if (i == length) |
404 | 384 | |
405 | 385 | |
406 | 386 | |
... | ... | @@ -406,20 +386,22 @@ |
406 | 386 | return -1; |
407 | 387 | } |
408 | 388 | |
409 | -int | |
410 | -i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) | |
389 | +static int | |
390 | +fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen, | |
391 | + u8 *data, int length) | |
411 | 392 | { |
393 | + struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; | |
412 | 394 | int i = -1; /* signal error */ |
413 | 395 | u8 *a = (u8*)&addr; |
414 | 396 | |
415 | - if (i2c_wait4bus() >= 0 | |
416 | - && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 | |
417 | - && __i2c_write(&a[4 - alen], alen) == alen) { | |
418 | - i = __i2c_write(data, length); | |
397 | + if (i2c_wait4bus(adap) >= 0 && | |
398 | + i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 && | |
399 | + __i2c_write(adap, &a[4 - alen], alen) == alen) { | |
400 | + i = __i2c_write(adap, data, length); | |
419 | 401 | } |
420 | 402 | |
421 | - writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); | |
422 | - if (i2c_wait4bus()) /* Wait until STOP */ | |
403 | + writeb(I2C_CR_MEN, &device->cr); | |
404 | + if (i2c_wait4bus(adap)) /* Wait until STOP */ | |
423 | 405 | debug("i2c_write: wait4bus timed out\n"); |
424 | 406 | |
425 | 407 | if (i == length) |
426 | 408 | |
427 | 409 | |
428 | 410 | |
429 | 411 | |
430 | 412 | |
431 | 413 | |
432 | 414 | |
433 | 415 | |
434 | 416 | |
... | ... | @@ -428,73 +410,43 @@ |
428 | 410 | return -1; |
429 | 411 | } |
430 | 412 | |
431 | -int | |
432 | -i2c_probe(uchar chip) | |
413 | +static int | |
414 | +fsl_i2c_probe(struct i2c_adapter *adap, uchar chip) | |
433 | 415 | { |
416 | + struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; | |
434 | 417 | /* For unknow reason the controller will ACK when |
435 | 418 | * probing for a slave with the same address, so skip |
436 | 419 | * it. |
437 | 420 | */ |
438 | - if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1)) | |
421 | + if (chip == (readb(&dev->adr) >> 1)) | |
439 | 422 | return -1; |
440 | 423 | |
441 | - return i2c_read(chip, 0, 0, NULL, 0); | |
424 | + return fsl_i2c_read(adap, chip, 0, 0, NULL, 0); | |
442 | 425 | } |
443 | 426 | |
444 | -int i2c_set_bus_num(unsigned int bus) | |
427 | +static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap, | |
428 | + unsigned int speed) | |
445 | 429 | { |
446 | -#if defined(CONFIG_I2C_MUX) | |
447 | - if (bus < CONFIG_SYS_MAX_I2C_BUS) { | |
448 | - i2c_bus_num = bus; | |
449 | - } else { | |
450 | - int ret; | |
430 | + struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; | |
451 | 431 | |
452 | - ret = i2x_mux_select_mux(bus); | |
453 | - if (ret) | |
454 | - return ret; | |
455 | - i2c_bus_num = 0; | |
456 | - } | |
457 | - i2c_bus_num_mux = bus; | |
458 | -#else | |
459 | -#ifdef CONFIG_SYS_I2C2_OFFSET | |
460 | - if (bus > 1) { | |
461 | -#else | |
462 | - if (bus > 0) { | |
463 | -#endif | |
464 | - return -1; | |
465 | - } | |
432 | + writeb(0, &dev->cr); /* stop controller */ | |
433 | + set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed); | |
434 | + writeb(I2C_CR_MEN, &dev->cr); /* start controller */ | |
466 | 435 | |
467 | - i2c_bus_num = bus; | |
468 | -#endif | |
469 | 436 | return 0; |
470 | 437 | } |
471 | 438 | |
472 | -int i2c_set_bus_speed(unsigned int speed) | |
473 | -{ | |
474 | - unsigned int i2c_clk = (i2c_bus_num == 1) | |
475 | - ? gd->arch.i2c2_clk : gd->arch.i2c1_clk; | |
476 | - | |
477 | - writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ | |
478 | - i2c_bus_speed[i2c_bus_num] = | |
479 | - set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed); | |
480 | - writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ | |
481 | - | |
482 | - return 0; | |
483 | -} | |
484 | - | |
485 | -unsigned int i2c_get_bus_num(void) | |
486 | -{ | |
487 | -#if defined(CONFIG_I2C_MUX) | |
488 | - return i2c_bus_num_mux; | |
489 | -#else | |
490 | - return i2c_bus_num; | |
439 | +/* | |
440 | + * Register fsl i2c adapters | |
441 | + */ | |
442 | +U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read, | |
443 | + fsl_i2c_write, fsl_i2c_set_bus_speed, | |
444 | + CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE, | |
445 | + 0) | |
446 | +#ifdef CONFIG_SYS_FSL_I2C2_OFFSET | |
447 | +U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read, | |
448 | + fsl_i2c_write, fsl_i2c_set_bus_speed, | |
449 | + CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE, | |
450 | + 1) | |
491 | 451 | #endif |
492 | -} | |
493 | - | |
494 | -unsigned int i2c_get_bus_speed(void) | |
495 | -{ | |
496 | - return i2c_bus_speed[i2c_bus_num]; | |
497 | -} | |
498 | - | |
499 | -#endif /* CONFIG_HARD_I2C */ |
... | ... | @@ -459,14 +459,14 @@ |
459 | 459 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
460 | 460 | |
461 | 461 | /* I2C */ |
462 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
463 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
464 | -#define CONFIG_I2C_MULTI_BUS | |
465 | -#define CONFIG_I2C_CMD_TREE | |
466 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed in Hz */ | |
467 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
468 | -#define CONFIG_SYS_I2C_OFFSET 0x118000 | |
469 | -#define CONFIG_SYS_I2C2_OFFSET 0x119000 | |
462 | +#define CONFIG_SYS_I2C | |
463 | +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ | |
464 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ | |
465 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
466 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ | |
467 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
468 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
469 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 | |
470 | 470 | |
471 | 471 | /* |
472 | 472 | * RTC configuration |
... | ... | @@ -275,12 +275,11 @@ |
275 | 275 | #define CONFIG_FIT |
276 | 276 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
277 | 277 | |
278 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
279 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
280 | -#define CONFIG_I2C_MULTI_BUS | |
281 | -#define CONFIG_I2C_CMD_TREE | |
282 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ | |
283 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
278 | +#define CONFIG_SYS_I2C | |
279 | +#define CONFIG_SYS_I2C_FSL | |
280 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
281 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
282 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
284 | 283 | |
285 | 284 | /* I2C EEPROM */ |
286 | 285 | #define CONFIG_CMD_EEPROM |
... | ... | @@ -451,15 +451,14 @@ |
451 | 451 | #define CONFIG_FIT |
452 | 452 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
453 | 453 | |
454 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
455 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
456 | -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
457 | -#define CONFIG_I2C_MULTI_BUS | |
458 | -#define CONFIG_I2C_CMD_TREE | |
459 | -#define CONFIG_SYS_I2C_SPEED 400800 /* I2C speed and slave address*/ | |
460 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
461 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
462 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
454 | +#define CONFIG_SYS_I2C | |
455 | +#define CONFIG_SYS_I2C_FSL | |
456 | +#define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ | |
457 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
458 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ | |
459 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
460 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
461 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
463 | 462 | |
464 | 463 | /* I2C EEPROM */ |
465 | 464 | #define CONFIG_ID_EEPROM |
... | ... | @@ -218,16 +218,16 @@ |
218 | 218 | /* -------------------------------------------------------------------- */ |
219 | 219 | |
220 | 220 | /* Generic FreeScale hardware I2C support */ |
221 | -#define CONFIG_HARD_I2C | |
222 | -#define CONFIG_FSL_I2C | |
221 | +#define CONFIG_SYS_I2C | |
222 | +#define CONFIG_SYS_I2C_FSL | |
223 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
224 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
225 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
226 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
227 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
228 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
229 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
223 | 230 | #define CONFIG_CMD_I2C |
224 | -#define CONFIG_I2C_MULTI_BUS | |
225 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
226 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
227 | - | |
228 | -/* I2C bus configuration */ | |
229 | -#define CONFIG_SYS_I2C_SPEED 400000 | |
230 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
231 | 231 | |
232 | 232 | /* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */ |
233 | 233 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
... | ... | @@ -82,11 +82,11 @@ |
82 | 82 | #undef CONFIG_MCFPIT |
83 | 83 | |
84 | 84 | /* I2C */ |
85 | -#define CONFIG_FSL_I2C | |
86 | -#define CONFIG_HARD_I2C /* I2C with hw support */ | |
87 | -#define CONFIG_SYS_I2C_SPEED 80000 | |
88 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
89 | -#define CONFIG_SYS_I2C_OFFSET 0x58000 | |
85 | +#define CONFIG_SYS_I2C | |
86 | +#define CONFIG_SYS_I2C_FSL | |
87 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
88 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
89 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
90 | 90 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
91 | 91 | |
92 | 92 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ |
... | ... | @@ -145,11 +145,11 @@ |
145 | 145 | #undef CONFIG_MCFPIT |
146 | 146 | |
147 | 147 | /* I2c */ |
148 | -#define CONFIG_FSL_I2C | |
149 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
150 | -#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */ | |
151 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
152 | -#define CONFIG_SYS_I2C_OFFSET 0x58000 | |
148 | +#define CONFIG_SYS_I2C | |
149 | +#define CONFIG_SYS_I2C_FSL | |
150 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
151 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
152 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
153 | 153 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
154 | 154 | |
155 | 155 | /* DSPI and Serial Flash */ |
... | ... | @@ -99,11 +99,11 @@ |
99 | 99 | #undef CONFIG_MCFPIT |
100 | 100 | |
101 | 101 | /* I2C */ |
102 | -#define CONFIG_FSL_I2C | |
103 | -#define CONFIG_HARD_I2C /* I2C with hw support */ | |
104 | -#define CONFIG_SYS_I2C_SPEED 80000 | |
105 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
106 | -#define CONFIG_SYS_I2C_OFFSET 0x00000300 | |
102 | +#define CONFIG_SYS_I2C | |
103 | +#define CONFIG_SYS_i2C_FSL | |
104 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
105 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
106 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 | |
107 | 107 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
108 | 108 | #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) |
109 | 109 | #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) |
... | ... | @@ -114,11 +114,11 @@ |
114 | 114 | #define CONFIG_HOSTNAME M5253DEMO |
115 | 115 | |
116 | 116 | /* I2C */ |
117 | -#define CONFIG_FSL_I2C | |
118 | -#define CONFIG_HARD_I2C /* I2C with hw support */ | |
119 | -#define CONFIG_SYS_I2C_SPEED 80000 | |
120 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
121 | -#define CONFIG_SYS_I2C_OFFSET 0x00000280 | |
117 | +#define CONFIG_SYS_I2C | |
118 | +#define CONFIG_SYS_I2C_FSL | |
119 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
120 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
121 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 | |
122 | 122 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
123 | 123 | #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) |
124 | 124 | #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) |
... | ... | @@ -109,11 +109,11 @@ |
109 | 109 | #endif |
110 | 110 | |
111 | 111 | /* I2C */ |
112 | -#define CONFIG_FSL_I2C | |
113 | -#define CONFIG_HARD_I2C /* I2C with hw support */ | |
114 | -#define CONFIG_SYS_I2C_SPEED 80000 | |
115 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
116 | -#define CONFIG_SYS_I2C_OFFSET 0x00000300 | |
112 | +#define CONFIG_SYS_I2C | |
113 | +#define CONFIG_SYS_I2C_FSL | |
114 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
115 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
116 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 | |
117 | 117 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
118 | 118 | |
119 | 119 | #define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ |
... | ... | @@ -109,11 +109,11 @@ |
109 | 109 | #endif |
110 | 110 | |
111 | 111 | /* I2C */ |
112 | -#define CONFIG_FSL_I2C | |
113 | -#define CONFIG_HARD_I2C /* I2C with hw support */ | |
114 | -#define CONFIG_SYS_I2C_SPEED 80000 | |
115 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
116 | -#define CONFIG_SYS_I2C_OFFSET 0x00000300 | |
112 | +#define CONFIG_SYS_I2C | |
113 | +#define CONFIG_SYS_I2C_FSL | |
114 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
115 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
116 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 | |
117 | 117 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
118 | 118 | #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) |
119 | 119 | #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) |
... | ... | @@ -101,11 +101,11 @@ |
101 | 101 | #undef CONFIG_MCFPIT |
102 | 102 | |
103 | 103 | /* I2C */ |
104 | -#define CONFIG_FSL_I2C | |
105 | -#define CONFIG_HARD_I2C /* I2C with hw support */ | |
106 | -#define CONFIG_SYS_I2C_SPEED 80000 | |
107 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
108 | -#define CONFIG_SYS_I2C_OFFSET 0x58000 | |
104 | +#define CONFIG_SYS_I2C | |
105 | +#define CONFIG_SYS_I2C_FSL | |
106 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
107 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
108 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
109 | 109 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
110 | 110 | |
111 | 111 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ |
... | ... | @@ -95,11 +95,11 @@ |
95 | 95 | #undef CONFIG_MCFPIT |
96 | 96 | |
97 | 97 | /* I2C */ |
98 | -#define CONFIG_FSL_I2C | |
99 | -#define CONFIG_HARD_I2C /* I2C with hw support */ | |
100 | -#define CONFIG_SYS_I2C_SPEED 80000 | |
101 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
102 | -#define CONFIG_SYS_I2C_OFFSET 0x58000 | |
98 | +#define CONFIG_SYS_I2C | |
99 | +#define CONFIG_SYS_I2C_FSL | |
100 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
101 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
102 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
103 | 103 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
104 | 104 | |
105 | 105 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ |
... | ... | @@ -95,11 +95,11 @@ |
95 | 95 | #undef CONFIG_MCFPIT |
96 | 96 | |
97 | 97 | /* I2C */ |
98 | -#define CONFIG_FSL_I2C | |
99 | -#define CONFIG_HARD_I2C /* I2C with hw support */ | |
100 | -#define CONFIG_SYS_I2C_SPEED 80000 | |
101 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
102 | -#define CONFIG_SYS_I2C_OFFSET 0x58000 | |
98 | +#define CONFIG_SYS_I2C | |
99 | +#define CONFIG_SYS_I2C_FSL | |
100 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
101 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
102 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
103 | 103 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
104 | 104 | |
105 | 105 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ |
... | ... | @@ -213,7 +213,7 @@ |
213 | 213 | #undef CONFIG_MCFPIT |
214 | 214 | |
215 | 215 | /* I2c */ |
216 | -#undef CONFIG_FSL_I2C | |
216 | +#undef CONFIG_SYS_FSL_I2C | |
217 | 217 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ |
218 | 218 | #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
219 | 219 | /* I2C speed and slave address */ |
... | ... | @@ -156,11 +156,11 @@ |
156 | 156 | #undef CONFIG_MCFPIT |
157 | 157 | |
158 | 158 | /* I2c */ |
159 | -#define CONFIG_FSL_I2C | |
160 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
161 | -#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */ | |
162 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
163 | -#define CONFIG_SYS_I2C_OFFSET 0x58000 | |
159 | +#define CONFIG_SYS_I2C | |
160 | +#define CONFIG_SYS_I2C_FSL | |
161 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
162 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
163 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
164 | 164 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
165 | 165 | |
166 | 166 | /* DSPI and Serial Flash */ |
... | ... | @@ -189,11 +189,11 @@ |
189 | 189 | #undef CONFIG_MCFPIT |
190 | 190 | |
191 | 191 | /* I2c */ |
192 | -#define CONFIG_FSL_I2C | |
193 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
194 | -#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */ | |
195 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
196 | -#define CONFIG_SYS_I2C_OFFSET 0x58000 | |
192 | +#define CONFIG_SYS_I2C | |
193 | +#define CONFIG_SYS_I2C_FSL | |
194 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
195 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
196 | +#define CONFIG_SYS_FSLI2C_OFFSET 0x58000 | |
197 | 197 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
198 | 198 | |
199 | 199 | /* DSPI and Serial Flash */ |
... | ... | @@ -120,11 +120,11 @@ |
120 | 120 | #endif |
121 | 121 | |
122 | 122 | /* I2C */ |
123 | -#define CONFIG_FSL_I2C | |
124 | -#define CONFIG_HARD_I2C /* I2C with hw support */ | |
125 | -#define CONFIG_SYS_I2C_SPEED 80000 | |
126 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
127 | -#define CONFIG_SYS_I2C_OFFSET 0x00008F00 | |
123 | +#define CONFIG_SYS_I2C | |
124 | +#define CONFIG_SYS_I2C_FSL | |
125 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
126 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
127 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 | |
128 | 128 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
129 | 129 | |
130 | 130 | /* PCI */ |
... | ... | @@ -117,11 +117,11 @@ |
117 | 117 | #endif |
118 | 118 | |
119 | 119 | /* I2C */ |
120 | -#define CONFIG_FSL_I2C | |
121 | -#define CONFIG_HARD_I2C /* I2C with hw support */ | |
122 | -#define CONFIG_SYS_I2C_SPEED 80000 | |
123 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
124 | -#define CONFIG_SYS_I2C_OFFSET 0x00008F00 | |
120 | +#define CONFIG_SYS_I2C | |
121 | +#define CONFIG_SYS_I2C_FSL | |
122 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
123 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
124 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 | |
125 | 125 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
126 | 126 | |
127 | 127 | /* PCI */ |
... | ... | @@ -224,13 +224,14 @@ |
224 | 224 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
225 | 225 | |
226 | 226 | /* I2C */ |
227 | -#define CONFIG_HARD_I2C | |
228 | -#define CONFIG_FSL_I2C | |
229 | -#define CONFIG_I2C_MULTI_BUS | |
230 | -#define CONFIG_SYS_I2C_SPEED 120000 | |
231 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
232 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
233 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
227 | +#define CONFIG_SYS_I2C | |
228 | +#define CONFIG_SYS_I2C_FSL | |
229 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
230 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
231 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
232 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
233 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
234 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
234 | 235 | |
235 | 236 | /* |
236 | 237 | * General PCI |
... | ... | @@ -350,14 +350,15 @@ |
350 | 350 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
351 | 351 | |
352 | 352 | /* I2C */ |
353 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
354 | -#define CONFIG_FSL_I2C | |
355 | -#define CONFIG_I2C_MULTI_BUS | |
356 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
357 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
358 | -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } /* Don't probe these addrs */ | |
359 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
360 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
353 | +#define CONFIG_SYS_I2C | |
354 | +#define CONFIG_SYS_I2C_FSL | |
355 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
356 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
357 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
358 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
359 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
360 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
361 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
361 | 362 | |
362 | 363 | /* |
363 | 364 | * SPI on header J8 |
... | ... | @@ -403,14 +403,15 @@ |
403 | 403 | #define CONFIG_SYS_HUSH_PARSER |
404 | 404 | |
405 | 405 | /* I2C */ |
406 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
407 | -#define CONFIG_FSL_I2C | |
408 | -#define CONFIG_I2C_MULTI_BUS | |
409 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
410 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
411 | -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ | |
412 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
413 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
406 | +#define CONFIG_SYS_I2C | |
407 | +#define CONFIG_SYS_I2C_FSL | |
408 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
409 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
410 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
411 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
412 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
413 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
414 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
414 | 415 | |
415 | 416 | /* |
416 | 417 | * General PCI |
... | ... | @@ -347,13 +347,12 @@ |
347 | 347 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
348 | 348 | |
349 | 349 | /* I2C */ |
350 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
351 | -#define CONFIG_FSL_I2C | |
352 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave addr */ | |
353 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
354 | -#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ | |
355 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
356 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
350 | +#define CONFIG_SYS_I2C | |
351 | +#define CONFIG_SYS_I2C_FSL | |
352 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
353 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
354 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
355 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
357 | 356 | |
358 | 357 | /* |
359 | 358 | * Board info - revision and where boot from |
... | ... | @@ -233,12 +233,12 @@ |
233 | 233 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
234 | 234 | |
235 | 235 | /* I2C */ |
236 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
237 | -#define CONFIG_FSL_I2C | |
238 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
239 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
240 | -#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ | |
241 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
236 | +#define CONFIG_SYS_I2C | |
237 | +#define CONFIG_SYS_I2C_FSL | |
238 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
239 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
240 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
241 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
242 | 242 | |
243 | 243 | /* |
244 | 244 | * Config on-board EEPROM |
... | ... | @@ -326,12 +326,12 @@ |
326 | 326 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
327 | 327 | |
328 | 328 | /* I2C */ |
329 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
330 | -#define CONFIG_FSL_I2C | |
331 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
332 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
333 | -#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ | |
334 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
329 | +#define CONFIG_SYS_I2C | |
330 | +#define CONFIG_SYS_I2C_FSL | |
331 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
332 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
333 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
334 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
335 | 335 | |
336 | 336 | /* |
337 | 337 | * Config on-board RTC |
... | ... | @@ -354,14 +354,15 @@ |
354 | 354 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
355 | 355 | |
356 | 356 | /* I2C */ |
357 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
358 | -#define CONFIG_FSL_I2C | |
359 | -#define CONFIG_I2C_MULTI_BUS | |
360 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
361 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
362 | -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ | |
363 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
364 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
357 | +#define CONFIG_SYS_I2C | |
358 | +#define CONFIG_SYS_I2C_FSL | |
359 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
360 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
361 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
362 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
363 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
364 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
365 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
365 | 366 | |
366 | 367 | /* SPI */ |
367 | 368 | #define CONFIG_MPC8XXX_SPI |
... | ... | @@ -90,7 +90,7 @@ |
90 | 90 | |
91 | 91 | #define CONFIG_PCI |
92 | 92 | #define CONFIG_RTC_DS1337 |
93 | -#define CONFIG_HARD_I2C | |
93 | +#define CONFIG_SYS_I2C | |
94 | 94 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ |
95 | 95 | |
96 | 96 | /* |
97 | 97 | |
... | ... | @@ -98,12 +98,15 @@ |
98 | 98 | */ |
99 | 99 | |
100 | 100 | /* I2C */ |
101 | -#ifdef CONFIG_HARD_I2C | |
101 | +#ifdef CONFIG_SYS_I2C | |
102 | +#define CONFIG_SYS_I2C_FSL | |
103 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
104 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
105 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
106 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
107 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
108 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
102 | 109 | |
103 | -#define CONFIG_FSL_I2C | |
104 | -#define CONFIG_I2C_MULTI_BUS | |
105 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
106 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
107 | 110 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ |
108 | 111 | #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ |
109 | 112 | |
... | ... | @@ -115,9 +118,6 @@ |
115 | 118 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ |
116 | 119 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ |
117 | 120 | |
118 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
119 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
120 | - | |
121 | 121 | /* Don't probe these addresses: */ |
122 | 122 | #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ |
123 | 123 | {1, CONFIG_SYS_I2C_8574_ADDR2}, \ |
... | ... | @@ -197,7 +197,7 @@ |
197 | 197 | #define CONFIG_VERY_BIG_RAM |
198 | 198 | #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) |
199 | 199 | |
200 | -#ifdef CONFIG_HARD_I2C | |
200 | +#ifdef CONFIG_SYS_I2C | |
201 | 201 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
202 | 202 | #endif |
203 | 203 | |
... | ... | @@ -543,7 +543,7 @@ |
543 | 543 | #define CONFIG_CMD_PCI |
544 | 544 | #endif |
545 | 545 | |
546 | -#ifdef CONFIG_HARD_I2C | |
546 | +#ifdef CONFIG_SYS_I2C | |
547 | 547 | #define CONFIG_CMD_I2C |
548 | 548 | #endif |
549 | 549 |
... | ... | @@ -423,13 +423,12 @@ |
423 | 423 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
424 | 424 | |
425 | 425 | /* I2C */ |
426 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
427 | -#define CONFIG_FSL_I2C | |
428 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
429 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
430 | -#define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */ | |
431 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
432 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
426 | +#define CONFIG_SYS_I2C | |
427 | +#define CONFIG_SYS_I2C_FSL | |
428 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
429 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
430 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
431 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } | |
433 | 432 | |
434 | 433 | /* |
435 | 434 | * Config on-board RTC |
... | ... | @@ -287,14 +287,15 @@ |
287 | 287 | #define CONFIG_OF_STDOUT_VIA_ALIAS |
288 | 288 | |
289 | 289 | /* I2C */ |
290 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
291 | -#define CONFIG_FSL_I2C | |
292 | -#define CONFIG_I2C_MULTI_BUS | |
293 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
294 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
295 | -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } /* Don't probe these addrs */ | |
296 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
297 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
290 | +#define CONFIG_SYS_I2C | |
291 | +#define CONFIG_SYS_I2C_FSL | |
292 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
293 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
294 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
295 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
296 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
297 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
298 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } | |
298 | 299 | |
299 | 300 | /* |
300 | 301 | * General PCI |
... | ... | @@ -341,13 +341,12 @@ |
341 | 341 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
342 | 342 | |
343 | 343 | /* I2C */ |
344 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
345 | -#define CONFIG_FSL_I2C | |
346 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
347 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
348 | -#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ | |
349 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
350 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
344 | +#define CONFIG_SYS_I2C | |
345 | +#define CONFIG_SYS_I2C_FSL | |
346 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
347 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
348 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
349 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
351 | 350 | |
352 | 351 | /* |
353 | 352 | * Config on-board RTC |
... | ... | @@ -367,13 +367,12 @@ |
367 | 367 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
368 | 368 | |
369 | 369 | /* I2C */ |
370 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
371 | -#define CONFIG_FSL_I2C | |
372 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
373 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
374 | -#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ | |
375 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
376 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
370 | +#define CONFIG_SYS_I2C | |
371 | +#define CONFIG_SYS_I2C_FSL | |
372 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
373 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
374 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
375 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
377 | 376 | |
378 | 377 | /* |
379 | 378 | * Config on-board RTC |
... | ... | @@ -434,14 +434,15 @@ |
434 | 434 | /* |
435 | 435 | * I2C |
436 | 436 | */ |
437 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
438 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
439 | -#define CONFIG_I2C_MULTI_BUS | |
440 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
441 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
442 | -#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ | |
443 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
444 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
437 | +#define CONFIG_SYS_I2C | |
438 | +#define CONFIG_SYS_I2C_FSL | |
439 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
440 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
441 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
442 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
443 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
444 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
445 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
445 | 446 | |
446 | 447 | /* |
447 | 448 | * I2C2 EEPROM |
... | ... | @@ -260,12 +260,12 @@ |
260 | 260 | /* |
261 | 261 | * I2C |
262 | 262 | */ |
263 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
264 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
265 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
266 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
267 | -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
268 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
263 | +#define CONFIG_SYS_I2C | |
264 | +#define CONFIG_SYS_I2C_FSL | |
265 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
266 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
267 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
268 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
269 | 269 | |
270 | 270 | /* RapidIO MMU */ |
271 | 271 | #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ |
... | ... | @@ -283,12 +283,12 @@ |
283 | 283 | /* |
284 | 284 | * I2C |
285 | 285 | */ |
286 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
287 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
288 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
289 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
290 | -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
291 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
286 | +#define CONFIG_SYS_I2C | |
287 | +#define CONFIG_SYS_I2C_FSL | |
288 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
289 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
290 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
291 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
292 | 292 | |
293 | 293 | /* EEPROM */ |
294 | 294 | #define CONFIG_ID_EEPROM |
... | ... | @@ -232,13 +232,13 @@ |
232 | 232 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
233 | 233 | |
234 | 234 | /* I2C */ |
235 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
236 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
237 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
235 | +#define CONFIG_SYS_I2C | |
236 | +#define CONFIG_SYS_I2C_FSL | |
237 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
238 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
239 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
240 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
238 | 241 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
239 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
240 | -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
241 | -#define CONFIG_SYS_I2C_OFFSET 0x3100 | |
242 | 242 | |
243 | 243 | /* |
244 | 244 | * General PCI |
... | ... | @@ -358,12 +358,12 @@ |
358 | 358 | /* |
359 | 359 | * I2C |
360 | 360 | */ |
361 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
362 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
363 | -#define CONFIG_SYS_I2C_SPEED 400000 | |
364 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
365 | -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
366 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
361 | +#define CONFIG_SYS_I2C | |
362 | +#define CONFIG_SYS_I2C_FSL | |
363 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
364 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
365 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
366 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
367 | 367 | |
368 | 368 | /* EEPROM */ |
369 | 369 | #define CONFIG_ID_EEPROM |
... | ... | @@ -281,12 +281,12 @@ |
281 | 281 | /* |
282 | 282 | * I2C |
283 | 283 | */ |
284 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
285 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
286 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
287 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
288 | -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
289 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
284 | +#define CONFIG_SYS_I2C | |
285 | +#define CONFIG_SYS_I2C_FSL | |
286 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
287 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
288 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
289 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
290 | 290 | |
291 | 291 | /* EEPROM */ |
292 | 292 | #define CONFIG_ID_EEPROM |
... | ... | @@ -254,12 +254,12 @@ |
254 | 254 | /* |
255 | 255 | * I2C |
256 | 256 | */ |
257 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
258 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
259 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
260 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
261 | -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
262 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
257 | +#define CONFIG_SYS_I2C | |
258 | +#define CONFIG_SYS_I2C_FSL | |
259 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
260 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
261 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
262 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
263 | 263 | |
264 | 264 | /* RapidIO MMU */ |
265 | 265 | #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ |
... | ... | @@ -266,15 +266,16 @@ |
266 | 266 | /* |
267 | 267 | * I2C |
268 | 268 | */ |
269 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
270 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
271 | -#define CONFIG_I2C_MULTI_BUS | |
272 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
269 | +#define CONFIG_SYS_I2C | |
270 | +#define CONFIG_SYS_I2C_FSL | |
271 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
272 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
273 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
274 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
275 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
276 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
277 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
273 | 278 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
274 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
275 | -#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ | |
276 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
277 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
278 | 279 | |
279 | 280 | /* |
280 | 281 | * General PCI |
... | ... | @@ -302,14 +302,15 @@ |
302 | 302 | /* |
303 | 303 | * I2C |
304 | 304 | */ |
305 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
306 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
307 | -#define CONFIG_I2C_MULTI_BUS | |
308 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
309 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
310 | -#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ | |
311 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
312 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
305 | +#define CONFIG_SYS_I2C | |
306 | +#define CONFIG_SYS_I2C_FSL | |
307 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
308 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
309 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
310 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
311 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
312 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
313 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
313 | 314 | |
314 | 315 | /* |
315 | 316 | * I2C2 EEPROM |
... | ... | @@ -431,15 +431,16 @@ |
431 | 431 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ |
432 | 432 | |
433 | 433 | /* I2C */ |
434 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
435 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
436 | -#define CONFIG_I2C_MULTI_BUS | |
437 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
434 | +#define CONFIG_SYS_I2C | |
435 | +#define CONFIG_SYS_I2C_FSL | |
436 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
437 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
438 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
439 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
440 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
441 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
442 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
438 | 443 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
439 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
440 | -#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ | |
441 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
442 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
443 | 444 | |
444 | 445 | /* |
445 | 446 | * I2C2 EEPROM |
... | ... | @@ -252,12 +252,12 @@ |
252 | 252 | /* |
253 | 253 | * I2C |
254 | 254 | */ |
255 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
256 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
257 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
258 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
259 | -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
260 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
255 | +#define CONFIG_SYS_I2C | |
256 | +#define CONFIG_SYS_I2C_FSL | |
257 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
258 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
259 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
260 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
261 | 261 | |
262 | 262 | /* |
263 | 263 | * General PCI |
... | ... | @@ -298,12 +298,12 @@ |
298 | 298 | /* |
299 | 299 | * I2C |
300 | 300 | */ |
301 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
302 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
303 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
304 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
305 | -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
306 | -#define CONFIG_SYS_I2C_OFFSET 0x3100 | |
301 | +#define CONFIG_SYS_I2C | |
302 | +#define CONFIG_SYS_I2C_FSL | |
303 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
304 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
305 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 | |
306 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
307 | 307 | |
308 | 308 | /* |
309 | 309 | * RapidIO MMU |
... | ... | @@ -44,7 +44,6 @@ |
44 | 44 | #define CONFIG_PCI |
45 | 45 | #define CONFIG_PCI_INDIRECT_BRIDGE |
46 | 46 | #define CONFIG_PCI_SKIP_HOST_BRIDGE |
47 | -#define CONFIG_HARD_I2C | |
48 | 47 | #define CONFIG_TSEC_ENET |
49 | 48 | #define CONFIG_MPC8XXX_SPI |
50 | 49 | #define CONFIG_HARD_SPI |
... | ... | @@ -52,13 +51,14 @@ |
52 | 51 | #define CONFIG_MISC_INIT_R |
53 | 52 | |
54 | 53 | /* I2C */ |
55 | -#define CONFIG_FSL_I2C | |
56 | -#define CONFIG_I2C_MULTI_BUS | |
57 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
58 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
59 | - | |
60 | -#define CONFIG_SYS_I2C_SPEED 100000 | |
61 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
54 | +#define CONFIG_SYS_I2C | |
55 | +#define CONFIG_SYS_I2C_FSL | |
56 | +#define CONFIG_SYS_FSL_I2C_SPEED 100000 | |
57 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
58 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
59 | +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 | |
60 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
61 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
62 | 62 | |
63 | 63 | /* |
64 | 64 | * DDR Setup |
... | ... | @@ -489,14 +489,15 @@ |
489 | 489 | #define CONFIG_FIT |
490 | 490 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
491 | 491 | |
492 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
493 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
494 | -#define CONFIG_I2C_MULTI_BUS | |
495 | -#define CONFIG_I2C_CMD_TREE | |
496 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ | |
497 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
498 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
499 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
492 | +/* I2C */ | |
493 | +#define CONFIG_SYS_I2C | |
494 | +#define CONFIG_SYS_I2C_FSL | |
495 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
496 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
497 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
498 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
499 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
500 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
500 | 501 | |
501 | 502 | /* I2C EEPROM */ |
502 | 503 | #undef CONFIG_ID_EEPROM |
... | ... | @@ -361,15 +361,15 @@ |
361 | 361 | #define CONFIG_FIT_VERBOSE |
362 | 362 | |
363 | 363 | /* I2C */ |
364 | -#define CONFIG_FSL_I2C | |
365 | -#define CONFIG_HARD_I2C | |
366 | -#define CONFIG_I2C_MULTI_BUS | |
367 | -#define CONFIG_SYS_I2C_SPEED 400000 | |
368 | -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
369 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
364 | +#define CONFIG_SYS_I2C | |
365 | +#define CONFIG_SYS_I2C_FSL | |
366 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
367 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
368 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
369 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
370 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
371 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
370 | 372 | #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} |
371 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
372 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
373 | 373 | |
374 | 374 | /* |
375 | 375 | * I2C2 EEPROM |
... | ... | @@ -204,13 +204,14 @@ |
204 | 204 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
205 | 205 | |
206 | 206 | /* I2C */ |
207 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
208 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
209 | -#define CONFIG_I2C_MULTI_BUS | |
210 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
211 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
212 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
213 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
207 | +#define CONFIG_SYS_I2C | |
208 | +#define CONFIG_SYS_I2C_FSL | |
209 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
210 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
211 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
212 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
213 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
214 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
214 | 215 | |
215 | 216 | /* |
216 | 217 | * I2C2 EEPROM |
... | ... | @@ -313,14 +313,15 @@ |
313 | 313 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
314 | 314 | |
315 | 315 | /* I2C */ |
316 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
317 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
318 | -#define CONFIG_I2C_MULTI_BUS | |
319 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
316 | +#define CONFIG_SYS_I2C | |
317 | +#define CONFIG_SYS_I2C_FSL | |
318 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
319 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
320 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
321 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
322 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
323 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
320 | 324 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 |
321 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
322 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
323 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
324 | 325 | |
325 | 326 | /* |
326 | 327 | * I2C2 EEPROM |
... | ... | @@ -367,15 +367,15 @@ |
367 | 367 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ |
368 | 368 | |
369 | 369 | /* I2C */ |
370 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
371 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
372 | -#define CONFIG_I2C_MULTI_BUS | |
373 | -#define CONFIG_I2C_CMD_TREE | |
374 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ | |
375 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
376 | -#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */ | |
377 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
378 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
370 | +#define CONFIG_SYS_I2C | |
371 | +#define CONFIG_SYS_I2C_FSL | |
372 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
373 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
374 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
375 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
376 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
377 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
378 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
379 | 379 | |
380 | 380 | /* |
381 | 381 | * I2C2 EEPROM |
... | ... | @@ -225,15 +225,15 @@ |
225 | 225 | #define CONFIG_FIT_VERBOSE 1 |
226 | 226 | |
227 | 227 | /* I2C */ |
228 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
229 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
230 | -#define CONFIG_I2C_MULTI_BUS | |
231 | -#define CONFIG_I2C_CMD_TREE | |
232 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ | |
233 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
228 | +#define CONFIG_SYS_I2C | |
229 | +#define CONFIG_SYS_I2C_FSL | |
230 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
231 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
232 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
233 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
234 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
235 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
234 | 236 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } |
235 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
236 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
237 | 237 | |
238 | 238 | /* |
239 | 239 | * I2C2 EEPROM |
... | ... | @@ -387,15 +387,16 @@ |
387 | 387 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
388 | 388 | |
389 | 389 | /* I2C */ |
390 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
391 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
392 | -#define CONFIG_I2C_MULTI_BUS | |
393 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
390 | +#define CONFIG_SYS_I2C | |
391 | +#define CONFIG_SYS_I2C_FSL | |
392 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
393 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
394 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
395 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
396 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
397 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
394 | 398 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
395 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
396 | -#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ | |
397 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
398 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
399 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
399 | 400 | |
400 | 401 | /* |
401 | 402 | * I2C2 EEPROM |
... | ... | @@ -367,14 +367,14 @@ |
367 | 367 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
368 | 368 | |
369 | 369 | /* I2C */ |
370 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
371 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
372 | -#define CONFIG_I2C_MULTI_BUS | |
373 | -#define CONFIG_I2C_CMD_TREE | |
374 | -#define CONFIG_SYS_I2C_SPEED 400000 | |
375 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
376 | -#define CONFIG_SYS_I2C_OFFSET 0x118000 | |
377 | -#define CONFIG_SYS_I2C2_OFFSET 0x118100 | |
370 | +#define CONFIG_SYS_I2C | |
371 | +#define CONFIG_SYS_I2C_FSL | |
372 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
373 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
374 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
375 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
376 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
377 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
378 | 378 | |
379 | 379 | /* |
380 | 380 | * RapidIO |
... | ... | @@ -245,14 +245,15 @@ |
245 | 245 | #define CONFIG_SYS_HUSH_PARSER |
246 | 246 | |
247 | 247 | /* I2C */ |
248 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
249 | -#define CONFIG_FSL_I2C | |
250 | -#define CONFIG_I2C_MULTI_BUS | |
251 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
252 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
253 | -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ | |
254 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
255 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
248 | +#define CONFIG_SYS_I2C | |
249 | +#define CONFIG_SYS_I2C_FSL | |
250 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
251 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
252 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
253 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
254 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
255 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
256 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
256 | 257 | |
257 | 258 | /* |
258 | 259 | * General PCI |
... | ... | @@ -187,11 +187,11 @@ |
187 | 187 | /* |
188 | 188 | * I2C |
189 | 189 | */ |
190 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
191 | -#define CONFIG_FSL_I2C | |
192 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */ | |
193 | -#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */ | |
194 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
190 | +#define CONFIG_SYS_I2C | |
191 | +#define CONFIG_SYS_I2C_FSL | |
192 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
193 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
194 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
195 | 195 | |
196 | 196 | /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ |
197 | 197 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
... | ... | @@ -116,11 +116,11 @@ |
116 | 116 | #undef CONFIG_MCFPIT |
117 | 117 | |
118 | 118 | /* I2C */ |
119 | -#define CONFIG_FSL_I2C | |
120 | -#define CONFIG_HARD_I2C /* I2C with hw support */ | |
121 | -#define CONFIG_SYS_I2C_SPEED 80000 | |
122 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
123 | -#define CONFIG_SYS_I2C_OFFSET 0x58000 | |
119 | +#define CONFIG_SYS_I2C | |
120 | +#define CONFIG_SYS_I2C_FSL | |
121 | +#define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
122 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
123 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
124 | 124 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
125 | 125 | |
126 | 126 | /* |
... | ... | @@ -192,15 +192,14 @@ |
192 | 192 | /* |
193 | 193 | * I2C |
194 | 194 | */ |
195 | -#define CONFIG_HARD_I2C | |
196 | -#define CONFIG_I2C_MULTI_BUS | |
197 | -#define CONFIG_CMD_I2C | |
198 | - | |
199 | -#define CONFIG_FSL_I2C | |
200 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
201 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
202 | -#define CONFIG_SYS_I2C_SPEED 400000 | |
203 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
195 | +#define CONFIG_SYS_I2C | |
196 | +#define CONFIG_SYS_I2C_FSL | |
197 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
198 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
199 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
200 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
201 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
202 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
204 | 203 | /* Probing DP501 I2C-Bridge will hang */ |
205 | 204 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x30}, {0, 0x37}, {0, 0x3a}, \ |
206 | 205 | {0, 0x3b}, {0, 0x50} } |
... | ... | @@ -362,14 +362,14 @@ |
362 | 362 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
363 | 363 | |
364 | 364 | /* I2C */ |
365 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
366 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
367 | -#define CONFIG_I2C_MULTI_BUS | |
368 | -#define CONFIG_I2C_CMD_TREE | |
369 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
370 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
371 | -#define CONFIG_SYS_I2C_OFFSET 0x118000 | |
372 | -#define CONFIG_SYS_I2C2_OFFSET 0x118100 | |
365 | +#define CONFIG_SYS_I2C | |
366 | +#define CONFIG_SYS_I2C_FSL | |
367 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
368 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
369 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
370 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
371 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
372 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 | |
373 | 373 | |
374 | 374 | /* |
375 | 375 | * RapidIO |
... | ... | @@ -262,14 +262,14 @@ |
262 | 262 | * I2C |
263 | 263 | */ |
264 | 264 | |
265 | -#define CONFIG_HARD_I2C | |
266 | -#define CONFIG_FSL_I2C | |
265 | +#define CONFIG_SYS_I2C | |
266 | +#define CONFIG_SYS_I2C_FSL | |
267 | 267 | |
268 | -#define CONFIG_SYS_I2C_OFFSET 0x00000300 | |
268 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 | |
269 | 269 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
270 | 270 | |
271 | -#define CONFIG_SYS_I2C_SPEED 100000 | |
272 | -#define CONFIG_SYS_I2C_SLAVE 0 | |
271 | +#define CONFIG_SYS_FSL_I2C_SPEED 100000 | |
272 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0 | |
273 | 273 | |
274 | 274 | #ifdef CONFIG_CMD_DATE |
275 | 275 | #define CONFIG_RTC_DS1338 |
... | ... | @@ -204,14 +204,21 @@ |
204 | 204 | #endif /* CFG_SYS_RAMBOOT */ |
205 | 205 | |
206 | 206 | /* I2C */ |
207 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
208 | -#define CONFIG_FSL_I2C | |
209 | -#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ | |
210 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
211 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
212 | -#define CONFIG_I2C_MULTI_BUS | |
213 | -#define CONFIG_SYS_MAX_I2C_BUS 1 | |
214 | -#define CONFIG_I2C_MUX | |
207 | +#define CONFIG_SYS_I2C | |
208 | +#define CONFIG_SYS_NUM_I2C_BUSES 4 | |
209 | +#define CONFIG_SYS_I2C_MAX_HOPS 1 | |
210 | +#define CONFIG_SYS_I2C_FSL | |
211 | +#define CONFIG_SYS_FSL_I2C_SPEED 200000 | |
212 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
213 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
214 | +#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
215 | +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 | |
216 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
217 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
218 | +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ | |
219 | + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ | |
220 | + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ | |
221 | + {1, {I2C_NULL_HOP} } } | |
215 | 222 | |
216 | 223 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
217 | 224 | #define CONFIG_DTT_LM75 /* ON Semi's LM75 */ |
... | ... | @@ -219,7 +226,7 @@ |
219 | 226 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
220 | 227 | #define CONFIG_SYS_DTT_LOW_TEMP -30 |
221 | 228 | #define CONFIG_SYS_DTT_HYSTERESIS 3 |
222 | -#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) | |
229 | +#define CONFIG_SYS_DTT_BUS_NUM 1 | |
223 | 230 | |
224 | 231 | #if defined(CONFIG_CMD_NAND) |
225 | 232 | #define CONFIG_NAND_KMETER1 |
... | ... | @@ -315,7 +322,7 @@ |
315 | 322 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
316 | 323 | CONFIG_KM_DEF_ENV \ |
317 | 324 | CONFIG_KM_DEF_ARCH \ |
318 | - "EEprom_ivm=pca9547:70:9\0" \ | |
325 | + "EEprom_ivm=2\0" \ | |
319 | 326 | "newenv=" \ |
320 | 327 | "prot off 0xF00C0000 +0x40000 && " \ |
321 | 328 | "era 0xF00C0000 +0x40000\0" \ |
... | ... | @@ -327,13 +327,14 @@ |
327 | 327 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
328 | 328 | |
329 | 329 | /* I2C */ |
330 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
331 | -#define CONFIG_FSL_I2C | |
332 | -#define CONFIG_I2C_MULTI_BUS | |
333 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
334 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
335 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
336 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
330 | +#define CONFIG_SYS_I2C | |
331 | +#define CONFIG_SYS_I2C_FSL | |
332 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
333 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
334 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
335 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
336 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
337 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
337 | 338 | |
338 | 339 | /* |
339 | 340 | * General PCI |
... | ... | @@ -221,13 +221,15 @@ |
221 | 221 | /* |
222 | 222 | * I2C buses and peripherals |
223 | 223 | */ |
224 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
225 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
226 | -#define CONFIG_I2C_MULTI_BUS | |
227 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
228 | -#define CONFIG_SYS_I2C_SLAVE 0x7f | |
229 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
230 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
224 | +#define CONFIG_SYS_I2C | |
225 | +#define CONFIG_SYS_I2C_FSL | |
226 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
227 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
228 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
229 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
230 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
231 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
232 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
231 | 233 | |
232 | 234 | /* I2C RTC - M41T81 */ |
233 | 235 | #define CONFIG_RTC_M41T62 |
... | ... | @@ -534,16 +534,16 @@ |
534 | 534 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
535 | 535 | |
536 | 536 | /* I2C */ |
537 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
538 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
539 | -#define CONFIG_I2C_MULTI_BUS | |
540 | -#define CONFIG_I2C_CMD_TREE | |
541 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C spd and slave address */ | |
537 | +#define CONFIG_SYS_I2C | |
538 | +#define CONFIG_SYS_I2C_FSL | |
539 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
540 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
541 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
542 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
543 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
544 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
545 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
542 | 546 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
543 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
544 | -#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe this addr */ | |
545 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
546 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
547 | 547 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ |
548 | 548 | |
549 | 549 | /* |
... | ... | @@ -304,14 +304,15 @@ |
304 | 304 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
305 | 305 | |
306 | 306 | /* I2C */ |
307 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
308 | -#define CONFIG_FSL_I2C | |
309 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
310 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
311 | -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
312 | -#define CONFIG_SYS_I2C1_OFFSET 0x3000 | |
313 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
314 | -#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET | |
307 | +#define CONFIG_SYS_I2C | |
308 | +#define CONFIG_SYS_I2C_FSL | |
309 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
310 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
311 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
312 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
313 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
314 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
315 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} } | |
315 | 316 | /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ |
316 | 317 | |
317 | 318 | /* TSEC */ |
... | ... | @@ -444,12 +444,12 @@ |
444 | 444 | /* |
445 | 445 | * I2C |
446 | 446 | */ |
447 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
448 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
449 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
447 | +#define CONFIG_SYS_I2C | |
448 | +#define CONFIG_SYS_I2C_FSL | |
449 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
450 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
451 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
450 | 452 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
451 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
452 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
453 | 453 | |
454 | 454 | /* |
455 | 455 | * General PCI |
... | ... | @@ -289,12 +289,12 @@ |
289 | 289 | /* |
290 | 290 | * I2C |
291 | 291 | */ |
292 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
293 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
294 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
295 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
296 | -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
297 | -#define CONFIG_SYS_I2C_OFFSET 0x3100 | |
292 | +#define CONFIG_SYS_I2C | |
293 | +#define CONFIG_SYS_I2C_FSL | |
294 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
295 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
296 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 | |
297 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
298 | 298 | |
299 | 299 | /* |
300 | 300 | * RapidIO MMU |
... | ... | @@ -235,14 +235,14 @@ |
235 | 235 | /* |
236 | 236 | * I2C |
237 | 237 | */ |
238 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
239 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
240 | -#define CONFIG_SYS_I2C_SPEED 102124 /* I2C speed and slave address */ | |
241 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
242 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
243 | - | |
244 | -#define CONFIG_I2C_MULTI_BUS | |
245 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
238 | +#define CONFIG_SYS_I2C | |
239 | +#define CONFIG_SYS_I2C_FSL | |
240 | +#define CONFIG_SYS_FSL_I2C_SPEED 102124 | |
241 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
242 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
243 | +#define CONFIG_SYS_FSL_I2C2_SPEED 102124 | |
244 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
245 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
246 | 246 | |
247 | 247 | /* I2C RTC */ |
248 | 248 | #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ |
... | ... | @@ -178,17 +178,18 @@ |
178 | 178 | /* |
179 | 179 | * I2C |
180 | 180 | */ |
181 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
182 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
183 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
184 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
181 | +#define CONFIG_SYS_I2C | |
182 | +#define CONFIG_SYS_I2C_FSL | |
183 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
184 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
185 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
186 | + | |
185 | 187 | #if 0 |
186 | 188 | #define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */ |
187 | 189 | #else |
188 | 190 | /* I did the 'if 0' so we could keep the syntax above if ever needed. */ |
189 | 191 | #undef CONFIG_SYS_I2C_NOPROBES |
190 | 192 | #endif |
191 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
192 | 193 | |
193 | 194 | /* RapdIO Map configuration, mapped 1:1. |
194 | 195 | */ |
... | ... | @@ -198,12 +198,12 @@ |
198 | 198 | /* |
199 | 199 | * I2C |
200 | 200 | */ |
201 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
202 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
203 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
204 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
201 | +#define CONFIG_SYS_I2C | |
202 | +#define CONFIG_SYS_I2C_FSL | |
203 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
204 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
205 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
205 | 206 | #undef CONFIG_SYS_I2C_NOPROBES |
206 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
207 | 207 | |
208 | 208 | /* I2C RTC */ |
209 | 209 | #define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */ |
... | ... | @@ -445,14 +445,15 @@ |
445 | 445 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
446 | 446 | |
447 | 447 | /* I2C */ |
448 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
449 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
450 | -#define CONFIG_I2C_MULTI_BUS | |
451 | -#define CONFIG_I2C_CMD_TREE | |
452 | -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ | |
453 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
454 | -#define CONFIG_SYS_I2C_OFFSET 0x118000 | |
455 | -#define CONFIG_SYS_I2C2_OFFSET 0x118100 | |
448 | +#define CONFIG_SYS_I2C | |
449 | +#define CONFIG_SYS_I2C_FSL | |
450 | +#define CONFIG_SYS_FSL_I2C_SPEED 100000 | |
451 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
452 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
453 | +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 | |
454 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
455 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 | |
456 | + | |
456 | 457 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ |
457 | 458 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ |
458 | 459 |
... | ... | @@ -237,16 +237,15 @@ |
237 | 237 | #define CONFIG_OF_STDOUT_VIA_ALIAS |
238 | 238 | |
239 | 239 | /* I2C */ |
240 | -#define CONFIG_I2C_MULTI_BUS | |
241 | -#define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
242 | -#define CONFIG_FSL_I2C | |
243 | -#define CONFIG_I2C_CMD_TREE | |
244 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
245 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
246 | -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ | |
247 | -#define CONFIG_SYS_I2C1_OFFSET 0x3000 | |
248 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
249 | -#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET | |
240 | +#define CONFIG_SYS_I2C | |
241 | +#define CONFIG_SYS_I2C_FSL | |
242 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
243 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
244 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
245 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
246 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
247 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
248 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
250 | 249 | /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ |
251 | 250 | |
252 | 251 | #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ |
... | ... | @@ -258,13 +258,14 @@ |
258 | 258 | /* |
259 | 259 | * I2C |
260 | 260 | */ |
261 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
262 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
263 | -#define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */ | |
264 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
265 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
266 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
267 | -#define CONFIG_I2C_MULTI_BUS | |
261 | +#define CONFIG_SYS_I2C | |
262 | +#define CONFIG_SYS_I2C_FSL | |
263 | +#define CONFIG_SYS_FSL_I2C_SPEED 100000 | |
264 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
265 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
266 | +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 | |
267 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
268 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
268 | 269 | |
269 | 270 | /* PEX8518 slave I2C interface */ |
270 | 271 | #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 |
... | ... | @@ -220,13 +220,14 @@ |
220 | 220 | /* |
221 | 221 | * I2C |
222 | 222 | */ |
223 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
224 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
225 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
226 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
227 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
228 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
229 | -#define CONFIG_I2C_MULTI_BUS | |
223 | +#define CONFIG_SYS_I2C | |
224 | +#define CONFIG_SYS_I2C_FSL | |
225 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
226 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
227 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
228 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
229 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
230 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
230 | 231 | |
231 | 232 | /* I2C EEPROM */ |
232 | 233 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
... | ... | @@ -258,13 +258,15 @@ |
258 | 258 | /* |
259 | 259 | * I2C |
260 | 260 | */ |
261 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
262 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
263 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
264 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
265 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
266 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
267 | -#define CONFIG_I2C_MULTI_BUS | |
261 | +#define CONFIG_SYS_I2C | |
262 | +#define CONFIG_SYS_I2C_FSL | |
263 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
264 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
265 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
266 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
267 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
268 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
269 | +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
268 | 270 | |
269 | 271 | /* PEX8518 slave I2C interface */ |
270 | 272 | #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 |
... | ... | @@ -249,13 +249,14 @@ |
249 | 249 | /* |
250 | 250 | * I2C |
251 | 251 | */ |
252 | -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
253 | -#define CONFIG_HARD_I2C /* I2C with hardware support */ | |
254 | -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
255 | -#define CONFIG_SYS_I2C_SLAVE 0x7F | |
256 | -#define CONFIG_SYS_I2C_OFFSET 0x3000 | |
257 | -#define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
258 | -#define CONFIG_I2C_MULTI_BUS | |
252 | +#define CONFIG_SYS_I2C | |
253 | +#define CONFIG_SYS_I2C_FSL | |
254 | +#define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
255 | +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
256 | +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
257 | +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
258 | +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
259 | +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
259 | 260 | |
260 | 261 | /* I2C DS7505 temperature sensor */ |
261 | 262 | #define CONFIG_DTT_LM75 |
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