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Commit 0133502e39ff89b67c26cb4015e0e7e8d9571184

Authored by Matthias Fuchs
Committed by Wolfgang Denk
1 parent 95c6bc7d4a
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Improve configuration of FPGA subsystem 

This patch removes the FPGA subsystem configuration through
the CONFIG_FPGA bitmask configuration option.

See README for the new options:

	CONFIG_FPGA,
	CONFIG_FPGA_<vendor>,
	CONFIG_FPGA_<family>

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

Showing 16 changed files with 69 additions and 62 deletions Side-by-side Diff

... ... @@ -1377,14 +1377,23 @@
1377 1377 SPI configuration items (port pins to use, etc). For
1378 1378 an example, see include/configs/sacsng.h.
1379 1379  
1380   -- FPGA Support: CONFIG_FPGA_COUNT
  1380 +- FPGA Support: CONFIG_FPGA
1381 1381  
1382   - Specify the number of FPGA devices to support.
  1382 + Enables FPGA subsystem.
1383 1383  
1384   - CONFIG_FPGA
  1384 + CONFIG_FPGA_<vendor>
1385 1385  
1386   - Used to specify the types of FPGA devices. For example,
1387   - #define CONFIG_FPGA CFG_XILINX_VIRTEX2
  1386 + Enables support for specific chip vendors.
  1387 + (ALTERA, XILINX)
  1388 +
  1389 + CONFIG_FPGA_<family>
  1390 +
  1391 + Enables support for FPGA family.
  1392 + (SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
  1393 +
  1394 + CONFIG_FPGA_COUNT
  1395 +
  1396 + Specify the number of FPGA devices to support.
1388 1397  
1389 1398 CFG_FPGA_PROG_FEEDBACK
1390 1399  
board/gen860t/fpga.c
Diff comments   View file @ 0133502
... ... @@ -34,7 +34,7 @@
34 34  
35 35 DECLARE_GLOBAL_DATA_PTR;
36 36  
37   -#if (CONFIG_FPGA)
  37 +#if defined(CONFIG_FPGA)
38 38  
39 39 #if 0
40 40 #define GEN860T_FPGA_DEBUG
board/gen860t/gen860t.c
Diff comments   View file @ 0133502
... ... @@ -254,7 +254,7 @@
254 254 mii_init ();
255 255 #endif
256 256  
257   -#if (CONFIG_FPGA)
  257 +#if defined(CONFIG_FPGA)
258 258 gen860t_init_fpga ();
259 259 #endif
260 260 return 0;
... ... @@ -28,7 +28,7 @@
28 28 #include <common.h> /* core U-Boot definitions */
29 29 #include <ACEX1K.h> /* ACEX device family */
30 30  
31   -#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
  31 +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_ACEX1K)
32 32  
33 33 /* Define FPGA_DEBUG to get debug printf's */
34 34 #ifdef FPGA_DEBUG
... ... @@ -363,5 +363,5 @@
363 363  
364 364 }
365 365  
366   -#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */
  366 +#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_ACEX1K */
... ... @@ -40,7 +40,7 @@
40 40 #define PRINTF(fmt,args...)
41 41 #endif
42 42  
43   -#if (CONFIG_FPGA & CFG_FPGA_ALTERA)
  43 +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA)
44 44  
45 45 /* Local Static Functions */
46 46 static int altera_validate (Altera_desc * desc, char *fn);
47 47  
... ... @@ -56,11 +56,11 @@
56 56 switch (desc->family) {
57 57 case Altera_ACEX1K:
58 58 case Altera_CYC2:
59   -#if (CONFIG_FPGA & CFG_ACEX1K)
  59 +#if defined(CONFIG_FPGA_ACEX1K)
60 60 PRINTF ("%s: Launching the ACEX1K Loader...\n",
61 61 __FUNCTION__);
62 62 ret_val = ACEX1K_load (desc, buf, bsize);
63   -#elif (CONFIG_FPGA & CFG_CYCLON2)
  63 +#elif defined CONFIG_FPGA_CYCLON2
64 64 PRINTF ("%s: Launching the CYCLON II Loader...\n",
65 65 __FUNCTION__);
66 66 ret_val = CYC2_load (desc, buf, bsize);
... ... @@ -88,7 +88,7 @@
88 88 } else {
89 89 switch (desc->family) {
90 90 case Altera_ACEX1K:
91   -#if (CONFIG_FPGA & CFG_ACEX)
  91 +#if defined(CONFIG_FPGA_ACEX)
92 92 PRINTF ("%s: Launching the ACEX1K Reader...\n",
93 93 __FUNCTION__);
94 94 ret_val = ACEX1K_dump (desc, buf, bsize);
95 95  
... ... @@ -156,9 +156,9 @@
156 156 switch (desc->family) {
157 157 case Altera_ACEX1K:
158 158 case Altera_CYC2:
159   -#if (CONFIG_FPGA & CFG_ACEX1K)
  159 +#if defined(CONFIG_FPGA_ACEX1K)
160 160 ACEX1K_info (desc);
161   -#elif (CONFIG_FPGA & CFG_CYCLON2)
  161 +#elif defined(CONFIG_FPGA_CYCLON2)
162 162 CYC2_info (desc);
163 163 #else
164 164 /* just in case */
... ... @@ -192,7 +192,7 @@
192 192 } else {
193 193 switch (desc->family) {
194 194 case Altera_ACEX1K:
195   -#if (CONFIG_FPGA & CFG_ACEX1K)
  195 +#if defined(CONFIG_FPGA_ACEX1K)
196 196 ret_val = ACEX1K_reloc (desc, reloc_offset);
197 197 #else
198 198 printf ("%s: No support for ACEX devices.\n",
... ... @@ -200,7 +200,7 @@
200 200 #endif
201 201 break;
202 202 case Altera_CYC2:
203   -#if (CONFIG_FPGA & CFG_CYCLON2)
  203 +#if defined(CONFIG_FPGA_CYCLON2)
204 204 ret_val = CYC2_reloc (desc, reloc_offset);
205 205 #else
206 206 printf ("%s: No support for CYCLON II devices.\n",
... ... @@ -249,5 +249,5 @@
249 249  
250 250 /* ------------------------------------------------------------------------- */
251 251  
252   -#endif /* CONFIG_FPGA & CFG_FPGA_ALTERA */
  252 +#endif /* CONFIG_FPGA & CONFIG_FPGA_ALTERA */
... ... @@ -58,7 +58,7 @@
58 58 /* Convert bitstream data and load into the fpga */
59 59 int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
60 60 {
61   -#if (CONFIG_FPGA & CFG_FPGA_XILINX)
  61 +#if defined(CONFIG_FPGA_XILINX)
62 62 unsigned int length;
63 63 unsigned char* swapdata;
64 64 unsigned int swapsize;
... ... @@ -27,7 +27,7 @@
27 27 #include <altera.h>
28 28 #include <ACEX1K.h> /* ACEX device family */
29 29  
30   -#if (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2))
  30 +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_CYCLON2)
31 31  
32 32 /* Define FPGA_DEBUG to get debug printf's */
33 33 #ifdef FPGA_DEBUG
... ... @@ -302,5 +302,5 @@
302 302 return ret_val;
303 303 }
304 304  
305   -#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) */
  305 +#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_CYCLON2 */
... ... @@ -67,14 +67,11 @@
67 67 static void fpga_no_sup( char *fn, char *msg )
68 68 {
69 69 if ( fn && msg ) {
70   - printf( "%s: No support for %s. CONFIG_FPGA defined as 0x%x.\n",
71   - fn, msg, CONFIG_FPGA );
  70 + printf( "%s: No support for %s.\n", fn, msg);
72 71 } else if ( msg ) {
73   - printf( "No support for %s. CONFIG_FPGA defined as 0x%x.\n",
74   - msg, CONFIG_FPGA );
  72 + printf( "No support for %s.\n", msg);
75 73 } else {
76   - printf( "No FPGA suport! CONFIG_FPGA defined as 0x%x.\n",
77   - CONFIG_FPGA );
  74 + printf( "No FPGA suport!\n");
78 75 }
79 76 }
80 77  
... ... @@ -112,11 +109,6 @@
112 109 printf( "%s: Null buffer.\n", fn );
113 110 return (fpga_desc * const)NULL;
114 111 }
115   - if ( !bsize ) {
116   - printf( "%s: Null buffer size.\n", fn );
117   - return (fpga_desc * const)NULL;
118   - }
119   -
120 112 return desc;
121 113 }
122 114  
... ... @@ -135,7 +127,7 @@
135 127  
136 128 switch ( desc->devtype ) {
137 129 case fpga_xilinx:
138   -#if CONFIG_FPGA & CFG_FPGA_XILINX
  130 +#if defined(CONFIG_FPGA_XILINX)
139 131 printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc );
140 132 ret_val = xilinx_info( desc->devdesc );
141 133 #else
... ... @@ -143,7 +135,7 @@
143 135 #endif
144 136 break;
145 137 case fpga_altera:
146   -#if CONFIG_FPGA & CFG_FPGA_ALTERA
  138 +#if defined(CONFIG_FPGA_ALTERA)
147 139 printf( "Altera Device\nDescriptor @ 0x%p\n", desc );
148 140 ret_val = altera_info( desc->devdesc );
149 141 #else
150 142  
... ... @@ -175,14 +167,14 @@
175 167  
176 168 switch ( devtype ) {
177 169 case fpga_xilinx:
178   -#if CONFIG_FPGA & CFG_FPGA_XILINX
  170 +#if defined(CONFIG_FPGA_XILINX)
179 171 ret_val = xilinx_reloc( desc, reloc_off );
180 172 #else
181 173 fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
182 174 #endif
183 175 break;
184 176 case fpga_altera:
185   -#if CONFIG_FPGA & CFG_FPGA_ALTERA
  177 +#if defined(CONFIG_FPGA_ALTERA)
186 178 ret_val = altera_reloc( desc, reloc_off );
187 179 #else
188 180 fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
189 181  
... ... @@ -268,14 +260,14 @@
268 260 if ( desc ) {
269 261 switch ( desc->devtype ) {
270 262 case fpga_xilinx:
271   -#if CONFIG_FPGA & CFG_FPGA_XILINX
  263 +#if defined(CONFIG_FPGA_XILINX)
272 264 ret_val = xilinx_load( desc->devdesc, buf, bsize );
273 265 #else
274 266 fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
275 267 #endif
276 268 break;
277 269 case fpga_altera:
278   -#if CONFIG_FPGA & CFG_FPGA_ALTERA
  270 +#if defined(CONFIG_FPGA_ALTERA)
279 271 ret_val = altera_load( desc->devdesc, buf, bsize );
280 272 #else
281 273 fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
282 274  
... ... @@ -301,14 +293,14 @@
301 293 if ( desc ) {
302 294 switch ( desc->devtype ) {
303 295 case fpga_xilinx:
304   -#if CONFIG_FPGA & CFG_FPGA_XILINX
  296 +#if defined(CONFIG_FPGA_XILINX)
305 297 ret_val = xilinx_dump( desc->devdesc, buf, bsize );
306 298 #else
307 299 fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
308 300 #endif
309 301 break;
310 302 case fpga_altera:
311   -#if CONFIG_FPGA & CFG_FPGA_ALTERA
  303 +#if defined(CONFIG_FPGA_ALTERA)
312 304 ret_val = altera_dump( desc->devdesc, buf, bsize );
313 305 #else
314 306 fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
... ... @@ -25,7 +25,7 @@
25 25 #include <common.h> /* core U-Boot definitions */
26 26 #include <spartan2.h> /* Spartan-II device family */
27 27  
28   -#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN2))
  28 +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN2)
29 29  
30 30 /* Define FPGA_DEBUG to get debug printf's */
31 31 #ifdef FPGA_DEBUG
... ... @@ -30,7 +30,7 @@
30 30 #include <common.h> /* core U-Boot definitions */
31 31 #include <spartan3.h> /* Spartan-II device family */
32 32  
33   -#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN3))
  33 +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN3)
34 34  
35 35 /* Define FPGA_DEBUG to get debug printf's */
36 36 #ifdef FPGA_DEBUG
... ... @@ -31,7 +31,7 @@
31 31 #include <common.h>
32 32 #include <virtex2.h>
33 33  
34   -#if (CONFIG_FPGA & (CFG_XILINX | CFG_VIRTEX2))
  34 +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_VIRTEX2)
35 35  
36 36 #if 0
37 37 #define FPGA_DEBUG
... ... @@ -32,7 +32,7 @@
32 32 #include <spartan2.h>
33 33 #include <spartan3.h>
34 34  
35   -#if (CONFIG_FPGA & CFG_FPGA_XILINX)
  35 +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
36 36  
37 37 #if 0
38 38 #define FPGA_DEBUG
... ... @@ -59,7 +59,7 @@
59 59 } else
60 60 switch (desc->family) {
61 61 case Xilinx_Spartan2:
62   -#if (CONFIG_FPGA & CFG_SPARTAN2)
  62 +#if defined(CONFIG_FPGA_SPARTAN2)
63 63 PRINTF ("%s: Launching the Spartan-II Loader...\n",
64 64 __FUNCTION__);
65 65 ret_val = Spartan2_load (desc, buf, bsize);
... ... @@ -69,7 +69,7 @@
69 69 #endif
70 70 break;
71 71 case Xilinx_Spartan3:
72   -#if (CONFIG_FPGA & CFG_SPARTAN3)
  72 +#if defined(CONFIG_FPGA_SPARTAN3)
73 73 PRINTF ("%s: Launching the Spartan-III Loader...\n",
74 74 __FUNCTION__);
75 75 ret_val = Spartan3_load (desc, buf, bsize);
... ... @@ -79,7 +79,7 @@
79 79 #endif
80 80 break;
81 81 case Xilinx_Virtex2:
82   -#if (CONFIG_FPGA & CFG_VIRTEX2)
  82 +#if defined(CONFIG_FPGA_VIRTEX2)
83 83 PRINTF ("%s: Launching the Virtex-II Loader...\n",
84 84 __FUNCTION__);
85 85 ret_val = Virtex2_load (desc, buf, bsize);
... ... @@ -106,7 +106,7 @@
106 106 } else
107 107 switch (desc->family) {
108 108 case Xilinx_Spartan2:
109   -#if (CONFIG_FPGA & CFG_SPARTAN2)
  109 +#if defined(CONFIG_FPGA_SPARTAN2)
110 110 PRINTF ("%s: Launching the Spartan-II Reader...\n",
111 111 __FUNCTION__);
112 112 ret_val = Spartan2_dump (desc, buf, bsize);
... ... @@ -116,7 +116,7 @@
116 116 #endif
117 117 break;
118 118 case Xilinx_Spartan3:
119   -#if (CONFIG_FPGA & CFG_SPARTAN3)
  119 +#if defined(CONFIG_FPGA_SPARTAN3)
120 120 PRINTF ("%s: Launching the Spartan-III Reader...\n",
121 121 __FUNCTION__);
122 122 ret_val = Spartan3_dump (desc, buf, bsize);
... ... @@ -126,7 +126,7 @@
126 126 #endif
127 127 break;
128 128 case Xilinx_Virtex2:
129   -#if (CONFIG_FPGA & CFG_VIRTEX2)
  129 +#if defined( CONFIG_FPGA_VIRTEX2)
130 130 PRINTF ("%s: Launching the Virtex-II Reader...\n",
131 131 __FUNCTION__);
132 132 ret_val = Virtex2_dump (desc, buf, bsize);
... ... @@ -198,7 +198,7 @@
198 198 printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
199 199 switch (desc->family) {
200 200 case Xilinx_Spartan2:
201   -#if (CONFIG_FPGA & CFG_SPARTAN2)
  201 +#if defined(CONFIG_FPGA_SPARTAN2)
202 202 Spartan2_info (desc);
203 203 #else
204 204 /* just in case */
... ... @@ -207,7 +207,7 @@
207 207 #endif
208 208 break;
209 209 case Xilinx_Spartan3:
210   -#if (CONFIG_FPGA & CFG_SPARTAN3)
  210 +#if defined(CONFIG_FPGA_SPARTAN3)
211 211 Spartan3_info (desc);
212 212 #else
213 213 /* just in case */
... ... @@ -216,7 +216,7 @@
216 216 #endif
217 217 break;
218 218 case Xilinx_Virtex2:
219   -#if (CONFIG_FPGA & CFG_VIRTEX2)
  219 +#if defined(CONFIG_FPGA_VIRTEX2)
220 220 Virtex2_info (desc);
221 221 #else
222 222 /* just in case */
... ... @@ -249,7 +249,7 @@
249 249 } else
250 250 switch (desc->family) {
251 251 case Xilinx_Spartan2:
252   -#if (CONFIG_FPGA & CFG_SPARTAN2)
  252 +#if defined(CONFIG_FPGA_SPARTAN2)
253 253 ret_val = Spartan2_reloc (desc, reloc_offset);
254 254 #else
255 255 printf ("%s: No support for Spartan-II devices.\n",
... ... @@ -257,7 +257,7 @@
257 257 #endif
258 258 break;
259 259 case Xilinx_Spartan3:
260   -#if (CONFIG_FPGA & CFG_SPARTAN3)
  260 +#if defined(CONFIG_FPGA_SPARTAN3)
261 261 ret_val = Spartan3_reloc (desc, reloc_offset);
262 262 #else
263 263 printf ("%s: No support for Spartan-III devices.\n",
... ... @@ -265,7 +265,7 @@
265 265 #endif
266 266 break;
267 267 case Xilinx_Virtex2:
268   -#if (CONFIG_FPGA & CFG_VIRTEX2)
  268 +#if defined(CONFIG_FPGA_VIRTEX2)
269 269 ret_val = Virtex2_reloc (desc, reloc_offset);
270 270 #else
271 271 printf ("%s: No support for Virtex-II devices.\n",
... ... @@ -308,5 +308,5 @@
308 308 return ret_val;
309 309 }
310 310  
311   -#endif /* CONFIG_FPGA & CFG_FPGA_XILINX */
  311 +#endif /* CONFIG_FPGA && CONFIG_FPGA_XILINX */
include/configs/GEN860T.h
Diff comments   View file @ 0133502
... ... @@ -273,7 +273,9 @@
273 273 * Virtex2 FPGA configuration support
274 274 */
275 275 #define CONFIG_FPGA_COUNT 1
276   -#define CONFIG_FPGA CFG_XILINX_VIRTEX2
  276 +#define CONFIG_FPGA
  277 +#define CONFIG_FPGA_XILINX
  278 +#define CONFIG_FPGA_VIRTEX2
277 279 #define CFG_FPGA_PROG_FEEDBACK
278 280  
279 281  
include/configs/M54455EVB.h
Diff comments   View file @ 0133502
... ... @@ -192,7 +192,9 @@
192 192  
193 193 /* FPGA - Spartan 2 */
194 194 /* experiment
195   -#define CONFIG_FPGA CFG_SPARTAN3
  195 +#define CONFIG_FPGA
  196 +#define CONFIG_FPGA_XILINX
  197 +#define CONFIG_FPGA_SPARTAN3
196 198 #define CONFIG_FPGA_COUNT 1
197 199 #define CFG_FPGA_PROG_FEEDBACK
198 200 #define CFG_FPGA_CHECK_CTRLC
include/configs/alpr.h
Diff comments   View file @ 0133502
... ... @@ -296,7 +296,9 @@
296 296 /*-----------------------------------------------------------------------
297 297 * FPGA stuff
298 298 *-----------------------------------------------------------------------*/
299   -#define CONFIG_FPGA CFG_ALTERA_CYCLON2
  299 +#define CONFIG_FPGA
  300 +#define CONFIG_FPGA_ALTERA
  301 +#define CONFIG_FPGA_CYCLON2
300 302 #define CFG_FPGA_CHECK_CTRLC
301 303 #define CFG_FPGA_PROG_FEEDBACK
302 304 #define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
... ... @@ -31,11 +31,11 @@
31 31 *********************************************************************/
32 32 #define CFG_SPARTAN2 CFG_FPGA_DEV( 0x1 )
33 33 #define CFG_VIRTEX_E CFG_FPGA_DEV( 0x2 )
34   -#define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 )
  34 +#define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 )
35 35 #define CFG_SPARTAN3 CFG_FPGA_DEV( 0x8 )
36 36 #define CFG_XILINX_SPARTAN2 (CFG_FPGA_XILINX | CFG_SPARTAN2)
37 37 #define CFG_XILINX_VIRTEX_E (CFG_FPGA_XILINX | CFG_VIRTEX_E)
38   -#define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2)
  38 +#define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2)
39 39 #define CFG_XILINX_SPARTAN3 (CFG_FPGA_XILINX | CFG_SPARTAN3)
40 40 /* XXX - Add new models here */
41 41