Commit 01996acd7788c831fc06872c59af99f3bd6f6b03
1 parent
c3e9e81a4c
Exists in
smarc-imx-l5.0.0_1.0.0-ga
ENGR00326994 iMX6: Checking PLL2 PFD0 and PFD2 for periph_clk before reset
u-boot v2014 upstream codes have a problem in pfd reset (s_init function) that imx6 Dual is not applied for PLL2 PFD2 reset. It is originated by using dynamical cpu type checking and introducing two cpu types: MXC_CPU_MX6Q and MXC_CPU_MX6D for iMX6 Dual/Quad platform. Fixed this problem by checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source, do not reset this PFD to avoid system hang. Signed-off-by: Ye.Li <B37916@freescale.com>
Showing 1 changed file with 16 additions and 7 deletions Side-by-side Diff
arch/arm/cpu/armv7/mx6/soc.c
| ... | ... | @@ -734,10 +734,11 @@ |
| 734 | 734 | void s_init(void) |
| 735 | 735 | { |
| 736 | 736 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
| 737 | - int is_6q = is_cpu_type(MXC_CPU_MX6Q); | |
| 737 | + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
| 738 | 738 | int is_6sx = is_cpu_type(MXC_CPU_MX6SX); |
| 739 | 739 | u32 mask480; |
| 740 | 740 | u32 mask528; |
| 741 | + u32 reg, periph1, periph2; | |
| 741 | 742 | |
| 742 | 743 | /* Don't reset PFD for MX6SX */ |
| 743 | 744 | if (is_6sx) |
| 744 | 745 | |
| 745 | 746 | |
| ... | ... | @@ -753,15 +754,23 @@ |
| 753 | 754 | ANATOP_PFD_CLKGATE_MASK(1) | |
| 754 | 755 | ANATOP_PFD_CLKGATE_MASK(2) | |
| 755 | 756 | ANATOP_PFD_CLKGATE_MASK(3); |
| 756 | - mask528 = ANATOP_PFD_CLKGATE_MASK(0) | | |
| 757 | - ANATOP_PFD_CLKGATE_MASK(1) | | |
| 757 | + mask528 = ANATOP_PFD_CLKGATE_MASK(1) | | |
| 758 | 758 | ANATOP_PFD_CLKGATE_MASK(3); |
| 759 | 759 | |
| 760 | - /* | |
| 761 | - * Don't reset PFD2 on DL/S | |
| 762 | - */ | |
| 763 | - if (is_6q) | |
| 760 | + reg = readl(&ccm->cbcmr); | |
| 761 | + periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) | |
| 762 | + >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET); | |
| 763 | + periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) | |
| 764 | + >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET); | |
| 765 | + | |
| 766 | + /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */ | |
| 767 | + if ((periph2 != 0x2) && (periph1 != 0x2)) | |
| 768 | + mask528 |= ANATOP_PFD_CLKGATE_MASK(0); | |
| 769 | + | |
| 770 | + if ((periph2 != 0x1) && (periph1 != 0x1) && | |
| 771 | + (periph2 != 0x3) && (periph1 != 0x3)) | |
| 764 | 772 | mask528 |= ANATOP_PFD_CLKGATE_MASK(2); |
| 773 | + | |
| 765 | 774 | writel(mask480, &anatop->pfd_480_set); |
| 766 | 775 | writel(mask528, &anatop->pfd_528_set); |
| 767 | 776 | writel(mask480, &anatop->pfd_480_clr); |