Eric Lee / smarc-uboot

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Commit 0345fb035f2ae88e374349c8519386fd2b46d312

Authored by Eric Lee
1 parent e29075cdf5
Exists in smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga

U-Boot for eMMC Boot Up

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

include/configs/smarcfimx6.h
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1 /* 1 /*
2 * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. 2 * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
3 * 3 *
4 * Configuration settings for the Freescale i.MX6Q SabreSD board. 4 * Configuration settings for the Freescale i.MX6Q SabreSD board.
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #ifndef __SMARCFIMX6_CONFIG_H 9 #ifndef __SMARCFIMX6_CONFIG_H
10 #define __SMARCFIMX6_CONFIG_H 10 #define __SMARCFIMX6_CONFIG_H
11 11
12 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/imx-regs.h>
13 #include <asm/imx-common/gpio.h> 13 #include <asm/imx-common/gpio.h>
14 14
15 #define CONFIG_MACH_TYPE_SMARCFIMX6 3990 /*Until the next sync */ 15 #define CONFIG_MACH_TYPE_SMARCFIMX6 3990 /*Until the next sync */
16 #define CONFIG_MACH_TYPE MACH_TYPE_SMARCFIMX6 16 #define CONFIG_MACH_TYPE MACH_TYPE_SMARCFIMX6
17 #if defined(CONFIG_SER0) 17 #if defined(CONFIG_SER0)
18 #define CONFIG_MXC_UART_BASE UART1_BASE 18 #define CONFIG_MXC_UART_BASE UART1_BASE
19 #define CONFIG_CONSOLE_DEV "ttymxc0" 19 #define CONFIG_CONSOLE_DEV "ttymxc0"
20 #endif 20 #endif
21 #if defined(CONFIG_SER1) 21 #if defined(CONFIG_SER1)
22 #define CONFIG_MXC_UART_BASE UART2_BASE 22 #define CONFIG_MXC_UART_BASE UART2_BASE
23 #define CONFIG_CONSOLE_DEV "ttymxc1" 23 #define CONFIG_CONSOLE_DEV "ttymxc1"
24 #endif 24 #endif
25 #if defined(CONFIG_SER2) 25 #if defined(CONFIG_SER2)
26 #define CONFIG_MXC_UART_BASE UART4_BASE 26 #define CONFIG_MXC_UART_BASE UART4_BASE
27 #define CONFIG_CONSOLE_DEV "ttymxc3" 27 #define CONFIG_CONSOLE_DEV "ttymxc3"
28 #endif 28 #endif
29 #if defined(CONFIG_SER3) 29 #if defined(CONFIG_SER3)
30 #define CONFIG_MXC_UART_BASE UART5_BASE 30 #define CONFIG_MXC_UART_BASE UART5_BASE
31 #define CONFIG_CONSOLE_DEV "ttymxc4" 31 #define CONFIG_CONSOLE_DEV "ttymxc4"
32 #endif 32 #endif
33 #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* SDHC3 */ 33 #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* SDHC3 */
34 34
35 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6SOLO) 35 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6SOLO)
36 #define CONFIG_DEFAULT_FDT_FILE "imx6dl-smarcfimx6.dtb" 36 #define CONFIG_DEFAULT_FDT_FILE "imx6dl-smarcfimx6.dtb"
37 #elif defined(CONFIG_MX6Q) 37 #elif defined(CONFIG_MX6Q)
38 #define CONFIG_DEFAULT_FDT_FILE "imx6q-smarcfimx6.dtb" 38 #define CONFIG_DEFAULT_FDT_FILE "imx6q-smarcfimx6.dtb"
39 #endif 39 #endif
40 40
41 #include "smarcfimx6_common.h" 41 #include "smarcfimx6_common.h"
42 42
43 /* USB Configs */ 43 /* USB Configs */
44 #define CONFIG_CMD_USB 44 #define CONFIG_CMD_USB
45 #define CONFIG_USB_EHCI 45 #define CONFIG_USB_EHCI
46 #define CONFIG_USB_EHCI_MX6 46 #define CONFIG_USB_EHCI_MX6
47 #define CONFIG_USB_STORAGE 47 #define CONFIG_USB_STORAGE
48 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 48 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
49 #define CONFIG_USB_HOST_ETHER 49 #define CONFIG_USB_HOST_ETHER
50 #define CONFIG_USB_ETHER_ASIX 50 #define CONFIG_USB_ETHER_ASIX
51 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 51 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
52 #define CONFIG_MXC_USB_FLAGS 0 52 #define CONFIG_MXC_USB_FLAGS 0
53 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ 53 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
54 54
55 #define CONFIG_SYS_FSL_USDHC_NUM 3 55 #define CONFIG_SYS_FSL_USDHC_NUM 3
56 #define CONFIG_SYS_MMC_ENV_DEV 0 /* 0 SDHC, 1 SDMMC, 2 eMMC */ 56 #define CONFIG_SYS_MMC_ENV_DEV 2 /* 0 SDHC, 1 SDMMC, 2 eMMC */
57 #define CONFIG_SYS_MMC_ENV_PART 2 /* user partition */ 57 #define CONFIG_SYS_MMC_ENV_PART 2 /* user partition */
58 58
59 #ifdef CONFIG_SYS_USE_SPINOR 59 #ifdef CONFIG_SYS_USE_SPINOR
60 #define CONFIG_SF_DEFAULT_CS (1|(IMX_GPIO_NR(5, 29)<<8)) /* Use SPI2 SS0 as chip select */ 60 #define CONFIG_SF_DEFAULT_CS (1|(IMX_GPIO_NR(5, 29)<<8)) /* Use SPI2 SS0 as chip select */
61 #endif 61 #endif
62 62
63 /* 63 /*
64 * imx6 q/dl/solo pcie would be failed to work properly in kernel, if 64 * imx6 q/dl/solo pcie would be failed to work properly in kernel, if
65 * the pcie module is iniialized/enumerated both in uboot and linux 65 * the pcie module is iniialized/enumerated both in uboot and linux
66 * kernel. 66 * kernel.
67 * rootcause:imx6 q/dl/solo pcie don't have the reset mechanism. 67 * rootcause:imx6 q/dl/solo pcie don't have the reset mechanism.
68 * it is only be RESET by the POR. So, the pcie module only be 68 * it is only be RESET by the POR. So, the pcie module only be
69 * initialized/enumerated once in one POR. 69 * initialized/enumerated once in one POR.
70 * Set to use pcie in kernel defaultly, mask the pcie config here. 70 * Set to use pcie in kernel defaultly, mask the pcie config here.
71 * Remove the mask freely, if the uboot pcie functions, rather than 71 * Remove the mask freely, if the uboot pcie functions, rather than
72 * the kernel's, are required. 72 * the kernel's, are required.
73 */ 73 */
74 /* #define CONFIG_CMD_PCI */ 74 /* #define CONFIG_CMD_PCI */
75 #ifdef CONFIG_CMD_PCI 75 #ifdef CONFIG_CMD_PCI
76 #define CONFIG_PCI 76 #define CONFIG_PCI
77 #define CONFIG_PCI_PNP 77 #define CONFIG_PCI_PNP
78 #define CONFIG_PCI_SCAN_SHOW 78 #define CONFIG_PCI_SCAN_SHOW
79 #define CONFIG_PCIE_IMX 79 #define CONFIG_PCIE_IMX
80 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(1, 20) 80 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(1, 20)
81 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 17) 81 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 17)
82 #endif 82 #endif
83 83
84 /*#define CONFIG_SPLASH_SCREEN*/ 84 /*#define CONFIG_SPLASH_SCREEN*/
85 /*#define CONFIG_MXC_EPDC*/ 85 /*#define CONFIG_MXC_EPDC*/
86 86
87 /* 87 /*
88 * SPLASH SCREEN Configs 88 * SPLASH SCREEN Configs
89 */ 89 */
90 #if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC) 90 #if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC)
91 /* 91 /*
92 * Framebuffer and LCD 92 * Framebuffer and LCD
93 */ 93 */
94 #define CONFIG_CMD_BMP 94 #define CONFIG_CMD_BMP
95 #define CONFIG_LCD 95 #define CONFIG_LCD
96 #define CONFIG_FB_BASE (CONFIG_SYS_TEXT_BASE + 0x300000) 96 #define CONFIG_FB_BASE (CONFIG_SYS_TEXT_BASE + 0x300000)
97 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 97 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
98 #undef LCD_TEST_PATTERN 98 #undef LCD_TEST_PATTERN
99 /* #define CONFIG_SPLASH_IS_IN_MMC 1 */ 99 /* #define CONFIG_SPLASH_IS_IN_MMC 1 */
100 #define LCD_BPP LCD_MONOCHROME 100 #define LCD_BPP LCD_MONOCHROME
101 /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ 101 /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
102 102
103 #define CONFIG_WORKING_BUF_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) 103 #define CONFIG_WORKING_BUF_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
104 #define CONFIG_WAVEFORM_BUF_ADDR (CONFIG_SYS_TEXT_BASE + 0x200000) 104 #define CONFIG_WAVEFORM_BUF_ADDR (CONFIG_SYS_TEXT_BASE + 0x200000)
105 #define CONFIG_WAVEFORM_FILE_OFFSET 0x600000 105 #define CONFIG_WAVEFORM_FILE_OFFSET 0x600000
106 #define CONFIG_WAVEFORM_FILE_SIZE 0xF0A00 106 #define CONFIG_WAVEFORM_FILE_SIZE 0xF0A00
107 #define CONFIG_WAVEFORM_FILE_IN_MMC 107 #define CONFIG_WAVEFORM_FILE_IN_MMC
108 108
109 #ifdef CONFIG_SPLASH_IS_IN_MMC 109 #ifdef CONFIG_SPLASH_IS_IN_MMC
110 #define CONFIG_SPLASH_IMG_OFFSET 0x4c000 110 #define CONFIG_SPLASH_IMG_OFFSET 0x4c000
111 #define CONFIG_SPLASH_IMG_SIZE 0x19000 111 #define CONFIG_SPLASH_IMG_SIZE 0x19000
112 #endif 112 #endif
113 #endif /* CONFIG_SPLASH_SCREEN && CONFIG_MXC_EPDC */ 113 #endif /* CONFIG_SPLASH_SCREEN && CONFIG_MXC_EPDC */
114 114
115 #endif /* __SMARCFIMX6_CONFIG_H */ 115 #endif /* __SMARCFIMX6_CONFIG_H */
116 116