Eric Lee / smarc-uboot

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Commit e29075cdf5360ea560e394c7998dfd6a599cc714

Authored by Eric Lee
1 parent 7b32eaef28
Exists in smarc-imx_v2014.04_3.14.28_1.0.0_ga and in 2 other branches smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga

Add SMARC-FiMX6 Solo/DualLite/Dual/Quad Core Initial Supports

Showing 20 changed files with 3556 additions and 5 deletions Side-by-side Diff

arch/arm/imx-common/cpu.c
Diff comments   View file @ e29075c
... ... @@ -199,9 +199,6 @@
199 199  
200 200 void arch_preboot_os(void)
201 201 {
202   -#if defined(CONFIG_LDO_BYPASS_CHECK)
203   - ldo_mode_set(check_ldo_bypass());
204   -#endif
205 202 #if defined(CONFIG_VIDEO_IPUV3)
206 203 /* disable video before launching O/S */
207 204 ipuv3_fb_shutdown();
arch/arm/include/asm/imx-common/video.h
Diff comments   View file @ e29075c
  1 +/*
  2 + * SPDX-License-Identifier: GPL-2.0+
  3 + */
  4 +
  5 +#ifndef __IMX_VIDEO_H_
  6 +#define __IMX_VIDEO_H_
  7 +
  8 +#include <linux/fb.h>
  9 +#include <ipu_pixfmt.h>
  10 +
  11 +struct display_info_t {
  12 + int bus;
  13 + int addr;
  14 + int pixfmt;
  15 + int (*detect)(struct display_info_t const *dev);
  16 + void (*enable)(struct display_info_t const *dev);
  17 + struct fb_videomode mode;
  18 +};
  19 +
  20 +#ifdef CONFIG_IMX_HDMI
  21 +extern int detect_hdmi(struct display_info_t const *dev);
  22 +#endif
  23 +
  24 +#ifdef CONFIG_IMX_VIDEO_SKIP
  25 +extern struct display_info_t const displays[];
  26 +extern size_t display_count;
  27 +#endif
  28 +
  29 +#endif
arch/arm/include/asm/mach-types.h
Diff comments   View file @ e29075c
... ... @@ -1105,6 +1105,7 @@
1105 1105 #define MACH_TYPE_ATDGP318 3494
1106 1106 #define MACH_TYPE_OMAP5_SEVM 3777
1107 1107 #define MACH_TYPE_ARMADILLO_800EVA 3863
  1108 +#define MACH_TYPE_SMARCFIMX6 3990
1108 1109 #define MACH_TYPE_KZM9G 4140
1109 1110  
1110 1111 #ifdef CONFIG_ARCH_EBSA110
... ... @@ -3625,6 +3626,18 @@
3625 3626 # define machine_is_armadillo5x0() (machine_arch_type == MACH_TYPE_ARMADILLO5X0)
3626 3627 #else
3627 3628 # define machine_is_armadillo5x0() (0)
  3629 +#endif
  3630 +
  3631 +#ifdef CONFIG_MACH_SMARCFIMX6
  3632 +# ifdef machine_arch_type
  3633 +# undef machine_arch_type
  3634 +# define machine_arch_type __machine_arch_type
  3635 +# else
  3636 +# define machine_arch_type MACH_TYPE_SMARCFIMX6
  3637 +# endif
  3638 +# define machine_is_smarcfimx6() (machine_arch_type == MACH_TYPE_SMARCFIMX6)
  3639 +#else
  3640 +# define machine_is_smarcfimx6() (0)
3628 3641 #endif
3629 3642  
3630 3643 #ifdef CONFIG_MACH_CC9P9360JS
board/embedian/smarcfimx6/Makefile
Diff comments   View file @ e29075c
  1 +#
  2 +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
  3 +#
  4 +# (C) Copyright 2011 Freescale Semiconductor, Inc.
  5 +#
  6 +# SPDX-License-Identifier: GPL-2.0+
  7 +#
  8 +
  9 +obj-y := smarcfimx6.o
  10 +
  11 +extra-$(CONFIG_USE_PLUGIN) := plugin.bin
  12 +$(obj)/plugin.bin: $(obj)/plugin.o
  13 + $(OBJCOPY) -O binary --gap-fill 0xff $< $@
board/embedian/smarcfimx6/README
Diff comments   View file @ e29075c
  1 +U-Boot for SMARC-FIMX6
  2 +--------------------
  3 +
  4 +This file contains information for the port of U-Boot to the Embedian SMARC-FiMX6.
  5 +
  6 +SMARC-FiMX6 is a computer on module that has six variants based on the following
  7 +SoCs and memory configurations: mx6 quad 2G, mx6 quad 1G, mx6 dual 2G, mx6 dual 1G, mx6 dual lite and mx6 solo.
  8 +
  9 +For more details about SMARC-FiMX6, please refer to:
  10 +http://www.embedian.com/
  11 +
  12 +Building U-boot for SMARC-FiMX6
  13 +-----------------------------
  14 +
  15 +To build U-Boot for the SMARC-FiMX6 Dual Lite version:
  16 +
  17 +$ make smarcfimx6_dl_1g_ser3_config
  18 +$ make
  19 +
  20 +To build U-Boot for the SMARC-FiMX6 Solo version:
  21 +
  22 +$ make smarcfimx6_solo_ser3_config
  23 +$ make
  24 +
  25 +To build U-Boot for the SMARC-FiMX6 Quad and Dual 1G memory version:
  26 +
  27 +$ make smarcfimx6_quad_1g_ser3_config
  28 +$ make
  29 +
  30 +To build U-Boot for the SMARC-FiMX6 Quad and Dual 2G memory version:
  31 +
  32 +$ make smarcfimx6_quad_2g_ser3_config
  33 +$ make
  34 +
  35 +Flashing U-boot into the SD card
  36 +--------------------------------
  37 +
  38 +- After the 'make' command completes, the generated 'u-boot.imx' binary must be
  39 +flashed into the SD card;
  40 +
  41 +$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=512 seek=2; sync
  42 +
  43 +(Note - the SD card node may vary, so adjust this as needed).
  44 +
  45 +- Insert the SD card into the slot located in the bottom of the board (same side
  46 +as the mx6 processor)
  47 +
  48 +- Connect the serial cable to the host PC
  49 +
  50 +- Power up the board and U-boot messages will appear in the serial console.
board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg
Diff comments   View file @ e29075c
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + * Jason Liu <r64343@freescale.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + *
  7 + * Refer docs/README.imxmage for more details about how-to configure
  8 + * and create imximage boot image
  9 + *
  10 + * The syntax is taken as close as possible with the kwbimage
  11 + */
  12 +
  13 +#define __ASSEMBLY__
  14 +#include <config.h>
  15 +
  16 +/* image version */
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of spi, sd, sata
  21 + * the board has no nand and eimnor
  22 + * spinor: flash_offset: 0x0400
  23 + * sata: flash_offset: 0x0400
  24 + * sd/mmc: flash_offset: 0x0400
  25 + */
  26 +
  27 +/* the same flash_offset as sd */
  28 +BOOT_FROM spi
  29 +
  30 +#ifdef CONFIG_USE_PLUGIN
  31 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  32 +PLUGIN board/embedian/smarcfimx6/plugin.bin 0x00907000
  33 +#else
  34 +
  35 +#ifdef CONFIG_SECURE_BOOT
  36 +CSF 0x2000
  37 +#endif
  38 +
  39 +/*
  40 + * Device Configuration Data (DCD)
  41 + *
  42 + * Each entry must have the format:
  43 + * Addr-type Address Value
  44 + *
  45 + * where:
  46 + * Addr-type register length (1,2 or 4 bytes)
  47 + * Address absolute address of the register
  48 + * value value to be stored in the register
  49 + */
  50 +/* Enable all clocks */
  51 +/*DATA 4 0x020c4068 0xffffffff
  52 +DATA 4 0x020c406c 0xffffffff
  53 +DATA 4 0x020c4070 0xffffffff
  54 +DATA 4 0x020c4074 0xffffffff
  55 +DATA 4 0x020c4078 0xffffffff
  56 +DATA 4 0x020c407c 0xffffffff
  57 +DATA 4 0x020c4080 0xffffffff
  58 +DATA 4 0x020c4084 0xffffffff*/
  59 +
  60 +/* IOMUX */
  61 +/* DDR IO TYPE */
  62 +DATA 4 0x020e0774 0x000C0000
  63 +DATA 4 0x020e0754 0x00000000
  64 +
  65 +/* CLOCK */
  66 +DATA 4 0x020e04ac 0x00000030
  67 +DATA 4 0x020e04b0 0x00000030
  68 +
  69 +/* ADDRESS */
  70 +DATA 4 0x020e0464 0x00000030
  71 +DATA 4 0x020e0490 0x00000030
  72 +DATA 4 0x020e074c 0x00000030
  73 +
  74 +/* CONTROL */
  75 +DATA 4 0x020e0494 0x00000030
  76 +DATA 4 0x020e04a0 0x00000000
  77 +DATA 4 0x020e04b4 0x00000030
  78 +DATA 4 0x020e04b8 0x00000030
  79 +DATA 4 0x020e076c 0x00000030
  80 +
  81 +/* DATA STROBE */
  82 +DATA 4 0x020e0750 0x00020000
  83 +DATA 4 0x020e04bc 0x00000030
  84 +DATA 4 0x020e04c0 0x00000030
  85 +DATA 4 0x020e04c4 0x00000030
  86 +DATA 4 0x020e04c8 0x00000030
  87 +DATA 4 0x020e04cc 0x00000030
  88 +DATA 4 0x020e04d0 0x00000030
  89 +DATA 4 0x020e04d4 0x00000030
  90 +DATA 4 0x020e04d8 0x00000030
  91 +
  92 +/* DATA */
  93 +DATA 4 0x020e0760 0x00020000
  94 +DATA 4 0x020e0764 0x00000030
  95 +DATA 4 0x020e0770 0x00000030
  96 +DATA 4 0x020e0778 0x00000030
  97 +DATA 4 0x020e077c 0x00000030
  98 +DATA 4 0x020e0780 0x00000030
  99 +DATA 4 0x020e0784 0x00000030
  100 +DATA 4 0x020e078c 0x00000030
  101 +DATA 4 0x020e0748 0x00000030
  102 +DATA 4 0x020e0470 0x00000030
  103 +DATA 4 0x020e0474 0x00000030
  104 +DATA 4 0x020e0478 0x00000030
  105 +DATA 4 0x020e047c 0x00000030
  106 +DATA 4 0x020e0480 0x00000030
  107 +DATA 4 0x020e0484 0x00000030
  108 +DATA 4 0x020e0488 0x00000030
  109 +DATA 4 0x020e048c 0x00000030
  110 +
  111 +/* Calibrations */
  112 +/* ZQ */
  113 +DATA 4 0x021b0800 0xa1390003
  114 +/* write leveling */
  115 +DATA 4 0x021b080c 0x001F001F
  116 +DATA 4 0x021b0810 0x001F001F
  117 +DATA 4 0x021b480c 0x001F001F
  118 +DATA 4 0x021b4810 0x001F001F
  119 +
  120 +/* DQS Read Gate */
  121 +DATA 4 0x021b083c 0x42540258
  122 +DATA 4 0x021b0840 0x023C023C
  123 +DATA 4 0x021b483c 0x42400244
  124 +DATA 4 0x021b4840 0x0230023C
  125 +
  126 +/* Read/Write Delay */
  127 +DATA 4 0x021b0848 0x4446484A
  128 +DATA 4 0x021b4848 0x4A4E5044
  129 +
  130 +DATA 4 0x021b0850 0x36322E34
  131 +DATA 4 0x021b4850 0x383A3830
  132 +
  133 +/* read data bit delay */
  134 +DATA 4 0x021b081c 0x33333333
  135 +DATA 4 0x021b0820 0x33333333
  136 +DATA 4 0x021b0824 0x33333333
  137 +DATA 4 0x021b0828 0x33333333
  138 +DATA 4 0x021b481c 0x33333333
  139 +DATA 4 0x021b4820 0x33333333
  140 +DATA 4 0x021b4824 0x33333333
  141 +DATA 4 0x021b4828 0x33333333
  142 +
  143 +/* Complete calibration by forced measurment */
  144 +DATA 4 0x021b08b8 0x00000800
  145 +DATA 4 0x021b48b8 0x00000800
  146 +
  147 +/* MMDC init */
  148 +DATA 4 0x021b0004 0x0002002D
  149 +DATA 4 0x021b0008 0x00335050
  150 +DATA 4 0x021b000c 0x3F435333
  151 +DATA 4 0x021b0010 0xB68E8B63
  152 +DATA 4 0x021b0014 0x01FF00DB
  153 +DATA 4 0x021b0018 0x00081740
  154 +DATA 4 0x021b001c 0x00008000
  155 +DATA 4 0x021b002c 0x000026d2
  156 +DATA 4 0x021b0030 0x00431023
  157 +DATA 4 0x021b0040 0x00000027
  158 +DATA 4 0x021b0000 0x831A0000
  159 +
  160 +/* Initialize CS0: K4B2G1646Q-BCK0 */
  161 +/* MR2 */
  162 +DATA 4 0x021b001c 0x04008032
  163 +/* MR3 */
  164 +DATA 4 0x021b001c 0x00008033
  165 +/* MR1 */
  166 +DATA 4 0x021b001c 0x00048031
  167 +/* MR0 */
  168 +DATA 4 0x021b001c 0x05208030
  169 +/* DDR device ZQ calibration */
  170 +DATA 4 0x021b001c 0x04008040
  171 +/*MDREF*/
  172 +DATA 4 0x021b0020 0x00005800
  173 +
  174 +/* final DDR setup, before operation start */
  175 +DATA 4 0x021b0818 0x00011117
  176 +/*DATA 4 0x021b4818 0x00011117*/
  177 +DATA 4 0x021b0004 0x0002556D
  178 +DATA 4 0x021b0404 0x00011006
  179 +DATA 4 0x021b001c 0x00000000
  180 +
  181 +/* set the default clock gate to save power */
  182 +DATA 4, 0x020c4068, 0x00C03F3F
  183 +DATA 4, 0x020c406c, 0x0030FC03
  184 +DATA 4, 0x020c4070, 0x0FFFC000
  185 +DATA 4, 0x020c4074, 0x3FF00000
  186 +DATA 4, 0x020c4078, 0x00FFF300
  187 +DATA 4, 0x020c407c, 0x0F0000C3
  188 +DATA 4, 0x020c4080, 0x000003FF
  189 +
  190 +/* enable AXI cache for VDOA/VPU/IPU */
  191 +DATA 4, 0x020e0010, 0xF00000CF
  192 +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  193 +DATA 4, 0x020e0018, 0x007F007F
  194 +DATA 4, 0x020e001c, 0x007F007F
  195 +#endif
board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg
Diff comments   View file @ e29075c
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + * Jason Liu <r64343@freescale.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + *
  7 + * Refer docs/README.imxmage for more details about how-to configure
  8 + * and create imximage boot image
  9 + *
  10 + * The syntax is taken as close as possible with the kwbimage
  11 + */
  12 +
  13 +#define __ASSEMBLY__
  14 +#include <config.h>
  15 +
  16 +/* image version */
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of spi, sd, sata
  21 + * the board has no nand and eimnor
  22 + * spinor: flash_offset: 0x0400
  23 + * sata: flash_offset: 0x0400
  24 + * sd/mmc: flash_offset: 0x0400
  25 + */
  26 +
  27 +/* the same flash_offset as sd */
  28 +BOOT_FROM spi
  29 +
  30 +#ifdef CONFIG_USE_PLUGIN
  31 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  32 +PLUGIN board/embedian/smarcfimx6/plugin.bin 0x00907000
  33 +#else
  34 +
  35 +#ifdef CONFIG_SECURE_BOOT
  36 +CSF 0x2000
  37 +#endif
  38 +
  39 +/*
  40 + * Device Configuration Data (DCD)
  41 + *
  42 + * Each entry must have the format:
  43 + * Addr-type Address Value
  44 + *
  45 + * where:
  46 + * Addr-type register length (1,2 or 4 bytes)
  47 + * Address absolute address of the register
  48 + * value value to be stored in the register
  49 + */
  50 +/* Enable all clocks */
  51 +/*DATA 4, 0x020c4068, 0xffffffff
  52 +DATA 4, 0x020c406c, 0xffffffff
  53 +DATA 4, 0x020c4070, 0xffffffff
  54 +DATA 4, 0x020c4074, 0xffffffff
  55 +DATA 4, 0x020c4078, 0xffffffff
  56 +DATA 4, 0x020c407c, 0xffffffff
  57 +DATA 4, 0x020c4080, 0xffffffff
  58 +DATA 4, 0x020c4084, 0xffffffff*/
  59 +
  60 +/* IOMUX */
  61 +/* DDR IO TYPE */
  62 +DATA 4, 0x020e0798, 0x000C0000
  63 +DATA 4, 0x020e0758, 0x00000000
  64 +
  65 +/* CLOCK */
  66 +DATA 4, 0x020e0588, 0x00000030
  67 +DATA 4, 0x020e0594, 0x00000030
  68 +
  69 +/* ADDRESS */
  70 +DATA 4, 0x020e056c, 0x00000030
  71 +DATA 4, 0x020e0578, 0x00000030
  72 +DATA 4, 0x020e074c, 0x00000030
  73 +/* CONTROL */
  74 +DATA 4, 0x020e057c, 0x00000030
  75 +DATA 4, 0x020e058c, 0x00000000
  76 +DATA 4, 0x020e059c, 0x00000030
  77 +DATA 4, 0x020e05a0, 0x00000030
  78 +DATA 4, 0x020e078c, 0x00000030
  79 +
  80 +/* DATA STROBE */
  81 +DATA 4, 0x020e0750, 0x00020000
  82 +DATA 4, 0x020e05a8, 0x00000030
  83 +DATA 4, 0x020e05b0, 0x00000030
  84 +DATA 4, 0x020e0524, 0x00000030
  85 +DATA 4, 0x020e051c, 0x00000030
  86 +DATA 4, 0x020e0518, 0x00000030
  87 +DATA 4, 0x020e050c, 0x00000030
  88 +DATA 4, 0x020e05b8, 0x00000030
  89 +DATA 4, 0x020e05c0, 0x00000030
  90 +/* DATA */
  91 +DATA 4, 0x020e0774, 0x00020000
  92 +DATA 4, 0x020e0784, 0x00000030
  93 +DATA 4, 0x020e0788, 0x00000030
  94 +DATA 4, 0x020e0794, 0x00000030
  95 +DATA 4, 0x020e079c, 0x00000030
  96 +DATA 4, 0x020e07a0, 0x00000030
  97 +DATA 4, 0x020e07a4, 0x00000030
  98 +DATA 4, 0x020e07a8, 0x00000030
  99 +DATA 4, 0x020e0748, 0x00000030
  100 +DATA 4, 0x020e05ac, 0x00000030
  101 +DATA 4, 0x020e05b4, 0x00000030
  102 +DATA 4, 0x020e0528, 0x00000030
  103 +DATA 4, 0x020e0520, 0x00000030
  104 +DATA 4, 0x020e0514, 0x00000030
  105 +DATA 4, 0x020e0510, 0x00000030
  106 +DATA 4, 0x020e05bc, 0x00000030
  107 +DATA 4, 0x020e05c4, 0x00000030
  108 +
  109 +/* Calibrations */
  110 +/* ZQ */
  111 +DATA 4, 0x021b0800, 0xa1390003
  112 +/* write leveling */
  113 +DATA 4, 0x021b080c, 0x001F001F
  114 +DATA 4, 0x021b0810, 0x001F001F
  115 +DATA 4, 0x021b480c, 0x001F001F
  116 +DATA 4, 0x021b4810, 0x001F001F
  117 +
  118 +/* DQS Read Gate */
  119 +DATA 4, 0x021b083c, 0x4544055C
  120 +DATA 4, 0x021b0840, 0x05400540
  121 +DATA 4, 0x021b483c, 0x4544054C
  122 +DATA 4, 0x021b4840, 0x05440510
  123 +
  124 +/* Read/Write Delay */
  125 +DATA 4, 0x021b0848, 0x463C3E42
  126 +DATA 4, 0x021b4848, 0x3E3A3844
  127 +
  128 +DATA 4, 0x021b0850, 0x38383E38
  129 +DATA 4, 0x021b4850, 0x42344838
  130 +
  131 +/* read data bit delay */
  132 +DATA 4, 0x021b081c, 0x33333333
  133 +DATA 4, 0x021b0820, 0x33333333
  134 +DATA 4, 0x021b0824, 0x33333333
  135 +DATA 4, 0x021b0828, 0x33333333
  136 +DATA 4, 0x021b481c, 0x33333333
  137 +DATA 4, 0x021b4820, 0x33333333
  138 +DATA 4, 0x021b4824, 0x33333333
  139 +DATA 4, 0x021b4828, 0x33333333
  140 +
  141 +/* Complete calibration by forced measurment */
  142 +DATA 4, 0x021b08b8, 0x00000800
  143 +DATA 4, 0x021b48b8, 0x00000800
  144 +
  145 +/* MMDC init */
  146 +DATA 4, 0x021b0004, 0x00020036
  147 +DATA 4, 0x021b0008, 0x09446060
  148 +DATA 4, 0x021b000c, 0x555B79A4
  149 +DATA 4, 0x021b0010, 0xDB538F64
  150 +DATA 4, 0x021b0014, 0x01FF00DD
  151 +DATA 4, 0x021b0018, 0x00081740
  152 +DATA 4, 0x021b001c, 0x00008000
  153 +DATA 4, 0x021b002c, 0x000026d2
  154 +DATA 4, 0x021b0030, 0x005B1023
  155 +DATA 4, 0x021b0040, 0x00000027
  156 +DATA 4, 0x021b0400, 0x11420000
  157 +DATA 4, 0x021b4400, 0x11420000
  158 +DATA 4, 0x021b0000, 0x831A0000
  159 +
  160 +/* Initialize CS0: K4B2G1646Q-BCK0 */
  161 +/* MR2 */
  162 +DATA 4, 0x021b001c, 0x04088032
  163 +/* MR3 */
  164 +DATA 4, 0x021b001c, 0x00008033
  165 +/* MR1 */
  166 +DATA 4, 0x021b001c, 0x00048031
  167 +/* MR0 */
  168 +DATA 4, 0x021b001c, 0x09408030
  169 +/* DDR device ZQ calibration */
  170 +DATA 4, 0x021b001c, 0x04008040
  171 +/*MDREF*/
  172 +DATA 4, 0x021b0020, 0x00005800
  173 +
  174 +/* final DDR setup, before operation start */
  175 +DATA 4, 0x021b0818, 0x00011117
  176 +/*DATA 4, 0x021b4818, 0x00011117*/
  177 +DATA 4, 0x021b0004, 0x00025576
  178 +DATA 4, 0x021b0404, 0x00011006
  179 +DATA 4, 0x021b001c, 0x00000000
  180 +
  181 +/* set the default clock gate to save power */
  182 +DATA 4, 0x020c4068, 0x00C03F3F
  183 +DATA 4, 0x020c406c, 0x0030FC03
  184 +DATA 4, 0x020c4070, 0x0FFFC000
  185 +DATA 4, 0x020c4074, 0x3FF00000
  186 +DATA 4, 0x020c4078, 0x00FFF300
  187 +DATA 4, 0x020c407c, 0x0F0000C3
  188 +DATA 4, 0x020c4080, 0x000003FF
  189 +
  190 +/* enable AXI cache for VDOA/VPU/IPU */
  191 +DATA 4, 0x020e0010, 0xF00000CF
  192 +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  193 +DATA 4, 0x020e0018, 0x007F007F
  194 +DATA 4, 0x020e001c, 0x007F007F
  195 +
  196 +/*
  197 + * Setup CCM_CCOSR register as follows:
  198 + *
  199 + * cko1_en = 1 --> CKO1 enabled
  200 + * cko1_div = 111 --> divide by 8
  201 + * cko1_sel = 1011 --> ahb_clk_root
  202 + *
  203 + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
  204 + */
  205 +DATA 4, 0x020c4060, 0x000000fb
  206 +#endif
board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg
Diff comments   View file @ e29075c
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + * Jason Liu <r64343@freescale.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + *
  7 + * Refer docs/README.imxmage for more details about how-to configure
  8 + * and create imximage boot image
  9 + *
  10 + * The syntax is taken as close as possible with the kwbimage
  11 + */
  12 +
  13 +#define __ASSEMBLY__
  14 +#include <config.h>
  15 +
  16 +/* image version */
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of spi, sd, sata
  21 + * the board has no nand and eimnor
  22 + * spinor: flash_offset: 0x0400
  23 + * sata: flash_offset: 0x0400
  24 + * sd/mmc: flash_offset: 0x0400
  25 + */
  26 +
  27 +/* the same flash_offset as sd */
  28 +BOOT_FROM spi
  29 +
  30 +#ifdef CONFIG_USE_PLUGIN
  31 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  32 +PLUGIN board/embedian/smarcfimx6/plugin.bin 0x00907000
  33 +#else
  34 +
  35 +#ifdef CONFIG_SECURE_BOOT
  36 +CSF 0x2000
  37 +#endif
  38 +
  39 +/*
  40 + * Device Configuration Data (DCD)
  41 + *
  42 + * Each entry must have the format:
  43 + * Addr-type Address Value
  44 + *
  45 + * where:
  46 + * Addr-type register length (1,2 or 4 bytes)
  47 + * Address absolute address of the register
  48 + * value value to be stored in the register
  49 + */
  50 +/* Enable all clocks */
  51 +/*DATA 4, 0x020c4068, 0xffffffff
  52 +DATA 4, 0x020c406c, 0xffffffff
  53 +DATA 4, 0x020c4070, 0xffffffff
  54 +DATA 4, 0x020c4074, 0xffffffff
  55 +DATA 4, 0x020c4078, 0xffffffff
  56 +DATA 4, 0x020c407c, 0xffffffff
  57 +DATA 4, 0x020c4080, 0xffffffff
  58 +DATA 4, 0x020c4084, 0xffffffff*/
  59 +
  60 +/* IOMUX */
  61 +/* DDR IO TYPE */
  62 +DATA 4, 0x020e0798, 0x000C0000
  63 +DATA 4, 0x020e0758, 0x00000000
  64 +
  65 +/* CLOCK */
  66 +DATA 4, 0x020e0588, 0x00000030
  67 +DATA 4, 0x020e0594, 0x00000030
  68 +
  69 +/* ADDRESS */
  70 +DATA 4, 0x020e056c, 0x00000030
  71 +DATA 4, 0x020e0578, 0x00000030
  72 +DATA 4, 0x020e074c, 0x00000030
  73 +/* CONTROL */
  74 +DATA 4, 0x020e057c, 0x00000030
  75 +DATA 4, 0x020e058c, 0x00000000
  76 +DATA 4, 0x020e059c, 0x00000030
  77 +DATA 4, 0x020e05a0, 0x00000030
  78 +DATA 4, 0x020e078c, 0x00000030
  79 +
  80 +/* DATA STROBE */
  81 +DATA 4, 0x020e0750, 0x00020000
  82 +DATA 4, 0x020e05a8, 0x00000030
  83 +DATA 4, 0x020e05b0, 0x00000030
  84 +DATA 4, 0x020e0524, 0x00000030
  85 +DATA 4, 0x020e051c, 0x00000030
  86 +DATA 4, 0x020e0518, 0x00000030
  87 +DATA 4, 0x020e050c, 0x00000030
  88 +DATA 4, 0x020e05b8, 0x00000030
  89 +DATA 4, 0x020e05c0, 0x00000030
  90 +/* DATA */
  91 +DATA 4, 0x020e0774, 0x00020000
  92 +DATA 4, 0x020e0784, 0x00000030
  93 +DATA 4, 0x020e0788, 0x00000030
  94 +DATA 4, 0x020e0794, 0x00000030
  95 +DATA 4, 0x020e079c, 0x00000030
  96 +DATA 4, 0x020e07a0, 0x00000030
  97 +DATA 4, 0x020e07a4, 0x00000030
  98 +DATA 4, 0x020e07a8, 0x00000030
  99 +DATA 4, 0x020e0748, 0x00000030
  100 +DATA 4, 0x020e05ac, 0x00000030
  101 +DATA 4, 0x020e05b4, 0x00000030
  102 +DATA 4, 0x020e0528, 0x00000030
  103 +DATA 4, 0x020e0520, 0x00000030
  104 +DATA 4, 0x020e0514, 0x00000030
  105 +DATA 4, 0x020e0510, 0x00000030
  106 +DATA 4, 0x020e05bc, 0x00000030
  107 +DATA 4, 0x020e05c4, 0x00000030
  108 +
  109 +/* Calibrations */
  110 +/* ZQ */
  111 +DATA 4, 0x021b0800, 0xa1390003
  112 +/* write leveling */
  113 +DATA 4, 0x021b080c, 0x001F001F
  114 +DATA 4, 0x021b0810, 0x001F001F
  115 +DATA 4, 0x021b480c, 0x001F001F
  116 +DATA 4, 0x021b4810, 0x001F001F
  117 +
  118 +/* DQS Read Gate */
  119 +DATA 4, 0x021b083c, 0x45400554
  120 +DATA 4, 0x021b0840, 0x0534052C
  121 +DATA 4, 0x021b483c, 0x453C0548
  122 +DATA 4, 0x021b4840, 0x053C050C
  123 +
  124 +/* Read/Write Delay */
  125 +DATA 4, 0x021b0848, 0x463E3E40
  126 +DATA 4, 0x021b4848, 0x3E3C3846
  127 +
  128 +DATA 4, 0x021b0850, 0x36383C36
  129 +DATA 4, 0x021b4850, 0x4234443C
  130 +
  131 +/* read data bit delay */
  132 +DATA 4, 0x021b081c, 0x33333333
  133 +DATA 4, 0x021b0820, 0x33333333
  134 +DATA 4, 0x021b0824, 0x33333333
  135 +DATA 4, 0x021b0828, 0x33333333
  136 +DATA 4, 0x021b481c, 0x33333333
  137 +DATA 4, 0x021b4820, 0x33333333
  138 +DATA 4, 0x021b4824, 0x33333333
  139 +DATA 4, 0x021b4828, 0x33333333
  140 +
  141 +/* Complete calibration by forced measurment */
  142 +DATA 4, 0x021b08b8, 0x00000800
  143 +DATA 4, 0x021b48b8, 0x00000800
  144 +
  145 +/* MMDC init */
  146 +DATA 4, 0x021b0004, 0x00020036
  147 +DATA 4, 0x021b0008, 0x09446060
  148 +DATA 4, 0x021b000c, 0x8A907BA4
  149 +DATA 4, 0x021b0010, 0xDB538F64
  150 +DATA 4, 0x021b0014, 0x01FF00DD
  151 +DATA 4, 0x021b0018, 0x00081740
  152 +DATA 4, 0x021b001c, 0x00008000
  153 +DATA 4, 0x021b002c, 0x000026d2
  154 +DATA 4, 0x021b0030, 0x00901023
  155 +DATA 4, 0x021b0040, 0x00000047
  156 +DATA 4, 0x021b0000, 0x841A0000
  157 +
  158 +/* Initialize CS0: K4B2G1646Q-BCK0 */
  159 +/* MR2 */
  160 +DATA 4, 0x021b001c, 0x04088032
  161 +/* MR3 */
  162 +DATA 4, 0x021b001c, 0x00008033
  163 +/* MR1 */
  164 +DATA 4, 0x021b001c, 0x00048031
  165 +/* MR0 */
  166 +DATA 4, 0x021b001c, 0x09408030
  167 +/* DDR device ZQ calibration */
  168 +DATA 4, 0x021b001c, 0x04008040
  169 +/*MDREF*/
  170 +DATA 4, 0x021b0020, 0x00005800
  171 +
  172 +/* final DDR setup, before operation start */
  173 +DATA 4, 0x021b0818, 0x00011117
  174 +/*DATA 4, 0x021b4818, 0x00011117*/
  175 +DATA 4, 0x021b0004, 0x00025576
  176 +DATA 4, 0x021b0404, 0x00011006
  177 +DATA 4, 0x021b001c, 0x00000000
  178 +
  179 +/* set the default clock gate to save power */
  180 +DATA 4, 0x020c4068, 0x00C03F3F
  181 +DATA 4, 0x020c406c, 0x0030FC03
  182 +DATA 4, 0x020c4070, 0x0FFFC000
  183 +DATA 4, 0x020c4074, 0x3FF00000
  184 +DATA 4, 0x020c4078, 0x00FFF300
  185 +DATA 4, 0x020c407c, 0x0F0000C3
  186 +DATA 4, 0x020c4080, 0x000003FF
  187 +
  188 +/* enable AXI cache for VDOA/VPU/IPU */
  189 +DATA 4, 0x020e0010, 0xF00000CF
  190 +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  191 +DATA 4, 0x020e0018, 0x007F007F
  192 +DATA 4, 0x020e001c, 0x007F007F
  193 +
  194 +/*
  195 + * Setup CCM_CCOSR register as follows:
  196 + *
  197 + * cko1_en = 1 --> CKO1 enabled
  198 + * cko1_div = 111 --> divide by 8
  199 + * cko1_sel = 1011 --> ahb_clk_root
  200 + *
  201 + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
  202 + */
  203 +DATA 4, 0x020c4060, 0x000000fb
  204 +#endif
board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg
Diff comments   View file @ e29075c
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + * Jason Liu <r64343@freescale.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + *
  7 + * Refer docs/README.imxmage for more details about how-to configure
  8 + * and create imximage boot image
  9 + *
  10 + * The syntax is taken as close as possible with the kwbimage
  11 + */
  12 +
  13 +#define __ASSEMBLY__
  14 +#include <config.h>
  15 +
  16 +/* image version */
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of spi, sd, sata
  21 + * the board has no nand and eimnor
  22 + * spinor: flash_offset: 0x0400
  23 + * sata: flash_offset: 0x0400
  24 + * sd/mmc: flash_offset: 0x0400
  25 + */
  26 +
  27 +/* the same flash_offset as sd */
  28 +BOOT_FROM spi
  29 +
  30 +#ifdef CONFIG_USE_PLUGIN
  31 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  32 +PLUGIN board/embedian/smarcfimx6/plugin.bin 0x00907000
  33 +#else
  34 +
  35 +#ifdef CONFIG_SECURE_BOOT
  36 +CSF 0x2000
  37 +#endif
  38 +
  39 +/*
  40 + * Device Configuration Data (DCD)
  41 + *
  42 + * Each entry must have the format:
  43 + * Addr-type Address Value
  44 + *
  45 + * where:
  46 + * Addr-type register length (1,2 or 4 bytes)
  47 + * Address absolute address of the register
  48 + * value value to be stored in the register
  49 + */
  50 +/* Enable all clocks */
  51 +/*DATA 4 0x020c4068 0xffffffff
  52 +DATA 4 0x020c406c 0xffffffff
  53 +DATA 4 0x020c4070 0xffffffff
  54 +DATA 4 0x020c4074 0xffffffff
  55 +DATA 4 0x020c4078 0xffffffff
  56 +DATA 4 0x020c407c 0xffffffff
  57 +DATA 4 0x020c4080 0xffffffff
  58 +DATA 4 0x020c4084 0xffffffff*/
  59 +
  60 +/* IOMUX */
  61 +/* DDR IO TYPE */
  62 +DATA 4 0x020e0774 0x000C0000
  63 +DATA 4 0x020e0754 0x00000000
  64 +
  65 +/* CLOCK */
  66 +DATA 4 0x020e04ac 0x00000030
  67 +DATA 4 0x020e04b0 0x00000030
  68 +
  69 +/* ADDRESS */
  70 +DATA 4 0x020e0464 0x00000030
  71 +DATA 4 0x020e0490 0x00000030
  72 +DATA 4 0x020e074c 0x00000030
  73 +
  74 +/* CONTROL */
  75 +DATA 4 0x020e0494 0x00000030
  76 +DATA 4 0x020e04a0 0x00000000
  77 +DATA 4 0x020e04b4 0x00000030
  78 +DATA 4 0x020e04b8 0x00000030
  79 +DATA 4 0x020e076c 0x00000030
  80 +
  81 +/* DATA STROBE */
  82 +DATA 4 0x020e0750 0x00020000
  83 +DATA 4 0x020e04bc 0x00000030
  84 +DATA 4 0x020e04c0 0x00000030
  85 +DATA 4 0x020e04c4 0x00000030
  86 +DATA 4 0x020e04c8 0x00000030
  87 +DATA 4 0x020e04cc 0x00000030
  88 +DATA 4 0x020e04d0 0x00000030
  89 +DATA 4 0x020e04d4 0x00000030
  90 +DATA 4 0x020e04d8 0x00000030
  91 +
  92 +/* DATA */
  93 +DATA 4 0x020e0760 0x00020000
  94 +DATA 4 0x020e0764 0x00000030
  95 +DATA 4 0x020e0770 0x00000030
  96 +DATA 4 0x020e0778 0x00000030
  97 +DATA 4 0x020e077c 0x00000030
  98 +DATA 4 0x020e0780 0x00000030
  99 +DATA 4 0x020e0784 0x00000030
  100 +DATA 4 0x020e078c 0x00000030
  101 +DATA 4 0x020e0748 0x00000030
  102 +DATA 4 0x020e0470 0x00000030
  103 +DATA 4 0x020e0474 0x00000030
  104 +DATA 4 0x020e0478 0x00000030
  105 +DATA 4 0x020e047c 0x00000030
  106 +DATA 4 0x020e0480 0x00000030
  107 +DATA 4 0x020e0484 0x00000030
  108 +DATA 4 0x020e0488 0x00000030
  109 +DATA 4 0x020e048c 0x00000030
  110 +
  111 +/* Calibrations */
  112 +/* ZQ */
  113 +DATA 4 0x021b0800 0xa1390003
  114 +/* write leveling */
  115 +DATA 4 0x021b080c 0x001F001F
  116 +DATA 4 0x021b0810 0x001F001F
  117 +DATA 4 0x021b480c 0x001F001F
  118 +DATA 4 0x021b4810 0x001F001F
  119 +
  120 +/* DQS Read Gate */
  121 +DATA 4 0x021b083c 0x42640264
  122 +DATA 4 0x021b0840 0x02400250
  123 +DATA 4 0x021b483c 0x42640264
  124 +DATA 4 0x021b4840 0x02400250
  125 +
  126 +/* Read/Write Delay */
  127 +DATA 4 0x021b0848 0x44484A4C
  128 +DATA 4 0x021b4848 0x44484A4C
  129 +
  130 +DATA 4 0x021b0850 0x3C383434
  131 +DATA 4 0x021b4850 0x3C383434
  132 +
  133 +/* read data bit delay */
  134 +DATA 4 0x021b081c 0x33333333
  135 +DATA 4 0x021b0820 0x33333333
  136 +DATA 4 0x021b0824 0x33333333
  137 +DATA 4 0x021b0828 0x33333333
  138 +DATA 4 0x021b481c 0x33333333
  139 +DATA 4 0x021b4820 0x33333333
  140 +DATA 4 0x021b4824 0x33333333
  141 +DATA 4 0x021b4828 0x33333333
  142 +
  143 +/* Complete calibration by forced measurment */
  144 +DATA 4 0x021b08b8 0x00000800
  145 +DATA 4 0x021b48b8 0x00000800
  146 +
  147 +/* MMDC init */
  148 +DATA 4 0x021b0004 0x0002002D
  149 +DATA 4 0x021b0008 0x00335050
  150 +DATA 4 0x021b000c 0x3F435333
  151 +DATA 4 0x021b0010 0xB68E8B63
  152 +DATA 4 0x021b0014 0x01FF00DB
  153 +DATA 4 0x021b0018 0x00081740
  154 +DATA 4 0x021b001c 0x00008000
  155 +DATA 4 0x021b002c 0x000026d2
  156 +DATA 4 0x021b0030 0x00431023
  157 +DATA 4 0x021b0040 0x00000017
  158 +DATA 4 0x021b0000 0x83190000
  159 +
  160 +/* Initialize CS0: K4B2G1646Q-BCK0 */
  161 +/* MR2 */
  162 +DATA 4 0x021b001c 0x04008032
  163 +/* MR3 */
  164 +DATA 4 0x021b001c 0x00008033
  165 +/* MR1 */
  166 +DATA 4 0x021b001c 0x00048031
  167 +/* MR0 */
  168 +DATA 4 0x021b001c 0x05208030
  169 +/* DDR device ZQ calibration */
  170 +DATA 4 0x021b001c 0x04008040
  171 +/*MDREF*/
  172 +DATA 4 0x021b0020 0x00005800
  173 +
  174 +/* final DDR setup, before operation start */
  175 +DATA 4 0x021b0818 0x00011117
  176 +/*DATA 4 0x021b4818 0x00011117*/
  177 +DATA 4 0x021b0004 0x0002556D
  178 +DATA 4 0x021b0404 0x00011006
  179 +DATA 4 0x021b001c 0x00000000
  180 +
  181 +/* set the default clock gate to save power */
  182 +DATA 4 0x020c4068 0x00C03F3F
  183 +DATA 4 0x020c406c 0x0030FC03
  184 +DATA 4 0x020c4070 0x0FFFC000
  185 +DATA 4 0x020c4074 0x3FF00000
  186 +DATA 4 0x020c4078 0x00FFF300
  187 +DATA 4 0x020c407c 0x0F0000C3
  188 +DATA 4 0x020c4080 0x000003FF
  189 +
  190 +/* enable AXI cache for VDOA/VPU/IPU */
  191 +DATA 4 0x020e0010 0xF00000CF
  192 +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  193 +DATA 4 0x020e0018 0x007F007F
  194 +DATA 4 0x020e001c 0x007F007F
  195 +#endif
board/embedian/smarcfimx6/plugin.S
Diff comments   View file @ e29075c
  1 +/*
  2 + * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <config.h>
  8 +
  9 +/* DDR script */
  10 +.macro smarcfimx6_quad_ddr_setting
  11 + ldr r0, =IOMUXC_BASE_ADDR
  12 + ldr r1, =0x000c0000
  13 + str r1, [r0, #0x798]
  14 + ldr r1, =0x00000000
  15 + str r1, [r0, #0x758]
  16 +
  17 + ldr r1, =0x00000030
  18 + str r1, [r0, #0x588]
  19 + str r1, [r0, #0x594]
  20 + str r1, [r0, #0x56c]
  21 + str r1, [r0, #0x578]
  22 + str r1, [r0, #0x74c]
  23 + str r1, [r0, #0x57c]
  24 +
  25 + ldr r1, =0x00000000
  26 + str r1, [r0, #0x58c]
  27 +
  28 + ldr r1, =0x00000030
  29 + str r1, [r0, #0x59c]
  30 + str r1, [r0, #0x5a0]
  31 + str r1, [r0, #0x78c]
  32 +
  33 + ldr r1, =0x00020000
  34 + str r1, [r0, #0x750]
  35 +
  36 + ldr r1, =0x00000030
  37 + str r1, [r0, #0x5a8]
  38 + str r1, [r0, #0x5b0]
  39 + str r1, [r0, #0x524]
  40 + str r1, [r0, #0x51c]
  41 + str r1, [r0, #0x518]
  42 + str r1, [r0, #0x50c]
  43 + str r1, [r0, #0x5b8]
  44 + str r1, [r0, #0x5c0]
  45 +
  46 + ldr r1, =0x00020000
  47 + str r1, [r0, #0x774]
  48 +
  49 + ldr r1, =0x00000030
  50 + str r1, [r0, #0x784]
  51 + str r1, [r0, #0x788]
  52 + str r1, [r0, #0x794]
  53 + str r1, [r0, #0x79c]
  54 + str r1, [r0, #0x7a0]
  55 + str r1, [r0, #0x7a4]
  56 + str r1, [r0, #0x7a8]
  57 + str r1, [r0, #0x748]
  58 + str r1, [r0, #0x5ac]
  59 + str r1, [r0, #0x5b4]
  60 + str r1, [r0, #0x528]
  61 + str r1, [r0, #0x520]
  62 + str r1, [r0, #0x514]
  63 + str r1, [r0, #0x510]
  64 + str r1, [r0, #0x5bc]
  65 + str r1, [r0, #0x5c4]
  66 +
  67 + ldr r0, =MMDC_P0_BASE_ADDR
  68 + ldr r2, =0xa1390003
  69 + str r2, [r0, #0x800]
  70 +
  71 + ldr r2, =0x001F001F
  72 + str r2, [r0, #0x80c]
  73 + str r2, [r0, #0x810]
  74 + ldr r1, =MMDC_P1_BASE_ADDR
  75 + str r2, [r1, #0x80c]
  76 + str r2, [r1, #0x810]
  77 +
  78 + ldr r2, =0x43270338
  79 + str r2, [r0, #0x83c]
  80 + ldr r2, =0x03200314
  81 + str r2, [r0, #0x840]
  82 +
  83 + ldr r2, =0x431A032F
  84 + str r2, [r1, #0x83c]
  85 + ldr r2, =0x03200263
  86 + str r2, [r1, #0x840]
  87 +
  88 + ldr r2, =0x4B434748
  89 + str r2, [r0, #0x848]
  90 + ldr r2, =0x4445404C
  91 + str r2, [r1, #0x848]
  92 +
  93 + ldr r2, =0x38444542
  94 + str r2, [r0, #0x850]
  95 + ldr r2, =0x4935493A
  96 + str r2, [r1, #0x850]
  97 +
  98 + ldr r2, =0x33333333
  99 + str r2, [r0, #0x81c]
  100 + str r2, [r0, #0x820]
  101 + str r2, [r0, #0x824]
  102 + str r2, [r0, #0x828]
  103 + str r2, [r1, #0x81c]
  104 + str r2, [r1, #0x820]
  105 + str r2, [r1, #0x824]
  106 + str r2, [r1, #0x828]
  107 +
  108 + ldr r2, =0x00000800
  109 + str r2, [r0, #0x8b8]
  110 + str r2, [r1, #0x8b8]
  111 +
  112 + ldr r2, =0x00020036
  113 + str r2, [r0, #0x004]
  114 + ldr r2, =0x09444040
  115 + str r2, [r0, #0x008]
  116 +
  117 + ldr r2, =0x555A7975
  118 + str r2, [r0, #0x00c]
  119 + ldr r2, =0xFF538F64
  120 + str r2, [r0, #0x010]
  121 +
  122 + ldr r2, =0x01FF00DB
  123 + str r2, [r0, #0x014]
  124 + ldr r2, =0x00001740
  125 + str r2, [r0, #0x018]
  126 +
  127 + ldr r2, =0x00008000
  128 + str r2, [r0, #0x01c]
  129 + ldr r2, =0x000026d2
  130 + str r2, [r0, #0x02c]
  131 + ldr r2, =0x005A1023
  132 + str r2, [r0, #0x030]
  133 + ldr r2, =0x00000027
  134 + str r2, [r0, #0x040]
  135 +
  136 + ldr r2, =0x831A0000
  137 + str r2, [r0, #0x000]
  138 +
  139 + ldr r2, =0x04088032
  140 + str r2, [r0, #0x01c]
  141 + ldr r2, =0x00008033
  142 + str r2, [r0, #0x01c]
  143 + ldr r2, =0x00048031
  144 + str r2, [r0, #0x01c]
  145 + ldr r2, =0x09408030
  146 + str r2, [r0, #0x01c]
  147 + ldr r2, =0x04008040
  148 + str r2, [r0, #0x01c]
  149 +
  150 + ldr r2, =0x00005800
  151 + str r2, [r0, #0x020]
  152 + ldr r2, =0x00011117
  153 + str r2, [r0, #0x818]
  154 + str r2, [r1, #0x818]
  155 + ldr r2, =0x00025576
  156 + str r2, [r0, #0x004]
  157 + ldr r2, =0x00011006
  158 + str r2, [r0, #0x404]
  159 + ldr r2, =0x00000000
  160 + str r2, [r0, #0x01c]
  161 +.endm
  162 +
  163 +.macro smarcfimx6_dl__ddr_setting
  164 + ldr r0, =IOMUXC_BASE_ADDR
  165 + ldr r1, =0x000c0000
  166 + str r1, [r0, #0x774]
  167 + ldr r1, =0x00000000
  168 + str r1, [r0, #0x754]
  169 +
  170 + ldr r1, =0x00000030
  171 + str r1, [r0, #0x4ac]
  172 + str r1, [r0, #0x4b0]
  173 + str r1, [r0, #0x464]
  174 + str r1, [r0, #0x490]
  175 + str r1, [r0, #0x74c]
  176 + str r1, [r0, #0x494]
  177 +
  178 + ldr r1, =0x00000000
  179 + str r1, [r0, #0x4a0]
  180 +
  181 + ldr r1, =0x00000030
  182 + str r1, [r0, #0x4b4]
  183 + str r1, [r0, #0x4b8]
  184 + str r1, [r0, #0x76c]
  185 +
  186 + ldr r1, =0x00020000
  187 + str r1, [r0, #0x750]
  188 +
  189 + ldr r1, =0x00000030
  190 + str r1, [r0, #0x4bc]
  191 + str r1, [r0, #0x4c0]
  192 + str r1, [r0, #0x4c4]
  193 + str r1, [r0, #0x4c8]
  194 + str r1, [r0, #0x4cc]
  195 + str r1, [r0, #0x4d0]
  196 + str r1, [r0, #0x4d4]
  197 + str r1, [r0, #0x4d8]
  198 +
  199 + ldr r1, =0x00020000
  200 + str r1, [r0, #0x760]
  201 +
  202 + ldr r1, =0x00000030
  203 + str r1, [r0, #0x764]
  204 + str r1, [r0, #0x770]
  205 + str r1, [r0, #0x778]
  206 + str r1, [r0, #0x77c]
  207 + str r1, [r0, #0x780]
  208 + str r1, [r0, #0x784]
  209 + str r1, [r0, #0x78c]
  210 + str r1, [r0, #0x748]
  211 + str r1, [r0, #0x470]
  212 + str r1, [r0, #0x474]
  213 + str r1, [r0, #0x478]
  214 + str r1, [r0, #0x47c]
  215 + str r1, [r0, #0x480]
  216 + str r1, [r0, #0x484]
  217 + str r1, [r0, #0x488]
  218 + str r1, [r0, #0x48c]
  219 +
  220 + ldr r0, =MMDC_P0_BASE_ADDR
  221 + ldr r2, =0xa1390003
  222 + str r2, [r0, #0x800]
  223 +
  224 + ldr r2, =0x001f001f
  225 + str r2, [r0, #0x80c]
  226 + str r2, [r0, #0x810]
  227 + ldr r1, =MMDC_P1_BASE_ADDR
  228 + str r2, [r1, #0x80c]
  229 + str r2, [r1, #0x810]
  230 +
  231 + ldr r2, =0x4220021F
  232 + str r2, [r0, #0x83c]
  233 + ldr r2, =0x0207017E
  234 + str r2, [r0, #0x840]
  235 +
  236 + ldr r2, =0x4201020C
  237 + str r2, [r1, #0x83c]
  238 + ldr r2, =0x01660172
  239 + str r2, [r1, #0x840]
  240 +
  241 + ldr r2, =0x4A4D4E4D
  242 + str r2, [r0, #0x848]
  243 + ldr r2, =0x4A4F5049
  244 + str r2, [r1, #0x848]
  245 +
  246 + ldr r2, =0x3F3C3D31
  247 + str r2, [r0, #0x850]
  248 + ldr r2, =0x3238372B
  249 + str r2, [r1, #0x850]
  250 +
  251 + ldr r2, =0x33333333
  252 + str r2, [r0, #0x81c]
  253 + str r2, [r0, #0x820]
  254 + str r2, [r0, #0x824]
  255 + str r2, [r0, #0x828]
  256 + str r2, [r1, #0x81c]
  257 + str r2, [r1, #0x820]
  258 + str r2, [r1, #0x824]
  259 + str r2, [r1, #0x828]
  260 +
  261 + ldr r2, =0x00000800
  262 + str r2, [r0, #0x8b8]
  263 + str r2, [r1, #0x8b8]
  264 +
  265 + ldr r2, =0x0002002D
  266 + str r2, [r0, #0x004]
  267 + ldr r2, =0x00333030
  268 + str r2, [r0, #0x008]
  269 +
  270 + ldr r2, =0x3F435313
  271 + str r2, [r0, #0x00c]
  272 + ldr r2, =0xB66E8B63
  273 + str r2, [r0, #0x010]
  274 +
  275 + ldr r2, =0x01FF00DB
  276 + str r2, [r0, #0x014]
  277 + ldr r2, =0x00001740
  278 + str r2, [r0, #0x018]
  279 +
  280 + ldr r2, =0x00008000
  281 + str r2, [r0, #0x01c]
  282 + ldr r2, =0x000026d2
  283 + str r2, [r0, #0x02c]
  284 + ldr r2, =0x00431023
  285 + str r2, [r0, #0x030]
  286 + ldr r2, =0x00000027
  287 + str r2, [r0, #0x040]
  288 +
  289 + ldr r2, =0x831A0000
  290 + str r2, [r0, #0x000]
  291 +
  292 + ldr r2, =0x04008032
  293 + str r2, [r0, #0x01c]
  294 + ldr r2, =0x00008033
  295 + str r2, [r0, #0x01c]
  296 + ldr r2, =0x00048031
  297 + str r2, [r0, #0x01c]
  298 + ldr r2, =0x05208030
  299 + str r2, [r0, #0x01c]
  300 + ldr r2, =0x04008040
  301 + str r2, [r0, #0x01c]
  302 +
  303 + ldr r2, =0x00005800
  304 + str r2, [r0, #0x020]
  305 + ldr r2, =0x00011117
  306 + str r2, [r0, #0x818]
  307 + str r2, [r1, #0x818]
  308 + ldr r2, =0x0002556D
  309 + str r2, [r0, #0x004]
  310 + ldr r2, =0x00011006
  311 + str r2, [r0, #0x404]
  312 + ldr r2, =0x00000000
  313 + str r2, [r0, #0x01c]
  314 +.endm
  315 +
  316 +.macro smarcfimx6_solo_ddr_setting
  317 + ldr r0, =IOMUXC_BASE_ADDR
  318 + ldr r1, =0x000c0000
  319 + str r1, [r0, #0x774]
  320 + ldr r1, =0x00000000
  321 + str r1, [r0, #0x754]
  322 +
  323 + ldr r1, =0x00000030
  324 + str r1, [r0, #0x4ac]
  325 + str r1, [r0, #0x4b0]
  326 + str r1, [r0, #0x464]
  327 + str r1, [r0, #0x490]
  328 + str r1, [r0, #0x74c]
  329 + str r1, [r0, #0x494]
  330 +
  331 + ldr r1, =0x00000000
  332 + str r1, [r0, #0x4a0]
  333 +
  334 + ldr r1, =0x00000030
  335 + str r1, [r0, #0x4b4]
  336 + str r1, [r0, #0x4b8]
  337 + str r1, [r0, #0x76c]
  338 +
  339 + ldr r1, =0x00020000
  340 + str r1, [r0, #0x750]
  341 +
  342 + ldr r1, =0x00000030
  343 + str r1, [r0, #0x4bc]
  344 + str r1, [r0, #0x4c0]
  345 + str r1, [r0, #0x4c4]
  346 + str r1, [r0, #0x4c8]
  347 +
  348 + ldr r1, =0x00020000
  349 + str r1, [r0, #0x760]
  350 +
  351 + ldr r1, =0x00000030
  352 + str r1, [r0, #0x764]
  353 + str r1, [r0, #0x770]
  354 + str r1, [r0, #0x778]
  355 + str r1, [r0, #0x77c]
  356 + str r1, [r0, #0x470]
  357 + str r1, [r0, #0x474]
  358 + str r1, [r0, #0x478]
  359 + str r1, [r0, #0x47c]
  360 +
  361 + ldr r0, =MMDC_P0_BASE_ADDR
  362 + ldr r2, =0xa1390003
  363 + str r2, [r0, #0x800]
  364 +
  365 + ldr r2, =0x001F001F
  366 + str r2, [r0, #0x80c]
  367 + str r2, [r0, #0x810]
  368 +
  369 + ldr r2, =0x42190219
  370 + str r2, [r0, #0x83c]
  371 + ldr r2, =0x017B0177
  372 + str r2, [r0, #0x840]
  373 +
  374 + ldr r2, =0x4B4D4E4D
  375 + str r2, [r0, #0x848]
  376 +
  377 + ldr r2, =0x3F3E2D36
  378 + str r2, [r0, #0x850]
  379 +
  380 + ldr r2, =0x33333333
  381 + str r2, [r0, #0x81c]
  382 + str r2, [r0, #0x820]
  383 + str r2, [r0, #0x824]
  384 + str r2, [r0, #0x828]
  385 +
  386 + ldr r2, =0x00000800
  387 + str r2, [r0, #0x8b8]
  388 +
  389 + ldr r2, =0x0002002D
  390 + str r2, [r0, #0x004]
  391 + ldr r2, =0x00333030
  392 + str r2, [r0, #0x008]
  393 +
  394 + ldr r2, =0x3F435313
  395 + str r2, [r0, #0x00c]
  396 + ldr r2, =0xB66E8B63
  397 + str r2, [r0, #0x010]
  398 +
  399 + ldr r2, =0x01FF00DB
  400 + str r2, [r0, #0x014]
  401 + ldr r2, =0x00001740
  402 + str r2, [r0, #0x018]
  403 +
  404 + ldr r2, =0x00008000
  405 + str r2, [r0, #0x01c]
  406 + ldr r2, =0x000026d2
  407 + str r2, [r0, #0x02c]
  408 + ldr r2, =0x00431023
  409 + str r2, [r0, #0x030]
  410 + ldr r2, =0x00000017
  411 + str r2, [r0, #0x040]
  412 +
  413 + ldr r2, =0x83190000
  414 + str r2, [r0, #0x000]
  415 +
  416 + ldr r2, =0x04008032
  417 + str r2, [r0, #0x01c]
  418 + ldr r2, =0x00008033
  419 + str r2, [r0, #0x01c]
  420 + ldr r2, =0x00048031
  421 + str r2, [r0, #0x01c]
  422 + ldr r2, =0x05208030
  423 + str r2, [r0, #0x01c]
  424 + ldr r2, =0x04008040
  425 + str r2, [r0, #0x01c]
  426 +
  427 + ldr r2, =0x00005800
  428 + str r2, [r0, #0x020]
  429 + ldr r2, =0x00011117
  430 + str r2, [r0, #0x818]
  431 + ldr r2, =0x0002556D
  432 + str r2, [r0, #0x004]
  433 + ldr r2, =0x00011006
  434 + str r2, [r0, #0x404]
  435 + ldr r2, =0x00000000
  436 + str r2, [r0, #0x01c]
  437 +.endm
  438 +.macro imx6_clock_gating
  439 + ldr r0, =CCM_BASE_ADDR
  440 + ldr r1, =0x00C03F3F
  441 + str r1, [r0, #0x068]
  442 + ldr r1, =0x0030FC03
  443 + str r1, [r0, #0x06c]
  444 + ldr r1, =0x0FFFC000
  445 + str r1, [r0, #0x070]
  446 + ldr r1, =0x3FF00000
  447 + str r1, [r0, #0x074]
  448 + ldr r1, =0x00FFF300
  449 + str r1, [r0, #0x078]
  450 + ldr r1, =0x0F0000C3
  451 + str r1, [r0, #0x07c]
  452 + ldr r1, =0x000003FF
  453 + str r1, [r0, #0x080]
  454 +.endm
  455 +
  456 +.macro imx6_qos_setting
  457 + ldr r0, =IOMUXC_BASE_ADDR
  458 + ldr r1, =0xF00000CF
  459 + str r1, [r0, #0x10]
  460 +
  461 + ldr r1, =0x007F007F
  462 + str r1, [r0, #0x18]
  463 + str r1, [r0, #0x1c]
  464 +.endm
  465 +
  466 +.macro imx6_ddr_setting
  467 +#if defined (CONFIG_MX6SOLO)
  468 + smarcfimx6_solo_ddr_setting
  469 +#elif defined (CONFIG_MX6DL)
  470 + smarcfimx6_dl_ddr_setting
  471 +#elif defined (CONFIG_MX6Q)
  472 + smarcfimx6_quad_ddr_setting
  473 +#else
  474 + #error "SOC not configured"
  475 +#endif
  476 +
  477 +.endm
  478 +
  479 +/* include the common plugin code here */
  480 +#include <asm/arch/mx6_plugin.S>
board/embedian/smarcfimx6/smarcfimx6.c
Diff comments   View file @ e29075c
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * Author: Fabio Estevam <fabio.estevam@freescale.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/io.h>
  11 +#include <asm/arch/clock.h>
  12 +#include <asm/arch/imx-regs.h>
  13 +#include <asm/arch/crm_regs.h>
  14 +#include <asm/arch/iomux.h>
  15 +#include <asm/arch/mx6-pins.h>
  16 +#include <asm/errno.h>
  17 +#include <asm/gpio.h>
  18 +#include <asm/imx-common/iomux-v3.h>
  19 +#include <asm/imx-common/boot_mode.h>
  20 +#include <mmc.h>
  21 +#include <fsl_esdhc.h>
  22 +#include <miiphy.h>
  23 +#include <netdev.h>
  24 +#include <phy.h>
  25 +
  26 +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
  27 +#include <lcd.h>
  28 +#include <mxc_epdc_fb.h>
  29 +#endif
  30 +#include <asm/arch/mxc_hdmi.h>
  31 +#include <asm/arch/crm_regs.h>
  32 +#include <linux/fb.h>
  33 +#include <ipu_pixfmt.h>
  34 +#include <asm/io.h>
  35 +#include <asm/arch/sys_proto.h>
  36 +#ifdef CONFIG_SYS_I2C_MXC
  37 +#include <i2c.h>
  38 +#include <asm/imx-common/mxc_i2c.h>
  39 +#endif
  40 +#include "smarcfimx6.h"
  41 +#ifdef CONFIG_CMD_SATA
  42 +#include <asm/imx-common/sata.h>
  43 +#endif
  44 +#ifdef CONFIG_FASTBOOT
  45 +#include <fastboot.h>
  46 +#ifdef CONFIG_ANDROID_RECOVERY
  47 +#include <recovery.h>
  48 +#endif
  49 +#endif /*CONFIG_FASTBOOT*/
  50 +
  51 +DECLARE_GLOBAL_DATA_PTR;
  52 +
  53 +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  54 + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  55 + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  56 +
  57 +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  58 + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  59 + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  60 +
  61 +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  62 + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  63 +
  64 +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  65 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  66 +
  67 +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  68 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  69 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  70 + PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  71 +
  72 +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
  73 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  74 +
  75 +#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
  76 + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  77 + PAD_CTL_SRE_SLOW)
  78 +
  79 +#ifdef CONFIG_SYS_I2C_MXC
  80 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  81 +/*I2C1 I2C_PM*/
  82 +struct i2c_pads_info i2c_pad_info1 = {
  83 + .scl = {
  84 + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  85 + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  86 + .gp = IMX_GPIO_NR(3, 21)
  87 + },
  88 + .sda = {
  89 + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  90 + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  91 + .gp = IMX_GPIO_NR(3, 28)
  92 + }
  93 +};
  94 +
  95 +/* I2C2 HDMI */
  96 +struct i2c_pads_info i2c_pad_info2 = {
  97 + .scl = {
  98 + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
  99 + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
  100 + .gp = IMX_GPIO_NR(4, 12)
  101 + },
  102 + .sda = {
  103 + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  104 + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  105 + .gp = IMX_GPIO_NR(4, 13)
  106 + }
  107 +};
  108 +
  109 +/* I2C3 TCA9546APWR */
  110 +struct i2c_pads_info i2c_pad_info3 = {
  111 + .scl = {
  112 + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
  113 + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
  114 + .gp = IMX_GPIO_NR(3, 17)
  115 + },
  116 + .sda = {
  117 + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
  118 + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
  119 + .gp = IMX_GPIO_NR(3, 18)
  120 + }
  121 +};
  122 +#endif
  123 +
  124 +int dram_init(void)
  125 +{
  126 +
  127 + gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  128 +
  129 + return 0;
  130 +}
  131 +
  132 +/* SER0/UART1 */
  133 +iomux_v3_cfg_t const uart1_pads[] = {
  134 + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  135 + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  136 + MX6_PAD_EIM_D20__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  137 + MX6_PAD_EIM_D19__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  138 +};
  139 +
  140 +/* SER1/UART2 */
  141 +iomux_v3_cfg_t const uart2_pads[] = {
  142 + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  143 + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  144 +};
  145 +
  146 +/* SER2/UART4 */
  147 +iomux_v3_cfg_t const uart4_pads[] = {
  148 + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  149 + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  150 + MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  151 + MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  152 +};
  153 +
  154 +/* SER3/UART5 Debug Port */
  155 +iomux_v3_cfg_t const uart5_pads[] = {
  156 + MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  157 + MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  158 +};
  159 +
  160 +iomux_v3_cfg_t const wdt_pads[] = {
  161 + MX6_PAD_EIM_D16__GPIO3_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
  162 +};
  163 +
  164 +iomux_v3_cfg_t const enet_pads[] = {
  165 + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  166 + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  167 + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  168 + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  169 + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  170 + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  171 + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  172 + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  173 + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  174 + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  175 + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  176 + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  177 + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  178 + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  179 + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  180 +};
  181 +
  182 +static void setup_iomux_enet(void)
  183 +{
  184 + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  185 + gpio_direction_input(IMX_GPIO_NR(4, 11));
  186 +}
  187 +
  188 +/* SDIO */
  189 +iomux_v3_cfg_t const usdhc2_pads[] = {
  190 + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  191 + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  192 + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  193 + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  194 + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  195 + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  196 + MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  197 + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
  198 + MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), /* SDIO_PWR_EN */
  199 +};
  200 +
  201 +/* SDMMC */
  202 +iomux_v3_cfg_t const usdhc3_pads[] = {
  203 + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  204 + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  205 + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  206 + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  207 + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  208 + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  209 + MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  210 +};
  211 +
  212 +/* eMMC */
  213 +iomux_v3_cfg_t const usdhc4_pads[] = {
  214 + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  215 + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  216 + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  217 + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  218 + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  219 + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  220 + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  221 + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  222 + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  223 + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  224 +};
  225 +
  226 +#ifdef CONFIG_SYS_USE_SPINOR
  227 +/* SPI0 */
  228 +iomux_v3_cfg_t const ecspi2_pads[] = {
  229 + MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  230 + MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  231 + MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  232 + MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/
  233 + MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/
  234 + MX6_PAD_EIM_D25__GPIO3_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/
  235 +};
  236 +
  237 +static void setup_spinor(void)
  238 +{
  239 + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
  240 + gpio_direction_output(IMX_GPIO_NR(5, 29), 0);
  241 + gpio_direction_output(IMX_GPIO_NR(3, 24), 0);
  242 + gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
  243 +}
  244 +#endif
  245 +
  246 +/* SPI1 */
  247 + iomux_v3_cfg_t const ecspi1_pads[] = {
  248 + MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  249 + MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  250 + MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  251 + MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/
  252 + MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/
  253 +};
  254 +
  255 +iomux_v3_cfg_t const pcie_pads[] = {
  256 + MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Present */
  257 + MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
  258 + MX6_PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Clock Request */
  259 +};
  260 +
  261 +static void setup_pcie(void)
  262 +{
  263 + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
  264 + gpio_direction_input(IMX_GPIO_NR(1, 16));
  265 + gpio_direction_input(IMX_GPIO_NR(1, 17));
  266 + gpio_direction_input(IMX_GPIO_NR(1, 19));
  267 + gpio_direction_output(IMX_GPIO_NR(1, 20), 0);
  268 +}
  269 +
  270 +/* CAN0/FLEXCAN1 */
  271 +iomux_v3_cfg_t const flexcan1_pads[] = {
  272 + MX6_PAD_GPIO_7__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP),
  273 + MX6_PAD_GPIO_8__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP),
  274 +};
  275 +
  276 +/* CAN1/FLEXCAN2 */
  277 +iomux_v3_cfg_t const flexcan2_pads[] = {
  278 + MX6_PAD_KEY_COL4__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP),
  279 + MX6_PAD_KEY_ROW4__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP),
  280 +};
  281 +
  282 +/* GPIOs */
  283 +iomux_v3_cfg_t const gpios_pads[] = {
  284 + MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */
  285 + MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */
  286 + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */
  287 + MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */
  288 + MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */
  289 + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */
  290 + MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */
  291 + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */
  292 + MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */
  293 + MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */
  294 + MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */
  295 +};
  296 +
  297 +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
  298 +static iomux_v3_cfg_t const epdc_enable_pads[] = {
  299 + MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  300 + MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  301 + MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  302 + MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  303 + MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  304 + MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  305 + MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  306 + MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  307 + MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  308 + MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  309 + MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  310 + MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  311 + MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  312 + MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  313 + MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  314 + MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  315 + MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  316 + MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  317 + MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  318 + MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  319 +};
  320 +
  321 +static iomux_v3_cfg_t const epdc_disable_pads[] = {
  322 + MX6_PAD_EIM_A16__GPIO2_IO22,
  323 + MX6_PAD_EIM_DA10__GPIO3_IO10,
  324 + MX6_PAD_EIM_DA12__GPIO3_IO12,
  325 + MX6_PAD_EIM_DA11__GPIO3_IO11,
  326 + MX6_PAD_EIM_LBA__GPIO2_IO27,
  327 + MX6_PAD_EIM_EB2__GPIO2_IO30,
  328 + MX6_PAD_EIM_CS0__GPIO2_IO23,
  329 + MX6_PAD_EIM_RW__GPIO2_IO26,
  330 + MX6_PAD_EIM_A21__GPIO2_IO17,
  331 + MX6_PAD_EIM_A22__GPIO2_IO16,
  332 + MX6_PAD_EIM_A23__GPIO6_IO06,
  333 + MX6_PAD_EIM_A24__GPIO5_IO04,
  334 + MX6_PAD_EIM_D31__GPIO3_IO31,
  335 + MX6_PAD_EIM_D27__GPIO3_IO27,
  336 + MX6_PAD_EIM_DA1__GPIO3_IO01,
  337 + MX6_PAD_EIM_EB1__GPIO2_IO29,
  338 + MX6_PAD_EIM_DA2__GPIO3_IO02,
  339 + MX6_PAD_EIM_DA4__GPIO3_IO04,
  340 + MX6_PAD_EIM_DA5__GPIO3_IO05,
  341 + MX6_PAD_EIM_DA6__GPIO3_IO06,
  342 +};
  343 +#endif
  344 +
  345 +static void setup_iomux_uart1(void)
  346 +{
  347 + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  348 +}
  349 +
  350 +static void setup_iomux_uart2(void)
  351 +{
  352 + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  353 +}
  354 +
  355 +static void setup_iomux_uart4(void)
  356 +{
  357 + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  358 +}
  359 +
  360 +static void setup_iomux_uart5(void)
  361 +{
  362 + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
  363 +}
  364 +
  365 +static void setup_iomux_wdt(void)
  366 +{
  367 + imx_iomux_v3_setup_multiple_pads(wdt_pads, ARRAY_SIZE(wdt_pads));
  368 +
  369 + /* Set HW_WDT as Output High */
  370 + gpio_direction_output(IMX_GPIO_NR(3, 16) , 1);
  371 +}
  372 +
  373 +static void setup_spi1(void)
  374 +{
  375 + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  376 + gpio_direction_output(IMX_GPIO_NR(4, 9), 0);
  377 + gpio_direction_output(IMX_GPIO_NR(4, 10), 0);
  378 +}
  379 +
  380 +static void setup_flexcan1(void)
  381 +{
  382 + imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads));
  383 +}
  384 +
  385 +static void setup_flexcan2(void)
  386 +{
  387 + imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads));
  388 +}
  389 +
  390 +static void setup_gpios(void)
  391 +{
  392 + imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads));
  393 + gpio_direction_output(IMX_GPIO_NR(6, 11), 0);
  394 + gpio_direction_output(IMX_GPIO_NR(2, 02), 0);
  395 + gpio_direction_output(IMX_GPIO_NR(2, 06), 0);
  396 + gpio_direction_output(IMX_GPIO_NR(2, 03), 0);
  397 + gpio_direction_output(IMX_GPIO_NR(2, 07), 0);
  398 + gpio_direction_input(IMX_GPIO_NR(6, 14));
  399 + gpio_direction_input(IMX_GPIO_NR(6, 07));
  400 + gpio_direction_input(IMX_GPIO_NR(2, 04));
  401 + gpio_direction_input(IMX_GPIO_NR(2, 00));
  402 + gpio_direction_input(IMX_GPIO_NR(2, 05));
  403 + gpio_direction_input(IMX_GPIO_NR(6, 8));
  404 +}
  405 +
  406 +#ifdef CONFIG_FSL_ESDHC
  407 +struct fsl_esdhc_cfg usdhc_cfg[3] = {
  408 + {USDHC2_BASE_ADDR},
  409 + {USDHC3_BASE_ADDR},
  410 + {USDHC4_BASE_ADDR},
  411 +};
  412 +
  413 +int mmc_get_env_devno(void)
  414 +{
  415 + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
  416 + u32 dev_no;
  417 + u32 bootsel;
  418 +
  419 + bootsel = (soc_sbmr & 0x000000FF) >> 6 ;
  420 +
  421 + /* If not boot from sd/mmc, use default value */
  422 + if (bootsel != 1)
  423 + return CONFIG_SYS_MMC_ENV_DEV;
  424 +
  425 + /* BOOT_CFG2[3] and BOOT_CFG2[4] */
  426 + dev_no = (soc_sbmr & 0x00001800) >> 11;
  427 +
  428 + /* need ubstract 1 to map to the mmc device id
  429 + * see the comments in board_mmc_init function
  430 + */
  431 +
  432 + dev_no--;
  433 +
  434 + return dev_no;
  435 +}
  436 +
  437 +int mmc_map_to_kernel_blk(int dev_no)
  438 +{
  439 + return dev_no + 1;
  440 +}
  441 +
  442 +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 28)
  443 +/*#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)*/
  444 +
  445 +int board_mmc_getcd(struct mmc *mmc)
  446 +{
  447 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  448 + int ret = 0;
  449 +
  450 + switch (cfg->esdhc_base) {
  451 + case USDHC2_BASE_ADDR:
  452 + ret = !gpio_get_value(USDHC2_CD_GPIO);
  453 + break;
  454 + case USDHC3_BASE_ADDR:
  455 + /*ret = !gpio_get_value(USDHC3_CD_GPIO);*/
  456 + break;
  457 + case USDHC4_BASE_ADDR:
  458 + ret = 1; /* eMMC/uSDHC4 is always present */
  459 + break;
  460 + }
  461 +
  462 + return ret;
  463 +}
  464 +
  465 +int board_mmc_init(bd_t *bis)
  466 +{
  467 + s32 status = 0;
  468 + int i;
  469 +
  470 + /*
  471 + * According to the board_mmc_init() the following map is done:
  472 + * (U-boot device node) (Physical Port)
  473 + * mmc0 SDIO
  474 + * mmc1 SDMMC
  475 + * mmc2 eMMC
  476 + */
  477 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  478 + switch (i) {
  479 + case 0:
  480 + imx_iomux_v3_setup_multiple_pads(
  481 + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  482 + gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
  483 + gpio_direction_input(USDHC2_CD_GPIO);
  484 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  485 + break;
  486 + case 1:
  487 + imx_iomux_v3_setup_multiple_pads(
  488 + usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  489 + /*gpio_direction_input(USDHC3_CD_GPIO);*/
  490 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  491 + break;
  492 + case 2:
  493 + imx_iomux_v3_setup_multiple_pads(
  494 + usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  495 + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  496 + break;
  497 + default:
  498 + printf("Warning: you configured more USDHC controllers"
  499 + "(%d) then supported by the board (%d)\n",
  500 + i + 1, CONFIG_SYS_FSL_USDHC_NUM);
  501 + return status;
  502 + }
  503 +
  504 + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  505 + }
  506 +
  507 + return status;
  508 +}
  509 +
  510 +int check_mmc_autodetect(void)
  511 +{
  512 + char *autodetect_str = getenv("mmcautodetect");
  513 +
  514 + if ((autodetect_str != NULL) &&
  515 + (strcmp(autodetect_str, "yes") == 0)) {
  516 + return 1;
  517 + }
  518 +
  519 + return 0;
  520 +}
  521 +
  522 +void board_late_mmc_env_init(void)
  523 +{
  524 + char cmd[32];
  525 + char mmcblk[32];
  526 + u32 dev_no = mmc_get_env_devno();
  527 +
  528 + if (!check_mmc_autodetect())
  529 + return;
  530 +
  531 + setenv_ulong("mmcdev", dev_no);
  532 +
  533 + /* Set mmcblk env */
  534 + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
  535 + mmc_map_to_kernel_blk(dev_no));
  536 + setenv("mmcroot", mmcblk);
  537 +
  538 + sprintf(cmd, "mmc dev %d", dev_no);
  539 + run_command(cmd, 0);
  540 +}
  541 +#endif
  542 +
  543 +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
  544 +#ifdef CONFIG_SPLASH_SCREEN
  545 +extern int mmc_get_env_devno(void);
  546 +int setup_splash_img(void)
  547 +{
  548 +#ifdef CONFIG_SPLASH_IS_IN_MMC
  549 + int mmc_dev = mmc_get_env_devno();
  550 + ulong offset = CONFIG_SPLASH_IMG_OFFSET;
  551 + ulong size = CONFIG_SPLASH_IMG_SIZE;
  552 + ulong addr = 0;
  553 + char *s = NULL;
  554 + struct mmc *mmc = find_mmc_device(mmc_dev);
  555 + uint blk_start, blk_cnt, n;
  556 +
  557 + s = getenv("splashimage");
  558 +
  559 + if (NULL == s) {
  560 + puts("env splashimage not found!\n");
  561 + return -1;
  562 + }
  563 + addr = simple_strtoul(s, NULL, 16);
  564 +
  565 + if (!mmc) {
  566 + printf("MMC Device %d not found\n", mmc_dev);
  567 + return -1;
  568 + }
  569 +
  570 + if (mmc_init(mmc)) {
  571 + puts("MMC init failed\n");
  572 + return -1;
  573 + }
  574 +
  575 + blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
  576 + blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
  577 + n = mmc->block_dev.block_read(mmc_dev, blk_start,
  578 + blk_cnt, (u_char *)addr);
  579 + flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
  580 +
  581 + return (n == blk_cnt) ? 0 : -1;
  582 +#endif
  583 +
  584 + return 0;
  585 +}
  586 +#endif
  587 +
  588 +vidinfo_t panel_info = {
  589 + .vl_refresh = 85,
  590 + .vl_col = 800,
  591 + .vl_row = 600,
  592 + .vl_pixclock = 26666667,
  593 + .vl_left_margin = 8,
  594 + .vl_right_margin = 100,
  595 + .vl_upper_margin = 4,
  596 + .vl_lower_margin = 8,
  597 + .vl_hsync = 4,
  598 + .vl_vsync = 1,
  599 + .vl_sync = 0,
  600 + .vl_mode = 0,
  601 + .vl_flag = 0,
  602 + .vl_bpix = 3,
  603 + .cmap = 0,
  604 +};
  605 +
  606 +struct epdc_timing_params panel_timings = {
  607 + .vscan_holdoff = 4,
  608 + .sdoed_width = 10,
  609 + .sdoed_delay = 20,
  610 + .sdoez_width = 10,
  611 + .sdoez_delay = 20,
  612 + .gdclk_hp_offs = 419,
  613 + .gdsp_offs = 20,
  614 + .gdoe_offs = 0,
  615 + .gdclk_offs = 5,
  616 + .num_ce = 1,
  617 +};
  618 +
  619 +static void setup_epdc_power(void)
  620 +{
  621 + /* Setup epdc voltage */
  622 +
  623 + /* EIM_A17 - GPIO2[21] for PWR_GOOD status */
  624 + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |
  625 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  626 + /* Set as input */
  627 + gpio_direction_input(IMX_GPIO_NR(2, 21));
  628 +
  629 + /* EIM_D17 - GPIO3[17] for VCOM control */
  630 + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |
  631 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  632 +
  633 + /* Set as output */
  634 + gpio_direction_output(IMX_GPIO_NR(3, 17), 1);
  635 +
  636 + /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */
  637 + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |
  638 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  639 + /* Set as output */
  640 + gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
  641 +
  642 + /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */
  643 + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |
  644 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  645 + /* Set as output */
  646 + gpio_direction_output(IMX_GPIO_NR(2, 20), 1);
  647 +}
  648 +
  649 +int setup_waveform_file(void)
  650 +{
  651 +#ifdef CONFIG_WAVEFORM_FILE_IN_MMC
  652 + int mmc_dev = mmc_get_env_devno();
  653 + ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
  654 + ulong size = CONFIG_WAVEFORM_FILE_SIZE;
  655 + ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
  656 + struct mmc *mmc = find_mmc_device(mmc_dev);
  657 + uint blk_start, blk_cnt, n;
  658 +
  659 + if (!mmc) {
  660 + printf("MMC Device %d not found\n", mmc_dev);
  661 + return -1;
  662 + }
  663 +
  664 + if (mmc_init(mmc)) {
  665 + puts("MMC init failed\n");
  666 + return -1;
  667 + }
  668 +
  669 + blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
  670 + blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
  671 + n = mmc->block_dev.block_read(mmc_dev, blk_start,
  672 + blk_cnt, (u_char *)addr);
  673 + flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
  674 +
  675 + return (n == blk_cnt) ? 0 : -1;
  676 +#else
  677 + return -1;
  678 +#endif
  679 +}
  680 +
  681 +static void epdc_enable_pins(void)
  682 +{
  683 + /* epdc iomux settings */
  684 + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
  685 + ARRAY_SIZE(epdc_enable_pads));
  686 +}
  687 +
  688 +static void epdc_disable_pins(void)
  689 +{
  690 + /* Configure MUX settings for EPDC pins to GPIO */
  691 + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
  692 + ARRAY_SIZE(epdc_disable_pads));
  693 +}
  694 +
  695 +static void setup_epdc(void)
  696 +{
  697 + unsigned int reg;
  698 + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  699 +
  700 + /*** epdc Maxim PMIC settings ***/
  701 +
  702 + /* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */
  703 + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |
  704 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  705 +
  706 + /* EPDC VCOM0 - GPIO3[17] for VCOM control */
  707 + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |
  708 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  709 +
  710 + /* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */
  711 + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |
  712 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  713 +
  714 + /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */
  715 + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |
  716 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  717 +
  718 + /*** Set pixel clock rates for EPDC ***/
  719 +
  720 + /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */
  721 + reg = readl(&ccm_regs->cscdr3);
  722 + reg &= ~0x7C000;
  723 + reg |= (1 << 16) | (1 << 14);
  724 + writel(reg, &ccm_regs->cscdr3);
  725 +
  726 + /* EPDC AXI clk enable */
  727 + reg = readl(&ccm_regs->CCGR3);
  728 + reg |= 0x00C0;
  729 + writel(reg, &ccm_regs->CCGR3);
  730 +
  731 + /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */
  732 + reg = readl(&ccm_regs->cscdr2);
  733 + reg &= ~0x3FE00;
  734 + reg |= (2 << 15) | (5 << 12);
  735 + writel(reg, &ccm_regs->cscdr2);
  736 +
  737 + /* PLL5 enable (defaults to 650) */
  738 + reg = readl(&ccm_regs->analog_pll_video);
  739 + reg &= ~((1 << 16) | (1 << 12));
  740 + reg |= (1 << 13);
  741 + writel(reg, &ccm_regs->analog_pll_video);
  742 +
  743 + /* EPDC PIX clk enable */
  744 + reg = readl(&ccm_regs->CCGR3);
  745 + reg |= 0x0C00;
  746 + writel(reg, &ccm_regs->CCGR3);
  747 +
  748 + panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR;
  749 + panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR;
  750 +
  751 + panel_info.epdc_data.wv_modes.mode_init = 0;
  752 + panel_info.epdc_data.wv_modes.mode_du = 1;
  753 + panel_info.epdc_data.wv_modes.mode_gc4 = 3;
  754 + panel_info.epdc_data.wv_modes.mode_gc8 = 2;
  755 + panel_info.epdc_data.wv_modes.mode_gc16 = 2;
  756 + panel_info.epdc_data.wv_modes.mode_gc32 = 2;
  757 +
  758 + panel_info.epdc_data.epdc_timings = panel_timings;
  759 +
  760 + setup_epdc_power();
  761 +
  762 + /* Assign fb_base */
  763 + gd->fb_base = CONFIG_FB_BASE;
  764 +}
  765 +
  766 +void epdc_power_on(void)
  767 +{
  768 + unsigned int reg;
  769 + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
  770 +
  771 + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
  772 + gpio_set_value(IMX_GPIO_NR(2, 20), 1);
  773 + udelay(1000);
  774 +
  775 + /* Enable epdc signal pin */
  776 + epdc_enable_pins();
  777 +
  778 + /* Set PMIC Wakeup to high - enable Display power */
  779 + gpio_set_value(IMX_GPIO_NR(3, 20), 1);
  780 +
  781 + /* Wait for PWRGOOD == 1 */
  782 + while (1) {
  783 + reg = readl(&gpio_regs->gpio_psr);
  784 + if (!(reg & (1 << 21)))
  785 + break;
  786 +
  787 + udelay(100);
  788 + }
  789 +
  790 + /* Enable VCOM */
  791 + gpio_set_value(IMX_GPIO_NR(3, 17), 1);
  792 +
  793 + udelay(500);
  794 +}
  795 +
  796 +void epdc_power_off(void)
  797 +{
  798 + /* Set PMIC Wakeup to low - disable Display power */
  799 + gpio_set_value(IMX_GPIO_NR(3, 20), 0);
  800 +
  801 + /* Disable VCOM */
  802 + gpio_set_value(IMX_GPIO_NR(3, 17), 0);
  803 +
  804 + epdc_disable_pins();
  805 +
  806 + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
  807 + gpio_set_value(IMX_GPIO_NR(2, 20), 0);
  808 +}
  809 +#endif
  810 +
  811 +#if defined(CONFIG_VIDEO_IPUV3)
  812 +
  813 +static iomux_v3_cfg_t const backlight_pads[] = {
  814 + /* Backlight Enable for RGB: S127 */
  815 + MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  816 +#define BACKLIGHT_EN IMX_GPIO_NR(1, 00)
  817 + /* PWM Backlight Control: S141 */
  818 + MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
  819 +#define BACKLIGHT_PWM IMX_GPIO_NR(1, 01)
  820 + /* Backlight Enable for LVDS: S127 */
  821 + /*MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  822 +#define LVDS_BACKLIGHT_EN IMX_GPIO_NR(1, 00)*/
  823 + /* LCD VDD Enable: S133 */
  824 + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  825 +#define LCD_VDD_EN IMX_GPIO_NR(1, 02)
  826 +};
  827 +
  828 +static iomux_v3_cfg_t const rgb_pads[] = {
  829 + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
  830 + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
  831 + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
  832 + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
  833 + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */
  834 + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
  835 + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
  836 + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
  837 + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
  838 + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
  839 + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
  840 + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
  841 + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
  842 + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
  843 + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
  844 + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
  845 + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
  846 + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
  847 + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
  848 + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
  849 + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
  850 + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
  851 + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
  852 + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
  853 + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
  854 + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
  855 + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
  856 + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
  857 + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
  858 +};
  859 +
  860 +struct display_info_t {
  861 + int bus;
  862 + int addr;
  863 + int pixfmt;
  864 + int (*detect)(struct display_info_t const *dev);
  865 + void (*enable)(struct display_info_t const *dev);
  866 + struct fb_videomode mode;
  867 +};
  868 +
  869 +
  870 +static int detect_hdmi(struct display_info_t const *dev)
  871 +{
  872 + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
  873 + return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
  874 +}
  875 +
  876 +static void do_enable_hdmi(struct display_info_t const *dev)
  877 +{
  878 + imx_enable_hdmi_phy();
  879 +}
  880 +
  881 +static int detect_i2c(struct display_info_t const *dev)
  882 +{
  883 + return ((0 == i2c_set_bus_num(dev->bus))
  884 + &&
  885 + (0 == i2c_probe(dev->addr)));
  886 +}
  887 +
  888 +static void enable_lvds(struct display_info_t const *dev)
  889 +{
  890 + struct iomuxc *iomux = (struct iomuxc *)
  891 + IOMUXC_BASE_ADDR;
  892 + u32 reg = readl(&iomux->gpr[2]);
  893 + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  894 + writel(reg, &iomux->gpr[2]);
  895 + gpio_direction_output(BACKLIGHT_EN, 1);
  896 +}
  897 +
  898 +static void enable_rgb(struct display_info_t const *dev)
  899 +{
  900 + imx_iomux_v3_setup_multiple_pads(
  901 + rgb_pads,
  902 + ARRAY_SIZE(rgb_pads));
  903 + gpio_direction_output(BACKLIGHT_EN, 1);
  904 + gpio_direction_output(LCD_VDD_EN, 1);
  905 + gpio_direction_output(BACKLIGHT_PWM, 1);
  906 +}
  907 +
  908 +static struct display_info_t const displays[] = {{
  909 + .bus = -1,
  910 + .addr = 0,
  911 + .pixfmt = IPU_PIX_FMT_RGB24,
  912 + .detect = detect_hdmi,
  913 + .enable = do_enable_hdmi,
  914 + .mode = {
  915 + .name = "HDMI",
  916 + .refresh = 60,
  917 + .xres = 1024,
  918 + .yres = 768,
  919 + .pixclock = 15385,
  920 + .left_margin = 220,
  921 + .right_margin = 40,
  922 + .upper_margin = 21,
  923 + .lower_margin = 7,
  924 + .hsync_len = 60,
  925 + .vsync_len = 10,
  926 + .sync = FB_SYNC_EXT,
  927 + .vmode = FB_VMODE_NONINTERLACED
  928 +} }, {
  929 + .bus = 3,
  930 + .addr = 0x4,
  931 + .pixfmt = IPU_PIX_FMT_LVDS666,
  932 + .detect = detect_i2c,
  933 + .enable = enable_lvds,
  934 + .mode = {
  935 + .name = "Hannstar-XGA",
  936 + .refresh = 60,
  937 + .xres = 1024,
  938 + .yres = 768,
  939 + .pixclock = 15385,
  940 + .left_margin = 220,
  941 + .right_margin = 40,
  942 + .upper_margin = 21,
  943 + .lower_margin = 7,
  944 + .hsync_len = 60,
  945 + .vsync_len = 10,
  946 + .sync = FB_SYNC_EXT,
  947 + .vmode = FB_VMODE_NONINTERLACED
  948 +} }, {
  949 + .bus = 3,
  950 + .addr = 0x38,
  951 + .pixfmt = IPU_PIX_FMT_LVDS666,
  952 + .detect = detect_i2c,
  953 + .enable = enable_lvds,
  954 + .mode = {
  955 + .name = "wsvga-lvds",
  956 + .refresh = 60,
  957 + .xres = 1024,
  958 + .yres = 600,
  959 + .pixclock = 15385,
  960 + .left_margin = 220,
  961 + .right_margin = 40,
  962 + .upper_margin = 21,
  963 + .lower_margin = 7,
  964 + .hsync_len = 60,
  965 + .vsync_len = 10,
  966 + .sync = FB_SYNC_EXT,
  967 + .vmode = FB_VMODE_NONINTERLACED
  968 +} }, {
  969 + .bus = 3,
  970 + .addr = 0x48,
  971 + .pixfmt = IPU_PIX_FMT_RGB666,
  972 + .detect = detect_i2c,
  973 + .enable = enable_rgb,
  974 + .mode = {
  975 + .name = "wvga-rgb",
  976 + .refresh = 57,
  977 + .xres = 800,
  978 + .yres = 480,
  979 + .pixclock = 37037,
  980 + .left_margin = 40,
  981 + .right_margin = 60,
  982 + .upper_margin = 10,
  983 + .lower_margin = 10,
  984 + .hsync_len = 20,
  985 + .vsync_len = 10,
  986 + .sync = 0,
  987 + .vmode = FB_VMODE_NONINTERLACED
  988 +} } };
  989 +int board_video_skip(void)
  990 +{
  991 + int i;
  992 + int ret;
  993 + char const *panel = getenv("panel");
  994 + if (!panel) {
  995 + for (i = 0; i < ARRAY_SIZE(displays); i++) {
  996 + struct display_info_t const *dev = displays+i;
  997 + if (dev->detect(dev)) {
  998 + panel = dev->mode.name;
  999 + printf("auto-detected panel %s\n", panel);
  1000 + break;
  1001 + }
  1002 + }
  1003 + if (!panel) {
  1004 + panel = displays[0].mode.name;
  1005 + printf("No panel detected: default to %s\n", panel);
  1006 + i = 0;
  1007 + }
  1008 + } else {
  1009 + for (i = 0; i < ARRAY_SIZE(displays); i++) {
  1010 + if (!strcmp(panel, displays[i].mode.name))
  1011 + break;
  1012 + }
  1013 + }
  1014 + if (i < ARRAY_SIZE(displays)) {
  1015 + ret = ipuv3_fb_init(&displays[i].mode, 0,
  1016 + displays[i].pixfmt);
  1017 + if (!ret) {
  1018 + displays[i].enable(displays+i);
  1019 + printf("Display: %s (%ux%u)\n",
  1020 + displays[i].mode.name,
  1021 + displays[i].mode.xres,
  1022 + displays[i].mode.yres);
  1023 + } else {
  1024 + printf("LCD %s cannot be configured: %d\n",
  1025 + displays[i].mode.name, ret);
  1026 + }
  1027 + } else {
  1028 + printf("unsupported panel %s\n", panel);
  1029 + ret = -EINVAL;
  1030 + }
  1031 + return (0 != ret);
  1032 +}
  1033 +
  1034 +static void setup_display(void)
  1035 +{
  1036 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1037 + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  1038 + int reg;
  1039 +
  1040 + enable_ipu_clock();
  1041 + imx_setup_hdmi();
  1042 + /* Turn on LDB0,IPU,IPU DI0 clocks */
  1043 + reg = __raw_readl(&mxc_ccm->CCGR3);
  1044 + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  1045 + writel(reg, &mxc_ccm->CCGR3);
  1046 +
  1047 + /* set LDB0, LDB1 clk select to 011/011 */
  1048 + reg = readl(&mxc_ccm->cs2cdr);
  1049 + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  1050 + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  1051 + reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  1052 + |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  1053 + writel(reg, &mxc_ccm->cs2cdr);
  1054 +
  1055 + reg = readl(&mxc_ccm->cscmr2);
  1056 + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  1057 + writel(reg, &mxc_ccm->cscmr2);
  1058 +
  1059 + reg = readl(&mxc_ccm->chsccdr);
  1060 + reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  1061 + <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  1062 + writel(reg, &mxc_ccm->chsccdr);
  1063 +
  1064 + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  1065 + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  1066 + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  1067 + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  1068 + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  1069 + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  1070 + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  1071 + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  1072 + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  1073 + writel(reg, &iomux->gpr[2]);
  1074 +
  1075 + reg = readl(&iomux->gpr[3]);
  1076 + reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
  1077 + |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  1078 + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  1079 + <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  1080 + writel(reg, &iomux->gpr[3]);
  1081 +
  1082 + /* backlights off until needed */
  1083 + /*imx_iomux_v3_setup_multiple_pads(backlight_pads,
  1084 + ARRAY_SIZE(backlight_pads));
  1085 + gpio_direction_input(BACKLIGHT_EN);*/
  1086 +}
  1087 +#endif /* CONFIG_VIDEO_IPUV3 */
  1088 +
  1089 +/*
  1090 + * Do not overwrite the console
  1091 + * Use always serial for U-Boot console
  1092 + */
  1093 +int overwrite_console(void)
  1094 +{
  1095 + return 1;
  1096 +}
  1097 +
  1098 +int board_eth_init(bd_t *bis)
  1099 +{
  1100 +#if defined(CONFIG_MAC_ADDR_IN_EEPROM)
  1101 +
  1102 + uchar env_enetaddr[6];
  1103 + int enetaddr_found;
  1104 +
  1105 + enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr);
  1106 +
  1107 + uint8_t enetaddr[8];
  1108 + int eeprom_mac_read;
  1109 +
  1110 + /* Read Ethernet MAC address from EEPROM */
  1111 + eeprom_mac_read = smarcfimx6_read_mac_address(enetaddr);
  1112 +
  1113 + /*
  1114 + * MAC address not present in the environment
  1115 + * try and read the MAC address from EEPROM flash
  1116 + * and set it.
  1117 + */
  1118 + if (!enetaddr_found) {
  1119 + if (eeprom_mac_read)
  1120 + /* Set Ethernet MAC address from EEPROM */
  1121 + smarcfimx6_sync_env_enetaddr(enetaddr);
  1122 + } else {
  1123 + /*
  1124 + * MAC address present in environment compare it with
  1125 + * the MAC address in EEPROM and warn on mismatch
  1126 + */
  1127 + if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
  1128 + printf("Warning: MAC address in EEPROM don't match "
  1129 + "with the MAC address in the environment\n");
  1130 + printf("Default using MAC address from environment\n");
  1131 + }
  1132 +
  1133 +#endif
  1134 +
  1135 + setup_iomux_enet();
  1136 + setup_pcie();
  1137 +
  1138 + return cpu_eth_init(bis);
  1139 +}
  1140 +
  1141 +int board_early_init_f(void)
  1142 +{
  1143 + setup_iomux_wdt();
  1144 + setup_iomux_uart1();
  1145 + setup_iomux_uart2();
  1146 + setup_iomux_uart4();
  1147 + setup_iomux_uart5();
  1148 +#if defined(CONFIG_VIDEO_IPUV3)
  1149 + setup_display();
  1150 +#endif
  1151 +
  1152 +#ifdef CONFIG_SYS_USE_SPINOR
  1153 + setup_spinor();
  1154 +#endif
  1155 +
  1156 + setup_spi1();
  1157 + setup_flexcan1();
  1158 + setup_flexcan2();
  1159 + setup_gpios();
  1160 +
  1161 +#ifdef CONFIG_CMD_SATA
  1162 + setup_sata();
  1163 +#endif
  1164 +
  1165 + return 0;
  1166 +}
  1167 +
  1168 +int board_init(void)
  1169 +{
  1170 + /* address of boot parameters */
  1171 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  1172 +
  1173 +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
  1174 + setup_epdc();
  1175 +#endif
  1176 +
  1177 +#ifdef CONFIG_SYS_I2C_MXC
  1178 + setup_i2c(0, CONFIG_SYS_I2C_SPEED,
  1179 + 0x50, &i2c_pad_info1);
  1180 + setup_i2c(2, CONFIG_SYS_I2C_SPEED,
  1181 + 0x70, &i2c_pad_info3);
  1182 +
  1183 + /* Configure I2C switch (PCA9546) to enable channel 0. */
  1184 + i2c_set_bus_num(2);
  1185 + uint8_t i2cbuf;
  1186 + i2cbuf = CONFIG_SYS_I2C_PCA9546_ENABLE;
  1187 + if (i2c_write(CONFIG_SYS_I2C_PCA9546_ADDR, 0,
  1188 + CONFIG_SYS_I2C_PCA9546_ADDR_LEN, &i2cbuf, 1)) {
  1189 + printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9546_ADDR);
  1190 + return 1;
  1191 + }
  1192 +
  1193 +#endif
  1194 + return 0;
  1195 +}
  1196 +
  1197 +#ifdef CONFIG_CMD_BMODE
  1198 +static const struct boot_mode board_boot_modes[] = {
  1199 + /* 4 bit bus width */
  1200 + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  1201 + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  1202 + /* 8 bit bus width */
  1203 + {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  1204 + {NULL, 0},
  1205 +};
  1206 +#endif
  1207 +
  1208 +int board_late_init(void)
  1209 +{
  1210 + // Make sure we enable ECSPI2 clock
  1211 + int reg;
  1212 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1213 + reg = readl(&mxc_ccm->CCGR1);
  1214 + reg |= MXC_CCM_CCGR1_ECSPI2S_MASK;
  1215 + writel(reg, &mxc_ccm->CCGR1);
  1216 +#ifdef CONFIG_CMD_BMODE
  1217 + add_board_boot_modes(board_boot_modes);
  1218 +#endif
  1219 +
  1220 +#ifdef CONFIG_ENV_IS_IN_MMC
  1221 + board_late_mmc_env_init();
  1222 +#endif
  1223 + return 0;
  1224 +}
  1225 +
  1226 +int checkboard(void)
  1227 +{
  1228 + puts("Board: SMARC-FiMX6 Rev.00A0\n");
  1229 + return 0;
  1230 +}
  1231 +
  1232 +#ifdef CONFIG_FASTBOOT
  1233 +
  1234 +void board_fastboot_setup(void)
  1235 +{
  1236 + switch (get_boot_device()) {
  1237 +#if defined(CONFIG_FASTBOOT_STORAGE_SATA)
  1238 + case SATA_BOOT:
  1239 + if (!getenv("fastboot_dev"))
  1240 + setenv("fastboot_dev", "sata");
  1241 + if (!getenv("bootcmd"))
  1242 + setenv("bootcmd", "booti sata");
  1243 + break;
  1244 +#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
  1245 +#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
  1246 + case SD2_BOOT:
  1247 + case MMC2_BOOT:
  1248 + if (!getenv("fastboot_dev"))
  1249 + setenv("fastboot_dev", "mmc0");
  1250 + if (!getenv("bootcmd"))
  1251 + setenv("bootcmd", "booti mmc0");
  1252 + break;
  1253 + case SD3_BOOT:
  1254 + case MMC3_BOOT:
  1255 + if (!getenv("fastboot_dev"))
  1256 + setenv("fastboot_dev", "mmc1");
  1257 + if (!getenv("bootcmd"))
  1258 + setenv("bootcmd", "booti mmc1");
  1259 + break;
  1260 + case MMC4_BOOT:
  1261 + if (!getenv("fastboot_dev"))
  1262 + setenv("fastboot_dev", "mmc2");
  1263 + if (!getenv("bootcmd"))
  1264 + setenv("bootcmd", "booti mmc2");
  1265 + break;
  1266 +#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
  1267 + default:
  1268 + printf("unsupported boot devices\n");
  1269 + break;
  1270 + }
  1271 +
  1272 +}
  1273 +
  1274 +#ifdef CONFIG_ANDROID_RECOVERY
  1275 +
  1276 +#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)
  1277 +iomux_v3_cfg_t const recovery_key_pads[] = {
  1278 + (MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  1279 +};
  1280 +
  1281 +int check_recovery_cmd_file(void)
  1282 +{
  1283 + int button_pressed = 0;
  1284 + int recovery_mode = 0;
  1285 +
  1286 + recovery_mode = recovery_check_and_clean_flag();
  1287 +
  1288 + /* Check Recovery Combo Button press or not. */
  1289 + imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
  1290 + ARRAY_SIZE(recovery_key_pads));
  1291 +
  1292 + gpio_direction_input(GPIO_VOL_DN_KEY);
  1293 +
  1294 + if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */
  1295 + button_pressed = 1;
  1296 + printf("Recovery key pressed\n");
  1297 + }
  1298 +
  1299 + return recovery_mode || button_pressed;
  1300 +}
  1301 +
  1302 +void board_recovery_setup(void)
  1303 +{
  1304 + int bootdev = get_boot_device();
  1305 +
  1306 + switch (bootdev) {
  1307 +#if defined(CONFIG_FASTBOOT_STORAGE_SATA)
  1308 + case SATA_BOOT:
  1309 + if (!getenv("bootcmd_android_recovery"))
  1310 + setenv("bootcmd_android_recovery",
  1311 + "booti sata recovery");
  1312 + break;
  1313 +#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
  1314 +#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
  1315 + case SD2_BOOT:
  1316 + case MMC2_BOOT:
  1317 + if (!getenv("bootcmd_android_recovery"))
  1318 + setenv("bootcmd_android_recovery",
  1319 + "booti mmc0 recovery");
  1320 + break;
  1321 + case SD3_BOOT:
  1322 + case MMC3_BOOT:
  1323 + if (!getenv("bootcmd_android_recovery"))
  1324 + setenv("bootcmd_android_recovery",
  1325 + "booti mmc1 recovery");
  1326 + break;
  1327 + case MMC4_BOOT:
  1328 + if (!getenv("bootcmd_android_recovery"))
  1329 + setenv("bootcmd_android_recovery",
  1330 + "booti mmc2 recovery");
  1331 + break;
  1332 +#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
  1333 + default:
  1334 + printf("Unsupported bootup device for recovery: dev: %d\n",
  1335 + bootdev);
  1336 + return;
  1337 + }
  1338 +
  1339 + printf("setup env for recovery..\n");
  1340 + setenv("bootcmd", "run bootcmd_android_recovery");
  1341 +}
  1342 +
  1343 +#endif /*CONFIG_ANDROID_RECOVERY*/
  1344 +
  1345 +#endif /*CONFIG_FASTBOOT*/
  1346 +
  1347 +#ifdef CONFIG_IMX_UDC
  1348 +iomux_v3_cfg_t const otg_udc_pads[] = {
  1349 + (MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
  1350 +};
  1351 +void udc_pins_setting(void)
  1352 +{
  1353 + imx_iomux_v3_setup_multiple_pads(otg_udc_pads,
  1354 + ARRAY_SIZE(otg_udc_pads));
  1355 +
  1356 + /*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/
  1357 + mxc_iomux_set_gpr_register(1, 13, 1, 0);
  1358 +}
  1359 +#endif /*CONFIG_IMX_UDC*/
  1360 +
  1361 +#ifdef CONFIG_USB_EHCI_MX6
  1362 +iomux_v3_cfg_t const usb_otg_pads[] = {
  1363 + MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  1364 + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
  1365 +};
  1366 +
  1367 +iomux_v3_cfg_t const usb_hc1_pads[] = {
  1368 + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  1369 +};
  1370 +
  1371 +int board_ehci_hcd_init(int port)
  1372 +{
  1373 + switch (port) {
  1374 + case 0:
  1375 + imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
  1376 + ARRAY_SIZE(usb_otg_pads));
  1377 +
  1378 + /*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/
  1379 + mxc_iomux_set_gpr_register(1, 13, 1, 0);
  1380 + break;
  1381 + case 1:
  1382 + imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
  1383 + ARRAY_SIZE(usb_hc1_pads));
  1384 + break;
  1385 + default:
  1386 + printf("MXC USB port %d not yet supported\n", port);
  1387 + return 1;
  1388 + }
  1389 + return 0;
  1390 +}
  1391 +
  1392 +int board_ehci_power(int port, int on)
  1393 +{
  1394 + switch (port) {
  1395 + case 0:
  1396 + break;
  1397 + case 1:
  1398 + if (on){
  1399 + gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
  1400 + gpio_direction_input(IMX_GPIO_NR(1, 30));
  1401 + }
  1402 + else
  1403 + gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
  1404 + break;
  1405 + default:
  1406 + printf("MXC USB port %d not yet supported\n", port);
  1407 + return 1;
  1408 + }
  1409 + return 0;
  1410 +}
  1411 +#endif
board/embedian/smarcfimx6/smarcfimx6.h
Diff comments   View file @ e29075c
  1 +/*
  2 + * smarcfimx6.h
  3 + *
  4 + * Embedian SMARC-FiMX6 boards information header
  5 + *
  6 + * Copyright (C) 2015, Embedian, Inc. - http://www.embedian.com/
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#ifndef _SMARCFIMX6_H_
  12 +#define _SMARCFIMX6_H_
  13 +
  14 +/*
  15 +* SMARC-FiMX6 Config held in module eeprom device.
  16 +*
  17 +* Header Format
  18 +*
  19 +* Name Size Contents
  20 +* (Bytes)
  21 +*-------------------------------------------------------------
  22 +* Header 4 0xAA, 0x55, 0x33, 0xEE
  23 +*
  24 +* Board Name 8 Name for board in ASCII.
  25 +* example "FIMX6Q1G" = "SMARC-FiMX6
  26 +* Quad Core and 1GB DDR3 memory"
  27 +*
  28 +* Version 4 Hardware version code for board in
  29 +* in ASCII. "00A0" = rev.0A
  30 +* Serial Number 12 Serial number of the board. This is a 12
  31 +* character string which is: WWYYMSkknnnn, where
  32 +* WW = 2 digit week of the year of production
  33 +* YY = 2 digit year of production
  34 +* kk = 2 digit module variants
  35 +* nnnn = incrementing board number
  36 +* Configuration Option 32 Codes to show the configuration
  37 +* setup on this board.
  38 +* MAC Address (LAN1) MAC Address for FEC controller
  39 +* MAC Address (LAN2, if any) MAC Address for 2nd LAN (if any)
  40 +* Available 32700 Available space for other non-volatile
  41 +* codes/data
  42 +*/
  43 +
  44 +#define HDR_NO_OF_MAC_ADDR 3
  45 +#define HDR_ETH_ALEN 6
  46 +#define HDR_NAME_LEN 8
  47 +
  48 +struct smarcfimx6_id {
  49 + unsigned int magic;
  50 + char name[HDR_NAME_LEN];
  51 + char version[4];
  52 + char serial[12];
  53 + char config[32];
  54 + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
  55 +};
  56 +
  57 +static inline int board_is_fimx6slo(struct smarcfimx6_id *header)
  58 +{
  59 + return !strncmp(header->name, "SMCMXSLO", HDR_NAME_LEN);
  60 +}
  61 +
  62 +static inline int board_is_fimx6u1g(struct smarcfimx6_id *header)
  63 +{
  64 + return !strncmp(header->name, "SMCMXU1G", HDR_NAME_LEN);
  65 +}
  66 +
  67 +static inline int board_is_fimx6d1g(struct smarcfimx6_id *header)
  68 +{
  69 + return !strncmp(header->name, "SMCMXD1G", HDR_NAME_LEN);
  70 +}
  71 +
  72 +static inline int board_is_fimx6d2g(struct smarcfimx6_id *header)
  73 +{
  74 + return !strncmp(header->name, "SMCMXD2G", HDR_NAME_LEN);
  75 +}
  76 +
  77 +static inline int board_is_fimx6q1g(struct smarcfimx6_id *header)
  78 +{
  79 + return !strncmp(header->name, "SMCMXQ1G", HDR_NAME_LEN);
  80 +}
  81 +
  82 +static inline int board_is_fimx6q2g(struct smarcfimx6_id *header)
  83 +{
  84 + return !strncmp(header->name, "SMCMXQ2G", HDR_NAME_LEN);
  85 +}
  86 +
  87 +/*
  88 + * Read ethernet MAC address from EEPROM for SMARC-FiMX6DVEVM compatible boards.
  89 + * Returns 1 if found, 0 otherwise.
  90 + */
  91 +int smarcfimx6_read_mac_address(uint8_t *buf)
  92 +{
  93 +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
  94 + /* Read MAC address. */
  95 + i2c_set_bus_num(0);
  96 + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x3C,
  97 + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
  98 + goto i2cerr;
  99 +
  100 + /* Check that MAC address is valid. */
  101 + if (!is_valid_ether_addr(buf))
  102 + goto err;
  103 +
  104 + return 1; /* Found */
  105 +
  106 +i2cerr:
  107 + printf("Read from EEPROM @ 0x%02x failed\n",
  108 + CONFIG_SYS_I2C_EEPROM_ADDR);
  109 +err:
  110 +#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
  111 +
  112 + return 0;
  113 +}
  114 +
  115 +/*
  116 + * If there is no MAC address in the environment, then it will be initialized
  117 + * (silently) from the value in the EEPROM.
  118 + */
  119 +void smarcfimx6_sync_env_enetaddr(uint8_t *rom_enetaddr)
  120 +{
  121 + uint8_t env_enetaddr[6];
  122 + int ret;
  123 +
  124 + ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
  125 + if (!ret) {
  126 + /*
  127 + * There is no MAC address in the environment, so we
  128 + * initialize it from the value in the EEPROM.
  129 + */
  130 + debug("### Setting environment from EEPROM MAC address = "
  131 + "\"%pM\"\n",
  132 + env_enetaddr);
  133 + ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr);
  134 + }
  135 + if (!ret)
  136 + printf("Failed to set mac address from EEPROM: %d\n", ret);
  137 +}
  138 +
  139 +#endif
... ... @@ -351,6 +351,27 @@
351 351 Active arm armv7 mx6 freescale mx6slevk mx6slevkandroid mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_USE_SPINOR,ANDROID_SUPPORT Fabio Estevam <fabio.estevam@freescale.com>
352 352  
353 353 Active arm armv7 mx6 freescale mx6slevk mx6slevk_spinor mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR Fabio Estevam <fabio.estevam@freescale.com>
  354 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_dl_1g_ser0 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg,MX6DL,SER0,DDR_MB=1024,SYS_USE_SPINOR Eric Lee <eric.lee@embedian.com>
  355 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_dl_1g_ser1 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg,MX6DL,SER1,DDR_MB=1024,SYS_USE_SPINORi Eric Lee <eric.lee@embedian.com>
  356 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_dl_1g_ser2 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg,MX6DL,SER2,DDR_MB=1024,SYS_USE_SPINOR Eric Lee <eric.lee@embedian.com>
  357 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_dl_1g_ser3 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg,MX6DL,SER3,DDR_MB=1024,SYS_USE_SPINOR Eric Lee <eric.lee@embedian.com>
  358 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_dl_android smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg,MX6DL,DDR_MB=1024,SYS_USE_SPINOR,ANDROID_SUPPORT Eric Lee <eric.lee@embedian.com>
  359 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_dl_android smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg,MX6DL,DDR_MB=1024,SYS_USE_SPINOR,ANDROID_SUPPORT Eric Lee <eric.lee@embedian.com>
  360 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_1g_ser0 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg,MX6Q,SER0,DDR_MB=1024,SYS_USE_SPINOR Eric Lee <eric.lee@embedian.com>
  361 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_1g_ser1 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg,MX6Q,SER1,DDR_MB=1024,SYS_USE_SPINOR Eric Lee <eric.lee@embedian.com>
  362 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_1g_ser2 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg,MX6Q,SER2,DDR_MB=1024,SYS_USE_SPINOR Eric Lee <eric.lee@embedian.com>
  363 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_1g_ser3 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg,MX6Q,SER3,DDR_MB=1024,SYS_USE_SPINOR Eric Lee <eric.lee@embedian.com>
  364 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_1g_android smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg,MX6Q,DDR_MB=1024,SYS_USE_SPINOR,ANDROID_SUPPORT Eric Lee <eric.lee@embedian.com>
  365 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_2g_ser0 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg,MX6Q,SER0,DDR_MB=1024,SYS_USE_SPINOR Eric Lee <eric.lee@embedian.com>
  366 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_2g_ser1 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg,MX6Q,SER1,DDR_MB=1024,SYS_USE_SPINOR Eric Lee <eric.lee@embedian.com>
  367 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_2g_ser2 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg,MX6Q,SER2,DDR_MB=1024,SYS_USE_SPINOR Eric Lee <eric.lee@embedian.com>
  368 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_2g_ser3 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg,MX6Q,SER3,DDR_MB=1024,SYS_USE_SPINOR Eric Lee <eric.lee@embedian.com>
  369 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_2g_android smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg,MX6Q,DDR_MB=1024,SYS_USE_SPINOR,ANDROID_SUPPORT Eric Lee <eric.lee@embedian.com>
  370 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_solo_ser0 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg,MX6SOLO,SER0,DDR_MB=512,SYS_USE_SPINOR,SYS_NOSMP="nosmp" Eric Lee <eric.lee@embedian.com>
  371 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_solo_ser1 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg,MX6SOLO,SER1,DDR_MB=512,SYS_USE_SPINOR,SYS_NOSMP="nosmp" Eric Lee <eric.lee@embedian.com>
  372 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_solo_ser2 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg,MX6SOLO,SER2,DDR_MB=512,SYS_USE_SPINOR,SYS_NOSMP="nosmp" Eric Lee <eric.lee@embedian.com>
  373 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_solo_ser3 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg,MX6SOLO,SER3,DDR_MB=512,SYS_USE_SPINOR,SYS_NOSMP="nosmp" Eric Lee <eric.lee@embedian.com>
  374 +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_solo_android smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg,MX6SOLO,DDR_MB=512,SYS_USE_SPINOR,SYS_NOSMP="nosmp",ANDROID_SUPPORT Eric Lee <eric.lee@embedian.com>
354 375 Active arm armv7 mx6 freescale mx6sx_17x17_arm2 mx6sx_17x17_arm2 mx6sx_17x17_arm2:IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg,MX6SX,DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb" Fabio Estevam <fabio.estevam@freescale.com>
355 376 Active arm armv7 mx6 freescale mx6sx_17x17_arm2 mx6sx_14x14_lpddr2_arm2 mx6sx_17x17_arm2:IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg,MX6SX,MX6SX_14x14,LPDDR2,DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb" Fabio Estevam <fabio.estevam@freescale.com>
356 377 Active arm armv7 mx6 freescale mx6sx_17x17_arm2 mx6sx_14x14_lpddr2_arm2_nand mx6sx_17x17_arm2:IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg,MX6SX,MX6SX_14x14,LPDDR2,DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb",SYS_BOOT_NAND Fabio Estevam <fabio.estevam@freescale.com>
drivers/i2c/i2c_core.c
Diff comments   View file @ e29075c
... ... @@ -127,6 +127,11 @@
127 127 return -1;
128 128 buf = (uint8_t)((channel & 0x03) | (1 << 2));
129 129 break;
  130 + case I2C_MUX_PCA9546_ID:
  131 + if (channel > 4)
  132 + return -1;
  133 + buf = (uint8_t)((channel & 0x04) | (1 << 3));
  134 + break;
130 135 case I2C_MUX_PCA9547_ID:
131 136 if (channel > 7)
132 137 return -1;
... ... @@ -238,8 +238,8 @@
238 238  
239 239 if ((start + blkcnt) > mmc->block_dev.lba) {
240 240 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
241   - printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
242   - start + blkcnt, mmc->block_dev.lba);
  241 + /*printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
  242 + start + blkcnt, mmc->block_dev.lba);*/
243 243 #endif
244 244 return 0;
245 245 }
... ... @@ -963,6 +963,9 @@
963 963 case 6:
964 964 mmc->version = MMC_VERSION_4_5;
965 965 break;
  966 + case 7:
  967 + mmc->version = MMC_VERSION_5_0;
  968 + break;
966 969 }
967 970  
968 971 /*
drivers/mtd/spi/sf_params.c
Diff comments   View file @ e29075c
... ... @@ -40,6 +40,7 @@
40 40 {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
41 41 {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
42 42 {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
  43 + {"MX25U3235F", 0xc22536, 0x0, 64 * 1024, 64, 0, SECT_4K},
43 44 {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
44 45 {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP},
45 46 {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP},
include/configs/smarcfimx6.h
Diff comments   View file @ e29075c
  1 +/*
  2 + * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * Configuration settings for the Freescale i.MX6Q SabreSD board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __SMARCFIMX6_CONFIG_H
  10 +#define __SMARCFIMX6_CONFIG_H
  11 +
  12 +#include <asm/arch/imx-regs.h>
  13 +#include <asm/imx-common/gpio.h>
  14 +
  15 +#define CONFIG_MACH_TYPE_SMARCFIMX6 3990 /*Until the next sync */
  16 +#define CONFIG_MACH_TYPE MACH_TYPE_SMARCFIMX6
  17 +#if defined(CONFIG_SER0)
  18 +#define CONFIG_MXC_UART_BASE UART1_BASE
  19 +#define CONFIG_CONSOLE_DEV "ttymxc0"
  20 +#endif
  21 +#if defined(CONFIG_SER1)
  22 +#define CONFIG_MXC_UART_BASE UART2_BASE
  23 +#define CONFIG_CONSOLE_DEV "ttymxc1"
  24 +#endif
  25 +#if defined(CONFIG_SER2)
  26 +#define CONFIG_MXC_UART_BASE UART4_BASE
  27 +#define CONFIG_CONSOLE_DEV "ttymxc3"
  28 +#endif
  29 +#if defined(CONFIG_SER3)
  30 +#define CONFIG_MXC_UART_BASE UART5_BASE
  31 +#define CONFIG_CONSOLE_DEV "ttymxc4"
  32 +#endif
  33 +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* SDHC3 */
  34 +
  35 +#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6SOLO)
  36 +#define CONFIG_DEFAULT_FDT_FILE "imx6dl-smarcfimx6.dtb"
  37 +#elif defined(CONFIG_MX6Q)
  38 +#define CONFIG_DEFAULT_FDT_FILE "imx6q-smarcfimx6.dtb"
  39 +#endif
  40 +
  41 +#include "smarcfimx6_common.h"
  42 +
  43 +/* USB Configs */
  44 +#define CONFIG_CMD_USB
  45 +#define CONFIG_USB_EHCI
  46 +#define CONFIG_USB_EHCI_MX6
  47 +#define CONFIG_USB_STORAGE
  48 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  49 +#define CONFIG_USB_HOST_ETHER
  50 +#define CONFIG_USB_ETHER_ASIX
  51 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  52 +#define CONFIG_MXC_USB_FLAGS 0
  53 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
  54 +
  55 +#define CONFIG_SYS_FSL_USDHC_NUM 3
  56 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* 0 SDHC, 1 SDMMC, 2 eMMC */
  57 +#define CONFIG_SYS_MMC_ENV_PART 2 /* user partition */
  58 +
  59 +#ifdef CONFIG_SYS_USE_SPINOR
  60 +#define CONFIG_SF_DEFAULT_CS (1|(IMX_GPIO_NR(5, 29)<<8)) /* Use SPI2 SS0 as chip select */
  61 +#endif
  62 +
  63 +/*
  64 + * imx6 q/dl/solo pcie would be failed to work properly in kernel, if
  65 + * the pcie module is iniialized/enumerated both in uboot and linux
  66 + * kernel.
  67 + * rootcause:imx6 q/dl/solo pcie don't have the reset mechanism.
  68 + * it is only be RESET by the POR. So, the pcie module only be
  69 + * initialized/enumerated once in one POR.
  70 + * Set to use pcie in kernel defaultly, mask the pcie config here.
  71 + * Remove the mask freely, if the uboot pcie functions, rather than
  72 + * the kernel's, are required.
  73 + */
  74 +/* #define CONFIG_CMD_PCI */
  75 +#ifdef CONFIG_CMD_PCI
  76 +#define CONFIG_PCI
  77 +#define CONFIG_PCI_PNP
  78 +#define CONFIG_PCI_SCAN_SHOW
  79 +#define CONFIG_PCIE_IMX
  80 +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(1, 20)
  81 +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 17)
  82 +#endif
  83 +
  84 +/*#define CONFIG_SPLASH_SCREEN*/
  85 +/*#define CONFIG_MXC_EPDC*/
  86 +
  87 +/*
  88 + * SPLASH SCREEN Configs
  89 + */
  90 +#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC)
  91 + /*
  92 + * Framebuffer and LCD
  93 + */
  94 + #define CONFIG_CMD_BMP
  95 + #define CONFIG_LCD
  96 + #define CONFIG_FB_BASE (CONFIG_SYS_TEXT_BASE + 0x300000)
  97 + #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  98 + #undef LCD_TEST_PATTERN
  99 + /* #define CONFIG_SPLASH_IS_IN_MMC 1 */
  100 + #define LCD_BPP LCD_MONOCHROME
  101 + /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
  102 +
  103 + #define CONFIG_WORKING_BUF_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
  104 + #define CONFIG_WAVEFORM_BUF_ADDR (CONFIG_SYS_TEXT_BASE + 0x200000)
  105 + #define CONFIG_WAVEFORM_FILE_OFFSET 0x600000
  106 + #define CONFIG_WAVEFORM_FILE_SIZE 0xF0A00
  107 + #define CONFIG_WAVEFORM_FILE_IN_MMC
  108 +
  109 +#ifdef CONFIG_SPLASH_IS_IN_MMC
  110 + #define CONFIG_SPLASH_IMG_OFFSET 0x4c000
  111 + #define CONFIG_SPLASH_IMG_SIZE 0x19000
  112 +#endif
  113 +#endif /* CONFIG_SPLASH_SCREEN && CONFIG_MXC_EPDC */
  114 +
  115 +#endif /* __SMARCFIMX6_CONFIG_H */
include/configs/smarcfimx6_common.h
Diff comments   View file @ e29075c
  1 +/*
  2 + * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * Configuration settings for the Freescale i.MX6Q SabreSD board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __SMARCFIMX6_COMMON_CONFIG_H
  10 +#define __SMARCFIMX6_COMMON_CONFIG_H
  11 +
  12 +#define CONFIG_MX6
  13 +
  14 +#ifdef CONFIG_MX6SOLO
  15 +#define CONFIG_MX6DL
  16 +#endif
  17 +
  18 +/* uncomment for PLUGIN mode support */
  19 +/* #define CONFIG_USE_PLUGIN */
  20 +
  21 +/* uncomment for SECURE mode support */
  22 +/* #define CONFIG_SECURE_BOOT */
  23 +
  24 +#include "mx6_common.h"
  25 +#include <linux/sizes.h>
  26 +
  27 +#define CONFIG_SYS_GENERIC_BOARD
  28 +#define CONFIG_DISPLAY_CPUINFO
  29 +#define CONFIG_DISPLAY_BOARDINFO
  30 +
  31 +#include <asm/arch/imx-regs.h>
  32 +#include <asm/imx-common/gpio.h>
  33 +
  34 +#define CONFIG_CMDLINE_TAG
  35 +#define CONFIG_SETUP_MEMORY_TAGS
  36 +#define CONFIG_INITRD_TAG
  37 +#define CONFIG_REVISION_TAG
  38 +
  39 +/* Size of malloc() pool */
  40 +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
  41 +
  42 +#define CONFIG_BOARD_EARLY_INIT_F
  43 +#define CONFIG_BOARD_LATE_INIT
  44 +#define CONFIG_MXC_GPIO
  45 +
  46 +#define CONFIG_MXC_UART
  47 +
  48 +#define CONFIG_CMD_FUSE
  49 +#ifdef CONFIG_CMD_FUSE
  50 +#define CONFIG_MXC_OCOTP
  51 +#endif
  52 +
  53 +/* MMC Configs */
  54 +#define CONFIG_FSL_ESDHC
  55 +#define CONFIG_FSL_USDHC
  56 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  57 +
  58 +#define CONFIG_MMC
  59 +#define CONFIG_CMD_MMC
  60 +#define CONFIG_GENERIC_MMC
  61 +#define CONFIG_BOUNCE_BUFFER
  62 +#define CONFIG_FS_FAT
  63 +#define CONFIG_FS_EXT4
  64 +#define CONFIG_EXT4_WRITE
  65 +#define CONFIG_CMD_EXT2
  66 +#define CONFIG_CMD_FAT
  67 +#define CONFIG_CMD_EXT4
  68 +#define CONFIG_CMD_EXT4_WRITE
  69 +#define CONFIG_CMD_PART
  70 +#define CONFIG_HOST_MAX_DEVICES 4
  71 +#define CONFIG_CMD_FS_GENERIC
  72 +#define CONFIG_DOS_PARTITION
  73 +#define CONFIG_PARTITION_UUIDS
  74 +
  75 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
  76 +
  77 +#define CONFIG_CMD_PING
  78 +#define CONFIG_CMD_DHCP
  79 +#define CONFIG_CMD_MII
  80 +#define CONFIG_CMD_NET
  81 +#define CONFIG_FEC_MXC
  82 +#define CONFIG_MII
  83 +#define IMX_FEC_BASE ENET_BASE_ADDR
  84 +#define CONFIG_FEC_XCV_TYPE RGMII
  85 +#define CONFIG_ETHPRIME "FEC"
  86 +#define CONFIG_FEC_MXC_PHYADDR 6
  87 +
  88 +#define CONFIG_PHYLIB
  89 +#define CONFIG_PHY_ATHEROS
  90 +
  91 +/* allow to overwrite serial and ethaddr */
  92 +#define CONFIG_ENV_OVERWRITE
  93 +#define CONFIG_CONS_INDEX 1
  94 +#define CONFIG_BAUDRATE 115200
  95 +
  96 +/* Command definition */
  97 +#include <config_cmd_default.h>
  98 +
  99 +#define CONFIG_CMD_BMODE
  100 +#define CONFIG_CMD_BOOTZ
  101 +#define CONFIG_SUPPORT_RAW_INITRD
  102 +#define CONFIG_CMD_SETEXPR
  103 +#undef CONFIG_CMD_IMLS
  104 +
  105 +#define CONFIG_BOOTDELAY 1
  106 +
  107 +#define CONFIG_LOADADDR 0x12000000
  108 +#define CONFIG_SYS_TEXT_BASE 0x17800000
  109 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  110 +
  111 +#ifdef CONFIG_SYS_BOOT_NAND
  112 +#define CONFIG_MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs) "
  113 +#else
  114 +#define CONFIG_MFG_NAND_PARTITION ""
  115 +#endif
  116 +
  117 +#define CONFIG_MFG_ENV_SETTINGS \
  118 + "mfgtool_args=setenv bootargs console=" CONFIG_CONSOLE_DEV ",115200 " \
  119 + "rdinit=/linuxrc " \
  120 + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  121 + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  122 + "g_mass_storage.iSerialNumber=\"\" "\
  123 + "enable_wait_mode=off "\
  124 + CONFIG_MFG_NAND_PARTITION \
  125 + "\0" \
  126 + "initrd_addr=0x12C00000\0" \
  127 + "initrd_high=0xffffffff\0" \
  128 + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  129 +
  130 +#if defined(CONFIG_SYS_BOOT_NAND)
  131 + /*
  132 + * The dts also enables the WEIN NOR which is mtd0.
  133 + * So the partions' layout for NAND is:
  134 + * mtd1: 16M (uboot)
  135 + * mtd2: 16M (kernel)
  136 + * mtd3: 16M (dtb)
  137 + * mtd4: left (rootfs)
  138 + */
  139 +#define CONFIG_EXTRA_ENV_SETTINGS \
  140 + CONFIG_MFG_ENV_SETTINGS \
  141 + "fdt_addr=0x18000000\0" \
  142 + "fdt_high=0xffffffff\0" \
  143 + "bootargs=console=" CONFIG_CONSOLE_DEV ",115200 ubi.mtd=4 " \
  144 + "root=ubi0:rootfs rootfstype=ubifs " \
  145 + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\
  146 + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
  147 + "nand read ${fdt_addr} 0x5000000 0x100000;"\
  148 + "bootz ${loadaddr} - ${fdt_addr}\0"
  149 +
  150 +#elif defined(CONFIG_SYS_BOOT_SATA)
  151 +
  152 +#define CONFIG_EXTRA_ENV_SETTINGS \
  153 + CONFIG_MFG_ENV_SETTINGS \
  154 + "fdt_addr=0x18000000\0" \
  155 + "fdt_high=0xffffffff\0" \
  156 + "bootargs=console=" CONFIG_CONSOLE_DEV ",115200 \0"\
  157 + "bootargs_sata=setenv bootargs ${bootargs} " \
  158 + "root=/dev/sda1 rootwait rw \0" \
  159 + "bootcmd_sata=run bootargs_sata; sata init; " \
  160 + "sata read ${loadaddr} 0x800 0x4000; " \
  161 + "sata read ${fdt_addr} 0x8000 0x800; " \
  162 + "bootz ${loadaddr} - ${fdt_addr} \0" \
  163 + "bootcmd=run bootcmd_sata \0"
  164 +
  165 +#else
  166 +#define CONFIG_EXTRA_ENV_SETTINGS \
  167 + CONFIG_MFG_ENV_SETTINGS \
  168 + "script=boot.scr\0" \
  169 + "image=zImage\0" \
  170 + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
  171 + "fdt_addr=0x18000000\0" \
  172 + "ethprime=FEC0\0" \
  173 + "fec.macaddr=${ethaddr}\0" \
  174 + "ipaddr=192.168.1.60\0" \
  175 + "boot_fdt=try\0" \
  176 + "ip_dyn=yes\0" \
  177 + "console=" CONFIG_CONSOLE_DEV "\0" \
  178 + "fdt_high=0xffffffff\0" \
  179 + "initrd_high=0xffffffff\0" \
  180 + "optargs= fec.macaddr=${ethaddr}\0" \
  181 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  182 + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  183 + "mmcroot=" CONFIG_MMCROOT " rootwait ro\0" \
  184 + "mmcrootfstype=ext4 rootwait\0" \
  185 + "mmcautodetect=yes\0" \
  186 + "update_sd_firmware=" \
  187 + "if test ${ip_dyn} = yes; then " \
  188 + "setenv get_cmd dhcp; " \
  189 + "else " \
  190 + "setenv get_cmd tftp; " \
  191 + "fi; " \
  192 + "if mmc dev ${mmcdev}; then " \
  193 + "if ${get_cmd} ${update_sd_firmware_filename}; then " \
  194 + "setexpr fw_sz ${filesize} / 0x200; " \
  195 + "setexpr fw_sz ${fw_sz} + 1; " \
  196 + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
  197 + "fi; " \
  198 + "fi\0" \
  199 + "smp=" CONFIG_SYS_NOSMP "\0"\
  200 + "mmcargs=setenv bootargs console=${console},${baudrate} ${smp} " \
  201 + "${optargs} " \
  202 + "root=${mmcroot}\0" \
  203 + "rootfstype=${mmcrootfstype} " \
  204 + "video=${video}\0" \
  205 + "loadbootenv=load mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \
  206 + "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \
  207 + "env import -t $loadaddr $filesize\0" \
  208 + "loadbootscript=" \
  209 + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  210 + "bootscript=echo Running bootscript from mmc ...; " \
  211 + "source\0" \
  212 + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  213 + "loadzimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  214 + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \
  215 + "mmcboot=echo Booting from mmc ...; " \
  216 + "run mmcargs; " \
  217 + "bootz ${loadaddr} - ${fdt_addr};\0" \
  218 + "mmcbootdefault=echo Booting from mmc ...; " \
  219 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  220 + "if run loadfdt; then " \
  221 + "bootz ${loadaddr} - ${fdt_addr}; " \
  222 + "else " \
  223 + "if test ${boot_fdt} = try; then " \
  224 + "bootz ${loadaddr}; " \
  225 + "else " \
  226 + "echo WARN: Cannot load the DT; " \
  227 + "fi; " \
  228 + "fi; " \
  229 + "else " \
  230 + "bootz ${loadaddr}; " \
  231 + "fi;\0" \
  232 + "netargs=setenv bootargs console=${console},${baudrate} ${smp} " \
  233 + "root=/dev/nfs " \
  234 + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  235 + "netboot=echo Booting from net ...; " \
  236 + "run netargs; " \
  237 + "if test ${ip_dyn} = yes; then " \
  238 + "setenv get_cmd dhcp; " \
  239 + "else " \
  240 + "setenv get_cmd tftp; " \
  241 + "fi; " \
  242 + "${get_cmd} ${image}; " \
  243 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  244 + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  245 + "bootz ${loadaddr} - ${fdt_addr}; " \
  246 + "else " \
  247 + "if test ${boot_fdt} = try; then " \
  248 + "bootz; " \
  249 + "else " \
  250 + "echo WARN: Cannot load the DT; " \
  251 + "fi; " \
  252 + "fi; " \
  253 + "else " \
  254 + "bootz; " \
  255 + "fi;\0"
  256 +
  257 +#define CONFIG_BOOTCOMMAND \
  258 + "mmc dev ${mmcdev};" \
  259 + "if mmc rescan; then " \
  260 + "echo SD/MMC found on device ${mmcdev};" \
  261 + "if run loadbootenv; then " \
  262 + "run importbootenv;" \
  263 + "fi;" \
  264 + "echo Checking if uenvcmd is set ...;" \
  265 + "if test -n $uenvcmd; then " \
  266 + "echo Running uenvcmd ...;" \
  267 + "run uenvcmd;" \
  268 + "fi;" \
  269 + "echo Running default loadzimage ...;" \
  270 + "if run loadzimage; then " \
  271 + "run loadfdt;" \
  272 + "run mmcboot;" \
  273 + "fi;" \
  274 + "else run netboot; fi"
  275 +#endif
  276 +
  277 +#define CONFIG_ARP_TIMEOUT 200UL
  278 +
  279 +/* Miscellaneous configurable options */
  280 +#define CONFIG_SYS_LONGHELP
  281 +#define CONFIG_SYS_HUSH_PARSER
  282 +#define CONFIG_SYS_PROMPT "# "
  283 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  284 +#define CONFIG_AUTO_COMPLETE
  285 +#define CONFIG_SYS_CBSIZE 1024
  286 +
  287 +/* Print Buffer Size */
  288 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  289 +#define CONFIG_SYS_MAXARGS 256
  290 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  291 +
  292 +#define CONFIG_CMD_MEMTEST
  293 +#define CONFIG_SYS_MEMTEST_START 0x10000000
  294 +#define CONFIG_SYS_MEMTEST_END 0x10010000
  295 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
  296 +
  297 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  298 +
  299 +#define CONFIG_CMDLINE_EDITING
  300 +#define CONFIG_STACKSIZE (128 * 1024)
  301 +
  302 +/* Physical Memory Map */
  303 +#define CONFIG_NR_DRAM_BANKS 1
  304 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
  305 +
  306 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
  307 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
  308 +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
  309 +
  310 +#define CONFIG_SYS_INIT_SP_OFFSET \
  311 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  312 +#define CONFIG_SYS_INIT_SP_ADDR \
  313 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  314 +
  315 +/* FLASH and environment organization */
  316 +#define CONFIG_SYS_NO_FLASH
  317 +
  318 +#define CONFIG_ENV_SIZE (8 * 1024)
  319 +
  320 +#ifndef CONFIG_SYS_NOSMP
  321 +#define CONFIG_SYS_NOSMP
  322 +#endif
  323 +
  324 +#if defined CONFIG_SYS_BOOT_SPINOR
  325 +#define CONFIG_SYS_USE_SPINOR
  326 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  327 +#elif defined CONFIG_SYS_BOOT_EIMNOR
  328 +#define CONFIG_SYS_USE_EIMNOR
  329 +#define CONFIG_ENV_IS_IN_FLASH
  330 +#elif defined CONFIG_SYS_BOOT_NAND
  331 +#define CONFIG_SYS_USE_NAND
  332 +#define CONFIG_ENV_IS_IN_NAND
  333 +#elif defined CONFIG_SYS_BOOT_SATA
  334 +#define CONFIG_ENV_IS_IN_SATA
  335 +#define CONFIG_CMD_SATA
  336 +#else
  337 +#define CONFIG_ENV_IS_IN_MMC
  338 +#endif
  339 +
  340 +#ifdef CONFIG_CMD_SATA
  341 +#define CONFIG_DWC_AHSATA
  342 +#define CONFIG_SYS_SATA_MAX_DEVICE 1
  343 +#define CONFIG_DWC_AHSATA_PORT_ID 0
  344 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
  345 +#define CONFIG_LBA48
  346 +#define CONFIG_LIBATA
  347 +#endif
  348 +
  349 +#ifdef CONFIG_SYS_USE_SPINOR
  350 +#define CONFIG_CMD_SF
  351 +#define CONFIG_CMD_SPI
  352 +#define CONFIG_SPI_FLASH
  353 +#define CONFIG_SPI_FLASH_MACRONIX
  354 +#define CONFIG_MXC_SPI
  355 +#define CONFIG_SF_DEFAULT_BUS 1
  356 +#define CONFIG_SF_DEFAULT_SPEED 12000000
  357 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
  358 +#endif
  359 +
  360 +#ifdef CONFIG_SYS_USE_EIMNOR
  361 +#undef CONFIG_SYS_NO_FLASH
  362 +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
  363 +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
  364 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  365 +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  366 +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
  367 +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
  368 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
  369 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  370 +#endif
  371 +
  372 +#ifdef CONFIG_SYS_USE_NAND
  373 +#define CONFIG_CMD_NAND
  374 +#define CONFIG_CMD_NAND_TRIMFFS
  375 +
  376 +/* NAND stuff */
  377 +#define CONFIG_NAND_MXS
  378 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  379 +#define CONFIG_SYS_NAND_BASE 0x40000000
  380 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  381 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  382 +
  383 +/* DMA stuff, needed for GPMI/MXS NAND support */
  384 +#define CONFIG_APBH_DMA
  385 +#define CONFIG_APBH_DMA_BURST
  386 +#define CONFIG_APBH_DMA_BURST8
  387 +#endif
  388 +
  389 +#if defined(CONFIG_ENV_IS_IN_MMC)
  390 +#define CONFIG_ENV_OFFSET (8 * 64 * 1024)
  391 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  392 +#define CONFIG_ENV_OFFSET (768 * 1024)
  393 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
  394 +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  395 +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  396 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
  397 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  398 +#elif defined(CONFIG_ENV_IS_IN_FLASH)
  399 +#undef CONFIG_ENV_SIZE
  400 +#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE
  401 +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE
  402 +#define CONFIG_ENV_OFFSET (4 * CONFIG_SYS_FLASH_SECT_SIZE)
  403 +#elif defined(CONFIG_ENV_IS_IN_NAND)
  404 +#undef CONFIG_ENV_SIZE
  405 +#define CONFIG_ENV_OFFSET (8 << 20)
  406 +#define CONFIG_ENV_SECT_SIZE (128 << 10)
  407 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  408 +#elif defined(CONFIG_ENV_IS_IN_SATA)
  409 +#define CONFIG_ENV_OFFSET (768 * 1024)
  410 +#define CONFIG_SATA_ENV_DEV 0
  411 +#define CONFIG_SYS_DCACHE_OFF /* remove when sata driver support cache */
  412 +#endif
  413 +
  414 +#define CONFIG_OF_LIBFDT
  415 +
  416 +#ifndef CONFIG_SYS_DCACHE_OFF
  417 +#define CONFIG_CMD_CACHE
  418 +#endif
  419 +
  420 +/*
  421 + * I2C configs
  422 + */
  423 +#define CONFIG_CMD_I2C
  424 +#define CONFIG_SYS_I2C
  425 +#define CONFIG_SYS_I2C_MXC
  426 +#define CONFIG_SYS_I2C_SPEED 100000
  427 +
  428 +/* I2C switch definitions for PCA9546 chip */
  429 +#define CONFIG_SYS_I2C_PCA9546_ADDR 0x70
  430 +#define CONFIG_SYS_I2C_PCA9546_ADDR_LEN 0 /* Single register. */
  431 +#define CONFIG_SYS_I2C_PCA9546_ENABLE 0x07 /* Enable channel 0,1,2. */
  432 +#define CONFIG_SYS_NUM_I2C_BUSES 5
  433 +#define CONFIG_SYS_I2C_MAX_HOPS 2
  434 +#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP}}, \
  435 + {1, {I2C_NULL_HOP}}, \
  436 + {2, {{I2C_MUX_PCA9546, 0x70, 1}}}, \
  437 + {2, {{I2C_MUX_PCA9546, 0x70, 2}}}, \
  438 + {2, {{I2C_MUX_PCA9546, 0x70, 3}}}, \
  439 + }
  440 +/*
  441 +* I2C EEPROM definitions EEPROM chip
  442 +*/
  443 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  444 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  445 +#define CONFIG_MAC_ADDR_IN_EEPROM
  446 +
  447 +/* Framebuffer */
  448 +#define CONFIG_VIDEO
  449 +#define CONFIG_VIDEO_IPUV3
  450 +#define CONFIG_CFB_CONSOLE
  451 +#define CONFIG_VGA_AS_SINGLE_DEVICE
  452 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  453 +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
  454 +#define CONFIG_VIDEO_BMP_RLE8
  455 +#define CONFIG_SPLASH_SCREEN
  456 +#define CONFIG_SPLASH_SCREEN_ALIGN
  457 +#define CONFIG_BMP_16BPP
  458 +#define CONFIG_VIDEO_LOGO
  459 +#define CONFIG_VIDEO_BMP_LOGO
  460 +#ifdef CONFIG_MX6DL
  461 +#define CONFIG_IPUV3_CLK 198000000
  462 +#else
  463 +#define CONFIG_IPUV3_CLK 264000000
  464 +#endif
  465 +#define CONFIG_IMX_HDMI
  466 +
  467 +#if defined(CONFIG_ANDROID_SUPPORT)
  468 +#include "mx6sabreandroid_common.h"
  469 +#endif
  470 +
  471 +#endif /* __SMARCFIMX6_COMMON_CONFIG_H */
... ... @@ -134,6 +134,8 @@
134 134 #define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"}
135 135 #define I2C_MUX_PCA9544_ID 3
136 136 #define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"}
  137 +#define I2C_MUX_PCA9546_ID 6
  138 +#define I2C_MUX_PCA9546 {I2C_MUX_PCA9546_ID, "PCA9546A"}
137 139 #define I2C_MUX_PCA9547_ID 4
138 140 #define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"}
139 141 #define I2C_MUX_PCA9548_ID 5
... ... @@ -30,6 +30,7 @@
30 30 #define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403)
31 31 #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429)
32 32 #define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405)
  33 +#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x500)
33 34  
34 35 #define MMC_MODE_HS 0x001
35 36 #define MMC_MODE_HS_52MHz 0x010