driver/ddr/fsl: Add support for multiple DDR clocks

Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>

driver/ddr/fsl: Add support for multiple DDR clocks
Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
York Sun
1 parent b87e6f88e9
Showing 14 changed files with 190 additions and 159 deletions Side-by-side Diff
drivers/ddr/fsl/arm_ddr_gen3.c
drivers/ddr/fsl/ctrl_regs.c
drivers/ddr/fsl/ddr1_dimm_params.c
drivers/ddr/fsl/ddr2_dimm_params.c
drivers/ddr/fsl/ddr3_dimm_params.c
drivers/ddr/fsl/ddr4_dimm_params.c
drivers/ddr/fsl/fsl_ddr_gen4.c
drivers/ddr/fsl/lc_common_dimm_params.c
drivers/ddr/fsl/main.c
drivers/ddr/fsl/mpc85xx_ddr_gen3.c
drivers/ddr/fsl/options.c
drivers/ddr/fsl/util.c
include/fsl_ddr.h
include/fsl_ddr_dimm_params.h
@@ -222,7 +222,7 @@
 	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
-		(get_ddr_freq(0) >> 20)) << 1;
+		(get_ddr_freq(ctrl_num) >> 20)) << 1;
 	total_gb_size_per_controller >>= 4;	/* shift down to gb size */
 	debug("total %d GB\n", total_gb_size_per_controller);
 	debug("Need to wait up to %d * 10ms\n", timeout);
@@ -17,8 +17,6 @@
 #include <fsl_immap.h>
 #include <asm/io.h>
  
-unsigned int picos_to_mclk(unsigned int picos);
-
 /*
  * Determine Rtt value.
  *
  
@@ -78,10 +76,11 @@
  *       16 for <= 2933MT/s
  *       18 for higher
  */
-static inline unsigned int compute_cas_write_latency(void)
+static inline unsigned int compute_cas_write_latency(
+				const unsigned int ctrl_num)
 {
 	unsigned int cwl;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 	if (mclk_ps >= 1250)
 		cwl = 9;
 	else if (mclk_ps >= 1070)
  
@@ -111,10 +110,11 @@
  *       11 if 0.935ns > tCK >= 0.833ns
  *       12 if 0.833ns > tCK >= 0.75ns
  */
-static inline unsigned int compute_cas_write_latency(void)
+static inline unsigned int compute_cas_write_latency(
+				const unsigned int ctrl_num)
 {
 	unsigned int cwl;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  
 	if (mclk_ps >= 2500)
 		cwl = 5;
@@ -287,7 +287,8 @@
  * Avoid writing for DDR I.  The new PQ38 DDR controller
  * dreams up non-zero default values to be backwards compatible.
  */
-static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
+static void set_timing_cfg_0(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const dimm_params_t *dimm_params)
 {
@@ -306,7 +307,7 @@
 	/* Mode register set cycle time (tMRD). */
 	unsigned char tmrd_mclk;
 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 #endif
  
 #ifdef CONFIG_SYS_FSL_DDR4
  
  
@@ -314,15 +315,15 @@
 	int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
 	trwt_mclk = 2;
 	twrt_mclk = 1;
-	act_pd_exit_mclk = picos_to_mclk(txp);
+	act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 	pre_pd_exit_mclk = act_pd_exit_mclk;
 	/*
 	 * MRS_CYC = max(tMRD, tMOD)
 	 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 	 */
-	tmrd_mclk = max(24U, picos_to_mclk(15000));
+	tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	unsigned int data_rate = get_ddr_freq(0);
+	unsigned int data_rate = get_ddr_freq(ctrl_num);
 	int txp;
 	unsigned int ip_rev;
 	int odt_overlap;
@@ -344,7 +345,8 @@
 		 * tMRD = 4nCK (8nCK for RDIMM)
 		 * tMOD = max(12nCK, 15ns)
 		 */
-		tmrd_mclk = max((unsigned int)12, picos_to_mclk(15000));
+		tmrd_mclk = max((unsigned int)12,
+				picos_to_mclk(ctrl_num, 15000));
 	} else {
 		/*
 		 * MRS_CYC = tMRD
@@ -388,7 +390,7 @@
 		taxpd_mclk = 1;
 	} else {
 		/* act_pd_exit_mclk = tXARD, see above */
-		act_pd_exit_mclk = picos_to_mclk(txp);
+		act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 		/* Mode register MR0[A12] is '1' - fast exit */
 		pre_pd_exit_mclk = act_pd_exit_mclk;
 		taxpd_mclk = 1;
@@ -424,11 +426,12 @@
 #endif	/* !defined(CONFIG_SYS_FSL_DDR1) */
  
 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
-static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency,
-			       unsigned int additive_latency)
+static void set_timing_cfg_3(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
+			     const memctl_options_t *popts,
+			     const common_timing_params_t *common_dimm,
+			     unsigned int cas_latency,
+			     unsigned int additive_latency)
 {
 	/* Extended precharge to activate interval (tRP) */
 	unsigned int ext_pretoact = 0;
  
  
  
@@ -447,18 +450,18 @@
 	/* Control Adjust */
 	unsigned int cntl_adj = 0;
  
-	ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
-	ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
-	ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
+	ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
+	ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
+	ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
 	ext_caslat = (2 * cas_latency - 1) >> 4;
 	ext_add_lat = additive_latency >> 4;
 #ifdef CONFIG_SYS_FSL_DDR4
-	ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4;
+	ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
 #else
-	ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
+	ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
 	/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 #endif
-	ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
+	ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
 		(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
  
 	ddr->timing_cfg_3 = (0
@@ -475,10 +478,11 @@
 }
  
 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
-static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency)
+static void set_timing_cfg_1(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
+			     const memctl_options_t *popts,
+			     const common_timing_params_t *common_dimm,
+			     unsigned int cas_latency)
 {
 	/* Precharge-to-activate interval (tRP) */
 	unsigned char pretoact_mclk;
@@ -510,9 +514,9 @@
 		1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 #endif
  
-	pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
-	acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
-	acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
+	pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
+	acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
+	acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
  
 	/*
 	 * Translate CAS Latency to a DDR controller field value:
  
@@ -547,19 +551,19 @@
 #endif
  
 #ifdef CONFIG_SYS_FSL_DDR4
-	refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
-	wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
-	acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U);
-	wrtord_mclk = max(2U, picos_to_mclk(2500));
+	refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
+	wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
+	acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
+	wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
 	if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 		printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 	else
 		wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 #else
-	refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
-	wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
-	acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
-	wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
+	refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
+	wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
+	acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
+	wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
 	if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
 		printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 	else
@@ -602,11 +606,12 @@
 }
  
 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
-static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency,
-			       unsigned int additive_latency)
+static void set_timing_cfg_2(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
+			     const memctl_options_t *popts,
+			     const common_timing_params_t *common_dimm,
+			     unsigned int cas_latency,
+			     unsigned int additive_latency)
 {
 	/* Additive latency */
 	unsigned char add_lat_mclk;
@@ -623,7 +628,7 @@
 	/* Window for four activates (tFAW) */
 	unsigned short four_act;
 #ifdef CONFIG_SYS_FSL_DDR3
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 #endif
  
 	/* FIXME add check that this must be less than acttorw_mclk */
  
  
@@ -641,13 +646,13 @@
 #elif defined(CONFIG_SYS_FSL_DDR2)
 	wr_lat = cas_latency - 1;
 #else
-	wr_lat = compute_cas_write_latency();
+	wr_lat = compute_cas_write_latency(ctrl_num);
 #endif
  
 #ifdef CONFIG_SYS_FSL_DDR4
-	rd_to_pre = picos_to_mclk(7500);
+	rd_to_pre = picos_to_mclk(ctrl_num, 7500);
 #else
-	rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
+	rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
 #endif
 	/*
 	 * JEDEC has some min requirements for tRTP
  
  
@@ -665,19 +670,20 @@
 	wr_data_delay = popts->write_data_delay;
 #ifdef CONFIG_SYS_FSL_DDR4
 	cpo = 0;
-	cke_pls = max(3U, picos_to_mclk(5000));
+	cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
 #elif defined(CONFIG_SYS_FSL_DDR3)
 	/*
 	 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
 	 *             max(3nCK, 5.625ns) for DDR3-1066, 1333
 	 *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
 	 */
-	cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 :
-				       (mclk_ps > 1245 ? 5625 : 5000)));
+	cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
+					(mclk_ps > 1245 ? 5625 : 5000)));
 #else
 	cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
 #endif
-	four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
+	four_act = picos_to_mclk(ctrl_num,
+				 popts->tfaw_window_four_activates_ps);
  
 	ddr->timing_cfg_2 = (0
 		| ((add_lat_mclk & 0xf) << 28)
@@ -818,7 +824,8 @@
 }
  
 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
-static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
+			       fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const unsigned int unq_mrs_en)
 {
@@ -865,7 +872,7 @@
 #endif
  
 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
-	slow = get_ddr_freq(0) < 1249000000;
+	slow = get_ddr_freq(ctrl_num) < 1249000000;
 #endif
  
 	if (popts->registered_dimm_en) {
@@ -915,7 +922,8 @@
  
 #ifdef CONFIG_SYS_FSL_DDR4
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
  
@@ -926,10 +934,10 @@
 	unsigned int wr_crc = 0;	/* Disable */
 	unsigned int rtt_wr = 0;	/* Rtt_WR - dynamic ODT off */
 	unsigned int srt = 0;	/* self-refresh temerature, normal range */
-	unsigned int cwl = compute_cas_write_latency() - 9;
+	unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
 	unsigned int mpr = 0;	/* serial */
 	unsigned int wc_lat;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  
 	if (popts->rtt_override)
 		rtt_wr = popts->rtt_wr_override_value;
@@ -1002,7 +1010,8 @@
 }
 #elif defined(CONFIG_SYS_FSL_DDR3)
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
@@ -1013,7 +1022,7 @@
 	unsigned int rtt_wr = 0;	/* Rtt_WR - dynamic ODT off */
 	unsigned int srt = 0;	/* self-refresh temerature, normal range */
 	unsigned int asr = 0;	/* auto self-refresh disable */
-	unsigned int cwl = compute_cas_write_latency() - 5;
+	unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
 	unsigned int pasr = 0;	/* partial array self refresh disable */
  
 	if (popts->rtt_override)
@@ -1077,7 +1086,8 @@
  
 #else /* for DDR2 and DDR1 */
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
@@ -1144,7 +1154,8 @@
 }
  
 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
-static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
@@ -1152,7 +1163,7 @@
 	int i;
 	unsigned short esdmode6 = 0;	/* Extended SDRAM mode 6 */
 	unsigned short esdmode7 = 0;	/* Extended SDRAM mode 7 */
-	unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps);
+	unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
  
 	esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
  
  
@@ -1196,14 +1207,15 @@
 #endif
  
 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
-static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm)
+static void set_ddr_sdram_interval(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
+				const memctl_options_t *popts,
+				const common_timing_params_t *common_dimm)
 {
 	unsigned int refint;	/* Refresh interval */
 	unsigned int bstopre;	/* Precharge interval */
  
-	refint = picos_to_mclk(common_dimm->refresh_rate_ps);
+	refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
  
 	bstopre = popts->bstopre;
  
@@ -1217,7 +1229,8 @@
  
 #ifdef CONFIG_SYS_FSL_DDR4
 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+			       fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const common_timing_params_t *common_dimm,
 			       unsigned int cas_latency,
@@ -1292,7 +1305,7 @@
 	 * 1=fast exit DLL on (tXP)
 	 */
  
-	wr_mclk = picos_to_mclk(common_dimm->twr_ps);
+	wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 	if (wr_mclk <= 24) {
 		wr = wr_table[wr_mclk - 10];
 	} else {
@@ -1387,7 +1400,8 @@
  
 #elif defined(CONFIG_SYS_FSL_DDR3)
 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+			       fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const common_timing_params_t *common_dimm,
 			       unsigned int cas_latency,
@@ -1466,7 +1480,7 @@
 	 */
 	dll_on = 1;
  
-	wr_mclk = picos_to_mclk(common_dimm->twr_ps);
+	wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 	if (wr_mclk <= 16) {
 		wr = wr_table[wr_mclk - 5];
 	} else {
@@ -1582,7 +1596,8 @@
 #else /* !CONFIG_SYS_FSL_DDR3 */
  
 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+			       fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const common_timing_params_t *common_dimm,
 			       unsigned int cas_latency,
@@ -1654,7 +1669,7 @@
 #if defined(CONFIG_SYS_FSL_DDR1)
 	wr = 0;       /* Historical */
 #elif defined(CONFIG_SYS_FSL_DDR2)
-	wr = picos_to_mclk(common_dimm->twr_ps);
+	wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 #endif
 	dll_res = 0;
 	mode = 0;
  
@@ -1842,15 +1857,16 @@
 	debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
 }
  
-static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
-			const common_timing_params_t *common_dimm)
+static void set_timing_cfg_7(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
+			     const common_timing_params_t *common_dimm)
 {
 	unsigned int txpr, tcksre, tcksrx;
 	unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
  
-	txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000));
-	tcksre = max(5U, picos_to_mclk(10000));
-	tcksrx = max(5U, picos_to_mclk(10000));
+	txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
+	tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
+	tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
 	par_lat = 0;
 	cs_to_cmd = 0;
  
  
@@ -1883,14 +1899,15 @@
 	debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
 }
  
-static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
+static void set_timing_cfg_8(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
 			     const memctl_options_t *popts,
 			     const common_timing_params_t *common_dimm,
 			     unsigned int cas_latency)
 {
 	unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
 	unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
-	unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps);
+	unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
 	unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
 			      ((ddr->timing_cfg_2 & 0x00040000) >> 14);
  
@@ -1914,8 +1931,8 @@
 		wwt_bg = tccdl - 4;
 	}
  
-	acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
-	wrtord_bg = max(4U, picos_to_mclk(7500));
+	acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
+	wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
 	if (popts->otf_burst_chop_en)
 		wrtord_bg += 2;
  
@@ -2147,7 +2164,8 @@
 }
  
 unsigned int
-compute_fsl_memctl_config_regs(const memctl_options_t *popts,
+compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
+			       const memctl_options_t *popts,
 			       fsl_ddr_cfg_regs_t *ddr,
 			       const common_timing_params_t *common_dimm,
 			       const dimm_params_t *dimm_params,
  
  
@@ -2319,14 +2337,14 @@
 	set_ddr_eor(ddr, popts);
  
 #if !defined(CONFIG_SYS_FSL_DDR1)
-	set_timing_cfg_0(ddr, popts, dimm_params);
+	set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
 #endif
  
-	set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
+	set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
 			 additive_latency);
-	set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
-	set_timing_cfg_2(ddr, popts, common_dimm,
-				cas_latency, additive_latency);
+	set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
+	set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
+			 cas_latency, additive_latency);
  
 	set_ddr_cdr1(ddr, popts);
 	set_ddr_cdr2(ddr, popts);
  
  
@@ -2338,15 +2356,15 @@
 	if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
 		ddr->debug[18] = popts->cswl_override;
  
-	set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
-	set_ddr_sdram_mode(ddr, popts, common_dimm,
-				cas_latency, additive_latency, unq_mrs_en);
-	set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
+	set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
+	set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
+			   cas_latency, additive_latency, unq_mrs_en);
+	set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
 #ifdef CONFIG_SYS_FSL_DDR4
 	set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
-	set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en);
+	set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
 #endif
-	set_ddr_sdram_interval(ddr, popts, common_dimm);
+	set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
 	set_ddr_data_init(ddr);
 	set_ddr_sdram_clk_cntl(ddr, popts);
 	set_ddr_init_addr(ddr);
@@ -2356,8 +2374,8 @@
 #ifdef CONFIG_SYS_FSL_DDR4
 	set_ddr_sdram_cfg_3(ddr, popts);
 	set_timing_cfg_6(ddr);
-	set_timing_cfg_7(ddr, common_dimm);
-	set_timing_cfg_8(ddr, popts, common_dimm, cas_latency);
+	set_timing_cfg_7(ctrl_num, ddr, common_dimm);
+	set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
 	set_timing_cfg_9(ddr);
 	set_ddr_dq_mapping(ddr, dimm_params);
 #endif
@@ -228,10 +228,10 @@
  *
  * FIXME: use #define for the retvals
  */
-unsigned int
-ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd,
-			     dimm_params_t *pdimm,
-			     unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+					 const ddr1_spd_eeprom_t *spd,
+					 dimm_params_t *pdimm,
+					 unsigned int dimm_number)
 {
 	unsigned int retval;
  
  
@@ -311,16 +311,16 @@
 					  & ~(1 << pdimm->caslat_x_minus_1));
  
 	/* Compute CAS latencies below that defined by SPD */
-	pdimm->caslat_lowest_derated
-		= compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps());
+	pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
+					get_memory_clk_period_ps(ctrl_num));
  
 	/* Compute timing parameters */
 	pdimm->trcd_ps = spd->trcd * 250;
 	pdimm->trp_ps = spd->trp * 250;
 	pdimm->tras_ps = spd->tras * 1000;
  
-	pdimm->twr_ps = mclk_to_picos(3);
-	pdimm->twtr_ps = mclk_to_picos(1);
+	pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
+	pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
 	pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
  
 	pdimm->trrd_ps = spd->trrd * 250;
@@ -335,7 +335,7 @@
 	pdimm->tdh_ps
 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
  
-	pdimm->trtp_ps = mclk_to_picos(2);	/* By the book. */
+	pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2);	/* By the book. */
 	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
 	pdimm->tqhs_ps = spd->tqhs * 10;
  
@@ -211,10 +211,10 @@
  *
  * FIXME: use #define for the retvals
  */
-unsigned int
-ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
-			     dimm_params_t *pdimm,
-			     unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+					 const ddr2_spd_eeprom_t *spd,
+					 dimm_params_t *pdimm,
+					 unsigned int dimm_number)
 {
 	unsigned int retval;
  
@@ -310,8 +310,8 @@
 					  & ~(1 << pdimm->caslat_x_minus_1));
  
 	/* Compute CAS latencies below that defined by SPD */
-	pdimm->caslat_lowest_derated
-		= compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());
+	pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency(
+					get_memory_clk_period_ps(ctrl_num));
  
 	/* Compute timing parameters */
 	pdimm->trcd_ps = spd->trcd * 250;
@@ -83,10 +83,10 @@
  * Writes the results to the dimm_params_t structure pointed by pdimm.
  *
  */
-unsigned int
-ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
-			     dimm_params_t *pdimm,
-			     unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+					 const ddr3_spd_eeprom_t *spd,
+					 dimm_params_t *pdimm,
+					 unsigned int dimm_number)
 {
 	unsigned int retval;
 	unsigned int mtb_ps;
@@ -119,10 +119,10 @@
  * Writes the results to the dimm_params_t structure pointed by pdimm.
  *
  */
-unsigned int
-ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd,
-			    dimm_params_t *pdimm,
-			    unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+					 const generic_spd_eeprom_t *spd,
+					 dimm_params_t *pdimm,
+					 unsigned int dimm_number)
 {
 	unsigned int retval;
 	int i;
@@ -287,7 +287,7 @@
 	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
-		(get_ddr_freq(0) >> 20)) << 2;
+		(get_ddr_freq(ctrl_num) >> 20)) << 2;
 	total_gb_size_per_controller >>= 4;	/* shift down to gb size */
 	debug("total %d GB\n", total_gb_size_per_controller);
 	debug("Need to wait up to %d * 10ms\n", timeout);
@@ -13,7 +13,8 @@
  
 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 static unsigned int
-compute_cas_latency(const dimm_params_t *dimm_params,
+compute_cas_latency(const unsigned int ctrl_num,
+		    const dimm_params_t *dimm_params,
 		    common_timing_params_t *outpdimm,
 		    unsigned int number_of_dimms)
 {
@@ -22,7 +23,7 @@
 	unsigned int caslat_actual;
 	unsigned int retry = 16;
 	unsigned int tmp;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 #ifdef CONFIG_SYS_FSL_DDR3
 	const unsigned int taamax = 20000;
 #else
  
@@ -72,12 +73,13 @@
 }
 #else	/* for DDR1 and DDR2 */
 static unsigned int
-compute_cas_latency(const dimm_params_t *dimm_params,
+compute_cas_latency(const unsigned int ctrl_num,
+		    const dimm_params_t *dimm_params,
 		    common_timing_params_t *outpdimm,
 		    unsigned int number_of_dimms)
 {
 	int i;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 	unsigned int lowest_good_caslat;
 	unsigned int not_ok;
 	unsigned int temp1, temp2;
@@ -212,7 +214,8 @@
  * by dimm_params.
  */
 unsigned int
-compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
+compute_lowest_common_dimm_parameters(const unsigned int ctrl_num,
+				      const dimm_params_t *dimm_params,
 				      common_timing_params_t *outpdimm,
 				      const unsigned int number_of_dimms)
 {
@@ -442,7 +445,8 @@
 		printf("ERROR: Mix different RDIMM detected!\n");
  
 	/* calculate cas latency for all DDR types */
-	if (compute_cas_latency(dimm_params, outpdimm, number_of_dimms))
+	if (compute_cas_latency(ctrl_num, dimm_params,
+				outpdimm, number_of_dimms))
 		return 1;
  
 	/* Determine if all DIMMs ECC capable. */
  
@@ -518,11 +522,12 @@
  
 #if defined(CONFIG_SYS_FSL_DDR2)
 	if ((outpdimm->lowest_common_spd_caslat < 4) &&
-	    (picos_to_mclk(trcd_ps) > outpdimm->lowest_common_spd_caslat)) {
-		additive_latency = picos_to_mclk(trcd_ps) -
+	    (picos_to_mclk(ctrl_num, trcd_ps) >
+	     outpdimm->lowest_common_spd_caslat)) {
+		additive_latency = picos_to_mclk(ctrl_num, trcd_ps) -
 				   outpdimm->lowest_common_spd_caslat;
-		if (mclk_to_picos(additive_latency) > trcd_ps) {
-			additive_latency = picos_to_mclk(trcd_ps);
+		if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
+			additive_latency = picos_to_mclk(ctrl_num, trcd_ps);
 			debug("setting additive_latency to %u because it was "
 				" greater than tRCD_ps\n", additive_latency);
 		}
@@ -534,7 +539,7 @@
 	 *
 	 * AL <= tRCD(min)
 	 */
-	if (mclk_to_picos(additive_latency) > trcd_ps) {
+	if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
 		printf("Error: invalid additive latency exceeds tRCD(min).\n");
 		return 1;
 	}
@@ -450,7 +450,8 @@
 					&(pinfo->spd_installed_dimms[i][j]);
 				dimm_params_t *pdimm =
 					&(pinfo->dimm_params[i][j]);
-				retval = compute_dimm_parameters(spd, pdimm, i);
+				retval = compute_dimm_parameters(
+							i, spd, pdimm, j);
 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 				if (!i && !j && retval) {
 					printf("SPD error on controller %d! "
@@ -507,10 +508,11 @@
 		for (i = first_ctrl; i <= last_ctrl; i++) {
 			debug("Computing lowest common DIMM"
 				" parameters for memctl=%u\n", i);
-			compute_lowest_common_dimm_parameters(
-				pinfo->dimm_params[i],
-				&timing_params[i],
-				CONFIG_DIMM_SLOTS_PER_CTLR);
+			compute_lowest_common_dimm_parameters
+				(i,
+				 pinfo->dimm_params[i],
+				 &timing_params[i],
+				 CONFIG_DIMM_SLOTS_PER_CTLR);
 		}
  
 	case STEP_GATHER_OPTS:
@@ -562,12 +564,13 @@
 				continue;
 			}
  
-			compute_fsl_memctl_config_regs(
-					&pinfo->memctl_opts[i],
-					&ddr_reg[i], &timing_params[i],
-					pinfo->dimm_params[i],
-					dbw_capacity_adjust[i],
-					size_only);
+			compute_fsl_memctl_config_regs
+				(i,
+				 &pinfo->memctl_opts[i],
+				 &ddr_reg[i], &timing_params[i],
+				 pinfo->dimm_params[i],
+				 dbw_capacity_adjust[i],
+				 size_only);
 		}
  
 	default:
@@ -426,7 +426,7 @@
 	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
-		(get_ddr_freq(0) >> 20)) << 1;
+		(get_ddr_freq(ctrl_num) >> 20)) << 1;
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 	timeout_save = timeout;
 #endif
  
@@ -538,12 +538,14 @@
 		case 1:
 			out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
 			break;
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 2
 		case 2:
 			out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
 			break;
 		case 3:
 			out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
 			break;
+#endif
 		}
 		clrbits_be32(&ddr->sdram_cfg, 0x2);
 	}
@@ -732,7 +732,7 @@
 #endif
  
 	/* Global Timing Parameters. */
-	debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
+	debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
  
 	/* Pick a caslat override. */
 	popts->cas_latency_override = 0;
@@ -785,7 +785,7 @@
 	 * FIXME: width, was considering looking at pdimm->primary_sdram_width
 	 */
 #if defined(CONFIG_SYS_FSL_DDR1)
-	popts->tfaw_window_four_activates_ps = mclk_to_picos(1);
+	popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
  
 #elif defined(CONFIG_SYS_FSL_DDR2)
 	/*
@@ -1036,7 +1036,7 @@
 	if (pdimm[0].n_ranks == 4)
 		popts->quad_rank_present = 1;
  
-	ddr_freq = get_ddr_freq(0) / 1000000;
+	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
 	if (popts->registered_dimm_en) {
 		popts->rcw_override = 1;
 		popts->rcw_1 = 0x000a5a00;
@@ -43,9 +43,9 @@
  * propagation, compute a suitably rounded mclk_ps to compute
  * a working memory controller configuration.
  */
-unsigned int get_memory_clk_period_ps(void)
+unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
 {
-	unsigned int data_rate = get_ddr_freq(0);
+	unsigned int data_rate = get_ddr_freq(ctrl_num);
 	unsigned int result;
  
 	/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
  
@@ -59,10 +59,10 @@
 }
  
 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
-unsigned int picos_to_mclk(unsigned int picos)
+unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
 {
 	unsigned long long clks, clks_rem;
-	unsigned long data_rate = get_ddr_freq(0);
+	unsigned long data_rate = get_ddr_freq(ctrl_num);
  
 	/* Short circuit for zero picos */
 	if (!picos)
  
@@ -88,9 +88,9 @@
 	return (unsigned int) clks;
 }
  
-unsigned int mclk_to_picos(unsigned int mclk)
+unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
 {
-	return get_memory_clk_period_ps() * mclk;
+	return get_memory_clk_period_ps(ctrl_num) * mclk;
 }
  
 #ifdef CONFIG_PPC
@@ -44,11 +44,12 @@
  * to this specific DDR technology.
  */
 static __inline__ int
-compute_dimm_parameters(const generic_spd_eeprom_t *spd,
+compute_dimm_parameters(const unsigned int ctrl_num,
+			const generic_spd_eeprom_t *spd,
 			dimm_params_t *pdimm,
 			unsigned int dimm_number)
 {
-	return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
+	return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
 }
 #endif
  
  
@@ -92,13 +93,15 @@
 				       unsigned int size_only);
 const char *step_to_string(unsigned int step);
  
-unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
+unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
+			       const memctl_options_t *popts,
 			       fsl_ddr_cfg_regs_t *ddr,
 			       const common_timing_params_t *common_dimm,
 			       const dimm_params_t *dimm_parameters,
 			       unsigned int dbw_capacity_adjust,
 			       unsigned int size_only);
 unsigned int compute_lowest_common_dimm_parameters(
+				const unsigned int ctrl_num,
 				const dimm_params_t *dimm_params,
 				common_timing_params_t *outpdimm,
 				unsigned int number_of_dimms);
@@ -108,9 +111,9 @@
 				unsigned int ctrl_num);
 void check_interleaving_options(fsl_ddr_info_t *pinfo);
  
-unsigned int mclk_to_picos(unsigned int mclk);
-unsigned int get_memory_clk_period_ps(void);
-unsigned int picos_to_mclk(unsigned int picos);
+unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
+unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
+unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
 void fsl_ddr_set_lawbar(
 		const common_timing_params_t *memctl_common_params,
 		unsigned int memctl_interleaved,
@@ -112,7 +112,7 @@
 #endif
 } dimm_params_t;
  
-extern unsigned int ddr_compute_dimm_parameters(
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
 					 const generic_spd_eeprom_t *spd,
 					 dimm_params_t *pdimm,
 					 unsigned int dimm_number);
...	...	@@ -222,7 +222,7 @@
222	222	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
223	223	>> SDRAM_CFG_DBW_SHIFT);
224	224	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
225		- (get_ddr_freq(0) >> 20)) << 1;
	225	+ (get_ddr_freq(ctrl_num) >> 20)) << 1;
226	226	total_gb_size_per_controller >>= 4; /* shift down to gb size */
227	227	debug("total %d GB\n", total_gb_size_per_controller);
228	228	debug("Need to wait up to %d * 10ms\n", timeout);
...	...	@@ -228,10 +228,10 @@
228	228	*
229	229	* FIXME: use #define for the retvals
230	230	*/
231		-unsigned int
232		-ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd,
233		- dimm_params_t *pdimm,
234		- unsigned int dimm_number)
	231	+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
	232	+ const ddr1_spd_eeprom_t *spd,
	233	+ dimm_params_t *pdimm,
	234	+ unsigned int dimm_number)
235	235	{
236	236	unsigned int retval;
237	237
238	238
...	...	@@ -311,16 +311,16 @@
311	311	& ~(1 << pdimm->caslat_x_minus_1));
312	312
313	313	/* Compute CAS latencies below that defined by SPD */
314		- pdimm->caslat_lowest_derated
315		- = compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps());
	314	+ pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
	315	+ get_memory_clk_period_ps(ctrl_num));
316	316
317	317	/* Compute timing parameters */
318	318	pdimm->trcd_ps = spd->trcd * 250;
319	319	pdimm->trp_ps = spd->trp * 250;
320	320	pdimm->tras_ps = spd->tras * 1000;
321	321
322		- pdimm->twr_ps = mclk_to_picos(3);
323		- pdimm->twtr_ps = mclk_to_picos(1);
	322	+ pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
	323	+ pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
324	324	pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
325	325
326	326	pdimm->trrd_ps = spd->trrd * 250;
...	...	@@ -335,7 +335,7 @@
335	335	pdimm->tdh_ps
336	336	= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
337	337
338		- pdimm->trtp_ps = mclk_to_picos(2); /* By the book. */
	338	+ pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2); /* By the book. */
339	339	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
340	340	pdimm->tqhs_ps = spd->tqhs * 10;
341	341
...	...	@@ -211,10 +211,10 @@
211	211	*
212	212	* FIXME: use #define for the retvals
213	213	*/
214		-unsigned int
215		-ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
216		- dimm_params_t *pdimm,
217		- unsigned int dimm_number)
	214	+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
	215	+ const ddr2_spd_eeprom_t *spd,
	216	+ dimm_params_t *pdimm,
	217	+ unsigned int dimm_number)
218	218	{
219	219	unsigned int retval;
220	220
...	...	@@ -310,8 +310,8 @@
310	310	& ~(1 << pdimm->caslat_x_minus_1));
311	311
312	312	/* Compute CAS latencies below that defined by SPD */
313		- pdimm->caslat_lowest_derated
314		- = compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());
	313	+ pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency(
	314	+ get_memory_clk_period_ps(ctrl_num));
315	315
316	316	/* Compute timing parameters */
317	317	pdimm->trcd_ps = spd->trcd * 250;
...	...	@@ -83,10 +83,10 @@
83	83	* Writes the results to the dimm_params_t structure pointed by pdimm.
84	84	*
85	85	*/
86		-unsigned int
87		-ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
88		- dimm_params_t *pdimm,
89		- unsigned int dimm_number)
	86	+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
	87	+ const ddr3_spd_eeprom_t *spd,
	88	+ dimm_params_t *pdimm,
	89	+ unsigned int dimm_number)
90	90	{
91	91	unsigned int retval;
92	92	unsigned int mtb_ps;
...	...	@@ -119,10 +119,10 @@
119	119	* Writes the results to the dimm_params_t structure pointed by pdimm.
120	120	*
121	121	*/
122		-unsigned int
123		-ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd,
124		- dimm_params_t *pdimm,
125		- unsigned int dimm_number)
	122	+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
	123	+ const generic_spd_eeprom_t *spd,
	124	+ dimm_params_t *pdimm,
	125	+ unsigned int dimm_number)
126	126	{
127	127	unsigned int retval;
128	128	int i;
...	...	@@ -287,7 +287,7 @@
287	287	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
288	288	>> SDRAM_CFG_DBW_SHIFT);
289	289	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
290		- (get_ddr_freq(0) >> 20)) << 2;
	290	+ (get_ddr_freq(ctrl_num) >> 20)) << 2;
291	291	total_gb_size_per_controller >>= 4; /* shift down to gb size */
292	292	debug("total %d GB\n", total_gb_size_per_controller);
293	293	debug("Need to wait up to %d * 10ms\n", timeout);
...	...	@@ -13,7 +13,8 @@
13	13
14	14	#if defined(CONFIG_SYS_FSL_DDR3) \|\| defined(CONFIG_SYS_FSL_DDR4)
15	15	static unsigned int
16		-compute_cas_latency(const dimm_params_t *dimm_params,
	16	+compute_cas_latency(const unsigned int ctrl_num,
	17	+ const dimm_params_t *dimm_params,
17	18	common_timing_params_t *outpdimm,
18	19	unsigned int number_of_dimms)
19	20	{
...	...	@@ -22,7 +23,7 @@
22	23	unsigned int caslat_actual;
23	24	unsigned int retry = 16;
24	25	unsigned int tmp;
25		- const unsigned int mclk_ps = get_memory_clk_period_ps();
	26	+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
26	27	#ifdef CONFIG_SYS_FSL_DDR3
27	28	const unsigned int taamax = 20000;
28	29	#else
29	30
...	...	@@ -72,12 +73,13 @@
72	73	}
73	74	#else /* for DDR1 and DDR2 */
74	75	static unsigned int
75		-compute_cas_latency(const dimm_params_t *dimm_params,
	76	+compute_cas_latency(const unsigned int ctrl_num,
	77	+ const dimm_params_t *dimm_params,
76	78	common_timing_params_t *outpdimm,
77	79	unsigned int number_of_dimms)
78	80	{
79	81	int i;
80		- const unsigned int mclk_ps = get_memory_clk_period_ps();
	82	+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
81	83	unsigned int lowest_good_caslat;
82	84	unsigned int not_ok;
83	85	unsigned int temp1, temp2;
...	...	@@ -212,7 +214,8 @@
212	214	* by dimm_params.
213	215	*/
214	216	unsigned int
215		-compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
	217	+compute_lowest_common_dimm_parameters(const unsigned int ctrl_num,
	218	+ const dimm_params_t *dimm_params,
216	219	common_timing_params_t *outpdimm,
217	220	const unsigned int number_of_dimms)
218	221	{
...	...	@@ -442,7 +445,8 @@
442	445	printf("ERROR: Mix different RDIMM detected!\n");
443	446
444	447	/* calculate cas latency for all DDR types */
445		- if (compute_cas_latency(dimm_params, outpdimm, number_of_dimms))
	448	+ if (compute_cas_latency(ctrl_num, dimm_params,
	449	+ outpdimm, number_of_dimms))
446	450	return 1;
447	451
448	452	/* Determine if all DIMMs ECC capable. */
449	453
...	...	@@ -518,11 +522,12 @@
518	522
519	523	#if defined(CONFIG_SYS_FSL_DDR2)
520	524	if ((outpdimm->lowest_common_spd_caslat < 4) &&
521		- (picos_to_mclk(trcd_ps) > outpdimm->lowest_common_spd_caslat)) {
522		- additive_latency = picos_to_mclk(trcd_ps) -
	525	+ (picos_to_mclk(ctrl_num, trcd_ps) >
	526	+ outpdimm->lowest_common_spd_caslat)) {
	527	+ additive_latency = picos_to_mclk(ctrl_num, trcd_ps) -
523	528	outpdimm->lowest_common_spd_caslat;
524		- if (mclk_to_picos(additive_latency) > trcd_ps) {
525		- additive_latency = picos_to_mclk(trcd_ps);
	529	+ if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
	530	+ additive_latency = picos_to_mclk(ctrl_num, trcd_ps);
526	531	debug("setting additive_latency to %u because it was "
527	532	" greater than tRCD_ps\n", additive_latency);
528	533	}
...	...	@@ -534,7 +539,7 @@
534	539	*
535	540	* AL <= tRCD(min)
536	541	*/
537		- if (mclk_to_picos(additive_latency) > trcd_ps) {
	542	+ if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
538	543	printf("Error: invalid additive latency exceeds tRCD(min).\n");
539	544	return 1;
540	545	}
...	...	@@ -450,7 +450,8 @@
450	450	&(pinfo->spd_installed_dimms[i][j]);
451	451	dimm_params_t *pdimm =
452	452	&(pinfo->dimm_params[i][j]);
453		- retval = compute_dimm_parameters(spd, pdimm, i);
	453	+ retval = compute_dimm_parameters(
	454	+ i, spd, pdimm, j);
454	455	#ifdef CONFIG_SYS_DDR_RAW_TIMING
455	456	if (!i && !j && retval) {
456	457	printf("SPD error on controller %d! "
...	...	@@ -507,10 +508,11 @@
507	508	for (i = first_ctrl; i <= last_ctrl; i++) {
508	509	debug("Computing lowest common DIMM"
509	510	" parameters for memctl=%u\n", i);
510		- compute_lowest_common_dimm_parameters(
511		- pinfo->dimm_params[i],
512		- &timing_params[i],
513		- CONFIG_DIMM_SLOTS_PER_CTLR);
	511	+ compute_lowest_common_dimm_parameters
	512	+ (i,
	513	+ pinfo->dimm_params[i],
	514	+ &timing_params[i],
	515	+ CONFIG_DIMM_SLOTS_PER_CTLR);
514	516	}
515	517
516	518	case STEP_GATHER_OPTS:
...	...	@@ -562,12 +564,13 @@
562	564	continue;
563	565	}
564	566
565		- compute_fsl_memctl_config_regs(
566		- &pinfo->memctl_opts[i],
567		- &ddr_reg[i], &timing_params[i],
568		- pinfo->dimm_params[i],
569		- dbw_capacity_adjust[i],
570		- size_only);
	567	+ compute_fsl_memctl_config_regs
	568	+ (i,
	569	+ &pinfo->memctl_opts[i],
	570	+ &ddr_reg[i], &timing_params[i],
	571	+ pinfo->dimm_params[i],
	572	+ dbw_capacity_adjust[i],
	573	+ size_only);
571	574	}
572	575
573	576	default:
...	...	@@ -426,7 +426,7 @@
426	426	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
427	427	>> SDRAM_CFG_DBW_SHIFT);
428	428	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
429		- (get_ddr_freq(0) >> 20)) << 1;
	429	+ (get_ddr_freq(ctrl_num) >> 20)) << 1;
430	430	#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
431	431	timeout_save = timeout;
432	432	#endif
433	433
...	...	@@ -538,12 +538,14 @@
538	538	case 1:
539	539	out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
540	540	break;
	541	+#if CONFIG_CHIP_SELECTS_PER_CTRL > 2
541	542	case 2:
542	543	out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
543	544	break;
544	545	case 3:
545	546	out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
546	547	break;
	548	+#endif
547	549	}
548	550	clrbits_be32(&ddr->sdram_cfg, 0x2);
549	551	}
...	...	@@ -732,7 +732,7 @@
732	732	#endif
733	733
734	734	/* Global Timing Parameters. */
735		- debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
	735	+ debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
736	736
737	737	/* Pick a caslat override. */
738	738	popts->cas_latency_override = 0;
...	...	@@ -785,7 +785,7 @@
785	785	* FIXME: width, was considering looking at pdimm->primary_sdram_width
786	786	*/
787	787	#if defined(CONFIG_SYS_FSL_DDR1)
788		- popts->tfaw_window_four_activates_ps = mclk_to_picos(1);
	788	+ popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
789	789
790	790	#elif defined(CONFIG_SYS_FSL_DDR2)
791	791	/*
...	...	@@ -1036,7 +1036,7 @@
1036	1036	if (pdimm[0].n_ranks == 4)
1037	1037	popts->quad_rank_present = 1;
1038	1038
1039		- ddr_freq = get_ddr_freq(0) / 1000000;
	1039	+ ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
1040	1040	if (popts->registered_dimm_en) {
1041	1041	popts->rcw_override = 1;
1042	1042	popts->rcw_1 = 0x000a5a00;