Eric Lee / smarc-uboot

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Commit 03f5c55021c2d6297e66cc11bfea75f149a5d71c

Authored by wdenk
1 parent cf33678e51
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Patches by Jon Loeliger, 24 Aug 2004: 

- Add support for the MPC8541 and MPC8555 CDS boards
- Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR

Showing 27 changed files with 3149 additions and 1109 deletions Side-by-side Diff

... ... @@ -2,11 +2,13 @@
2 2 Changes since U-Boot 1.1.1:
3 3 ======================================================================
4 4  
5   -* Patch by Jon Loeliger, 24 Aug 2004:
  5 +* Patches by Jon Loeliger, 24 Aug 2004:
  6 + - Add support for the MPC8541 and MPC8555 CDS boards
  7 + - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR
  8 + - Convert MPC85xxADS to use common CFI flash driver
6 9 - Fix PCI window on MPC85xx; remove unneeded PCI initialization
7 10 from board_early_init_f()
8 11 - Provide SW workaround for PCI initialization on 85xx CDS
9   - - Convert MPC85xxADS to use common CFI flash driver
10 12  
11 13 * Patches by George G. Davis, 24 Aug 2004:
12 14 - Enable ramdisk/initrd tagged param support for omap1610h2_config
... ... @@ -100,7 +100,8 @@
100 100 #########################################################################
101 101  
102 102 LIST_85xx=" \
103   - MPC8540ADS MPC8560ADS sbc8560 stxgp3 \
  103 + MPC8540ADS MPC8541CDS MPC8555CDS MPC8560ADS \
  104 + sbc8560 stxgp3 \
104 105 "
105 106  
106 107 #########################################################################
... ... @@ -1087,9 +1087,12 @@
1087 1087 MPC8560ADS_config: unconfig
1088 1088 @./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads
1089 1089  
1090   -stxgp3_config: unconfig
1091   - @./mkconfig $(@:_config=) ppc mpc85xx stxgp3
  1090 +MPC8541CDS_config: unconfig
  1091 + @./mkconfig $(@:_config=) ppc mpc85xx mpc8541cds cds
1092 1092  
  1093 +MPC8555CDS_config: unconfig
  1094 + @./mkconfig $(@:_config=) ppc mpc85xx mpc8555cds cds
  1095 +
1093 1096 sbc8560_config \
1094 1097 sbc8560_33_config \
1095 1098 sbc8560_66_config: unconfig
... ... @@ -1101,6 +1104,9 @@
1101 1104 echo "... 33 MHz PCI" ; \
1102 1105 fi
1103 1106 @./mkconfig -a sbc8560 ppc mpc85xx sbc8560
  1107 +
  1108 +stxgp3_config: unconfig
  1109 + @./mkconfig $(@:_config=) ppc mpc85xx stxgp3
1104 1110  
1105 1111 #########################################################################
1106 1112 ## 74xx/7xx Systems
board/cds/common/cadmus.c
Diff comments   View file @ 03f5c55
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +
  24 +#include <common.h>
  25 +
  26 +
  27 +/*
  28 + * CADMUS Board System Registers
  29 + */
  30 +#ifndef CFG_CADMUS_BASE_REG
  31 +#define CFG_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
  32 +#endif
  33 +
  34 +typedef struct cadmus_reg {
  35 + u_char cm_ver; /* Board version */
  36 + u_char cm_csr; /* General control/status */
  37 + u_char cm_rst; /* Reset control */
  38 + u_char cm_hsclk; /* High speed clock */
  39 + u_char cm_hsxclk; /* High speed clock extended */
  40 + u_char cm_led; /* LED data */
  41 + u_char cm_pci; /* PCI control/status */
  42 + u_char cm_dma; /* DMA control */
  43 + u_char cm_reserved[248]; /* Total 256 bytes */
  44 +} cadmus_reg_t;
  45 +
  46 +
  47 +unsigned int
  48 +get_board_version(void)
  49 +{
  50 + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
  51 +
  52 + return cadmus->cm_ver;
  53 +}
  54 +
  55 +
  56 +unsigned long
  57 +get_clock_freq(void)
  58 +{
  59 + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
  60 +
  61 + uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
  62 +
  63 + if (pci1_speed == 0) {
  64 + return 33000000;
  65 + } else if (pci1_speed == 1) {
  66 + return 66000000;
  67 + } else {
  68 + /* Really, unknown. Be safe? */
  69 + return 33000000;
  70 + }
  71 +}
  72 +
  73 +
  74 +unsigned int
  75 +get_pci_slot(void)
  76 +{
  77 + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
  78 +
  79 + /*
  80 + * PCI slot in USER bits CSR[6:7] by convention.
  81 + */
  82 + return ((cadmus->cm_csr >> 6) & 0x3) + 1;
  83 +}
  84 +
  85 +
  86 +unsigned int
  87 +get_pci_dual(void)
  88 +{
  89 + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
  90 +
  91 + /*
  92 + * PCI DUAL in CM_PCI[3]
  93 + */
  94 + return cadmus->cm_pci & 0x10;
  95 +}
board/cds/common/cadmus.h
Diff comments   View file @ 03f5c55
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +#ifndef __CADMUS_H_
  24 +#define __CADMUS_H_
  25 +
  26 +
  27 +/*
  28 + * CADMUS Board System Register interface.
  29 + */
  30 +
  31 +/*
  32 + * Returns board version register.
  33 + */
  34 +extern unsigned int get_board_version(void);
  35 +
  36 +/*
  37 + * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
  38 + */
  39 +extern unsigned long get_clock_freq(void);
  40 +
  41 +
  42 +/*
  43 + * Returns 1 - 4, as found in the USER CSR[6:7] bits.
  44 + */
  45 +extern unsigned int get_pci_slot(void);
  46 +
  47 +
  48 +/*
  49 + * Returns PCI DUAL as found in CM_PCI[3].
  50 + */
  51 +extern unsigned int get_pci_dual(void);
  52 +
  53 +
  54 +#endif /* __CADMUS_H_ */
board/cds/common/eeprom.c
Diff comments   View file @ 03f5c55
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +
  24 +#include <common.h>
  25 +#include <i2c.h>
  26 +
  27 +#include "eeprom.h"
  28 +
  29 +
  30 +typedef struct {
  31 + char idee_pcbid[4]; /* "CCID" for CDC v1.X */
  32 + u8 idee_major;
  33 + u8 idee_minor;
  34 + char idee_serial[10];
  35 + char idee_errata[2];
  36 + char idee_date[8]; /* yyyymmdd */
  37 + /* The rest of the EEPROM space is reserved */
  38 +} id_eeprom_t;
  39 +
  40 +
  41 +unsigned int
  42 +get_cpu_board_revision(void)
  43 +{
  44 + uint major = 0;
  45 + uint minor = 0;
  46 +
  47 + id_eeprom_t id_eeprom;
  48 +
  49 + i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2,
  50 + (uchar *) &id_eeprom, sizeof(id_eeprom));
  51 +
  52 + major = id_eeprom.idee_major;
  53 + minor = id_eeprom.idee_minor;
  54 +
  55 + if (major == 0xff && minor == 0xff) {
  56 + major = minor = 0;
  57 + }
  58 +
  59 + return MPC85XX_CPU_BOARD_REV(major,minor);
  60 +}
board/cds/common/eeprom.h
Diff comments   View file @ 03f5c55
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +#ifndef __EEPROM_H_
  24 +#define __EEPROM_H_
  25 +
  26 +
  27 +/*
  28 + * EEPROM Board System Register interface.
  29 + */
  30 +
  31 +
  32 +/*
  33 + * CPU Board Revision
  34 + */
  35 +#define MPC85XX_CPU_BOARD_REV(maj, min) ((((maj)&0xff) << 8) | ((min) & 0xff))
  36 +#define MPC85XX_CPU_BOARD_MAJOR(rev) (((rev) >> 8) & 0xff)
  37 +#define MPC85XX_CPU_BOARD_MINOR(rev) ((rev) & 0xff)
  38 +
  39 +#define MPC85XX_CPU_BOARD_REV_UNKNOWN MPC85XX_CPU_BOARD_REV(0,0)
  40 +#define MPC85XX_CPU_BOARD_REV_1_0 MPC85XX_CPU_BOARD_REV(1,0)
  41 +#define MPC85XX_CPU_BOARD_REV_1_1 MPC85XX_CPU_BOARD_REV(1,1)
  42 +
  43 +/*
  44 + * Returns CPU board revision register as a 16-bit value with
  45 + * the Major in the high byte, and Minor in the low byte.
  46 + */
  47 +extern unsigned int get_cpu_board_revision(void);
  48 +
  49 +
  50 +#endif /* __CADMUS_H_ */
board/cds/mpc8541cds/Makefile
Diff comments   View file @ 03f5c55
  1 +#
  2 +# Copyright 2004 Freescale Semiconductor.
  3 +# (C) Copyright 2001
  4 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5 +#
  6 +# See file CREDITS for list of people who contributed to this
  7 +# project.
  8 +#
  9 +# This program is free software; you can redistribute it and/or
  10 +# modify it under the terms of the GNU General Public License as
  11 +# published by the Free Software Foundation; either version 2 of
  12 +# the License, or (at your option) any later version.
  13 +#
  14 +# This program is distributed in the hope that it will be useful,
  15 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 +# GNU General Public License for more details.
  18 +#
  19 +# You should have received a copy of the GNU General Public License
  20 +# along with this program; if not, write to the Free Software
  21 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 +# MA 02111-1307 USA
  23 +#
  24 +
  25 +include $(TOPDIR)/config.mk
  26 +
  27 +LIB = lib$(BOARD).a
  28 +
  29 +OBJS := $(BOARD).o \
  30 + ../common/cadmus.o \
  31 + ../common/eeprom.o
  32 +
  33 +SOBJS := init.o
  34 +
  35 +$(LIB): $(OBJS) $(SOBJS)
  36 + $(AR) crv $@ $(OBJS)
  37 +
  38 +clean:
  39 + rm -f $(OBJS) $(SOBJS)
  40 +
  41 +distclean: clean
  42 + rm -f $(LIB) core *.bak .depend
  43 +
  44 +#########################################################################
  45 +
  46 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  47 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  48 +
  49 +-include .depend
  50 +
  51 +#########################################################################
board/cds/mpc8541cds/config.mk
Diff comments   View file @ 03f5c55
  1 +#
  2 +# Copyright 2004 Freescale Semiconductor.
  3 +#
  4 +# See file CREDITS for list of people who contributed to this
  5 +# project.
  6 +#
  7 +# This program is free software; you can redistribute it and/or
  8 +# modify it under the terms of the GNU General Public License as
  9 +# published by the Free Software Foundation; either version 2 of
  10 +# the License, or (at your option) any later version.
  11 +#
  12 +# This program is distributed in the hope that it will be useful,
  13 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 +# GNU General Public License for more details.
  16 +#
  17 +# You should have received a copy of the GNU General Public License
  18 +# along with this program; if not, write to the Free Software
  19 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 +# MA 02111-1307 USA
  21 +#
  22 +
  23 +#
  24 +# mpc8541cds board
  25 +#
  26 +TEXT_BASE = 0xfff80000
  27 +
  28 +PLATFORM_CPPFLAGS += -DCONFIG_E500=1
  29 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
  30 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8541=1
board/cds/mpc8541cds/init.S
Diff comments   View file @ 03f5c55
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor.
  3 + * Copyright 2002,2003, Motorola Inc.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <ppc_asm.tmpl>
  25 +#include <ppc_defs.h>
  26 +#include <asm/cache.h>
  27 +#include <asm/mmu.h>
  28 +#include <config.h>
  29 +#include <mpc85xx.h>
  30 +
  31 +
  32 +/*
  33 + * TLB0 and TLB1 Entries
  34 + *
  35 + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
  36 + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
  37 + * these TLB entries are established.
  38 + *
  39 + * The TLB entries for DDR are dynamically setup in spd_sdram()
  40 + * and use TLB1 Entries 8 through 15 as needed according to the
  41 + * size of DDR memory.
  42 + *
  43 + * MAS0: tlbsel, esel, nv
  44 + * MAS1: valid, iprot, tid, ts, tsize
  45 + * MAS2: epn, sharen, x0, x1, w, i, m, g, e
  46 + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  47 + */
  48 +
  49 +#define entry_start \
  50 + mflr r1 ; \
  51 + bl 0f ;
  52 +
  53 +#define entry_end \
  54 +0: mflr r0 ; \
  55 + mtlr r1 ; \
  56 + blr ;
  57 +
  58 +
  59 + .section .bootpg, "ax"
  60 + .globl tlb1_entry
  61 +tlb1_entry:
  62 + entry_start
  63 +
  64 + /*
  65 + * Number of TLB0 and TLB1 entries in the following table
  66 + */
  67 + .long 13
  68 +
  69 +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
  70 + /*
  71 + * TLB0 4K Non-cacheable, guarded
  72 + * 0xff700000 4K Initial CCSRBAR mapping
  73 + *
  74 + * This ends up at a TLB0 Index==0 entry, and must not collide
  75 + * with other TLB0 Entries.
  76 + */
  77 + .long TLB1_MAS0(0, 0, 0)
  78 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  79 + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
  80 + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
  81 +#else
  82 +#error("Update the number of table entries in tlb1_entry")
  83 +#endif
  84 +
  85 + /*
  86 + * TLB0 16K Cacheable, non-guarded
  87 + * 0xd001_0000 16K Temporary Global data for initialization
  88 + *
  89 + * Use four 4K TLB0 entries. These entries must be cacheable
  90 + * as they provide the bootstrap memory before the memory
  91 + * controler and real memory have been configured.
  92 + *
  93 + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
  94 + * and must not collide with other TLB0 entries.
  95 + */
  96 + .long TLB1_MAS0(0, 0, 0)
  97 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  98 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
  99 + 0,0,0,0,0,0,0,0)
  100 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
  101 + 0,0,0,0,0,1,0,1,0,1)
  102 +
  103 + .long TLB1_MAS0(0, 0, 0)
  104 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  105 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
  106 + 0,0,0,0,0,0,0,0)
  107 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
  108 + 0,0,0,0,0,1,0,1,0,1)
  109 +
  110 + .long TLB1_MAS0(0, 0, 0)
  111 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  112 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
  113 + 0,0,0,0,0,0,0,0)
  114 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
  115 + 0,0,0,0,0,1,0,1,0,1)
  116 +
  117 + .long TLB1_MAS0(0, 0, 0)
  118 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  119 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
  120 + 0,0,0,0,0,0,0,0)
  121 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
  122 + 0,0,0,0,0,1,0,1,0,1)
  123 +
  124 +
  125 + /*
  126 + * TLB 0: 16M Non-cacheable, guarded
  127 + * 0xff000000 16M FLASH
  128 + * Out of reset this entry is only 4K.
  129 + */
  130 + .long TLB1_MAS0(1, 0, 0)
  131 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
  132 + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
  133 + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
  134 +
  135 + /*
  136 + * TLB 1: 256M Non-cacheable, guarded
  137 + * 0x80000000 256M PCI1 MEM First half
  138 + */
  139 + .long TLB1_MAS0(1, 1, 0)
  140 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  141 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
  142 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
  143 +
  144 + /*
  145 + * TLB 2: 256M Non-cacheable, guarded
  146 + * 0x90000000 256M PCI1 MEM Second half
  147 + */
  148 + .long TLB1_MAS0(1, 2, 0)
  149 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  150 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
  151 + 0,0,0,0,1,0,1,0)
  152 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
  153 + 0,0,0,0,0,1,0,1,0,1)
  154 +
  155 + /*
  156 + * TLB 3: 256M Non-cacheable, guarded
  157 + * 0xa0000000 256M PCI2 MEM First half
  158 + */
  159 + .long TLB1_MAS0(1, 3, 0)
  160 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  161 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
  162 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
  163 +
  164 + /*
  165 + * TLB 4: 256M Non-cacheable, guarded
  166 + * 0xb0000000 256M PCI2 MEM Second half
  167 + */
  168 + .long TLB1_MAS0(1, 4, 0)
  169 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  170 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
  171 + 0,0,0,0,1,0,1,0)
  172 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
  173 + 0,0,0,0,0,1,0,1,0,1)
  174 +
  175 + /*
  176 + * TLB 5: 64M Non-cacheable, guarded
  177 + * 0xe000_0000 1M CCSRBAR
  178 + * 0xe200_0000 16M PCI1 IO
  179 + * 0xe300_0000 16M PCI2 IO
  180 + */
  181 + .long TLB1_MAS0(1, 5, 0)
  182 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  183 + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
  184 + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
  185 +
  186 + /*
  187 + * TLB 6: 64M Cacheable, non-guarded
  188 + * 0xf000_0000 64M LBC SDRAM
  189 + */
  190 + .long TLB1_MAS0(1, 6, 0)
  191 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  192 + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
  193 + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
  194 +
  195 + /*
  196 + * TLB 7: 1M Non-cacheable, guarded
  197 + * 0xf8000000 1M CADMUS registers
  198 + */
  199 + .long TLB1_MAS0(1, 7, 0)
  200 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
  201 + .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
  202 + .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
  203 +
  204 + entry_end
  205 +
  206 +/*
  207 + * LAW(Local Access Window) configuration:
  208 + *
  209 + * 0x0000_0000 0x7fff_ffff DDR 2G
  210 + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
  211 + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
  212 + * 0xe000_0000 0xe000_ffff CCSR 1M
  213 + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
  214 + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
  215 + * 0xf000_0000 0xf7ff_ffff SDRAM 128M
  216 + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
  217 + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
  218 + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
  219 + *
  220 + * Notes:
  221 + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  222 + * If flash is 8M at default position (last 8M), no LAW needed.
  223 + *
  224 + * The defines below are 1-off of the actual LAWAR0 usage.
  225 + * So LAWAR3 define uses the LAWAR4 register in the ECM.
  226 + */
  227 +
  228 +#define LAWBAR0 0
  229 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
  230 +
  231 +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
  232 +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
  233 +
  234 +#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
  235 +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
  236 +
  237 +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
  238 +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
  239 +
  240 +#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
  241 +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
  242 +
  243 +/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
  244 +#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
  245 +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
  246 +
  247 + .section .bootpg, "ax"
  248 + .globl law_entry
  249 +
  250 +law_entry:
  251 + entry_start
  252 + .long 6
  253 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
  254 + .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
  255 + entry_end
board/cds/mpc8541cds/mpc8541cds.c
Diff comments   View file @ 03f5c55
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor.
  3 + *
  4 + * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +
  25 +
  26 +#include <common.h>
  27 +#include <pci.h>
  28 +#include <asm/processor.h>
  29 +#include <asm/immap_85xx.h>
  30 +#include <spd.h>
  31 +
  32 +#include "../common/cadmus.h"
  33 +#include "../common/eeprom.h"
  34 +
  35 +#if defined(CONFIG_DDR_ECC)
  36 +extern void ddr_enable_ecc(unsigned int dram_size);
  37 +#endif
  38 +
  39 +extern long int spd_sdram(void);
  40 +
  41 +void local_bus_init(void);
  42 +void sdram_init(void);
  43 +
  44 +
  45 +
  46 +int
  47 +board_early_init_f(void)
  48 +{
  49 + return 0;
  50 +}
  51 +
  52 +
  53 +int
  54 +checkboard(void)
  55 +{
  56 + volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
  57 + volatile ccsr_gur_t *gur = &immap->im_gur;
  58 +
  59 + /* PCI slot in USER bits CSR[6:7] by convention. */
  60 + uint pci_slot = get_pci_slot();
  61 +
  62 + uint pci_dual = get_pci_dual(); /* PCI DUAL in CM_PCI[3] */
  63 + uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
  64 + uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
  65 + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
  66 +
  67 + uint pci1_speed = get_clock_freq(); /* PCI PSPEED in [4:5] */
  68 +
  69 + uint cpu_board_rev = get_cpu_board_revision();
  70 +
  71 + printf("Board: CDS Version 0x%02x, PCI Slot %d\n",
  72 + get_board_version(),
  73 + pci_slot);
  74 +
  75 + printf("CPU Board Revision %d.%d (0x%04x)\n",
  76 + MPC85XX_CPU_BOARD_MAJOR(cpu_board_rev),
  77 + MPC85XX_CPU_BOARD_MINOR(cpu_board_rev),
  78 + cpu_board_rev);
  79 +
  80 + printf(" PCI1: %d bit, %s MHz, %s\n",
  81 + (pci1_32) ? 32 : 64,
  82 + (pci1_speed == 33000000) ? "33" :
  83 + (pci1_speed == 66000000) ? "66" : "unknown",
  84 + pci1_clk_sel ? "sync" : "async"
  85 + );
  86 +
  87 + if (pci_dual) {
  88 + printf(" PCI2: 32 bit, 66 MHz, %s\n",
  89 + pci2_clk_sel ? "sync" : "async"
  90 + );
  91 + } else {
  92 + printf(" PCI2: disabled\n");
  93 + }
  94 +
  95 + /*
  96 + * Initialize local bus.
  97 + */
  98 + local_bus_init();
  99 +
  100 + return 0;
  101 +}
  102 +
  103 +
  104 +long int
  105 +initdram(int board_type)
  106 +{
  107 + long dram_size = 0;
  108 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  109 +
  110 + puts("Initializing\n");
  111 +
  112 +#if defined(CONFIG_DDR_DLL)
  113 + {
  114 + /*
  115 + * Work around to stabilize DDR DLL MSYNC_IN.
  116 + * Errata DDR9 seems to have been fixed.
  117 + * This is now the workaround for Errata DDR11:
  118 + * Override DLL = 1, Course Adj = 1, Tap Select = 0
  119 + */
  120 +
  121 + volatile ccsr_gur_t *gur= &immap->im_gur;
  122 +
  123 + gur->ddrdllcr = 0x81000000;
  124 + asm("sync;isync;msync");
  125 + udelay(200);
  126 + }
  127 +#endif
  128 +
  129 + dram_size = spd_sdram();
  130 +
  131 +
  132 +#if defined(CONFIG_DDR_ECC)
  133 + /*
  134 + * Initialize and enable DDR ECC.
  135 + */
  136 + ddr_enable_ecc(dram_size);
  137 +#endif
  138 +
  139 +
  140 + /*
  141 + * SDRAM Initialization
  142 + */
  143 + sdram_init();
  144 +
  145 + puts(" DDR: ");
  146 + return dram_size;
  147 +}
  148 +
  149 +
  150 +/*
  151 + * Initialize Local Bus
  152 + */
  153 +
  154 +void
  155 +local_bus_init(void)
  156 +{
  157 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  158 + volatile ccsr_gur_t *gur = &immap->im_gur;
  159 + volatile ccsr_lbc_t *lbc = &immap->im_lbc;
  160 +
  161 + uint clkdiv;
  162 + uint lbc_hz;
  163 + sys_info_t sysinfo;
  164 + uint temp_lbcdll;
  165 +
  166 + /*
  167 + * Errata LBC11.
  168 + * Fix Local Bus clock glitch when DLL is enabled.
  169 + *
  170 + * If localbus freq is < 66Mhz, DLL bypass mode must be used.
  171 + * If localbus freq is > 133Mhz, DLL can be safely enabled.
  172 + * Between 66 and 133, the DLL is enabled with an override workaround.
  173 + */
  174 +
  175 + get_sys_info(&sysinfo);
  176 + clkdiv = lbc->lcrr & 0x0f;
  177 + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
  178 +
  179 + if (lbc_hz < 66) {
  180 + lbc->lcrr |= 0x80000000; /* DLL Bypass */
  181 +
  182 + } else if (lbc_hz >= 133) {
  183 + lbc->lcrr &= (~0x80000000); /* DLL Enabled */
  184 +
  185 + } else {
  186 + lbc->lcrr &= (~0x8000000); /* DLL Enabled */
  187 + udelay(200);
  188 +
  189 + /*
  190 + * Sample LBC DLL ctrl reg, upshift it to set the
  191 + * override bits.
  192 + */
  193 + temp_lbcdll = gur->lbcdllcr;
  194 + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
  195 + asm("sync;isync;msync");
  196 + }
  197 +}
  198 +
  199 +
  200 +/*
  201 + * Initialize SDRAM memory on the Local Bus.
  202 + */
  203 +
  204 +void
  205 +sdram_init(void)
  206 +{
  207 +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
  208 +
  209 + uint idx;
  210 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  211 + volatile ccsr_lbc_t *lbc = &immap->im_lbc;
  212 + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
  213 + uint cpu_board_rev;
  214 + uint lsdmr_common;
  215 +
  216 + puts(" SDRAM: ");
  217 +
  218 + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
  219 +
  220 + /*
  221 + * Setup SDRAM Base and Option Registers
  222 + */
  223 + lbc->or2 = CFG_OR2_PRELIM;
  224 + asm("msync");
  225 +
  226 + lbc->br2 = CFG_BR2_PRELIM;
  227 + asm("msync");
  228 +
  229 + lbc->lbcr = CFG_LBC_LBCR;
  230 + asm("msync");
  231 +
  232 +
  233 + lbc->lsrt = CFG_LBC_LSRT;
  234 + lbc->mrtpr = CFG_LBC_MRTPR;
  235 + asm("msync");
  236 +
  237 + /*
  238 + * Determine which address lines to use baed on CPU board rev.
  239 + */
  240 + cpu_board_rev = get_cpu_board_revision();
  241 + lsdmr_common = CFG_LBC_LSDMR_COMMON;
  242 + if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
  243 + lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
  244 + } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
  245 + lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
  246 + } else {
  247 + /*
  248 + * Assume something unable to identify itself is
  249 + * really old, and likely has lines 16/17 mapped.
  250 + */
  251 + lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
  252 + }
  253 +
  254 + /*
  255 + * Issue PRECHARGE ALL command.
  256 + */
  257 + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
  258 + asm("sync;msync");
  259 + *sdram_addr = 0xff;
  260 + ppcDcbf((unsigned long) sdram_addr);
  261 + udelay(100);
  262 +
  263 + /*
  264 + * Issue 8 AUTO REFRESH commands.
  265 + */
  266 + for (idx = 0; idx < 8; idx++) {
  267 + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
  268 + asm("sync;msync");
  269 + *sdram_addr = 0xff;
  270 + ppcDcbf((unsigned long) sdram_addr);
  271 + udelay(100);
  272 + }
  273 +
  274 + /*
  275 + * Issue 8 MODE-set command.
  276 + */
  277 + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
  278 + asm("sync;msync");
  279 + *sdram_addr = 0xff;
  280 + ppcDcbf((unsigned long) sdram_addr);
  281 + udelay(100);
  282 +
  283 + /*
  284 + * Issue NORMAL OP command.
  285 + */
  286 + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
  287 + asm("sync;msync");
  288 + *sdram_addr = 0xff;
  289 + ppcDcbf((unsigned long) sdram_addr);
  290 + udelay(200); /* Overkill. Must wait > 200 bus cycles */
  291 +
  292 +#endif /* enable SDRAM init */
  293 +}
  294 +
  295 +
  296 +#if defined(CFG_DRAM_TEST)
  297 +int
  298 +testdram(void)
  299 +{
  300 + uint *pstart = (uint *) CFG_MEMTEST_START;
  301 + uint *pend = (uint *) CFG_MEMTEST_END;
  302 + uint *p;
  303 +
  304 + printf("Testing DRAM from 0x%08x to 0x%08x\n",
  305 + CFG_MEMTEST_START,
  306 + CFG_MEMTEST_END);
  307 +
  308 + printf("DRAM test phase 1:\n");
  309 + for (p = pstart; p < pend; p++)
  310 + *p = 0xaaaaaaaa;
  311 +
  312 + for (p = pstart; p < pend; p++) {
  313 + if (*p != 0xaaaaaaaa) {
  314 + printf ("DRAM test fails at: %08x\n", (uint) p);
  315 + return 1;
  316 + }
  317 + }
  318 +
  319 + printf("DRAM test phase 2:\n");
  320 + for (p = pstart; p < pend; p++)
  321 + *p = 0x55555555;
  322 +
  323 + for (p = pstart; p < pend; p++) {
  324 + if (*p != 0x55555555) {
  325 + printf ("DRAM test fails at: %08x\n", (uint) p);
  326 + return 1;
  327 + }
  328 + }
  329 +
  330 + printf("DRAM test passed.\n");
  331 + return 0;
  332 +}
  333 +#endif
  334 +
  335 +
  336 +
  337 +#if defined(CONFIG_PCI)
  338 +
  339 +/*
  340 + * Initialize PCI Devices, report devices found.
  341 + */
  342 +
  343 +#ifndef CONFIG_PCI_PNP
  344 +static struct pci_config_table pci_mpc85xxcds_config_table[] = {
  345 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  346 + PCI_IDSEL_NUMBER, PCI_ANY_ID,
  347 + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
  348 + PCI_ENET0_MEMADDR,
  349 + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
  350 + } },
  351 + { }
  352 +};
  353 +#endif
  354 +
  355 +
  356 +static struct pci_controller hose = {
  357 +#ifndef CONFIG_PCI_PNP
  358 + config_table: pci_mpc85xxcds_config_table,
  359 +#endif
  360 +};
  361 +
  362 +#endif /* CONFIG_PCI */
  363 +
  364 +
  365 +void
  366 +pci_init_board(void)
  367 +{
  368 +#ifdef CONFIG_PCI
  369 + extern void pci_mpc85xx_init(struct pci_controller *hose);
  370 +
  371 + pci_mpc85xx_init(&hose);
  372 +#endif
  373 +}
board/cds/mpc8541cds/u-boot.lds
Diff comments   View file @ 03f5c55
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +OUTPUT_ARCH(powerpc)
  24 +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
  25 +/* Do we need any of these for elf?
  26 + __DYNAMIC = 0; */
  27 +SECTIONS
  28 +{
  29 + .resetvec 0xFFFFFFFC :
  30 + {
  31 + *(.resetvec)
  32 + } = 0xffff
  33 +
  34 + .bootpg 0xFFFFF000 :
  35 + {
  36 + cpu/mpc85xx/start.o (.bootpg)
  37 + board/cds/mpc8541cds/init.o (.bootpg)
  38 + } = 0xffff
  39 +
  40 + /* Read-only sections, merged into text segment: */
  41 + . = + SIZEOF_HEADERS;
  42 + .interp : { *(.interp) }
  43 + .hash : { *(.hash) }
  44 + .dynsym : { *(.dynsym) }
  45 + .dynstr : { *(.dynstr) }
  46 + .rel.text : { *(.rel.text) }
  47 + .rela.text : { *(.rela.text) }
  48 + .rel.data : { *(.rel.data) }
  49 + .rela.data : { *(.rela.data) }
  50 + .rel.rodata : { *(.rel.rodata) }
  51 + .rela.rodata : { *(.rela.rodata) }
  52 + .rel.got : { *(.rel.got) }
  53 + .rela.got : { *(.rela.got) }
  54 + .rel.ctors : { *(.rel.ctors) }
  55 + .rela.ctors : { *(.rela.ctors) }
  56 + .rel.dtors : { *(.rel.dtors) }
  57 + .rela.dtors : { *(.rela.dtors) }
  58 + .rel.bss : { *(.rel.bss) }
  59 + .rela.bss : { *(.rela.bss) }
  60 + .rel.plt : { *(.rel.plt) }
  61 + .rela.plt : { *(.rela.plt) }
  62 + .init : { *(.init) }
  63 + .plt : { *(.plt) }
  64 + .text :
  65 + {
  66 + cpu/mpc85xx/start.o (.text)
  67 + board/cds/mpc8541cds/init.o (.text)
  68 + cpu/mpc85xx/traps.o (.text)
  69 + cpu/mpc85xx/interrupts.o (.text)
  70 + cpu/mpc85xx/cpu_init.o (.text)
  71 + cpu/mpc85xx/cpu.o (.text)
  72 + cpu/mpc85xx/tsec.o (.text)
  73 + cpu/mpc85xx/speed.o (.text)
  74 + cpu/mpc85xx/pci.o (.text)
  75 + common/dlmalloc.o (.text)
  76 + lib_generic/crc32.o (.text)
  77 + lib_ppc/extable.o (.text)
  78 + lib_generic/zlib.o (.text)
  79 + *(.text)
  80 + *(.fixup)
  81 + *(.got1)
  82 + }
  83 + _etext = .;
  84 + PROVIDE (etext = .);
  85 + .rodata :
  86 + {
  87 + *(.rodata)
  88 + *(.rodata1)
  89 + *(.rodata.str1.4)
  90 + }
  91 + .fini : { *(.fini) } =0
  92 + .ctors : { *(.ctors) }
  93 + .dtors : { *(.dtors) }
  94 +
  95 + /* Read-write section, merged into data segment: */
  96 + . = (. + 0x00FF) & 0xFFFFFF00;
  97 + _erotext = .;
  98 + PROVIDE (erotext = .);
  99 + .reloc :
  100 + {
  101 + *(.got)
  102 + _GOT2_TABLE_ = .;
  103 + *(.got2)
  104 + _FIXUP_TABLE_ = .;
  105 + *(.fixup)
  106 + }
  107 + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
  108 + __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
  109 +
  110 + .data :
  111 + {
  112 + *(.data)
  113 + *(.data1)
  114 + *(.sdata)
  115 + *(.sdata2)
  116 + *(.dynamic)
  117 + CONSTRUCTORS
  118 + }
  119 + _edata = .;
  120 + PROVIDE (edata = .);
  121 +
  122 + __u_boot_cmd_start = .;
  123 + .u_boot_cmd : { *(.u_boot_cmd) }
  124 + __u_boot_cmd_end = .;
  125 +
  126 + __start___ex_table = .;
  127 + __ex_table : { *(__ex_table) }
  128 + __stop___ex_table = .;
  129 +
  130 + . = ALIGN(256);
  131 + __init_begin = .;
  132 + .text.init : { *(.text.init) }
  133 + .data.init : { *(.data.init) }
  134 + . = ALIGN(256);
  135 + __init_end = .;
  136 +
  137 + __bss_start = .;
  138 + .bss :
  139 + {
  140 + *(.sbss) *(.scommon)
  141 + *(.dynbss)
  142 + *(.bss)
  143 + *(COMMON)
  144 + }
  145 + _end = . ;
  146 + PROVIDE (end = .);
  147 +}
board/cds/mpc8555cds/Makefile
Diff comments   View file @ 03f5c55
  1 +#
  2 +# Copyright 2004 Freescale Semiconductor.
  3 +# (C) Copyright 2001
  4 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5 +#
  6 +# See file CREDITS for list of people who contributed to this
  7 +# project.
  8 +#
  9 +# This program is free software; you can redistribute it and/or
  10 +# modify it under the terms of the GNU General Public License as
  11 +# published by the Free Software Foundation; either version 2 of
  12 +# the License, or (at your option) any later version.
  13 +#
  14 +# This program is distributed in the hope that it will be useful,
  15 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 +# GNU General Public License for more details.
  18 +#
  19 +# You should have received a copy of the GNU General Public License
  20 +# along with this program; if not, write to the Free Software
  21 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 +# MA 02111-1307 USA
  23 +#
  24 +
  25 +include $(TOPDIR)/config.mk
  26 +
  27 +LIB = lib$(BOARD).a
  28 +
  29 +OBJS := $(BOARD).o \
  30 + ../common/cadmus.o \
  31 + ../common/eeprom.o
  32 +
  33 +SOBJS := init.o
  34 +
  35 +$(LIB): $(OBJS) $(SOBJS)
  36 + $(AR) crv $@ $(OBJS)
  37 +
  38 +clean:
  39 + rm -f $(OBJS) $(SOBJS)
  40 +
  41 +distclean: clean
  42 + rm -f $(LIB) core *.bak .depend
  43 +
  44 +#########################################################################
  45 +
  46 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  47 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  48 +
  49 +-include .depend
  50 +
  51 +#########################################################################
board/cds/mpc8555cds/config.mk
Diff comments   View file @ 03f5c55
  1 +#
  2 +# Copyright 2004 Freescale Semiconductor.
  3 +#
  4 +# See file CREDITS for list of people who contributed to this
  5 +# project.
  6 +#
  7 +# This program is free software; you can redistribute it and/or
  8 +# modify it under the terms of the GNU General Public License as
  9 +# published by the Free Software Foundation; either version 2 of
  10 +# the License, or (at your option) any later version.
  11 +#
  12 +# This program is distributed in the hope that it will be useful,
  13 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 +# GNU General Public License for more details.
  16 +#
  17 +# You should have received a copy of the GNU General Public License
  18 +# along with this program; if not, write to the Free Software
  19 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 +# MA 02111-1307 USA
  21 +#
  22 +
  23 +#
  24 +# mpc8555cds board
  25 +#
  26 +TEXT_BASE = 0xfff80000
  27 +
  28 +PLATFORM_CPPFLAGS += -DCONFIG_E500=1
  29 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
  30 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8555=1
board/cds/mpc8555cds/init.S
Diff comments   View file @ 03f5c55
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor.
  3 + * Copyright 2002,2003, Motorola Inc.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <ppc_asm.tmpl>
  25 +#include <ppc_defs.h>
  26 +#include <asm/cache.h>
  27 +#include <asm/mmu.h>
  28 +#include <config.h>
  29 +#include <mpc85xx.h>
  30 +
  31 +
  32 +/*
  33 + * TLB0 and TLB1 Entries
  34 + *
  35 + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
  36 + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
  37 + * these TLB entries are established.
  38 + *
  39 + * The TLB entries for DDR are dynamically setup in spd_sdram()
  40 + * and use TLB1 Entries 8 through 15 as needed according to the
  41 + * size of DDR memory.
  42 + *
  43 + * MAS0: tlbsel, esel, nv
  44 + * MAS1: valid, iprot, tid, ts, tsize
  45 + * MAS2: epn, sharen, x0, x1, w, i, m, g, e
  46 + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  47 + */
  48 +
  49 +#define entry_start \
  50 + mflr r1 ; \
  51 + bl 0f ;
  52 +
  53 +#define entry_end \
  54 +0: mflr r0 ; \
  55 + mtlr r1 ; \
  56 + blr ;
  57 +
  58 +
  59 + .section .bootpg, "ax"
  60 + .globl tlb1_entry
  61 +tlb1_entry:
  62 + entry_start
  63 +
  64 + /*
  65 + * Number of TLB0 and TLB1 entries in the following table
  66 + */
  67 + .long 13
  68 +
  69 +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
  70 + /*
  71 + * TLB0 4K Non-cacheable, guarded
  72 + * 0xff700000 4K Initial CCSRBAR mapping
  73 + *
  74 + * This ends up at a TLB0 Index==0 entry, and must not collide
  75 + * with other TLB0 Entries.
  76 + */
  77 + .long TLB1_MAS0(0, 0, 0)
  78 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  79 + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
  80 + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
  81 +#else
  82 +#error("Update the number of table entries in tlb1_entry")
  83 +#endif
  84 +
  85 + /*
  86 + * TLB0 16K Cacheable, non-guarded
  87 + * 0xd001_0000 16K Temporary Global data for initialization
  88 + *
  89 + * Use four 4K TLB0 entries. These entries must be cacheable
  90 + * as they provide the bootstrap memory before the memory
  91 + * controler and real memory have been configured.
  92 + *
  93 + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
  94 + * and must not collide with other TLB0 entries.
  95 + */
  96 + .long TLB1_MAS0(0, 0, 0)
  97 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  98 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
  99 + 0,0,0,0,0,0,0,0)
  100 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
  101 + 0,0,0,0,0,1,0,1,0,1)
  102 +
  103 + .long TLB1_MAS0(0, 0, 0)
  104 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  105 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
  106 + 0,0,0,0,0,0,0,0)
  107 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
  108 + 0,0,0,0,0,1,0,1,0,1)
  109 +
  110 + .long TLB1_MAS0(0, 0, 0)
  111 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  112 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
  113 + 0,0,0,0,0,0,0,0)
  114 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
  115 + 0,0,0,0,0,1,0,1,0,1)
  116 +
  117 + .long TLB1_MAS0(0, 0, 0)
  118 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  119 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
  120 + 0,0,0,0,0,0,0,0)
  121 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
  122 + 0,0,0,0,0,1,0,1,0,1)
  123 +
  124 +
  125 + /*
  126 + * TLB 0: 16M Non-cacheable, guarded
  127 + * 0xff000000 16M FLASH
  128 + * Out of reset this entry is only 4K.
  129 + */
  130 + .long TLB1_MAS0(1, 0, 0)
  131 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
  132 + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
  133 + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
  134 +
  135 + /*
  136 + * TLB 1: 256M Non-cacheable, guarded
  137 + * 0x80000000 256M PCI1 MEM First half
  138 + */
  139 + .long TLB1_MAS0(1, 1, 0)
  140 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  141 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
  142 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
  143 +
  144 + /*
  145 + * TLB 2: 256M Non-cacheable, guarded
  146 + * 0x90000000 256M PCI1 MEM Second half
  147 + */
  148 + .long TLB1_MAS0(1, 2, 0)
  149 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  150 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
  151 + 0,0,0,0,1,0,1,0)
  152 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
  153 + 0,0,0,0,0,1,0,1,0,1)
  154 +
  155 + /*
  156 + * TLB 3: 256M Non-cacheable, guarded
  157 + * 0xa0000000 256M PCI2 MEM First half
  158 + */
  159 + .long TLB1_MAS0(1, 3, 0)
  160 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  161 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
  162 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
  163 +
  164 + /*
  165 + * TLB 4: 256M Non-cacheable, guarded
  166 + * 0xb0000000 256M PCI2 MEM Second half
  167 + */
  168 + .long TLB1_MAS0(1, 4, 0)
  169 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  170 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
  171 + 0,0,0,0,1,0,1,0)
  172 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
  173 + 0,0,0,0,0,1,0,1,0,1)
  174 +
  175 + /*
  176 + * TLB 5: 64M Non-cacheable, guarded
  177 + * 0xe000_0000 1M CCSRBAR
  178 + * 0xe200_0000 16M PCI1 IO
  179 + * 0xe300_0000 16M PCI2 IO
  180 + */
  181 + .long TLB1_MAS0(1, 5, 0)
  182 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  183 + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
  184 + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
  185 +
  186 + /*
  187 + * TLB 6: 64M Cacheable, non-guarded
  188 + * 0xf000_0000 64M LBC SDRAM
  189 + */
  190 + .long TLB1_MAS0(1, 6, 0)
  191 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  192 + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
  193 + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
  194 +
  195 + /*
  196 + * TLB 7: 1M Non-cacheable, guarded
  197 + * 0xf8000000 1M CADMUS registers
  198 + */
  199 + .long TLB1_MAS0(1, 7, 0)
  200 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
  201 + .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
  202 + .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
  203 +
  204 + entry_end
  205 +
  206 +/*
  207 + * LAW(Local Access Window) configuration:
  208 + *
  209 + * 0x0000_0000 0x7fff_ffff DDR 2G
  210 + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
  211 + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
  212 + * 0xe000_0000 0xe000_ffff CCSR 1M
  213 + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
  214 + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
  215 + * 0xf000_0000 0xf7ff_ffff SDRAM 128M
  216 + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
  217 + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
  218 + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
  219 + *
  220 + * Notes:
  221 + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  222 + * If flash is 8M at default position (last 8M), no LAW needed.
  223 + *
  224 + * The defines below are 1-off of the actual LAWAR0 usage.
  225 + * So LAWAR3 define uses the LAWAR4 register in the ECM.
  226 + */
  227 +
  228 +#define LAWBAR0 0
  229 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
  230 +
  231 +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
  232 +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
  233 +
  234 +#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
  235 +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
  236 +
  237 +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
  238 +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
  239 +
  240 +#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
  241 +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
  242 +
  243 +/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
  244 +#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
  245 +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
  246 +
  247 + .section .bootpg, "ax"
  248 + .globl law_entry
  249 +
  250 +law_entry:
  251 + entry_start
  252 + .long 6
  253 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
  254 + .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
  255 + entry_end
board/cds/mpc8555cds/mpc8555cds.c
Diff comments   View file @ 03f5c55
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +
  24 +#include <common.h>
  25 +#include <pci.h>
  26 +#include <asm/processor.h>
  27 +#include <asm/immap_85xx.h>
  28 +#include <spd.h>
  29 +
  30 +#include "../common/cadmus.h"
  31 +#include "../common/eeprom.h"
  32 +
  33 +#if defined(CONFIG_DDR_ECC)
  34 +extern void ddr_enable_ecc(unsigned int dram_size);
  35 +#endif
  36 +
  37 +extern long int spd_sdram(void);
  38 +
  39 +void local_bus_init(void);
  40 +void sdram_init(void);
  41 +
  42 +
  43 +
  44 +int
  45 +board_early_init_f(void)
  46 +{
  47 + return 0;
  48 +}
  49 +
  50 +
  51 +int
  52 +checkboard(void)
  53 +{
  54 + volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
  55 + volatile ccsr_gur_t *gur = &immap->im_gur;
  56 +
  57 + /* PCI slot in USER bits CSR[6:7] by convention. */
  58 + uint pci_slot = get_pci_slot();
  59 +
  60 + uint pci_dual = get_pci_dual(); /* PCI DUAL in CM_PCI[3] */
  61 + uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
  62 + uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
  63 + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
  64 +
  65 + uint pci1_speed = get_clock_freq(); /* PCI PSPEED in [4:5] */
  66 +
  67 + uint cpu_board_rev = get_cpu_board_revision();
  68 +
  69 + printf("Board: CDS Version 0x%02x, PCI Slot %d\n",
  70 + get_board_version(),
  71 + pci_slot);
  72 +
  73 + printf("CPU Board Revision %d.%d (0x%04x)\n",
  74 + MPC85XX_CPU_BOARD_MAJOR(cpu_board_rev),
  75 + MPC85XX_CPU_BOARD_MINOR(cpu_board_rev),
  76 + cpu_board_rev);
  77 +
  78 + printf(" PCI1: %d bit, %s MHz, %s\n",
  79 + (pci1_32) ? 32 : 64,
  80 + (pci1_speed == 33000000) ? "33" :
  81 + (pci1_speed == 66000000) ? "66" : "unknown",
  82 + pci1_clk_sel ? "sync" : "async"
  83 + );
  84 +
  85 + if (pci_dual) {
  86 + printf(" PCI2: 32 bit, 66 MHz, %s\n",
  87 + pci2_clk_sel ? "sync" : "async"
  88 + );
  89 + } else {
  90 + printf(" PCI2: disabled\n");
  91 + }
  92 +
  93 + /*
  94 + * Initialize local bus.
  95 + */
  96 + local_bus_init();
  97 +
  98 + return 0;
  99 +}
  100 +
  101 +
  102 +long int
  103 +initdram(int board_type)
  104 +{
  105 + long dram_size = 0;
  106 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  107 +
  108 + puts("Initializing\n");
  109 +
  110 +#if defined(CONFIG_DDR_DLL)
  111 + {
  112 + /*
  113 + * Work around to stabilize DDR DLL MSYNC_IN.
  114 + * Errata DDR9 seems to have been fixed.
  115 + * This is now the workaround for Errata DDR11:
  116 + * Override DLL = 1, Course Adj = 1, Tap Select = 0
  117 + */
  118 +
  119 + volatile ccsr_gur_t *gur= &immap->im_gur;
  120 +
  121 + gur->ddrdllcr = 0x81000000;
  122 + asm("sync;isync;msync");
  123 + udelay(200);
  124 + }
  125 +#endif
  126 +
  127 + dram_size = spd_sdram();
  128 +
  129 +
  130 +#if defined(CONFIG_DDR_ECC)
  131 + /*
  132 + * Initialize and enable DDR ECC.
  133 + */
  134 + ddr_enable_ecc(dram_size);
  135 +#endif
  136 +
  137 +
  138 + /*
  139 + * SDRAM Initialization
  140 + */
  141 + sdram_init();
  142 +
  143 + puts(" DDR: ");
  144 + return dram_size;
  145 +}
  146 +
  147 +
  148 +/*
  149 + * Initialize Local Bus
  150 + */
  151 +
  152 +void
  153 +local_bus_init(void)
  154 +{
  155 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  156 + volatile ccsr_gur_t *gur = &immap->im_gur;
  157 + volatile ccsr_lbc_t *lbc = &immap->im_lbc;
  158 +
  159 + uint clkdiv;
  160 + uint lbc_hz;
  161 + sys_info_t sysinfo;
  162 + uint temp_lbcdll;
  163 +
  164 + /*
  165 + * Errata LBC11.
  166 + * Fix Local Bus clock glitch when DLL is enabled.
  167 + *
  168 + * If localbus freq is < 66Mhz, DLL bypass mode must be used.
  169 + * If localbus freq is > 133Mhz, DLL can be safely enabled.
  170 + * Between 66 and 133, the DLL is enabled with an override workaround.
  171 + */
  172 +
  173 + get_sys_info(&sysinfo);
  174 + clkdiv = lbc->lcrr & 0x0f;
  175 + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
  176 +
  177 + if (lbc_hz < 66) {
  178 + lbc->lcrr |= 0x80000000; /* DLL Bypass */
  179 +
  180 + } else if (lbc_hz >= 133) {
  181 + lbc->lcrr &= (~0x80000000); /* DLL Enabled */
  182 +
  183 + } else {
  184 + lbc->lcrr &= (~0x8000000); /* DLL Enabled */
  185 + udelay(200);
  186 +
  187 + /*
  188 + * Sample LBC DLL ctrl reg, upshift it to set the
  189 + * override bits.
  190 + */
  191 + temp_lbcdll = gur->lbcdllcr;
  192 + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
  193 + asm("sync;isync;msync");
  194 + }
  195 +}
  196 +
  197 +
  198 +/*
  199 + * Initialize SDRAM memory on the Local Bus.
  200 + */
  201 +
  202 +void
  203 +sdram_init(void)
  204 +{
  205 +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
  206 +
  207 + uint idx;
  208 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  209 + volatile ccsr_lbc_t *lbc = &immap->im_lbc;
  210 + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
  211 + uint cpu_board_rev;
  212 + uint lsdmr_common;
  213 +
  214 + puts(" SDRAM: ");
  215 +
  216 + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
  217 +
  218 + /*
  219 + * Setup SDRAM Base and Option Registers
  220 + */
  221 + lbc->or2 = CFG_OR2_PRELIM;
  222 + asm("msync");
  223 +
  224 + lbc->br2 = CFG_BR2_PRELIM;
  225 + asm("msync");
  226 +
  227 + lbc->lbcr = CFG_LBC_LBCR;
  228 + asm("msync");
  229 +
  230 +
  231 + lbc->lsrt = CFG_LBC_LSRT;
  232 + lbc->mrtpr = CFG_LBC_MRTPR;
  233 + asm("msync");
  234 +
  235 + /*
  236 + * Determine which address lines to use baed on CPU board rev.
  237 + */
  238 + cpu_board_rev = get_cpu_board_revision();
  239 + lsdmr_common = CFG_LBC_LSDMR_COMMON;
  240 + if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
  241 + lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
  242 + } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
  243 + lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
  244 + } else {
  245 + /*
  246 + * Assume something unable to identify itself is
  247 + * really old, and likely has lines 16/17 mapped.
  248 + */
  249 + lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
  250 + }
  251 +
  252 + /*
  253 + * Issue PRECHARGE ALL command.
  254 + */
  255 + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
  256 + asm("sync;msync");
  257 + *sdram_addr = 0xff;
  258 + ppcDcbf((unsigned long) sdram_addr);
  259 + udelay(100);
  260 +
  261 + /*
  262 + * Issue 8 AUTO REFRESH commands.
  263 + */
  264 + for (idx = 0; idx < 8; idx++) {
  265 + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
  266 + asm("sync;msync");
  267 + *sdram_addr = 0xff;
  268 + ppcDcbf((unsigned long) sdram_addr);
  269 + udelay(100);
  270 + }
  271 +
  272 + /*
  273 + * Issue 8 MODE-set command.
  274 + */
  275 + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
  276 + asm("sync;msync");
  277 + *sdram_addr = 0xff;
  278 + ppcDcbf((unsigned long) sdram_addr);
  279 + udelay(100);
  280 +
  281 + /*
  282 + * Issue NORMAL OP command.
  283 + */
  284 + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
  285 + asm("sync;msync");
  286 + *sdram_addr = 0xff;
  287 + ppcDcbf((unsigned long) sdram_addr);
  288 + udelay(200); /* Overkill. Must wait > 200 bus cycles */
  289 +
  290 +#endif /* enable SDRAM init */
  291 +}
  292 +
  293 +
  294 +#if defined(CFG_DRAM_TEST)
  295 +int
  296 +testdram(void)
  297 +{
  298 + uint *pstart = (uint *) CFG_MEMTEST_START;
  299 + uint *pend = (uint *) CFG_MEMTEST_END;
  300 + uint *p;
  301 +
  302 + printf("Testing DRAM from 0x%08x to 0x%08x\n",
  303 + CFG_MEMTEST_START,
  304 + CFG_MEMTEST_END);
  305 +
  306 + printf("DRAM test phase 1:\n");
  307 + for (p = pstart; p < pend; p++)
  308 + *p = 0xaaaaaaaa;
  309 +
  310 + for (p = pstart; p < pend; p++) {
  311 + if (*p != 0xaaaaaaaa) {
  312 + printf ("DRAM test fails at: %08x\n", (uint) p);
  313 + return 1;
  314 + }
  315 + }
  316 +
  317 + printf("DRAM test phase 2:\n");
  318 + for (p = pstart; p < pend; p++)
  319 + *p = 0x55555555;
  320 +
  321 + for (p = pstart; p < pend; p++) {
  322 + if (*p != 0x55555555) {
  323 + printf ("DRAM test fails at: %08x\n", (uint) p);
  324 + return 1;
  325 + }
  326 + }
  327 +
  328 + printf("DRAM test passed.\n");
  329 + return 0;
  330 +}
  331 +#endif
  332 +
  333 +
  334 +
  335 +#if defined(CONFIG_PCI)
  336 +
  337 +/*
  338 + * Initialize PCI Devices, report devices found.
  339 + */
  340 +
  341 +#ifndef CONFIG_PCI_PNP
  342 +static struct pci_config_table pci_mpc85xxcds_config_table[] = {
  343 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  344 + PCI_IDSEL_NUMBER, PCI_ANY_ID,
  345 + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
  346 + PCI_ENET0_MEMADDR,
  347 + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
  348 + } },
  349 + { }
  350 +};
  351 +#endif
  352 +
  353 +
  354 +static struct pci_controller hose = {
  355 +#ifndef CONFIG_PCI_PNP
  356 + config_table: pci_mpc85xxcds_config_table,
  357 +#endif
  358 +};
  359 +
  360 +#endif /* CONFIG_PCI */
  361 +
  362 +
  363 +void
  364 +pci_init_board(void)
  365 +{
  366 +#ifdef CONFIG_PCI
  367 + extern void pci_mpc85xx_init(struct pci_controller *hose);
  368 +
  369 + pci_mpc85xx_init(&hose);
  370 +#endif
  371 +}
board/cds/mpc8555cds/u-boot.lds
Diff comments   View file @ 03f5c55
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +OUTPUT_ARCH(powerpc)
  24 +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
  25 +/* Do we need any of these for elf?
  26 + __DYNAMIC = 0; */
  27 +SECTIONS
  28 +{
  29 + .resetvec 0xFFFFFFFC :
  30 + {
  31 + *(.resetvec)
  32 + } = 0xffff
  33 +
  34 + .bootpg 0xFFFFF000 :
  35 + {
  36 + cpu/mpc85xx/start.o (.bootpg)
  37 + board/cds/mpc8555cds/init.o (.bootpg)
  38 + } = 0xffff
  39 +
  40 + /* Read-only sections, merged into text segment: */
  41 + . = + SIZEOF_HEADERS;
  42 + .interp : { *(.interp) }
  43 + .hash : { *(.hash) }
  44 + .dynsym : { *(.dynsym) }
  45 + .dynstr : { *(.dynstr) }
  46 + .rel.text : { *(.rel.text) }
  47 + .rela.text : { *(.rela.text) }
  48 + .rel.data : { *(.rel.data) }
  49 + .rela.data : { *(.rela.data) }
  50 + .rel.rodata : { *(.rel.rodata) }
  51 + .rela.rodata : { *(.rela.rodata) }
  52 + .rel.got : { *(.rel.got) }
  53 + .rela.got : { *(.rela.got) }
  54 + .rel.ctors : { *(.rel.ctors) }
  55 + .rela.ctors : { *(.rela.ctors) }
  56 + .rel.dtors : { *(.rel.dtors) }
  57 + .rela.dtors : { *(.rela.dtors) }
  58 + .rel.bss : { *(.rel.bss) }
  59 + .rela.bss : { *(.rela.bss) }
  60 + .rel.plt : { *(.rel.plt) }
  61 + .rela.plt : { *(.rela.plt) }
  62 + .init : { *(.init) }
  63 + .plt : { *(.plt) }
  64 + .text :
  65 + {
  66 + cpu/mpc85xx/start.o (.text)
  67 + board/cds/mpc8555cds/init.o (.text)
  68 + cpu/mpc85xx/traps.o (.text)
  69 + cpu/mpc85xx/interrupts.o (.text)
  70 + cpu/mpc85xx/cpu_init.o (.text)
  71 + cpu/mpc85xx/cpu.o (.text)
  72 + cpu/mpc85xx/tsec.o (.text)
  73 + cpu/mpc85xx/speed.o (.text)
  74 + cpu/mpc85xx/pci.o (.text)
  75 + common/dlmalloc.o (.text)
  76 + lib_generic/crc32.o (.text)
  77 + lib_ppc/extable.o (.text)
  78 + lib_generic/zlib.o (.text)
  79 + *(.text)
  80 + *(.fixup)
  81 + *(.got1)
  82 + }
  83 + _etext = .;
  84 + PROVIDE (etext = .);
  85 + .rodata :
  86 + {
  87 + *(.rodata)
  88 + *(.rodata1)
  89 + *(.rodata.str1.4)
  90 + }
  91 + .fini : { *(.fini) } =0
  92 + .ctors : { *(.ctors) }
  93 + .dtors : { *(.dtors) }
  94 +
  95 + /* Read-write section, merged into data segment: */
  96 + . = (. + 0x00FF) & 0xFFFFFF00;
  97 + _erotext = .;
  98 + PROVIDE (erotext = .);
  99 + .reloc :
  100 + {
  101 + *(.got)
  102 + _GOT2_TABLE_ = .;
  103 + *(.got2)
  104 + _FIXUP_TABLE_ = .;
  105 + *(.fixup)
  106 + }
  107 + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
  108 + __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
  109 +
  110 + .data :
  111 + {
  112 + *(.data)
  113 + *(.data1)
  114 + *(.sdata)
  115 + *(.sdata2)
  116 + *(.dynamic)
  117 + CONSTRUCTORS
  118 + }
  119 + _edata = .;
  120 + PROVIDE (edata = .);
  121 +
  122 + __u_boot_cmd_start = .;
  123 + .u_boot_cmd : { *(.u_boot_cmd) }
  124 + __u_boot_cmd_end = .;
  125 +
  126 + __start___ex_table = .;
  127 + __ex_table : { *(__ex_table) }
  128 + __stop___ex_table = .;
  129 +
  130 + . = ALIGN(256);
  131 + __init_begin = .;
  132 + .text.init : { *(.text.init) }
  133 + .data.init : { *(.data.init) }
  134 + . = ALIGN(256);
  135 + __init_end = .;
  136 +
  137 + __bss_start = .;
  138 + .bss :
  139 + {
  140 + *(.sbss) *(.scommon)
  141 + *(.dynbss)
  142 + *(.bss)
  143 + *(COMMON)
  144 + }
  145 + _end = . ;
  146 + PROVIDE (end = .);
  147 +}
board/mpc8540ads/flash.c
View file @ 03f5c55
1   -/*
2   - * (C) Copyright 2003 Motorola Inc.
3   - * Xianghua Xiao,(X.Xiao@motorola.com)
4   - *
5   - * (C) Copyright 2000, 2001
6   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7   - *
8   - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
9   - * Add support the Sharp chips on the mpc8260ads.
10   - * I started with board/ip860/flash.c and made changes I found in
11   - * the MTD project by David Schleef.
12   - *
13   - * See file CREDITS for list of people who contributed to this
14   - * project.
15   - *
16   - * This program is free software; you can redistribute it and/or
17   - * modify it under the terms of the GNU General Public License as
18   - * published by the Free Software Foundation; either version 2 of
19   - * the License, or (at your option) any later version.
20   - *
21   - * This program is distributed in the hope that it will be useful,
22   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
23   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24   - * GNU General Public License for more details.
25   - *
26   - * You should have received a copy of the GNU General Public License
27   - * along with this program; if not, write to the Free Software
28   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29   - * MA 02111-1307 USA
30   - */
31   -
32   -#include <common.h>
33   -
34   -#if !defined(CFG_NO_FLASH)
35   -
36   -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
37   -
38   -#if defined(CFG_ENV_IS_IN_FLASH)
39   -# ifndef CFG_ENV_ADDR
40   -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
41   -# endif
42   -# ifndef CFG_ENV_SIZE
43   -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
44   -# endif
45   -# ifndef CFG_ENV_SECT_SIZE
46   -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
47   -# endif
48   -#endif
49   -
50   -#undef DEBUG
51   -
52   -/*-----------------------------------------------------------------------
53   - * Functions
54   - */
55   -static ulong flash_get_size (vu_long *addr, flash_info_t *info);
56   -static int write_word (flash_info_t *info, ulong dest, ulong data);
57   -static int clear_block_lock_bit(vu_long * addr);
58   -/*-----------------------------------------------------------------------
59   - */
60   -
61   -unsigned long flash_init (void)
62   -{
63   - unsigned long size;
64   - int i;
65   -
66   - /* Init: enable write,
67   - * or we cannot even write flash commands
68   - */
69   - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
70   - flash_info[i].flash_id = FLASH_UNKNOWN;
71   -
72   - /* set the default sector offset */
73   - }
74   -
75   - /* Static FLASH Bank configuration here - FIXME XXX */
76   -
77   - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
78   -
79   - if (flash_info[0].flash_id == FLASH_UNKNOWN) {
80   - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
81   - size, size<<20);
82   - }
83   -
84   - /* Re-do sizing to get full correct info */
85   - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
86   -
87   - flash_info[0].size = size;
88   -
89   -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
90   - /* monitor protection ON by default */
91   - flash_protect(FLAG_PROTECT_SET,
92   - CFG_MONITOR_BASE,
93   - CFG_MONITOR_BASE+monitor_flash_len-1,
94   - &flash_info[0]);
95   -
96   -#ifdef CFG_ENV_IS_IN_FLASH
97   - /* ENV protection ON by default */
98   - flash_protect(FLAG_PROTECT_SET,
99   - CFG_ENV_ADDR,
100   - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
101   - &flash_info[0]);
102   -#endif
103   -#endif
104   - return (size);
105   -}
106   -
107   -/*-----------------------------------------------------------------------
108   - */
109   -void flash_print_info (flash_info_t *info)
110   -{
111   - int i;
112   -
113   - if (info->flash_id == FLASH_UNKNOWN) {
114   - printf ("missing or unknown FLASH type\n");
115   - return;
116   - }
117   -
118   - switch (info->flash_id & FLASH_VENDMASK) {
119   - case FLASH_MAN_INTEL: printf ("Intel "); break;
120   - case FLASH_MAN_SHARP: printf ("Sharp "); break;
121   - default: printf ("Unknown Vendor "); break;
122   - }
123   -
124   - switch (info->flash_id & FLASH_TYPEMASK) {
125   - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
126   - break;
127   - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
128   - break;
129   - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
130   - break;
131   - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
132   - break;
133   - case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
134   - break;
135   - default: printf ("Unknown Chip Type\n");
136   - break;
137   - }
138   -
139   - printf (" Size: %ld MB in %d Sectors\n",
140   - info->size >> 20, info->sector_count);
141   -
142   - printf (" Sector Start Addresses:");
143   - for (i=0; i<info->sector_count; ++i) {
144   - if ((i % 5) == 0)
145   - printf ("\n ");
146   - printf (" %08lX%s",
147   - info->start[i],
148   - info->protect[i] ? " (RO)" : " "
149   - );
150   - }
151   - printf ("\n");
152   -}
153   -
154   -/*
155   - * The following code cannot be run from FLASH!
156   - */
157   -
158   -static ulong flash_get_size (vu_long *addr, flash_info_t *info)
159   -{
160   - short i;
161   - ulong value;
162   - ulong base = (ulong)addr;
163   - ulong sector_offset;
164   -
165   -#ifdef DEBUG
166   - printf("Check flash at 0x%08x\n",(uint)addr);
167   -#endif
168   - /* Write "Intelligent Identifier" command: read Manufacturer ID */
169   - *addr = 0x90909090;
170   - udelay(20);
171   - asm("sync");
172   -
173   - value = addr[0] & 0x00FF00FF;
174   -
175   -#ifdef DEBUG
176   - printf("manufacturer=0x%x\n",(uint)value);
177   -#endif
178   - switch (value) {
179   - case MT_MANUFACT: /* SHARP, MT or => Intel */
180   - case INTEL_ALT_MANU:
181   - info->flash_id = FLASH_MAN_INTEL;
182   - break;
183   - default:
184   - printf("unknown manufacturer: %x\n", (unsigned int)value);
185   - info->flash_id = FLASH_UNKNOWN;
186   - info->sector_count = 0;
187   - info->size = 0;
188   - return (0); /* no or unknown flash */
189   - }
190   -
191   - value = addr[1] & 0x00FF00FF; /* device ID */
192   -
193   -#ifdef DEBUG
194   - printf("deviceID=0x%x\n",(uint)value);
195   -#endif
196   - switch (value) {
197   - case (INTEL_ID_28F016S):
198   - info->flash_id += FLASH_28F016SV;
199   - info->sector_count = 32;
200   - info->size = 0x00400000;
201   - sector_offset = 0x20000;
202   - break; /* => 2x2 MB */
203   -
204   - case (INTEL_ID_28F160S3):
205   - info->flash_id += FLASH_28F160S3;
206   - info->sector_count = 32;
207   - info->size = 0x00400000;
208   - sector_offset = 0x20000;
209   - break; /* => 2x2 MB */
210   -
211   - case (INTEL_ID_28F320S3):
212   - info->flash_id += FLASH_28F320S3;
213   - info->sector_count = 64;
214   - info->size = 0x00800000;
215   - sector_offset = 0x20000;
216   - break; /* => 2x4 MB */
217   -
218   - case (INTEL_ID_28F640J3A):
219   - info->flash_id += FLASH_28F640J3A;
220   - info->sector_count = 64;
221   - info->size = 0x01000000;
222   - sector_offset = 0x40000;
223   - break; /* => 2x8 MB */
224   -
225   - case SHARP_ID_28F016SCL:
226   - case SHARP_ID_28F016SCZ:
227   - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
228   - info->sector_count = 32;
229   - info->size = 0x00800000;
230   - sector_offset = 0x40000;
231   - break; /* => 4x2 MB */
232   -
233   -
234   - default:
235   - info->flash_id = FLASH_UNKNOWN;
236   - return (0); /* => no or unknown flash */
237   -
238   - }
239   -
240   - /* set up sector start address table */
241   - for (i = 0; i < info->sector_count; i++) {
242   - info->start[i] = base;
243   - base += sector_offset;
244   - /* don't know how to check sector protection */
245   - info->protect[i] = 0;
246   - }
247   -
248   - /*
249   - * Prevent writes to uninitialized FLASH.
250   - */
251   - if (info->flash_id != FLASH_UNKNOWN) {
252   - addr = (vu_long *)info->start[0];
253   - *addr = 0xFFFFFF; /* reset bank to read array mode */
254   - asm("sync");
255   - }
256   -
257   - return (info->size);
258   -}
259   -
260   -
261   -/*-----------------------------------------------------------------------
262   - */
263   -
264   -int flash_erase (flash_info_t *info, int s_first, int s_last)
265   -{
266   - int flag, prot, sect;
267   - ulong start, now, last;
268   -
269   - if ((s_first < 0) || (s_first > s_last)) {
270   - if (info->flash_id == FLASH_UNKNOWN) {
271   - printf ("- missing\n");
272   - } else {
273   - printf ("- no sectors to erase\n");
274   - }
275   - return 1;
276   - }
277   -
278   - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
279   - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
280   - printf ("Can't erase unknown flash type %08lx - aborted\n",
281   - info->flash_id);
282   - return 1;
283   - }
284   -
285   - prot = 0;
286   - for (sect=s_first; sect<=s_last; ++sect) {
287   - if (info->protect[sect]) {
288   - prot++;
289   - }
290   - }
291   -
292   - if (prot) {
293   - printf ("- Warning: %d protected sectors will not be erased!\n",
294   - prot);
295   - } else {
296   - printf ("\n");
297   - }
298   -
299   -#ifdef DEBUG
300   - printf("\nFlash Erase:\n");
301   -#endif
302   - /* Make Sure Block Lock Bit is not set. */
303   - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
304   - return 1;
305   - }
306   -
307   - /* Start erase on unprotected sectors */
308   -#if defined(DEBUG)
309   - printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
310   -#endif
311   - for (sect = s_first; sect<=s_last; sect++) {
312   - if (info->protect[sect] == 0) { /* not protected */
313   - vu_long *addr = (vu_long *)(info->start[sect]);
314   - asm("sync");
315   -
316   - last = start = get_timer (0);
317   -
318   - /* Disable interrupts which might cause a timeout here */
319   - flag = disable_interrupts();
320   -
321   - /* Reset Array */
322   - *addr = 0xffffffff;
323   - asm("sync");
324   - /* Clear Status Register */
325   - *addr = 0x50505050;
326   - asm("sync");
327   - /* Single Block Erase Command */
328   - *addr = 0x20202020;
329   - asm("sync");
330   - /* Confirm */
331   - *addr = 0xD0D0D0D0;
332   - asm("sync");
333   -
334   - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
335   - /* Resume Command, as per errata update */
336   - *addr = 0xD0D0D0D0;
337   - asm("sync");
338   - }
339   -
340   - /* re-enable interrupts if necessary */
341   - if (flag)
342   - enable_interrupts();
343   -
344   - /* wait at least 80us - let's wait 1 ms */
345   - udelay (1000);
346   - while ((*addr & 0x00800080) != 0x00800080) {
347   - if(*addr & 0x00200020){
348   - printf("Error in Block Erase - Lock Bit may be set!\n");
349   - printf("Status Register = 0x%X\n", (uint)*addr);
350   - *addr = 0xFFFFFFFF; /* reset bank */
351   - asm("sync");
352   - return 1;
353   - }
354   - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
355   - printf ("Timeout\n");
356   - *addr = 0xFFFFFFFF; /* reset bank */
357   - asm("sync");
358   - return 1;
359   - }
360   - /* show that we're waiting */
361   - if ((now - last) > 1000) { /* every second */
362   - putc ('.');
363   - last = now;
364   - }
365   - }
366   -
367   - /* reset to read mode */
368   - *addr = 0xFFFFFFFF;
369   - asm("sync");
370   - }
371   - }
372   -
373   - printf ("flash erase done\n");
374   - return 0;
375   -}
376   -
377   -/*-----------------------------------------------------------------------
378   - * Copy memory to flash, returns:
379   - * 0 - OK
380   - * 1 - write timeout
381   - * 2 - Flash not erased
382   - */
383   -
384   -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
385   -{
386   - ulong cp, wp, data;
387   - int i, l, rc;
388   -
389   - wp = (addr & ~3); /* get lower word aligned address */
390   -
391   - /*
392   - * handle unaligned start bytes
393   - */
394   - if ((l = addr - wp) != 0) {
395   - data = 0;
396   - for (i=0, cp=wp; i<l; ++i, ++cp) {
397   - data = (data << 8) | (*(uchar *)cp);
398   - }
399   - for (; i<4 && cnt>0; ++i) {
400   - data = (data << 8) | *src++;
401   - --cnt;
402   - ++cp;
403   - }
404   - for (; cnt==0 && i<4; ++i, ++cp) {
405   - data = (data << 8) | (*(uchar *)cp);
406   - }
407   -
408   - if ((rc = write_word(info, wp, data)) != 0) {
409   - return (rc);
410   - }
411   - wp += 4;
412   - }
413   -
414   - /*
415   - * handle word aligned part
416   - */
417   - while (cnt >= 4) {
418   - data = 0;
419   - for (i=0; i<4; ++i) {
420   - data = (data << 8) | *src++;
421   - }
422   - if ((rc = write_word(info, wp, data)) != 0) {
423   - return (rc);
424   - }
425   - wp += 4;
426   - cnt -= 4;
427   - }
428   -
429   - if (cnt == 0) {
430   - return (0);
431   - }
432   -
433   - /*
434   - * handle unaligned tail bytes
435   - */
436   - data = 0;
437   - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
438   - data = (data << 8) | *src++;
439   - --cnt;
440   - }
441   - for (; i<4; ++i, ++cp) {
442   - data = (data << 8) | (*(uchar *)cp);
443   - }
444   -
445   - return (write_word(info, wp, data));
446   -}
447   -
448   -/*-----------------------------------------------------------------------
449   - * Write a word to Flash, returns:
450   - * 0 - OK
451   - * 1 - write timeout
452   - * 2 - Flash not erased
453   - */
454   -static int write_word (flash_info_t *info, ulong dest, ulong data)
455   -{
456   - vu_long *addr = (vu_long *)dest;
457   - ulong start, csr;
458   - int flag;
459   -
460   - /* Check if Flash is (sufficiently) erased */
461   - if ((*addr & data) != data) {
462   - return (2);
463   - }
464   - /* Disable interrupts which might cause a timeout here */
465   - flag = disable_interrupts();
466   -
467   - /* Write Command */
468   - *addr = 0x10101010;
469   - asm("sync");
470   -
471   - /* Write Data */
472   - *addr = data;
473   -
474   - /* re-enable interrupts if necessary */
475   - if (flag)
476   - enable_interrupts();
477   -
478   - /* data polling for D7 */
479   - start = get_timer (0);
480   - flag = 0;
481   -
482   - while (((csr = *addr) & 0x00800080) != 0x00800080) {
483   - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
484   - flag = 1;
485   - break;
486   - }
487   - }
488   - if (csr & 0x40404040) {
489   - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
490   - flag = 1;
491   - }
492   -
493   - /* Clear Status Registers Command */
494   - *addr = 0x50505050;
495   - asm("sync");
496   - /* Reset to read array mode */
497   - *addr = 0xFFFFFFFF;
498   - asm("sync");
499   -
500   - return (flag);
501   -}
502   -
503   -/*-----------------------------------------------------------------------
504   - * Clear Block Lock Bit, returns:
505   - * 0 - OK
506   - * 1 - Timeout
507   - */
508   -
509   -static int clear_block_lock_bit(vu_long * addr)
510   -{
511   - ulong start, now;
512   -
513   - /* Reset Array */
514   - *addr = 0xffffffff;
515   - asm("sync");
516   - /* Clear Status Register */
517   - *addr = 0x50505050;
518   - asm("sync");
519   -
520   - *addr = 0x60606060;
521   - asm("sync");
522   - *addr = 0xd0d0d0d0;
523   - asm("sync");
524   -
525   - start = get_timer (0);
526   - while((*addr & 0x00800080) != 0x00800080){
527   - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
528   - printf ("Timeout on clearing Block Lock Bit\n");
529   - *addr = 0xFFFFFFFF; /* reset bank */
530   - asm("sync");
531   - return 1;
532   - }
533   - }
534   - return 0;
535   -}
536   -
537   -#endif /* !CFG_NO_FLASH */
board/mpc8560ads/flash.c
View file @ 03f5c55
1   -/*
2   - * (C) Copyright 2003 Motorola Inc.
3   - * Xianghua Xiao,(X.Xiao@motorola.com)
4   - *
5   - * (C) Copyright 2000, 2001
6   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7   - *
8   - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
9   - * Add support the Sharp chips on the mpc8260ads.
10   - * I started with board/ip860/flash.c and made changes I found in
11   - * the MTD project by David Schleef.
12   - *
13   - * See file CREDITS for list of people who contributed to this
14   - * project.
15   - *
16   - * This program is free software; you can redistribute it and/or
17   - * modify it under the terms of the GNU General Public License as
18   - * published by the Free Software Foundation; either version 2 of
19   - * the License, or (at your option) any later version.
20   - *
21   - * This program is distributed in the hope that it will be useful,
22   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
23   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24   - * GNU General Public License for more details.
25   - *
26   - * You should have received a copy of the GNU General Public License
27   - * along with this program; if not, write to the Free Software
28   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29   - * MA 02111-1307 USA
30   - */
31   -
32   -#include <common.h>
33   -
34   -#if !defined(CFG_NO_FLASH)
35   -
36   -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
37   -
38   -#if defined(CFG_ENV_IS_IN_FLASH)
39   -# ifndef CFG_ENV_ADDR
40   -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
41   -# endif
42   -# ifndef CFG_ENV_SIZE
43   -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
44   -# endif
45   -# ifndef CFG_ENV_SECT_SIZE
46   -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
47   -# endif
48   -#endif
49   -
50   -#undef DEBUG
51   -
52   -/*-----------------------------------------------------------------------
53   - * Functions
54   - */
55   -static ulong flash_get_size (vu_long *addr, flash_info_t *info);
56   -static int write_word (flash_info_t *info, ulong dest, ulong data);
57   -static int clear_block_lock_bit(vu_long * addr);
58   -/*-----------------------------------------------------------------------
59   - */
60   -
61   -unsigned long flash_init (void)
62   -{
63   - unsigned long size;
64   - int i;
65   -
66   - /* Init: enable write,
67   - * or we cannot even write flash commands
68   - */
69   - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
70   - flash_info[i].flash_id = FLASH_UNKNOWN;
71   -
72   - /* set the default sector offset */
73   - }
74   -
75   - /* Static FLASH Bank configuration here - FIXME XXX */
76   -
77   - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
78   -
79   - if (flash_info[0].flash_id == FLASH_UNKNOWN) {
80   - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
81   - size, size<<20);
82   - }
83   -
84   - /* Re-do sizing to get full correct info */
85   - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
86   -
87   - flash_info[0].size = size;
88   -
89   -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
90   - /* monitor protection ON by default */
91   - flash_protect(FLAG_PROTECT_SET,
92   - CFG_MONITOR_BASE,
93   - CFG_MONITOR_BASE+monitor_flash_len-1,
94   - &flash_info[0]);
95   -
96   -#ifdef CFG_ENV_IS_IN_FLASH
97   - /* ENV protection ON by default */
98   - flash_protect(FLAG_PROTECT_SET,
99   - CFG_ENV_ADDR,
100   - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
101   - &flash_info[0]);
102   -#endif
103   -#endif
104   - return (size);
105   -}
106   -
107   -/*-----------------------------------------------------------------------
108   - */
109   -void flash_print_info (flash_info_t *info)
110   -{
111   - int i;
112   -
113   - if (info->flash_id == FLASH_UNKNOWN) {
114   - printf ("missing or unknown FLASH type\n");
115   - return;
116   - }
117   -
118   - switch (info->flash_id & FLASH_VENDMASK) {
119   - case FLASH_MAN_INTEL: printf ("Intel "); break;
120   - case FLASH_MAN_SHARP: printf ("Sharp "); break;
121   - default: printf ("Unknown Vendor "); break;
122   - }
123   -
124   - switch (info->flash_id & FLASH_TYPEMASK) {
125   - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
126   - break;
127   - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
128   - break;
129   - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
130   - break;
131   - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
132   - break;
133   - case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
134   - break;
135   - default: printf ("Unknown Chip Type\n");
136   - break;
137   - }
138   -
139   - printf (" Size: %ld MB in %d Sectors\n",
140   - info->size >> 20, info->sector_count);
141   -
142   - printf (" Sector Start Addresses:");
143   - for (i=0; i<info->sector_count; ++i) {
144   - if ((i % 5) == 0)
145   - printf ("\n ");
146   - printf (" %08lX%s",
147   - info->start[i],
148   - info->protect[i] ? " (RO)" : " "
149   - );
150   - }
151   - printf ("\n");
152   -}
153   -
154   -/*
155   - * The following code cannot be run from FLASH!
156   - */
157   -
158   -static ulong flash_get_size (vu_long *addr, flash_info_t *info)
159   -{
160   - short i;
161   - ulong value;
162   - ulong base = (ulong)addr;
163   - ulong sector_offset;
164   -
165   -#ifdef DEBUG
166   - printf("Check flash at 0x%08x\n",(uint)addr);
167   -#endif
168   - /* Write "Intelligent Identifier" command: read Manufacturer ID */
169   - *addr = 0x90909090;
170   - udelay(20);
171   - asm("sync");
172   -
173   - value = addr[0] & 0x00FF00FF;
174   -
175   -#ifdef DEBUG
176   - printf("manufacturer=0x%x\n",(uint)value);
177   -#endif
178   - switch (value) {
179   - case MT_MANUFACT: /* SHARP, MT or => Intel */
180   - case INTEL_ALT_MANU:
181   - info->flash_id = FLASH_MAN_INTEL;
182   - break;
183   - default:
184   - printf("unknown manufacturer: %x\n", (unsigned int)value);
185   - info->flash_id = FLASH_UNKNOWN;
186   - info->sector_count = 0;
187   - info->size = 0;
188   - return (0); /* no or unknown flash */
189   - }
190   -
191   - value = addr[1] & 0x00FF00FF; /* device ID */
192   -
193   -#ifdef DEBUG
194   - printf("deviceID=0x%x\n",(uint)value);
195   -#endif
196   - switch (value) {
197   - case (INTEL_ID_28F016S):
198   - info->flash_id += FLASH_28F016SV;
199   - info->sector_count = 32;
200   - info->size = 0x00400000;
201   - sector_offset = 0x20000;
202   - break; /* => 2x2 MB */
203   -
204   - case (INTEL_ID_28F160S3):
205   - info->flash_id += FLASH_28F160S3;
206   - info->sector_count = 32;
207   - info->size = 0x00400000;
208   - sector_offset = 0x20000;
209   - break; /* => 2x2 MB */
210   -
211   - case (INTEL_ID_28F320S3):
212   - info->flash_id += FLASH_28F320S3;
213   - info->sector_count = 64;
214   - info->size = 0x00800000;
215   - sector_offset = 0x20000;
216   - break; /* => 2x4 MB */
217   -
218   - case (INTEL_ID_28F640J3A):
219   - info->flash_id += FLASH_28F640J3A;
220   - info->sector_count = 64;
221   - info->size = 0x01000000;
222   - sector_offset = 0x40000;
223   - break; /* => 8 MB */
224   -
225   - case SHARP_ID_28F016SCL:
226   - case SHARP_ID_28F016SCZ:
227   - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
228   - info->sector_count = 32;
229   - info->size = 0x00800000;
230   - sector_offset = 0x40000;
231   - break; /* => 4x2 MB */
232   -
233   -
234   - default:
235   - info->flash_id = FLASH_UNKNOWN;
236   - return (0); /* => no or unknown flash */
237   -
238   - }
239   -
240   - /* set up sector start address table */
241   - for (i = 0; i < info->sector_count; i++) {
242   - info->start[i] = base;
243   - base += sector_offset;
244   - /* don't know how to check sector protection */
245   - info->protect[i] = 0;
246   - }
247   -
248   - /*
249   - * Prevent writes to uninitialized FLASH.
250   - */
251   - if (info->flash_id != FLASH_UNKNOWN) {
252   - addr = (vu_long *)info->start[0];
253   - *addr = 0xFFFFFF; /* reset bank to read array mode */
254   - asm("sync");
255   - }
256   -
257   - return (info->size);
258   -}
259   -
260   -
261   -/*-----------------------------------------------------------------------
262   - */
263   -
264   -int flash_erase (flash_info_t *info, int s_first, int s_last)
265   -{
266   - int flag, prot, sect;
267   - ulong start, now, last;
268   -
269   - if ((s_first < 0) || (s_first > s_last)) {
270   - if (info->flash_id == FLASH_UNKNOWN) {
271   - printf ("- missing\n");
272   - } else {
273   - printf ("- no sectors to erase\n");
274   - }
275   - return 1;
276   - }
277   -
278   - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
279   - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
280   - printf ("Can't erase unknown flash type %08lx - aborted\n",
281   - info->flash_id);
282   - return 1;
283   - }
284   -
285   - prot = 0;
286   - for (sect=s_first; sect<=s_last; ++sect) {
287   - if (info->protect[sect]) {
288   - prot++;
289   - }
290   - }
291   -
292   - if (prot) {
293   - printf ("- Warning: %d protected sectors will not be erased!\n",
294   - prot);
295   - } else {
296   - printf ("\n");
297   - }
298   -
299   -#ifdef DEBUG
300   - printf("\nFlash Erase:\n");
301   -#endif
302   - /* Make Sure Block Lock Bit is not set. */
303   - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
304   - return 1;
305   - }
306   -
307   - /* Start erase on unprotected sectors */
308   -#if defined(DEBUG)
309   - printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
310   -#endif
311   - for (sect = s_first; sect<=s_last; sect++) {
312   - if (info->protect[sect] == 0) { /* not protected */
313   - vu_long *addr = (vu_long *)(info->start[sect]);
314   - asm("sync");
315   -
316   - last = start = get_timer (0);
317   -
318   - /* Disable interrupts which might cause a timeout here */
319   - flag = disable_interrupts();
320   -
321   - /* Reset Array */
322   - *addr = 0xffffffff;
323   - asm("sync");
324   - /* Clear Status Register */
325   - *addr = 0x50505050;
326   - asm("sync");
327   - /* Single Block Erase Command */
328   - *addr = 0x20202020;
329   - asm("sync");
330   - /* Confirm */
331   - *addr = 0xD0D0D0D0;
332   - asm("sync");
333   -
334   - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
335   - /* Resume Command, as per errata update */
336   - *addr = 0xD0D0D0D0;
337   - asm("sync");
338   - }
339   -
340   - /* re-enable interrupts if necessary */
341   - if (flag)
342   - enable_interrupts();
343   -
344   - /* wait at least 80us - let's wait 1 ms */
345   - udelay (1000);
346   - while ((*addr & 0x00800080) != 0x00800080) {
347   - if(*addr & 0x00200020){
348   - printf("Error in Block Erase - Lock Bit may be set!\n");
349   - printf("Status Register = 0x%X\n", (uint)*addr);
350   - *addr = 0xFFFFFFFF; /* reset bank */
351   - asm("sync");
352   - return 1;
353   - }
354   - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
355   - printf ("Timeout\n");
356   - *addr = 0xFFFFFFFF; /* reset bank */
357   - asm("sync");
358   - return 1;
359   - }
360   - /* show that we're waiting */
361   - if ((now - last) > 1000) { /* every second */
362   - putc ('.');
363   - last = now;
364   - }
365   - }
366   -
367   - /* reset to read mode */
368   - *addr = 0xFFFFFFFF;
369   - asm("sync");
370   - }
371   - }
372   -
373   - printf ("flash erase done\n");
374   - return 0;
375   -}
376   -
377   -/*-----------------------------------------------------------------------
378   - * Copy memory to flash, returns:
379   - * 0 - OK
380   - * 1 - write timeout
381   - * 2 - Flash not erased
382   - */
383   -
384   -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
385   -{
386   - ulong cp, wp, data;
387   - int i, l, rc;
388   -
389   - wp = (addr & ~3); /* get lower word aligned address */
390   -
391   - /*
392   - * handle unaligned start bytes
393   - */
394   - if ((l = addr - wp) != 0) {
395   - data = 0;
396   - for (i=0, cp=wp; i<l; ++i, ++cp) {
397   - data = (data << 8) | (*(uchar *)cp);
398   - }
399   - for (; i<4 && cnt>0; ++i) {
400   - data = (data << 8) | *src++;
401   - --cnt;
402   - ++cp;
403   - }
404   - for (; cnt==0 && i<4; ++i, ++cp) {
405   - data = (data << 8) | (*(uchar *)cp);
406   - }
407   -
408   - if ((rc = write_word(info, wp, data)) != 0) {
409   - return (rc);
410   - }
411   - wp += 4;
412   - }
413   -
414   - /*
415   - * handle word aligned part
416   - */
417   - while (cnt >= 4) {
418   - data = 0;
419   - for (i=0; i<4; ++i) {
420   - data = (data << 8) | *src++;
421   - }
422   - if ((rc = write_word(info, wp, data)) != 0) {
423   - return (rc);
424   - }
425   - wp += 4;
426   - cnt -= 4;
427   - }
428   -
429   - if (cnt == 0) {
430   - return (0);
431   - }
432   -
433   - /*
434   - * handle unaligned tail bytes
435   - */
436   - data = 0;
437   - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
438   - data = (data << 8) | *src++;
439   - --cnt;
440   - }
441   - for (; i<4; ++i, ++cp) {
442   - data = (data << 8) | (*(uchar *)cp);
443   - }
444   -
445   - return (write_word(info, wp, data));
446   -}
447   -
448   -/*-----------------------------------------------------------------------
449   - * Write a word to Flash, returns:
450   - * 0 - OK
451   - * 1 - write timeout
452   - * 2 - Flash not erased
453   - */
454   -static int write_word (flash_info_t *info, ulong dest, ulong data)
455   -{
456   - vu_long *addr = (vu_long *)dest;
457   - ulong start, csr;
458   - int flag;
459   -
460   - /* Check if Flash is (sufficiently) erased */
461   - if ((*addr & data) != data) {
462   - return (2);
463   - }
464   - /* Disable interrupts which might cause a timeout here */
465   - flag = disable_interrupts();
466   -
467   - /* Write Command */
468   - *addr = 0x10101010;
469   - asm("sync");
470   -
471   - /* Write Data */
472   - *addr = data;
473   -
474   - /* re-enable interrupts if necessary */
475   - if (flag)
476   - enable_interrupts();
477   -
478   - /* data polling for D7 */
479   - start = get_timer (0);
480   - flag = 0;
481   -
482   - while (((csr = *addr) & 0x00800080) != 0x00800080) {
483   - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
484   - flag = 1;
485   - break;
486   - }
487   - }
488   - if (csr & 0x40404040) {
489   - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
490   - flag = 1;
491   - }
492   -
493   - /* Clear Status Registers Command */
494   - *addr = 0x50505050;
495   - asm("sync");
496   - /* Reset to read array mode */
497   - *addr = 0xFFFFFFFF;
498   - asm("sync");
499   -
500   - return (flag);
501   -}
502   -
503   -/*-----------------------------------------------------------------------
504   - * Clear Block Lock Bit, returns:
505   - * 0 - OK
506   - * 1 - Timeout
507   - */
508   -
509   -static int clear_block_lock_bit(vu_long * addr)
510   -{
511   - ulong start, now;
512   -
513   - /* Reset Array */
514   - *addr = 0xffffffff;
515   - asm("sync");
516   - /* Clear Status Register */
517   - *addr = 0x50505050;
518   - asm("sync");
519   -
520   - *addr = 0x60606060;
521   - asm("sync");
522   - *addr = 0xd0d0d0d0;
523   - asm("sync");
524   -
525   - start = get_timer (0);
526   - while((*addr & 0x00800080) != 0x00800080){
527   - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
528   - printf ("Timeout on clearing Block Lock Bit\n");
529   - *addr = 0xFFFFFFFF; /* reset bank */
530   - asm("sync");
531   - return 1;
532   - }
533   - }
534   - return 0;
535   -}
536   -
537   -#endif /* !CFG_NO_FLASH */
... ... @@ -79,24 +79,33 @@
79 79 #endif
80 80 print_str ("busfreq", strmhz(buf, bd->bi_busfreq));
81 81 #endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300 */
  82 +
82 83 puts ("ethaddr =");
83 84 for (i=0; i<6; ++i) {
84 85 printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
85 86 }
86   -#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB) || \
87   - (defined CONFIG_MPC8540ADS) || (defined CONFIG_MPC8560ADS) || \
88   - (defined CONFIG_MPC8555CDS)
  87 +
  88 +#if defined(CONFIG_ETH1ADDR)
89 89 puts ("\neth1addr =");
90 90 for (i=0; i<6; ++i) {
91 91 printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
92 92 }
93   -#endif /* CONFIG_PN62 */
94   -#if defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS) || defined(CONFIG_MPC8555CDS)
  93 +#endif
  94 +
  95 +#if defined(CONFIG_ETH2ADDR)
95 96 puts ("\neth2addr =");
96 97 for (i=0; i<6; ++i) {
97 98 printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
98 99 }
99 100 #endif
  101 +
  102 +#if defined(CONFIG_ETH3ADDR)
  103 + puts ("\neth3addr =");
  104 + for (i=0; i<6; ++i) {
  105 + printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]);
  106 + }
  107 +#endif
  108 +
100 109 #ifdef CONFIG_HERMES
101 110 print_str ("ethspeed", strmhz(buf, bd->bi_ethspeed));
102 111 #endif
doc/README.mpc85xxads
Diff comments   View file @ 03f5c55
... ... @@ -7,7 +7,7 @@
7 7 0. Toolchain
8 8  
9 9 The Binutils in current ELDK toolchain will not support MPC85xx
10   - chip. You need use the newest binutils-2.14.tar.bz2 from
  10 + chip. You need to use binutils-2.14.tar.bz2 (or newer) from
11 11 http://ftp.gnu.org/gnu/binutils.
12 12  
13 13 The 8540/8560 ADS code base is known to compile using:
14 14  
... ... @@ -191,10 +191,10 @@
191 191  
192 192 4.4 Reflash U-boot Image using U-boot
193 193  
194   - => tftp 0 u-boot.bin
  194 + => tftp 10000 u-boot.bin
195 195 => protect off fff80000 ffffffff
196 196 => erase fff80000 ffffffff
197   - => cp.b 0 fff80000 80000
  197 + => cp.b 10000 fff80000 80000
198 198  
199 199  
200 200 4.5 Reflash U-Boot with a BDI-2000
doc/README.mpc85xxcds
Diff comments   View file @ 03f5c55
  1 +Motorola MPC85xxCDS boards
  2 +--------------------------
  3 +
  4 +The CDS family of boards consists of a PCI backplane called the
  5 +"Arcadia", a PCI-form-factor carrier card that plugs into a PCI slot,
  6 +and a CPU daughter card that bolts onto the daughter card.
  7 +
  8 +Much of the content of the README.mpc85xxads for the 85xx ADS boards
  9 +applies to the 85xx CDS boards as well. In particular the toolchain,
  10 +the switch nomenclature, and the basis for the memory map. There are
  11 +some differences, though.
  12 +
  13 +
  14 +Building U-Boot
  15 +---------------
  16 +
  17 +The Binutils in current ELDK toolchain will not support MPC85xx
  18 +chip. You need to use binutils-2.14.tar.bz2 (or newer) from
  19 + http://ftp.gnu.org/gnu/binutils.
  20 +
  21 +The 85xx CDS code base is known to compile using:
  22 + gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)
  23 +
  24 +
  25 +Memory Map
  26 +----------
  27 +
  28 +The memory map for u-boot and linux has been extended w.r.t. the ADS
  29 +platform to allow for utilization of all 85xx CDS devices. The memory
  30 +map is setup for linux to operate properly. The linux source when
  31 +configured for MPC85xx CDS has been updated to reflect the new memory
  32 +map.
  33 +
  34 +The mapping is:
  35 +
  36 + 0x0000_0000 0x7fff_ffff DDR 2G
  37 + 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
  38 + 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
  39 + 0xe000_0000 0xe00f_ffff CCSR 1M
  40 + 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
  41 + 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
  42 + 0xf000_0000 0xf7ff_ffff SDRAM 128M
  43 + 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
  44 + 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
  45 + 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
  46 +
  47 + (*) The system control registers (CADMUS) start at offset 0xfdb0_4000
  48 + within the NVRAM/CADMUS region of memory.
  49 +
  50 +
  51 +Using Flash
  52 +-----------
  53 +
  54 +The CDS board has two flash banks, each 8MB in size (2^23 = 0x00800000).
  55 +There is a switch which allows the boot-bank to be selected. The switch
  56 +settings for updating flash are given below.
  57 +
  58 +The u-boot commands for copying the boot-bank into the secondary bank are
  59 +as follows:
  60 +
  61 + erase ff780000 ff7fffff
  62 + cp.b fff80000 ff780000 80000
  63 +
  64 +
  65 +U-boot/kermit commands for downloading an image, then copying
  66 +it into the secondary bank:
  67 +
  68 + loadb
  69 + [Drop to kermit:
  70 + ^\c
  71 + send <u-boot-bin-image>
  72 + c
  73 + ]
  74 +
  75 + erase ff780000 ff7fffff
  76 + cp.b $loadaddr ff780000 80000
  77 +
  78 +
  79 +U-boot commands for downloading an image via tftp and flashing
  80 +it into the second bank:
  81 +
  82 + tftp 10000 <u-boot.bin.image>
  83 + erase ff780000 ff7fffff
  84 + cp.b 10000 ff780000 80000
  85 +
  86 +
  87 +After copying the image into the second bank of flash, be sure to toggle
  88 +SW2[2] on the carrier card before resetting the board in order to set the
  89 +secondary bank as the boot-bank.
  90 +
  91 +
  92 +Carrier Board Switches
  93 +----------------------
  94 +
  95 +As a reminder, you should read the README.mpc85xxads too.
  96 +
  97 +Most switches on the carrier board should not be changed. The only
  98 +user-settable switches on the carrier board are used to configure
  99 +the flash banks and determining the PCI slot.
  100 +
  101 +The first two bits of SW2 control how flash is used on the board:
  102 +
  103 + 12345678
  104 + --------
  105 + SW2=00XXXXXX FLASH: Boot bank 1, bank 2 available.
  106 + 01XXXXXX FLASH: Boot bank 2, bank 1 available (swapped).
  107 + 10XXXXXX FLASH: Boot promjet, bank 1 available
  108 + 11XXXXXX FLASH: Boot promjet, bank 2 available
  109 +
  110 +The boot bank is always mapped to FF80_0000 and listed first by
  111 +the "flinfo" command. The secondary bank is always FF00_0000.
  112 +
  113 +When using PCI, linux needs to know to which slot the CDS carrier is
  114 +connected.. By convention, the user-specific bits of SW2 are used to
  115 +convey this information:
  116 +
  117 + 12345678
  118 + --------
  119 + SW2=xxxxxx00 PCI SLOT INFORM: The CDS carrier is in slot0 of the Arcadia
  120 + xxxxxx01 PCI SLOT INFORM: The CDS carrier is in slot1 of the Arcadia
  121 + xxxxxx10 PCI SLOT INFORM: The CDS carrier is in slot2 of the Arcadia
  122 + xxxxxx11 PCI SLOT INFORM: The CDS carrier is in slot3 of the Arcadia
  123 +
  124 +These are cleverly, er, clearly silkscreened as Slot 1 through 4,
  125 +respectively, on the Arcadia near the support posts.
  126 +
  127 +
  128 +The default setting of all switches on the carrier board is:
  129 +
  130 + 12345678
  131 + --------
  132 + SW1=01101100
  133 + SW2=0x1111yy x=Flash bank, yy=PCI slot
  134 + SW3=11101111
  135 + SW4=10001000
  136 +
  137 +
  138 +CPU Card Switches
  139 +-----------------
  140 +
  141 +Most switches on the CPU Card should not be changed. However, the
  142 +frequency can be changed by setting SW3:
  143 +
  144 + 12345678
  145 + --------
  146 + SW3=XX00XXXX == CORE:CCB 2:1
  147 + XX01XXXX == CORE:CCB 5:2
  148 + XX10XXXX == CORE:CCB 3:1
  149 + XX11XXXX == CORE:CCB 7:2
  150 + XXXX1000 == CCB:SYSCLK 8:1
  151 + XXXX1010 == CCB:SYSCLK 10:1
  152 +
  153 +A safe default setting for all switches on the CPU board is:
  154 +
  155 + 12345678
  156 + --------
  157 + SW1=10001111
  158 + SW2=01000111
  159 + SW3=00001000
  160 + SW4=11111110
  161 +
  162 +
  163 +eDINK Info
  164 +----------
  165 +
  166 +One bank of flash may contain an eDINK image.
  167 +
  168 +Memory Map:
  169 +
  170 + CCSRBAR @ 0xe0000000
  171 + Flash Bank 1 @ 0xfe000000
  172 + Flash Bank 2 @ 0xff000000
  173 + Ram @ 0
  174 +
  175 +Commands for downloading a u-boot image to memory from edink:
  176 +
  177 + env -c
  178 + time -s 4/8/2004 4:30p
  179 + dl -k -b -o 100000
  180 + [Drop to kermit:
  181 + ^\c
  182 + transmit /binary <u-boot-bin-image>
  183 + c
  184 + ]
  185 +
  186 + fu -l 100000 fe780000 80000
include/asm-ppc/immap_85xx.h
Diff comments   View file @ 03f5c55
... ... @@ -156,7 +156,9 @@
156 156 char res6[4075];
157 157 } ccsr_i2c_t;
158 158  
159   -#if defined (CONFIG_MPC8540) || defined (CONFIG_MPC8555)
  159 +#if defined(CONFIG_MPC8540) \
  160 + || defined(CONFIG_MPC8541) \
  161 + || defined(CONFIG_MPC8555)
160 162 /* DUART Registers(0x4000-0x5000) */
161 163 typedef struct ccsr_duart {
162 164 char res1[1280];
... ... @@ -1021,7 +1023,9 @@
1021 1023 } ccsr_pic_t;
1022 1024  
1023 1025 /* CPM Block(0x8_0000-0xc_0000) */
1024   -#if defined (CONFIG_MPC8540) || defined (CONFIG_MPC8555)
  1026 +#if defined(CONFIG_MPC8540) \
  1027 + || defined(CONFIG_MPC8541) \
  1028 + || defined(CONFIG_MPC8555)
1025 1029 typedef struct ccsr_cpm {
1026 1030 char res[262144];
1027 1031 } ccsr_cpm_t;
include/asm-ppc/u-boot.h
Diff comments   View file @ 03f5c55
... ... @@ -77,27 +77,19 @@
77 77 #if defined(CONFIG_HYMOD)
78 78 hymod_conf_t bi_hymod_conf; /* hymod configuration information */
79 79 #endif
80   -#if defined(CFG_GT_6426x) || \
81   - defined(CONFIG_PN62) || \
82   - defined(CONFIG_PPCHAMELEONEVB) || \
83   - defined(CONFIG_SXNI855T) || \
84   - defined(CONFIG_SVM_SC8xx) || \
85   - defined(CONFIG_MPC8540ADS) || \
86   - defined(CONFIG_MPC8555CDS) || \
87   - defined(CONFIG_MPC8560ADS) || \
88   - defined(CONFIG_440_GX)
  80 +
  81 +#if defined(CONFIG_ETH1ADDR)
89 82 /* second onboard ethernet port */
90 83 unsigned char bi_enet1addr[6];
91 84 #endif
92   -#if defined(CFG_GT_6426x) || defined(CONFIG_SVM_SC8xx) || \
93   - defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS) || \
94   - defined(CONFIG_MPC8555CDS) || defined(CONFIG_440_GX)
  85 +#if defined(CONFIG_ETH2ADDR)
95 86 /* third onboard ethernet port */
96 87 unsigned char bi_enet2addr[6];
97 88 #endif
98   -#if defined(CONFIG_440_GX)
  89 +#if defined(CONFIG_ETH3ADDR)
99 90 unsigned char bi_enet3addr[6];
100 91 #endif
  92 +
101 93 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440_GX)
102 94 unsigned int bi_opbfreq; /* OPB clock in Hz */
103 95 int bi_iic_fast[2]; /* Use fast i2c mode */
include/configs/MPC8541CDS.h
Diff comments   View file @ 03f5c55
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +/*
  24 + * mpc8541cds board configuration file
  25 + *
  26 + * Please refer to doc/README.mpc85xxcds for more info.
  27 + *
  28 + */
  29 +
  30 +#ifndef __CONFIG_H
  31 +#define __CONFIG_H
  32 +
  33 +/* High Level Configuration Options */
  34 +#define CONFIG_BOOKE 1 /* BOOKE */
  35 +#define CONFIG_E500 1 /* BOOKE e500 family */
  36 +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
  37 +#define CONFIG_MPC8541 1 /* MPC8541 specific */
  38 +#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
  39 +
  40 +#define CONFIG_PCI
  41 +#define CONFIG_TSEC_ENET /* tsec ethernet support */
  42 +#define CONFIG_ENV_OVERWRITE
  43 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  44 +#define CONFIG_DDR_ECC /* only for ECC DDR module */
  45 +#define CONFIG_DDR_DLL /* possible DLL fix needed */
  46 +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
  47 +
  48 +/*
  49 + * When initializing flash, if we cannot find the manufacturer ID,
  50 + * assume this is the AMD flash associated with the CDS board.
  51 + * This allows booting from a promjet.
  52 + */
  53 +#define CONFIG_ASSUME_AMD_FLASH
  54 +
  55 +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
  56 +
  57 +#ifndef __ASSEMBLY__
  58 +extern unsigned long get_clock_freq(void);
  59 +#endif
  60 +#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
  61 +
  62 +/*
  63 + * These can be toggled for performance analysis, otherwise use default.
  64 + */
  65 +#define CONFIG_L2_CACHE /* toggle L2 cache */
  66 +#define CONFIG_BTB /* toggle branch predition */
  67 +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
  68 +
  69 +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  70 +
  71 +#undef CFG_DRAM_TEST /* memory test, takes time */
  72 +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
  73 +#define CFG_MEMTEST_END 0x00400000
  74 +
  75 +
  76 +/*
  77 + * Base addresses -- Note these are effective addresses where the
  78 + * actual resources get mapped (not physical addresses)
  79 + */
  80 +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  81 +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  82 +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
  83 +
  84 +
  85 +/*
  86 + * DDR Setup
  87 + */
  88 +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  89 +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
  90 +
  91 +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  92 +
  93 +/*
  94 + * Make sure required options are set
  95 + */
  96 +#ifndef CONFIG_SPD_EEPROM
  97 +#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  98 +#endif
  99 +
  100 +
  101 +
  102 +/*
  103 + * SDRAM on the Local Bus
  104 + */
  105 +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  106 +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  107 +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
  108 +
  109 +#define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */
  110 +#define CFG_BR1_PRELIM 0xff001001 /* port size 16bit */
  111 +
  112 +#define CFG_OR0_PRELIM 0xff806e61 /* 8MB Flash */
  113 +#define CFG_OR1_PRELIM 0xff806e61 /* 8MB Flash */
  114 +
  115 +#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
  116 +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
  117 +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
  118 +#undef CFG_FLASH_CHECKSUM
  119 +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  120 +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  121 +
  122 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
  123 +
  124 +#define CFG_FLASH_CFI_DRIVER
  125 +#define CFG_FLASH_CFI
  126 +#define CFG_FLASH_EMPTY_INFO
  127 +
  128 +#undef CONFIG_CLOCKS_IN_MHZ
  129 +
  130 +/*
  131 + * Local Bus Definitions
  132 + */
  133 +
  134 +/*
  135 + * Base Register 2 and Option Register 2 configure SDRAM.
  136 + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
  137 + *
  138 + * For BR2, need:
  139 + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  140 + * port-size = 32-bits = BR2[19:20] = 11
  141 + * no parity checking = BR2[21:22] = 00
  142 + * SDRAM for MSEL = BR2[24:26] = 011
  143 + * Valid = BR[31] = 1
  144 + *
  145 + * 0 4 8 12 16 20 24 28
  146 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  147 + *
  148 + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
  149 + * FIXME: the top 17 bits of BR2.
  150 + */
  151 +
  152 +#define CFG_BR2_PRELIM 0xf0001861
  153 +
  154 +/*
  155 + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
  156 + *
  157 + * For OR2, need:
  158 + * 64MB mask for AM, OR2[0:7] = 1111 1100
  159 + * XAM, OR2[17:18] = 11
  160 + * 9 columns OR2[19-21] = 010
  161 + * 13 rows OR2[23-25] = 100
  162 + * EAD set for extra time OR[31] = 1
  163 + *
  164 + * 0 4 8 12 16 20 24 28
  165 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  166 + */
  167 +
  168 +#define CFG_OR2_PRELIM 0xfc006901
  169 +
  170 +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  171 +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
  172 +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  173 +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  174 +
  175 +/*
  176 + * LSDMR masks
  177 + */
  178 +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
  179 +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
  180 +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
  181 +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
  182 +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
  183 +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
  184 +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
  185 +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
  186 +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
  187 +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
  188 +
  189 +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
  190 +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
  191 +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
  192 +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
  193 +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
  194 +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
  195 +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
  196 +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
  197 +
  198 +/*
  199 + * Common settings for all Local Bus SDRAM commands.
  200 + * At run time, either BSMA1516 (for CPU 1.1)
  201 + * or BSMA1617 (for CPU 1.0) (old)
  202 + * is OR'ed in too.
  203 + */
  204 +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
  205 + | CFG_LBC_LSDMR_PRETOACT7 \
  206 + | CFG_LBC_LSDMR_ACTTORW7 \
  207 + | CFG_LBC_LSDMR_BL8 \
  208 + | CFG_LBC_LSDMR_WRC4 \
  209 + | CFG_LBC_LSDMR_CL3 \
  210 + | CFG_LBC_LSDMR_RFEN \
  211 + )
  212 +
  213 +/*
  214 + * The CADMUS registers are connected to CS3 on CDS.
  215 + * The new memory map places CADMUS at 0xf8000000.
  216 + *
  217 + * For BR3, need:
  218 + * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
  219 + * port-size = 8-bits = BR[19:20] = 01
  220 + * no parity checking = BR[21:22] = 00
  221 + * GPMC for MSEL = BR[24:26] = 000
  222 + * Valid = BR[31] = 1
  223 + *
  224 + * 0 4 8 12 16 20 24 28
  225 + * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
  226 + *
  227 + * For OR3, need:
  228 + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
  229 + * disable buffer ctrl OR[19] = 0
  230 + * CSNT OR[20] = 1
  231 + * ACS OR[21:22] = 11
  232 + * XACS OR[23] = 1
  233 + * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
  234 + * SETA OR[28] = 0
  235 + * TRLX OR[29] = 1
  236 + * EHTR OR[30] = 1
  237 + * EAD extra time OR[31] = 1
  238 + *
  239 + * 0 4 8 12 16 20 24 28
  240 + * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  241 + */
  242 +
  243 +#define CADMUS_BASE_ADDR 0xf8000000
  244 +#define CFG_BR3_PRELIM 0xf8000801
  245 +#define CFG_OR3_PRELIM 0xfff00ff7
  246 +
  247 +
  248 +#define CONFIG_L1_INIT_RAM
  249 +#define CFG_INIT_RAM_LOCK 1
  250 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  251 +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
  252 +
  253 +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
  254 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  255 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  256 +
  257 +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  258 +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  259 +
  260 +/* Serial Port */
  261 +#define CONFIG_CONS_INDEX 2
  262 +#undef CONFIG_SERIAL_SOFTWARE_FIFO
  263 +#define CFG_NS16550
  264 +#define CFG_NS16550_SERIAL
  265 +#define CFG_NS16550_REG_SIZE 1
  266 +#define CFG_NS16550_CLK get_bus_freq(0)
  267 +
  268 +#define CFG_BAUDRATE_TABLE \
  269 + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  270 +
  271 +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
  272 +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
  273 +
  274 +/* Use the HUSH parser */
  275 +#define CFG_HUSH_PARSER
  276 +#ifdef CFG_HUSH_PARSER
  277 +#define CFG_PROMPT_HUSH_PS2 "> "
  278 +#endif
  279 +
  280 +/* I2C */
  281 +#define CONFIG_HARD_I2C /* I2C with hardware support */
  282 +#undef CONFIG_SOFT_I2C /* I2C bit-banged */
  283 +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  284 +#define CFG_I2C_EEPROM_ADDR 0x57
  285 +#define CFG_I2C_SLAVE 0x7F
  286 +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  287 +
  288 +/*
  289 + * General PCI
  290 + * Addresses are mapped 1-1.
  291 + */
  292 +#define CFG_PCI1_MEM_BASE 0x80000000
  293 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
  294 +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
  295 +#define CFG_PCI1_IO_BASE 0xe2000000
  296 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
  297 +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
  298 +
  299 +#define CFG_PCI2_MEM_BASE 0xa0000000
  300 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
  301 +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
  302 +#define CFG_PCI2_IO_BASE 0xe3000000
  303 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
  304 +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
  305 +
  306 +
  307 +#if defined(CONFIG_PCI)
  308 +
  309 +#define CONFIG_NET_MULTI
  310 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
  311 +
  312 +#undef CONFIG_EEPRO100
  313 +#undef CONFIG_TULIP
  314 +
  315 +#if !defined(CONFIG_PCI_PNP)
  316 + #define PCI_ENET0_IOADDR 0xe0000000
  317 + #define PCI_ENET0_MEMADDR 0xe0000000
  318 + #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
  319 +#endif
  320 +
  321 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  322 +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  323 +
  324 +#endif /* CONFIG_PCI */
  325 +
  326 +
  327 +#if defined(CONFIG_TSEC_ENET)
  328 +
  329 +#ifndef CONFIG_NET_MULTI
  330 +#define CONFIG_NET_MULTI 1
  331 +#endif
  332 +
  333 +#define CONFIG_MII 1 /* MII PHY management */
  334 +#define CONFIG_MPC85XX_TSEC1 1
  335 +#define CONFIG_MPC85XX_TSEC2 1
  336 +#undef CONFIG_MPC85XX_FEC
  337 +#define TSEC1_PHY_ADDR 0
  338 +#define TSEC2_PHY_ADDR 1
  339 +#define FEC_PHY_ADDR 3
  340 +#define TSEC1_PHYIDX 0
  341 +#define TSEC2_PHYIDX 0
  342 +#define FEC_PHYIDX 0
  343 +#define CONFIG_ETHPRIME "MOTO ENET0"
  344 +
  345 +#endif /* CONFIG_TSEC_ENET */
  346 +
  347 +
  348 +
  349 +/*
  350 + * Environment
  351 + */
  352 +#define CFG_ENV_IS_IN_FLASH 1
  353 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
  354 +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
  355 +#define CFG_ENV_SIZE 0x2000
  356 +
  357 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  358 +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  359 +
  360 +#if defined(CONFIG_PCI)
  361 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  362 + | CFG_CMD_PCI \
  363 + | CFG_CMD_PING \
  364 + | CFG_CMD_I2C \
  365 + | CFG_CMD_MII)
  366 +#else
  367 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  368 + | CFG_CMD_PING \
  369 + | CFG_CMD_I2C \
  370 + | CFG_CMD_MII)
  371 +#endif
  372 +
  373 +
  374 +#include <cmd_confdefs.h>
  375 +
  376 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  377 +
  378 +/*
  379 + * Miscellaneous configurable options
  380 + */
  381 +#define CFG_LONGHELP /* undef to save memory */
  382 +#define CFG_LOAD_ADDR 0x2000000 /* default load address */
  383 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  384 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  385 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  386 +#else
  387 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  388 +#endif
  389 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  390 +#define CFG_MAXARGS 16 /* max number of command args */
  391 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  392 +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
  393 +
  394 +/*
  395 + * For booting Linux, the board info and command line data
  396 + * have to be in the first 8 MB of memory, since this is
  397 + * the maximum mapped by the Linux kernel during initialization.
  398 + */
  399 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  400 +
  401 +/* Cache Configuration */
  402 +#define CFG_DCACHE_SIZE 32768
  403 +#define CFG_CACHELINE_SIZE 32
  404 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  405 +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
  406 +#endif
  407 +
  408 +/*
  409 + * Internal Definitions
  410 + *
  411 + * Boot Flags
  412 + */
  413 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  414 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  415 +
  416 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  417 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  418 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  419 +#endif
  420 +
  421 +
  422 +/*
  423 + * Environment Configuration
  424 + */
  425 +
  426 +/* The mac addresses for all ethernet interface */
  427 +#if defined(CONFIG_TSEC_ENET)
  428 +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
  429 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
  430 +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
  431 +#endif
  432 +
  433 +#define CONFIG_IPADDR 192.168.1.253
  434 +
  435 +#define CONFIG_HOSTNAME unknown
  436 +#define CONFIG_ROOTPATH /nfsroot
  437 +#define CONFIG_BOOTFILE your.uImage
  438 +
  439 +#define CONFIG_SERVERIP 192.168.1.1
  440 +#define CONFIG_GATEWAYIP 192.168.1.1
  441 +#define CONFIG_NETMASK 255.255.255.0
  442 +
  443 +#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
  444 +
  445 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  446 +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
  447 +
  448 +#define CONFIG_BAUDRATE 115200
  449 +
  450 +#define CONFIG_EXTRA_ENV_SETTINGS \
  451 + "netdev=eth0\0" \
  452 + "consoledev=ttyS1\0" \
  453 + "ramdiskaddr=400000\0" \
  454 + "ramdiskfile=your.ramdisk.u-boot\0"
  455 +
  456 +#define CONFIG_NFSBOOTCOMMAND \
  457 + "setenv bootargs root=/dev/nfs rw " \
  458 + "nfsroot=$serverip:$rootpath " \
  459 + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  460 + "console=$consoledev,$baudrate $othbootargs;" \
  461 + "tftp $loadaddr $bootfile;" \
  462 + "bootm $loadaddr"
  463 +
  464 +#define CONFIG_RAMBOOTCOMMAND \
  465 + "setenv bootargs root=/dev/ram rw " \
  466 + "console=$consoledev,$baudrate $othbootargs;" \
  467 + "tftp $ramdiskaddr $ramdiskfile;" \
  468 + "tftp $loadaddr $bootfile;" \
  469 + "bootm $loadaddr $ramdiskaddr"
  470 +
  471 +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  472 +
  473 +
  474 +#endif /* __CONFIG_H */
include/configs/MPC8555CDS.h
Diff comments   View file @ 03f5c55
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +/*
  24 + * mpc8555cds board configuration file
  25 + *
  26 + * Please refer to doc/README.mpc85xxcds for more info.
  27 + *
  28 + */
  29 +
  30 +#ifndef __CONFIG_H
  31 +#define __CONFIG_H
  32 +
  33 +/* High Level Configuration Options */
  34 +#define CONFIG_BOOKE 1 /* BOOKE */
  35 +#define CONFIG_E500 1 /* BOOKE e500 family */
  36 +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
  37 +#define CONFIG_MPC8555 1 /* MPC8555 specific */
  38 +#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
  39 +
  40 +#define CONFIG_PCI
  41 +#define CONFIG_TSEC_ENET /* tsec ethernet support */
  42 +#define CONFIG_ENV_OVERWRITE
  43 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  44 +#define CONFIG_DDR_ECC /* only for ECC DDR module */
  45 +#define CONFIG_DDR_DLL /* possible DLL fix needed */
  46 +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
  47 +
  48 +/*
  49 + * When initializing flash, if we cannot find the manufacturer ID,
  50 + * assume this is the AMD flash associated with the CDS board.
  51 + * This allows booting from a promjet.
  52 + */
  53 +#define CONFIG_ASSUME_AMD_FLASH
  54 +
  55 +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
  56 +
  57 +#ifndef __ASSEMBLY__
  58 +extern unsigned long get_clock_freq(void);
  59 +#endif
  60 +#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
  61 +
  62 +/*
  63 + * These can be toggled for performance analysis, otherwise use default.
  64 + */
  65 +#define CONFIG_L2_CACHE /* toggle L2 cache */
  66 +#define CONFIG_BTB /* toggle branch predition */
  67 +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
  68 +
  69 +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  70 +
  71 +#undef CFG_DRAM_TEST /* memory test, takes time */
  72 +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
  73 +#define CFG_MEMTEST_END 0x00400000
  74 +
  75 +
  76 +/*
  77 + * Base addresses -- Note these are effective addresses where the
  78 + * actual resources get mapped (not physical addresses)
  79 + */
  80 +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  81 +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  82 +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
  83 +
  84 +
  85 +/*
  86 + * DDR Setup
  87 + */
  88 +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  89 +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
  90 +
  91 +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  92 +
  93 +/*
  94 + * Make sure required options are set
  95 + */
  96 +#ifndef CONFIG_SPD_EEPROM
  97 +#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  98 +#endif
  99 +
  100 +
  101 +
  102 +/*
  103 + * SDRAM on the Local Bus
  104 + */
  105 +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  106 +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  107 +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
  108 +
  109 +#define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */
  110 +#define CFG_BR1_PRELIM 0xff001001 /* port size 16bit */
  111 +
  112 +#define CFG_OR0_PRELIM 0xff806e61 /* 8MB Flash */
  113 +#define CFG_OR1_PRELIM 0xff806e61 /* 8MB Flash */
  114 +
  115 +#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
  116 +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
  117 +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
  118 +#undef CFG_FLASH_CHECKSUM
  119 +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  120 +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  121 +
  122 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
  123 +
  124 +#define CFG_FLASH_CFI_DRIVER
  125 +#define CFG_FLASH_CFI
  126 +#define CFG_FLASH_EMPTY_INFO
  127 +
  128 +#undef CONFIG_CLOCKS_IN_MHZ
  129 +
  130 +/*
  131 + * Local Bus Definitions
  132 + */
  133 +
  134 +/*
  135 + * Base Register 2 and Option Register 2 configure SDRAM.
  136 + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
  137 + *
  138 + * For BR2, need:
  139 + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  140 + * port-size = 32-bits = BR2[19:20] = 11
  141 + * no parity checking = BR2[21:22] = 00
  142 + * SDRAM for MSEL = BR2[24:26] = 011
  143 + * Valid = BR[31] = 1
  144 + *
  145 + * 0 4 8 12 16 20 24 28
  146 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  147 + *
  148 + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
  149 + * FIXME: the top 17 bits of BR2.
  150 + */
  151 +
  152 +#define CFG_BR2_PRELIM 0xf0001861
  153 +
  154 +/*
  155 + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
  156 + *
  157 + * For OR2, need:
  158 + * 64MB mask for AM, OR2[0:7] = 1111 1100
  159 + * XAM, OR2[17:18] = 11
  160 + * 9 columns OR2[19-21] = 010
  161 + * 13 rows OR2[23-25] = 100
  162 + * EAD set for extra time OR[31] = 1
  163 + *
  164 + * 0 4 8 12 16 20 24 28
  165 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  166 + */
  167 +
  168 +#define CFG_OR2_PRELIM 0xfc006901
  169 +
  170 +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  171 +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
  172 +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  173 +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  174 +
  175 +/*
  176 + * LSDMR masks
  177 + */
  178 +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
  179 +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
  180 +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
  181 +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
  182 +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
  183 +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
  184 +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
  185 +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
  186 +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
  187 +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
  188 +
  189 +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
  190 +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
  191 +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
  192 +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
  193 +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
  194 +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
  195 +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
  196 +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
  197 +
  198 +/*
  199 + * Common settings for all Local Bus SDRAM commands.
  200 + * At run time, either BSMA1516 (for CPU 1.1)
  201 + * or BSMA1617 (for CPU 1.0) (old)
  202 + * is OR'ed in too.
  203 + */
  204 +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
  205 + | CFG_LBC_LSDMR_PRETOACT7 \
  206 + | CFG_LBC_LSDMR_ACTTORW7 \
  207 + | CFG_LBC_LSDMR_BL8 \
  208 + | CFG_LBC_LSDMR_WRC4 \
  209 + | CFG_LBC_LSDMR_CL3 \
  210 + | CFG_LBC_LSDMR_RFEN \
  211 + )
  212 +
  213 +/*
  214 + * The CADMUS registers are connected to CS3 on CDS.
  215 + * The new memory map places CADMUS at 0xf8000000.
  216 + *
  217 + * For BR3, need:
  218 + * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
  219 + * port-size = 8-bits = BR[19:20] = 01
  220 + * no parity checking = BR[21:22] = 00
  221 + * GPMC for MSEL = BR[24:26] = 000
  222 + * Valid = BR[31] = 1
  223 + *
  224 + * 0 4 8 12 16 20 24 28
  225 + * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
  226 + *
  227 + * For OR3, need:
  228 + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
  229 + * disable buffer ctrl OR[19] = 0
  230 + * CSNT OR[20] = 1
  231 + * ACS OR[21:22] = 11
  232 + * XACS OR[23] = 1
  233 + * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
  234 + * SETA OR[28] = 0
  235 + * TRLX OR[29] = 1
  236 + * EHTR OR[30] = 1
  237 + * EAD extra time OR[31] = 1
  238 + *
  239 + * 0 4 8 12 16 20 24 28
  240 + * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  241 + */
  242 +
  243 +#define CADMUS_BASE_ADDR 0xf8000000
  244 +#define CFG_BR3_PRELIM 0xf8000801
  245 +#define CFG_OR3_PRELIM 0xfff00ff7
  246 +
  247 +
  248 +#define CONFIG_L1_INIT_RAM
  249 +#define CFG_INIT_RAM_LOCK 1
  250 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  251 +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
  252 +
  253 +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
  254 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  255 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  256 +
  257 +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  258 +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  259 +
  260 +/* Serial Port */
  261 +#define CONFIG_CONS_INDEX 2
  262 +#undef CONFIG_SERIAL_SOFTWARE_FIFO
  263 +#define CFG_NS16550
  264 +#define CFG_NS16550_SERIAL
  265 +#define CFG_NS16550_REG_SIZE 1
  266 +#define CFG_NS16550_CLK get_bus_freq(0)
  267 +
  268 +#define CFG_BAUDRATE_TABLE \
  269 + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  270 +
  271 +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
  272 +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
  273 +
  274 +/* Use the HUSH parser */
  275 +#define CFG_HUSH_PARSER
  276 +#ifdef CFG_HUSH_PARSER
  277 +#define CFG_PROMPT_HUSH_PS2 "> "
  278 +#endif
  279 +
  280 +/* I2C */
  281 +#define CONFIG_HARD_I2C /* I2C with hardware support */
  282 +#undef CONFIG_SOFT_I2C /* I2C bit-banged */
  283 +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  284 +#define CFG_I2C_EEPROM_ADDR 0x57
  285 +#define CFG_I2C_SLAVE 0x7F
  286 +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  287 +
  288 +/*
  289 + * General PCI
  290 + * Addresses are mapped 1-1.
  291 + */
  292 +#define CFG_PCI1_MEM_BASE 0x80000000
  293 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
  294 +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
  295 +#define CFG_PCI1_IO_BASE 0xe2000000
  296 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
  297 +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
  298 +
  299 +#define CFG_PCI2_MEM_BASE 0xa0000000
  300 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
  301 +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
  302 +#define CFG_PCI2_IO_BASE 0xe3000000
  303 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
  304 +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
  305 +
  306 +
  307 +#if defined(CONFIG_PCI)
  308 +
  309 +#define CONFIG_NET_MULTI
  310 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
  311 +
  312 +#undef CONFIG_EEPRO100
  313 +#undef CONFIG_TULIP
  314 +
  315 +#if !defined(CONFIG_PCI_PNP)
  316 + #define PCI_ENET0_IOADDR 0xe0000000
  317 + #define PCI_ENET0_MEMADDR 0xe0000000
  318 + #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
  319 +#endif
  320 +
  321 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  322 +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  323 +
  324 +#endif /* CONFIG_PCI */
  325 +
  326 +
  327 +#if defined(CONFIG_TSEC_ENET)
  328 +
  329 +#ifndef CONFIG_NET_MULTI
  330 +#define CONFIG_NET_MULTI 1
  331 +#endif
  332 +
  333 +#define CONFIG_MII 1 /* MII PHY management */
  334 +#define CONFIG_MPC85XX_TSEC1 1
  335 +#define CONFIG_MPC85XX_TSEC2 1
  336 +#undef CONFIG_MPC85XX_FEC
  337 +#define TSEC1_PHY_ADDR 0
  338 +#define TSEC2_PHY_ADDR 1
  339 +#define FEC_PHY_ADDR 3
  340 +#define TSEC1_PHYIDX 0
  341 +#define TSEC2_PHYIDX 0
  342 +#define FEC_PHYIDX 0
  343 +#define CONFIG_ETHPRIME "MOTO ENET0"
  344 +
  345 +#endif /* CONFIG_TSEC_ENET */
  346 +
  347 +
  348 +
  349 +/*
  350 + * Environment
  351 + */
  352 +#define CFG_ENV_IS_IN_FLASH 1
  353 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
  354 +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
  355 +#define CFG_ENV_SIZE 0x2000
  356 +
  357 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  358 +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  359 +
  360 +#if defined(CONFIG_PCI)
  361 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  362 + | CFG_CMD_PCI \
  363 + | CFG_CMD_PING \
  364 + | CFG_CMD_I2C \
  365 + | CFG_CMD_MII)
  366 +#else
  367 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  368 + | CFG_CMD_PING \
  369 + | CFG_CMD_I2C \
  370 + | CFG_CMD_MII)
  371 +#endif
  372 +
  373 +
  374 +#include <cmd_confdefs.h>
  375 +
  376 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  377 +
  378 +/*
  379 + * Miscellaneous configurable options
  380 + */
  381 +#define CFG_LONGHELP /* undef to save memory */
  382 +#define CFG_LOAD_ADDR 0x2000000 /* default load address */
  383 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  384 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  385 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  386 +#else
  387 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  388 +#endif
  389 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  390 +#define CFG_MAXARGS 16 /* max number of command args */
  391 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  392 +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
  393 +
  394 +/*
  395 + * For booting Linux, the board info and command line data
  396 + * have to be in the first 8 MB of memory, since this is
  397 + * the maximum mapped by the Linux kernel during initialization.
  398 + */
  399 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  400 +
  401 +/* Cache Configuration */
  402 +#define CFG_DCACHE_SIZE 32768
  403 +#define CFG_CACHELINE_SIZE 32
  404 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  405 +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
  406 +#endif
  407 +
  408 +/*
  409 + * Internal Definitions
  410 + *
  411 + * Boot Flags
  412 + */
  413 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  414 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  415 +
  416 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  417 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  418 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  419 +#endif
  420 +
  421 +
  422 +/*
  423 + * Environment Configuration
  424 + */
  425 +
  426 +/* The mac addresses for all ethernet interface */
  427 +#if defined(CONFIG_TSEC_ENET)
  428 +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
  429 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
  430 +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
  431 +#endif
  432 +
  433 +#define CONFIG_IPADDR 192.168.1.253
  434 +
  435 +#define CONFIG_HOSTNAME unknown
  436 +#define CONFIG_ROOTPATH /nfsroot
  437 +#define CONFIG_BOOTFILE your.uImage
  438 +
  439 +#define CONFIG_SERVERIP 192.168.1.1
  440 +#define CONFIG_GATEWAYIP 192.168.1.1
  441 +#define CONFIG_NETMASK 255.255.255.0
  442 +
  443 +#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
  444 +
  445 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  446 +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
  447 +
  448 +#define CONFIG_BAUDRATE 115200
  449 +
  450 +#define CONFIG_EXTRA_ENV_SETTINGS \
  451 + "netdev=eth0\0" \
  452 + "consoledev=ttyS1\0" \
  453 + "ramdiskaddr=400000\0" \
  454 + "ramdiskfile=your.ramdisk.u-boot\0"
  455 +
  456 +#define CONFIG_NFSBOOTCOMMAND \
  457 + "setenv bootargs root=/dev/nfs rw " \
  458 + "nfsroot=$serverip:$rootpath " \
  459 + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  460 + "console=$consoledev,$baudrate $othbootargs;" \
  461 + "tftp $loadaddr $bootfile;" \
  462 + "bootm $loadaddr"
  463 +
  464 +#define CONFIG_RAMBOOTCOMMAND \
  465 + "setenv bootargs root=/dev/ram rw " \
  466 + "console=$consoledev,$baudrate $othbootargs;" \
  467 + "tftp $ramdiskaddr $ramdiskfile;" \
  468 + "tftp $loadaddr $bootfile;" \
  469 + "bootm $loadaddr $ramdiskaddr"
  470 +
  471 +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  472 +
  473 +
  474 +#endif /* __CONFIG_H */
... ... @@ -779,9 +779,7 @@
779 779 load_sernum_ethaddr ();
780 780 #endif
781 781  
782   -#if defined(CFG_GT_6426x) || defined(CONFIG_PN62) || defined(CONFIG_PPCHAMELEONEVB) || \
783   - defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8555CDS) || \
784   - defined(CONFIG_MPC8560ADS) || defined(CONFIG_440_GX)
  782 +#if defined(CONFIG_ETH1ADDR)
785 783 /* handle the 2nd ethernet address */
786 784  
787 785 s = getenv ("eth1addr");
... ... @@ -792,9 +790,7 @@
792 790 s = (*e) ? e + 1 : e;
793 791 }
794 792 #endif
795   -#if defined(CFG_GT_6426x) || defined(CONFIG_MPC8540ADS) || \
796   - defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8560ADS) || \
797   - defined(CONFIG_440_GX)
  793 +#if defined(CONFIG_ETH2ADDR)
798 794 /* handle the 3rd ethernet address */
799 795  
800 796 s = getenv ("eth2addr");
... ... @@ -810,7 +806,7 @@
810 806 }
811 807 #endif
812 808  
813   -#if defined(CONFIG_440_GX)
  809 +#if defined(CONFIG_ETH3ADDR)
814 810 /* handle 4th ethernet address */
815 811 s = getenv("eth3addr");
816 812 #if defined(CONFIG_XPEDITE1K)