sh: Update MS7750SE01 platform

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

sh: Update MS7750SE01 platform
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu
1 parent 516ad760db
Showing 3 changed files with 94 additions and 50 deletions Side-by-side Diff
board/ms7750se/lowlevel_init.S
board/ms7750se/ms7750se.c
include/configs/ms7750se.h
 /*
-	modified from SH-IPL+g
-	Renesaso SuperH Solution Enginge MS775x BSC setting 
-	Coyright (c) 2007 Nobuhiro Iwamatsu
+ modified from SH-IPL+g
+ Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
+
+ Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R 
+ 
+ Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
 */
  
 #include <config.h>
  
  
  
  
  
  
  
@@ -9,38 +30,34 @@
  
 #include <asm/processor.h>
  
-#ifdef CONFIG_CPU_SUBTYPE_SH7751
+#ifdef CONFIG_CPU_SH7751
 #define BCR2_D_VALUE	0x2FFC	   /* Area 1-6 width: 32/32/32/32/32/16 */
 #define WCR1_D_VALUE    0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
-#ifdef CONFIG_MRSHPC
+#ifdef CONFIG_MARUBUN_PCCARD
 #define WCR2_D_VALUE    0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
 				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
-#else /* CONFIG_MRSHPC*/
+#else /* CONFIG_MARUBUN_PCCARD */
 #define WCR2_D_VALUE    0x7FFE4FE7 /* A6:3  A6B:7 A5:15 A5B:7 A4:15
 				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
-#endif /* CONFIG_MRSHPC */
+#endif /* CONFIG_MARUBUN_PCCARD */
 #define WCR3_D_VALUE	0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
 				      A2: 1-3 A1: 1-3 A0: 0-1 */
-#define LED_ADDRESS	0xBA000000 /* Address of LED register */ 	
 #define RTCOR_D_VALUE	0xA50D	   /* Write code A5, data 0D (~15us?) */
 #define SDMR3_ADDRESS	0xFF940088 /* SDMR3 address on 32-bit bus */
 #define MCR_D1_VALUE	0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
 #define MCR_D2_VALUE	0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
-#define SWITCH_ADDR	0xB9000000 /* Address of DIP switches */
-#else /* CONFIG_CPU_SUBTYPE_SH7751 */
+#else /* CONFIG_CPU_SH7751 */
 #define BCR2_D_VALUE	0x2E3C	   /* Area 1-6 width: 32/32/64/16/32/16 */
 #define WCR1_D_VALUE	0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
 #define WCR2_D_VALUE	0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
 				      A3:2  A2:15 A1:15 A0:15 A0B:7  */
 #define WCR3_D_VALUE	0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
 				      A2: 1-3 A1: 1-3 A0: 0-1 */
-#define LED_ADDRESS	0xB0C00000 /* Address of LED register */ 	
 #define RTCOR_D_VALUE	0xA510	   /* Write code A5, data 10 (~15us?) */
 #define SDMR3_ADDRESS	0xFF940110 /* SDMR3 address on 64-bit bus */
 #define MCR_D1_VALUE	0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
 #define MCR_D2_VALUE	0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
-#define SWITCH_ADDR	0xb0800000 /* Address of DIP switches */
-#endif /* CONFIG_CPU_SUBTYPE_SH7751 */
+#endif /* CONFIG_CPU_SH7751 */
  
 	.global lowlevel_init
 	.text
@@ -48,8 +65,8 @@
  
 lowlevel_init:
  
-	mov.l   L_CCR, r1               ! CCR Address
-	mov.l   L_CCR_DISABLE, r0       ! CCR Data
+	mov.l   CCR_A, r1               ! CCR Address
+	mov.l   CCR_D_DISABLE, r0       ! CCR Data
 	mov.l   r0, @r1
  
 init_bsc:
@@ -77,11 +94,6 @@
 	mov.l	WCR3_D,r0	/* WCR3 Data */
 	mov.l	r0,@r1
  
-	mov.l	LED_A,r1	/* LED Address */
-	mov	#0xff,r0	/* LED ALL 'on' */
-	shll8	r0
-	mov.w	r0,@r1
-
 	mov.l	MCR_A,r1	/* MCR Address */
 	mov.l	MCR_D1,r0	/* MCR Data1 */
 	mov.l	r0,@r1
  
  
  
@@ -129,19 +141,19 @@
  
 	.align	2
  
-L_CCR:          .long   CCR
-L_CCR_DISABLE:  .long   0x0808
+CCR_A:          .long   CCR
+CCR_D_DISABLE:  .long   0x0808
 FRQCR_A:	.long	FRQCR
 FRQCR_D:
-#ifdef CONFIG_CPU_SUBTYPE_SH_R
+#ifdef CONFIG_CPU_TYPE_R
 		.long	0x00000e1a	/* 12:3:3 */
-#else
+#else	/* CONFIG_CPU_TYPE_R */
 #ifdef CONFIG_GOOD_SESH4
 		.long	0x00000e13	/* 6:2:1 */
 #else
 		.long	0x00000e23	/* 6:1:1 */
 #endif
-#endif	/* CONFIG_CPU_SUBTYPE_SH_R */
+#endif	/* CONFIG_CPU_TYPE_R */
  
 BCR1_A:		.long	BCR1
 BCR1_D:		.long	0x00000008	/* Area 3 SDRAM */
@@ -153,7 +165,6 @@
 WCR2_D:		.long	WCR2_D_VALUE	/* Per-area access and burst wait states */
 WCR3_A:		.long	WCR3
 WCR3_D:		.long	WCR3_D_VALUE	/* Address setup and data hold cycles */
-LED_A:		.long	LED_ADDRESS	/* LED Address */
 RTCSR_A:	.long	RTCSR	
 RTCSR_D:	.long	0xA518		/* RTCSR Write Code A5h Data 18h */
 RTCNT_A:	.long	RTCNT
@@ -26,7 +26,7 @@
  
 int checkboard(void)
 {
-	puts("BOARD: SH7750 Solution Engine\n");
+	puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
 	return 0;
 }
  
-#ifndef __CONFIG_H
-#define __CONFIG_H
+/*
+ * Configuation settings for the Hitachi Solution Engine 7750
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
  
-#undef DEBUG
+#ifndef __MS7750SE_H
+#define __MS7750SE_H
  
+#undef DEBUG
 #define CONFIG_SH		1
 #define CONFIG_SH4		1
 #define CONFIG_CPU_SH7750	1
+/* #define CONFIG_CPU_SH7751	1 */
+/* #define CONFIG_CPU_TYPE_R	1 */
 #define CONFIG_MS7750SE		1
 #define __LITTLE_ENDIAN__	1
  
-//#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_NET |CFG_CMD_PING)
-#define CONFIG_COMMANDS        	CONFIG_CMD_DFL & ~CFG_CMD_NET 
+/*
+ * Command line configuration.
+ */
+//#include <config_cmd_default.h>
  
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_ENV
+
 #define CFG_SCIF_CONSOLE	1
 #define CONFIG_BAUDRATE		38400
 #define CONFIG_CONS_SCIF1	1
 #define BOARD_LATE_INIT		1
  
-#include <cmd_confdefs.h>
-
 #define CONFIG_BOOTDELAY	-1
-#define CONFIG_BOOTARGS    	"console=ttySC0,115200"
+#define CONFIG_BOOTARGS    	"console=ttySC0,38400"
 #define CONFIG_ENV_OVERWRITE	1
  
+/* SDRAM */
 #define CFG_SDRAM_BASE		(0x8C000000)
 #define CFG_SDRAM_SIZE		(64 * 1024 * 1024)
  
 #define CFG_LONGHELP		
-#define CFG_PROMPT		"=> "		
-#define CFG_CBSIZE		256	
-#define CFG_PBSIZE		256	
+#define CFG_PROMPT		"=> "
+#define CFG_CBSIZE		256
+#define CFG_PBSIZE		256
 #define CFG_MAXARGS		16
-#define CFG_BARGSIZE		512	
-#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }		/* List of legal baudrate settings for this board */
+#define CFG_BARGSIZE		512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
  
 #define CFG_MEMTEST_START	(CFG_SDRAM_BASE)
 #define CFG_MEMTEST_END		(TEXT_BASE - 0x100000)
  
+/* NOR Flash */
+/* #define CFG_FLASH_BASE		(0xA1000000)*/
+#define CFG_FLASH_BASE		(0xA0000000)
+#define CFG_MAX_FLASH_BANKS	(1)	/* Max number of 
+				 	 * Flash memory banks
+				 	 */
+#define CFG_MAX_FLASH_SECT	142
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
  
 #define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 4 * 1024 * 1024)
 #define CFG_MONITOR_BASE	(CFG_FLASH_BASE)	/* Address of u-boot image in Flash */
-#define CFG_MONITOR_LEN		(128 * 1024)	
+#define CFG_MONITOR_LEN		(128 * 1024)
 #define CFG_MALLOC_LEN		(256 * 1024)		/* Size of DRAM reserved for malloc() use */
  
 #define CFG_GBL_DATA_SIZE	(256)			/* size in bytes reserved for initial data */
-#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)	
+#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)
 #define CFG_RX_ETH_BUFFER	(8)
  
 #define CFG_FLASH_CFI
@@ -53,12 +92,6 @@
 #undef  CFG_FLASH_QUIET_TEST
 #define CFG_FLASH_EMPTY_INFO				/* print 'E' for empty sector on flinfo */
  
-#define CFG_FLASH_BASE		(0xA1000000)
-#define CFG_MAX_FLASH_BANKS	(1)			/* Max number of 
-						 	 * Flash memory banks
-						 	 */
-#define CFG_MAX_FLASH_SECT	142
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
  
 #define CFG_ENV_IS_IN_FLASH
 #define CFG_ENV_SECT_SIZE	0x20000
  
  
@@ -67,10 +100,10 @@
 #define CFG_FLASH_ERASE_TOUT  	120000
 #define CFG_FLASH_WRITE_TOUT	500
  
+/* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
 #define TMU_CLK_DIVIDER		4
 #define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
-#define	CFG_PLL_SETTLING_TIME	100		/* in us */
  
-#endif /* __CONFIG_H */
+#endif /* __MS7750SE_H */
1	1	/*
2		- modified from SH-IPL+g
3		- Renesaso SuperH Solution Enginge MS775x BSC setting
4		- Coyright (c) 2007 Nobuhiro Iwamatsu
	2	+ modified from SH-IPL+g
	3	+ Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
	4	+
	5	+ Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
	6	+
	7	+ Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
	8	+
	9	+ * See file CREDITS for list of people who contributed to this
	10	+ * project.
	11	+ *
	12	+ * This program is free software; you can redistribute it and/or
	13	+ * modify it under the terms of the GNU General Public License as
	14	+ * published by the Free Software Foundation; either version 2 of
	15	+ * the License, or (at your option) any later version.
	16	+ *
	17	+ * This program is distributed in the hope that it will be useful,
	18	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	+ * GNU General Public License for more details.
	21	+ *
	22	+ * You should have received a copy of the GNU General Public License
	23	+ * along with this program; if not, write to the Free Software
	24	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	+ * MA 02111-1307 USA
5	26	*/
6	27
7	28	#include <config.h>
8	29
9	30
10	31
11	32
12	33
13	34
14	35
...	...	@@ -9,38 +30,34 @@
9	30
10	31	#include <asm/processor.h>
11	32
12		-#ifdef CONFIG_CPU_SUBTYPE_SH7751
	33	+#ifdef CONFIG_CPU_SH7751
13	34	#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
14	35	#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
15		-#ifdef CONFIG_MRSHPC
	36	+#ifdef CONFIG_MARUBUN_PCCARD
16	37	#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
17	38	A3:2 A2:15 A1:15 A0:6 A0B:7 */
18		-#else /* CONFIG_MRSHPC*/
	39	+#else /* CONFIG_MARUBUN_PCCARD */
19	40	#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
20	41	A3:2 A2:15 A1:15 A0:6 A0B:7 */
21		-#endif /* CONFIG_MRSHPC */
	42	+#endif /* CONFIG_MARUBUN_PCCARD */
22	43	#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
23	44	A2: 1-3 A1: 1-3 A0: 0-1 */
24		-#define LED_ADDRESS 0xBA000000 /* Address of LED register */
25	45	#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
26	46	#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
27	47	#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
28	48	#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
29		-#define SWITCH_ADDR 0xB9000000 /* Address of DIP switches */
30		-#else /* CONFIG_CPU_SUBTYPE_SH7751 */
	49	+#else /* CONFIG_CPU_SH7751 */
31	50	#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
32	51	#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
33	52	#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
34	53	A3:2 A2:15 A1:15 A0:15 A0B:7 */
35	54	#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
36	55	A2: 1-3 A1: 1-3 A0: 0-1 */
37		-#define LED_ADDRESS 0xB0C00000 /* Address of LED register */
38	56	#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
39	57	#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
40	58	#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
41	59	#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
42		-#define SWITCH_ADDR 0xb0800000 /* Address of DIP switches */
43		-#endif /* CONFIG_CPU_SUBTYPE_SH7751 */
	60	+#endif /* CONFIG_CPU_SH7751 */
44	61
45	62	.global lowlevel_init
46	63	.text
...	...	@@ -48,8 +65,8 @@
48	65
49	66	lowlevel_init:
50	67
51		- mov.l L_CCR, r1 ! CCR Address
52		- mov.l L_CCR_DISABLE, r0 ! CCR Data
	68	+ mov.l CCR_A, r1 ! CCR Address
	69	+ mov.l CCR_D_DISABLE, r0 ! CCR Data
53	70	mov.l r0, @r1
54	71
55	72	init_bsc:
...	...	@@ -77,11 +94,6 @@
77	94	mov.l WCR3_D,r0 /* WCR3 Data */
78	95	mov.l r0,@r1
79	96
80		- mov.l LED_A,r1 /* LED Address */
81		- mov #0xff,r0 /* LED ALL 'on' */
82		- shll8 r0
83		- mov.w r0,@r1
84		-
85	97	mov.l MCR_A,r1 /* MCR Address */
86	98	mov.l MCR_D1,r0 /* MCR Data1 */
87	99	mov.l r0,@r1
88	100
89	101
90	102
...	...	@@ -129,19 +141,19 @@
129	141
130	142	.align 2
131	143
132		-L_CCR: .long CCR
133		-L_CCR_DISABLE: .long 0x0808
	144	+CCR_A: .long CCR
	145	+CCR_D_DISABLE: .long 0x0808
134	146	FRQCR_A: .long FRQCR
135	147	FRQCR_D:
136		-#ifdef CONFIG_CPU_SUBTYPE_SH_R
	148	+#ifdef CONFIG_CPU_TYPE_R
137	149	.long 0x00000e1a /* 12:3:3 */
138		-#else
	150	+#else /* CONFIG_CPU_TYPE_R */
139	151	#ifdef CONFIG_GOOD_SESH4
140	152	.long 0x00000e13 /* 6:2:1 */
141	153	#else
142	154	.long 0x00000e23 /* 6:1:1 */
143	155	#endif
144		-#endif /* CONFIG_CPU_SUBTYPE_SH_R */
	156	+#endif /* CONFIG_CPU_TYPE_R */
145	157
146	158	BCR1_A: .long BCR1
147	159	BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
...	...	@@ -153,7 +165,6 @@
153	165	WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
154	166	WCR3_A: .long WCR3
155	167	WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
156		-LED_A: .long LED_ADDRESS /* LED Address */
157	168	RTCSR_A: .long RTCSR
158	169	RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */
159	170	RTCNT_A: .long RTCNT
...	...	@@ -26,7 +26,7 @@
26	26
27	27	int checkboard(void)
28	28	{
29		- puts("BOARD: SH7750 Solution Engine\n");
	29	+ puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
30	30	return 0;
31	31	}
32	32
1		-#ifndef __CONFIG_H
2		-#define __CONFIG_H
	1	+/*
	2	+ * Configuation settings for the Hitachi Solution Engine 7750
	3	+ *
	4	+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	5	+ *
	6	+ * See file CREDITS for list of people who contributed to this
	7	+ * project.
	8	+ *
	9	+ * This program is free software; you can redistribute it and/or
	10	+ * modify it under the terms of the GNU General Public License as
	11	+ * published by the Free Software Foundation; either version 2 of
	12	+ * the License, or (at your option) any later version.
	13	+ *
	14	+ * This program is distributed in the hope that it will be useful,
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ *
	19	+ * You should have received a copy of the GNU General Public License
	20	+ * along with this program; if not, write to the Free Software
	21	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	+ * MA 02111-1307 USA
	23	+ */
3	24
4		-#undef DEBUG
	25	+#ifndef __MS7750SE_H
	26	+#define __MS7750SE_H
5	27
	28	+#undef DEBUG
6	29	#define CONFIG_SH 1
7	30	#define CONFIG_SH4 1
8	31	#define CONFIG_CPU_SH7750 1
	32	+/* #define CONFIG_CPU_SH7751 1 */
	33	+/* #define CONFIG_CPU_TYPE_R 1 */
9	34	#define CONFIG_MS7750SE 1
10	35	#define __LITTLE_ENDIAN__ 1
11	36
12		-//#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| CFG_CMD_NET \|CFG_CMD_PING)
13		-#define CONFIG_COMMANDS CONFIG_CMD_DFL & ~CFG_CMD_NET
	37	+/*
	38	+ * Command line configuration.
	39	+ */
	40	+//#include <config_cmd_default.h>
14	41
	42	+#define CONFIG_CMD_DFL
	43	+#define CONFIG_CMD_FLASH
	44	+#define CONFIG_CMD_ENV
	45	+
15	46	#define CFG_SCIF_CONSOLE 1
16	47	#define CONFIG_BAUDRATE 38400
17	48	#define CONFIG_CONS_SCIF1 1
18	49	#define BOARD_LATE_INIT 1
19	50
20		-#include <cmd_confdefs.h>
21		-
22	51	#define CONFIG_BOOTDELAY -1
23		-#define CONFIG_BOOTARGS "console=ttySC0,115200"
	52	+#define CONFIG_BOOTARGS "console=ttySC0,38400"
24	53	#define CONFIG_ENV_OVERWRITE 1
25	54
	55	+/* SDRAM */
26	56	#define CFG_SDRAM_BASE (0x8C000000)
27	57	#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
28	58
29	59	#define CFG_LONGHELP
30		-#define CFG_PROMPT "=> "
31		-#define CFG_CBSIZE 256
32		-#define CFG_PBSIZE 256
	60	+#define CFG_PROMPT "=> "
	61	+#define CFG_CBSIZE 256
	62	+#define CFG_PBSIZE 256
33	63	#define CFG_MAXARGS 16
34		-#define CFG_BARGSIZE 512
35		-#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } /* List of legal baudrate settings for this board */
	64	+#define CFG_BARGSIZE 512
	65	+/* List of legal baudrate settings for this board */
	66	+#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
36	67
37	68	#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
38	69	#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
39	70
	71	+/* NOR Flash */
	72	+/* #define CFG_FLASH_BASE (0xA1000000)*/
	73	+#define CFG_FLASH_BASE (0xA0000000)
	74	+#define CFG_MAX_FLASH_BANKS (1) /* Max number of
	75	+ * Flash memory banks
	76	+ */
	77	+#define CFG_MAX_FLASH_SECT 142
	78	+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
40	79
41	80	#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
42	81	#define CFG_MONITOR_BASE (CFG_FLASH_BASE) /* Address of u-boot image in Flash */
43		-#define CFG_MONITOR_LEN (128 * 1024)
	82	+#define CFG_MONITOR_LEN (128 * 1024)
44	83	#define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
45	84
46	85	#define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */
47		-#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
	86	+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
48	87	#define CFG_RX_ETH_BUFFER (8)
49	88
50	89	#define CFG_FLASH_CFI
...	...	@@ -53,12 +92,6 @@
53	92	#undef CFG_FLASH_QUIET_TEST
54	93	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
55	94
56		-#define CFG_FLASH_BASE (0xA1000000)
57		-#define CFG_MAX_FLASH_BANKS (1) /* Max number of
58		- * Flash memory banks
59		- */
60		-#define CFG_MAX_FLASH_SECT 142
61		-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
62	95
63	96	#define CFG_ENV_IS_IN_FLASH
64	97	#define CFG_ENV_SECT_SIZE 0x20000
65	98
66	99
...	...	@@ -67,10 +100,10 @@
67	100	#define CFG_FLASH_ERASE_TOUT 120000
68	101	#define CFG_FLASH_WRITE_TOUT 500
69	102
	103	+/* Board Clock */
70	104	#define CONFIG_SYS_CLK_FREQ 33333333
71	105	#define TMU_CLK_DIVIDER 4
72	106	#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
73		-#define CFG_PLL_SETTLING_TIME 100 /* in us */
74	107
75		-#endif /* __CONFIG_H */
	108	+#endif /* __MS7750SE_H */