powerpc/usb: fix bug of CPU hang when missing USB PHY clock

when missing USB PHY clock, u-boot will hang during USB initialization when issuing "usb start". We should check USBGP[PHY_CLK_VALID] bit to avoid CPU hanging in this case. Due to controller issue of PHY_CLK_VALID in ULPI mode, we set USB_EN before checking PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: Marek Vasut <marex@denx.de>

powerpc/usb: fix bug of CPU hang when missing USB PHY clock
when missing USB PHY clock, u-boot will hang during USB initialization when issuing "usb start". We should check USBGP[PHY_CLK_VALID] bit to avoid CPU hanging in this case. Due to controller issue of PHY_CLK_VALID in ULPI mode, we set USB_EN before checking PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
Shengzhou Liu · Marek Vasut
1 parent 8b8d779dac
Showing 1 changed file with 16 additions and 6 deletions Side-by-side Diff
drivers/usb/host/ehci-fsl.c
@@ -30,6 +30,18 @@
  
 #include "ehci.h"
  
+/* Check USB PHY clock valid */
+static int usb_phy_clk_valid(struct usb_ehci *ehci)
+{
+	if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
+			in_be32(&ehci->prictrl))) {
+		printf("USB PHY clock invalid!\n");
+		return 0;
+	} else {
+		return 1;
+	}
+}
+
 /*
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
  
  
  
  
@@ -82,17 +94,15 @@
 		udelay(1000); /* delay required for PHY Clk to appear */
 #endif
 		out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
+		setbits_be32(&ehci->control, USB_EN);
 	} else {
-#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
-		clrbits_be32(&ehci->control, UTMI_PHY_EN);
 		setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
+		clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
 		udelay(1000); /* delay required for PHY Clk to appear */
-#endif
+		if (!usb_phy_clk_valid(ehci))
+			return -EINVAL;
 		out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
 	}
-
-	/* Enable interface. */
-	setbits_be32(&ehci->control, USB_EN);
  
 	out_be32(&ehci->prictrl, 0x0000000c);
 	out_be32(&ehci->age_cnt_limit, 0x00000040);
...	...	@@ -30,6 +30,18 @@
30	30
31	31	#include "ehci.h"
32	32
	33	+/* Check USB PHY clock valid */
	34	+static int usb_phy_clk_valid(struct usb_ehci *ehci)
	35	+{
	36	+ if (!((in_be32(&ehci->control) & PHY_CLK_VALID) \|\|
	37	+ in_be32(&ehci->prictrl))) {
	38	+ printf("USB PHY clock invalid!\n");
	39	+ return 0;
	40	+ } else {
	41	+ return 1;
	42	+ }
	43	+}
	44	+
33	45	/*
34	46	* Create the appropriate control structures to manage
35	47	* a new EHCI host controller.
36	48
37	49
38	50
39	51
...	...	@@ -82,17 +94,15 @@
82	94	udelay(1000); /* delay required for PHY Clk to appear */
83	95	#endif
84	96	out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
	97	+ setbits_be32(&ehci->control, USB_EN);
85	98	} else {
86		-#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
87		- clrbits_be32(&ehci->control, UTMI_PHY_EN);
88	99	setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
	100	+ clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
89	101	udelay(1000); /* delay required for PHY Clk to appear */
90		-#endif
	102	+ if (!usb_phy_clk_valid(ehci))
	103	+ return -EINVAL;
91	104	out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
92	105	}
93		-
94		- /* Enable interface. */
95		- setbits_be32(&ehci->control, USB_EN);
96	106
97	107	out_be32(&ehci->prictrl, 0x0000000c);
98	108	out_be32(&ehci->age_cnt_limit, 0x00000040);