Commit 04818bbdc34cb02b2590af8e5f77118ed8a8d755
Committed by
York Sun
York Sun
1 parent
3bab3d8324
Exists in
v2017.01-smarct4x
and in
37 other branches
driver/nand: Update SRAM initialize logic for IFC.
IFC controller v1.1.0 requires internal SRAM initialize by reading NAND flash. Higher controller versions have provided "SRAM init" bit in NCFGR register space. update SRAM initialize logic to reflect the same. Also print error message in case of Page read error. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Showing 2 changed files with 33 additions and 4 deletions Side-by-side Diff
drivers/mtd/nand/fsl_ifc_nand.c
| ... | ... | @@ -806,12 +806,30 @@ |
| 806 | 806 | { |
| 807 | 807 | } |
| 808 | 808 | |
| 809 | -static void fsl_ifc_sram_init(void) | |
| 809 | +static int fsl_ifc_sram_init(uint32_t ver) | |
| 810 | 810 | { |
| 811 | 811 | struct fsl_ifc *ifc = ifc_ctrl->regs; |
| 812 | 812 | uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0; |
| 813 | + uint32_t ncfgr = 0; | |
| 813 | 814 | long long end_tick; |
| 814 | 815 | |
| 816 | + if (ver > FSL_IFC_V1_1_0) { | |
| 817 | + ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr); | |
| 818 | + ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN); | |
| 819 | + | |
| 820 | + /* wait for SRAM_INIT bit to be clear or timeout */ | |
| 821 | + end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); | |
| 822 | + while (end_tick > get_ticks()) { | |
| 823 | + ifc_ctrl->status = | |
| 824 | + ifc_in32(&ifc->ifc_nand.nand_evter_stat); | |
| 825 | + | |
| 826 | + if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN)) | |
| 827 | + return 0; | |
| 828 | + } | |
| 829 | + printf("fsl-ifc: Failed to Initialise SRAM\n"); | |
| 830 | + return 1; | |
| 831 | + } | |
| 832 | + | |
| 815 | 833 | cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT; |
| 816 | 834 | |
| 817 | 835 | /* Save CSOR and CSOR_ext */ |
| 818 | 836 | |
| ... | ... | @@ -854,11 +872,18 @@ |
| 854 | 872 | break; |
| 855 | 873 | } |
| 856 | 874 | |
| 875 | + if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) { | |
| 876 | + printf("fsl-ifc: Failed to Initialise SRAM\n"); | |
| 877 | + return 1; | |
| 878 | + } | |
| 879 | + | |
| 857 | 880 | ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); |
| 858 | 881 | |
| 859 | 882 | /* Restore CSOR and CSOR_ext */ |
| 860 | 883 | ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); |
| 861 | 884 | ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); |
| 885 | + | |
| 886 | + return 0; | |
| 862 | 887 | } |
| 863 | 888 | |
| 864 | 889 | static int fsl_ifc_chip_init(int devnum, u8 *addr) |
| ... | ... | @@ -868,7 +893,7 @@ |
| 868 | 893 | struct fsl_ifc_mtd *priv; |
| 869 | 894 | struct nand_ecclayout *layout; |
| 870 | 895 | uint32_t cspr = 0, csor = 0, ver = 0; |
| 871 | - int ret; | |
| 896 | + int ret = 0; | |
| 872 | 897 | |
| 873 | 898 | if (!ifc_ctrl) { |
| 874 | 899 | fsl_ifc_ctrl_init(); |
| ... | ... | @@ -1010,8 +1035,10 @@ |
| 1010 | 1035 | } |
| 1011 | 1036 | |
| 1012 | 1037 | ver = ifc_in32(&ifc_ctrl->regs->ifc_rev); |
| 1013 | - if (ver == FSL_IFC_V1_1_0) | |
| 1014 | - fsl_ifc_sram_init(); | |
| 1038 | + if (ver >= FSL_IFC_V1_1_0) | |
| 1039 | + ret = fsl_ifc_sram_init(ver); | |
| 1040 | + if (ret) | |
| 1041 | + return ret; | |
| 1015 | 1042 | |
| 1016 | 1043 | ret = nand_scan_ident(mtd, 1, NULL); |
| 1017 | 1044 | if (ret) |
include/fsl_ifc.h
| ... | ... | @@ -367,6 +367,8 @@ |
| 367 | 367 | */ |
| 368 | 368 | /* Auto Boot Mode */ |
| 369 | 369 | #define IFC_NAND_NCFGR_BOOT 0x80000000 |
| 370 | +/* SRAM INIT EN */ | |
| 371 | +#define IFC_NAND_SRAM_INIT_EN 0x20000000 | |
| 370 | 372 | /* Addressing Mode-ROW0+n/COL0 */ |
| 371 | 373 | #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 |
| 372 | 374 | /* Addressing Mode-ROW0+n/COL0+n */ |