Add support for a Freescale non-CPM SPI controller

This patch adds support for the SPI controller found on Freescale PowerPC processors such as the MCP834x family. Additionally, a new config option, CONFIG_HARD_SPI, is added for general purpose SPI controller use. Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

Add support for a Freescale non-CPM SPI controller
This patch adds support for the SPI controller found on Freescale PowerPC processors such as the MCP834x family. Additionally, a new config option, CONFIG_HARD_SPI, is added for general purpose SPI controller use. Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Ben Warren · Kim Phillips
1 parent a8cb43a89b
Showing 7 changed files with 264 additions and 4 deletions Side-by-side Diff
Makefile
README
drivers/spi/Makefile
drivers/spi/mpc8xxx_spi.c
include/asm-ppc/immap_83xx.h
include/asm-ppc/mpc8xxx_spi.h
lib_ppc/board.c
@@ -230,6 +230,7 @@
 LIBS += drivers/net/sk98lin/libsk98lin.a
 LIBS += drivers/pci/libpci.a
 LIBS += drivers/pcmcia/libpcmcia.a
+LIBS += drivers/spi/libspi.a
 ifeq ($(CPU),mpc83xx)
 LIBS += drivers/qe/qe.a
 endif
@@ -377,6 +378,7 @@
 TAG_SUBDIRS += drivers/qe
 TAG_SUBDIRS += drivers/rtc
 TAG_SUBDIRS += drivers/serial
+TAG_SUBDIRS += drivers/spi
 TAG_SUBDIRS += drivers/usb
 TAG_SUBDIRS += drivers/video
  
@@ -1377,6 +1377,14 @@
 		SPI configuration items (port pins to use, etc). For
 		an example, see include/configs/sacsng.h.
  
+		CONFIG_HARD_SPI
+
+		Enables a hardware SPI driver for general-purpose reads
+		and writes.  As with CONFIG_SOFT_SPI, the board configuration
+		must define a list of chip-select function pointers.
+		Currently supported on some MPC8xxx processors.  For an
+		example, see include/configs/mpc8349emds.h.
+
 - FPGA Support: CONFIG_FPGA
  
 		Enables FPGA subsystem.
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB 	:= $(obj)libspi.a
+
+COBJS-y += mpc8xxx_spi.o
+
+COBJS	:= $(COBJS-y)
+SRCS 	:= $(COBJS:.o=.c)
+OBJS 	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+/*
+ * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
+ * With help from the common/soft_spi and cpu/mpc8260 drivers
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/mpc8xxx_spi.h>
+
+#ifdef CONFIG_HARD_SPI
+
+#define SPI_EV_NE	0x80000000 >> 22	/* Receiver Not Empty */
+#define SPI_EV_NF	0x80000000 >> 23	/* Transmitter Not Full */
+
+#define SPI_MODE_LOOP	0x80000000 >> 1	/* Loopback mode */
+#define SPI_MODE_REV	0x80000000 >> 5	/* Reverse mode - MSB first */
+#define SPI_MODE_MS	0x80000000 >> 6	/* Always master */
+#define SPI_MODE_EN	0x80000000 >> 7	/* Enable interface */
+
+#define SPI_PRESCALER(reg, div) (reg)=((reg) & 0xfff0ffff) | ((div)<<16)
+#define SPI_CHARLENGTH(reg, div) (reg)=((reg) & 0xff0fffff) | ((div)<<20)
+
+#define SPI_TIMEOUT	1000
+
+void spi_init(void)
+{
+	volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi;
+
+	/* ------------------------------------------------
+	 * SPI pins on the MPC83xx are not muxed, so all we do is initialize
+	 * some registers
+	 * ------------------------------------------------ */
+	spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
+	SPI_PRESCALER(spi->mode, 1);	/* Use SYSCLK / 8  (16.67MHz typ.) */
+	spi->event = 0xffffffff;	/* Clear all SPI events */
+	spi->mask = 0x00000000;	/* Mask  all SPI interrupts */
+	spi->com = 0;		/* LST bit doesn't do anything, so disregard */
+}
+
+int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar * dout, uchar * din)
+{
+	volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi;
+	unsigned int tmpdout, tmpdin, event;
+	int numBlks = bitlen / 32 + (bitlen % 32 ? 1 : 0);
+	int tm, isRead = 0;
+	unsigned char charSize = 32;
+
+	debug("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n",
+	      (int)chipsel, *(uint *) dout, *(uint *) din, bitlen);
+
+	if (chipsel != NULL)
+		(*chipsel) (1);	/* select the target chip */
+
+	spi->event = 0xffffffff;	/* Clear all SPI events */
+
+	/* handle data in 32-bit chunks */
+	while (numBlks--) {
+		tmpdout = 0;
+		charSize = (bitlen >= 32 ? 32 : bitlen);
+
+		/* Shift data so it's msb-justified */
+		tmpdout = *(u32 *) dout >> (32 - charSize);
+
+		/* The LEN field of the SPMODE register is set as follows:
+		 *
+		 * Bit length           setting
+		 * l <= 4               3
+		 * 4 < l <= 16          l - 1
+		 * l > 16               0
+		 */
+
+		if (bitlen <= 16)
+			SPI_CHARLENGTH(spi->mode, bitlen <= 4 ? 3 : bitlen - 1);
+		else {
+			SPI_CHARLENGTH(spi->mode, 0);
+			/* Set up the next iteration if sending > 32 bits */
+			bitlen -= 32;
+			dout += 4;
+		}
+
+		spi->tx = tmpdout;	/* Write the data out */
+		debug("*** spi_xfer: ... %08x written\n", tmpdout);
+
+		/* --------------------------------
+		 * Wait for SPI transmit to get out
+		 * or time out (1 second = 1000 ms)
+		 * The NE event must be read and cleared first
+		 * -------------------------------- */
+		for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
+			event = spi->event;
+			if (event & SPI_EV_NE) {
+				tmpdin = spi->rx;
+				spi->event |= SPI_EV_NE;
+				isRead = 1;
+
+				*(u32 *) din = (tmpdin << (32 - charSize));
+				if (charSize == 32) {
+					/* Advance output buffer by 32 bits */
+					din += 4;
+				}
+			}
+			/* Only bail when we've had both NE and NF events.
+			 * This will cause timeouts on RO devices, so maybe
+			 * in the future put an arbitrary delay after writing
+			 * the device.  Arbitrary delays suck, though... */
+			if (isRead && (event & SPI_EV_NF))
+				break;
+		}
+		if (tm >= SPI_TIMEOUT)
+			puts("*** spi_xfer: Time out during SPI transfer");
+
+		debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
+	}
+
+	if (chipsel != NULL)
+		(*chipsel) (0);	/* deselect the target chip */
+	return 0;
+}
+
+#endif				/* CONFIG_HARD_SPI */
@@ -30,6 +30,7 @@
  
 #include <asm/types.h>
 #include <asm/fsl_i2c.h>
+#include <asm/mpc8xxx_spi.h>
  
 /*
  * Local Access Window
@@ -627,7 +628,7 @@
 	u8			res3[0x900];
 	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
 	u8			res4[0x1000];
-	spi83xx_t		spi;		/* Serial Peripheral Interface */
+	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[2];	/* PCI Software Configuration Registers */
 	ios83xx_t		ios;		/* Sequencer */
@@ -661,7 +662,7 @@
 	u8			res2[0x900];
 	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
 	u8			res3[0x1000];
-	spi83xx_t		spi;		/* Serial Peripheral Interface */
+	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
 	u8			res4[0x80];
@@ -696,7 +697,7 @@
 	u8			res2[0x900];
 	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
 	u8			res3[0x1000];
-	spi83xx_t		spi;		/* Serial Peripheral Interface */
+	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
 	u8			res4[0x80];
@@ -741,7 +742,7 @@
 	u8			res2[0x900];
 	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
 	u8			res3[0x1000];
-	spi83xx_t		spi;		/* Serial Peripheral Interface */
+	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
 	u8			res4[0x80];
+/*
+ * Freescale non-CPM SPI Controller
+ *
+ * Copyright 2008 Qstreams Networks, Inc.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_MPC8XXX_SPI_H_
+#define _ASM_MPC8XXX_SPI_H_
+
+#include <asm/types.h>
+
+#if defined(CONFIG_MPC834X) || \
+	defined(CONFIG_MPC8313) || \
+	defined(CONFIG_MPC8315) || \
+	defined(CONFIG_MPC837X)
+
+typedef struct spi8xxx
+{
+	u8 res0[0x20];	/* 0x0-0x01f reserved */
+	u32 mode;	/* mode register  */
+	u32 event;	/* event register */
+	u32 mask;	/* mask register  */
+	u32 com;	/* command register */
+	u32 tx;		/* transmit register */
+	u32 rx;		/* receive register */
+	u8 res1[0xC8];	/* fill up to 0x100 */
+} spi8xxx_t;
+
+#endif
+
+#endif	/* _ASM_MPC8XXX_SPI_H_ */
@@ -87,6 +87,9 @@
     defined(CONFIG_SOFT_I2C)
 #include <i2c.h>
 #endif
+#if defined(CONFIG_HARD_SPI)
+#include <spi.h>
+#endif
 #if defined(CONFIG_CMD_NAND)
 void nand_init (void);
 #endif
@@ -247,6 +250,16 @@
 }
 #endif
  
+#if defined(CONFIG_HARD_SPI)
+static int init_func_spi (void)
+{
+	puts ("SPI:   ");
+	spi_init ();
+	puts ("ready\n");
+	return (0);
+}
+#endif
+
 /***********************************************************************/
  
 #if defined(CONFIG_WATCHDOG)
@@ -328,6 +341,9 @@
 	INIT_FUNC_WATCHDOG_RESET
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
 	init_func_i2c,
+#endif
+#if defined(CONFIG_HARD_SPI)
+	init_func_spi,
 #endif
 #if defined(CONFIG_DTT)		/* Digital Thermometers and Thermostats */
 	dtt_init,
...	...	@@ -230,6 +230,7 @@
230	230	LIBS += drivers/net/sk98lin/libsk98lin.a
231	231	LIBS += drivers/pci/libpci.a
232	232	LIBS += drivers/pcmcia/libpcmcia.a
	233	+LIBS += drivers/spi/libspi.a
233	234	ifeq ($(CPU),mpc83xx)
234	235	LIBS += drivers/qe/qe.a
235	236	endif
...	...	@@ -377,6 +378,7 @@
377	378	TAG_SUBDIRS += drivers/qe
378	379	TAG_SUBDIRS += drivers/rtc
379	380	TAG_SUBDIRS += drivers/serial
	381	+TAG_SUBDIRS += drivers/spi
380	382	TAG_SUBDIRS += drivers/usb
381	383	TAG_SUBDIRS += drivers/video
382	384
...	...	@@ -1377,6 +1377,14 @@
1377	1377	SPI configuration items (port pins to use, etc). For
1378	1378	an example, see include/configs/sacsng.h.
1379	1379
	1380	+ CONFIG_HARD_SPI
	1381	+
	1382	+ Enables a hardware SPI driver for general-purpose reads
	1383	+ and writes. As with CONFIG_SOFT_SPI, the board configuration
	1384	+ must define a list of chip-select function pointers.
	1385	+ Currently supported on some MPC8xxx processors. For an
	1386	+ example, see include/configs/mpc8349emds.h.
	1387	+
1380	1388	- FPGA Support: CONFIG_FPGA
1381	1389
1382	1390	Enables FPGA subsystem.
	1	+#
	2	+# (C) Copyright 2000-2007
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+
	26	+LIB := $(obj)libspi.a
	27	+
	28	+COBJS-y += mpc8xxx_spi.o
	29	+
	30	+COBJS := $(COBJS-y)
	31	+SRCS := $(COBJS:.o=.c)
	32	+OBJS := $(addprefix $(obj),$(COBJS))
	33	+
	34	+all: $(LIB)
	35	+
	36	+$(LIB): $(obj).depend $(OBJS)
	37	+ $(AR) $(ARFLAGS) $@ $(OBJS)
	38	+
	39	+#########################################################################
	40	+
	41	+# defines $(obj).depend target
	42	+include $(SRCTREE)/rules.mk
	43	+
	44	+sinclude $(obj).depend
	45	+
	46	+#########################################################################
	1	+/*
	2	+ * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
	3	+ * With help from the common/soft_spi and cpu/mpc8260 drivers
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+#include <spi.h>
	26	+#include <asm/mpc8xxx_spi.h>
	27	+
	28	+#ifdef CONFIG_HARD_SPI
	29	+
	30	+#define SPI_EV_NE 0x80000000 >> 22 /* Receiver Not Empty */
	31	+#define SPI_EV_NF 0x80000000 >> 23 /* Transmitter Not Full */
	32	+
	33	+#define SPI_MODE_LOOP 0x80000000 >> 1 /* Loopback mode */
	34	+#define SPI_MODE_REV 0x80000000 >> 5 /* Reverse mode - MSB first */
	35	+#define SPI_MODE_MS 0x80000000 >> 6 /* Always master */
	36	+#define SPI_MODE_EN 0x80000000 >> 7 /* Enable interface */
	37	+
	38	+#define SPI_PRESCALER(reg, div) (reg)=((reg) & 0xfff0ffff) \| ((div)<<16)
	39	+#define SPI_CHARLENGTH(reg, div) (reg)=((reg) & 0xff0fffff) \| ((div)<<20)
	40	+
	41	+#define SPI_TIMEOUT 1000
	42	+
	43	+void spi_init(void)
	44	+{
	45	+ volatile spi8xxx_t spi = &((immap_t ) (CFG_IMMR))->spi;
	46	+
	47	+ /* ------------------------------------------------
	48	+ * SPI pins on the MPC83xx are not muxed, so all we do is initialize
	49	+ * some registers
	50	+ * ------------------------------------------------ */
	51	+ spi->mode = SPI_MODE_REV \| SPI_MODE_MS \| SPI_MODE_EN;
	52	+ SPI_PRESCALER(spi->mode, 1); /* Use SYSCLK / 8 (16.67MHz typ.) */
	53	+ spi->event = 0xffffffff; /* Clear all SPI events */
	54	+ spi->mask = 0x00000000; /* Mask all SPI interrupts */
	55	+ spi->com = 0; /* LST bit doesn't do anything, so disregard */
	56	+}
	57	+
	58	+int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar * dout, uchar * din)
	59	+{
	60	+ volatile spi8xxx_t spi = &((immap_t ) (CFG_IMMR))->spi;
	61	+ unsigned int tmpdout, tmpdin, event;
	62	+ int numBlks = bitlen / 32 + (bitlen % 32 ? 1 : 0);
	63	+ int tm, isRead = 0;
	64	+ unsigned char charSize = 32;
	65	+
	66	+ debug("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n",
	67	+ (int)chipsel, (uint ) dout, (uint ) din, bitlen);
	68	+
	69	+ if (chipsel != NULL)
	70	+ (chipsel) (1); / select the target chip */
	71	+
	72	+ spi->event = 0xffffffff; /* Clear all SPI events */
	73	+
	74	+ /* handle data in 32-bit chunks */
	75	+ while (numBlks--) {
	76	+ tmpdout = 0;
	77	+ charSize = (bitlen >= 32 ? 32 : bitlen);
	78	+
	79	+ /* Shift data so it's msb-justified */
	80	+ tmpdout = (u32 ) dout >> (32 - charSize);
	81	+
	82	+ /* The LEN field of the SPMODE register is set as follows:
	83	+ *
	84	+ * Bit length setting
	85	+ * l <= 4 3
	86	+ * 4 < l <= 16 l - 1
	87	+ * l > 16 0
	88	+ */
	89	+
	90	+ if (bitlen <= 16)
	91	+ SPI_CHARLENGTH(spi->mode, bitlen <= 4 ? 3 : bitlen - 1);
	92	+ else {
	93	+ SPI_CHARLENGTH(spi->mode, 0);
	94	+ /* Set up the next iteration if sending > 32 bits */
	95	+ bitlen -= 32;
	96	+ dout += 4;
	97	+ }
	98	+
	99	+ spi->tx = tmpdout; /* Write the data out */
	100	+ debug("*** spi_xfer: ... %08x written\n", tmpdout);
	101	+
	102	+ /* --------------------------------
	103	+ * Wait for SPI transmit to get out
	104	+ * or time out (1 second = 1000 ms)
	105	+ * The NE event must be read and cleared first
	106	+ * -------------------------------- */
	107	+ for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
	108	+ event = spi->event;
	109	+ if (event & SPI_EV_NE) {
	110	+ tmpdin = spi->rx;
	111	+ spi->event \|= SPI_EV_NE;
	112	+ isRead = 1;
	113	+
	114	+ (u32 ) din = (tmpdin << (32 - charSize));
	115	+ if (charSize == 32) {
	116	+ /* Advance output buffer by 32 bits */
	117	+ din += 4;
	118	+ }
	119	+ }
	120	+ /* Only bail when we've had both NE and NF events.
	121	+ * This will cause timeouts on RO devices, so maybe
	122	+ * in the future put an arbitrary delay after writing
	123	+ * the device. Arbitrary delays suck, though... */
	124	+ if (isRead && (event & SPI_EV_NF))
	125	+ break;
	126	+ }
	127	+ if (tm >= SPI_TIMEOUT)
	128	+ puts("*** spi_xfer: Time out during SPI transfer");
	129	+
	130	+ debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
	131	+ }
	132	+
	133	+ if (chipsel != NULL)
	134	+ (chipsel) (0); / deselect the target chip */
	135	+ return 0;
	136	+}
	137	+
	138	+#endif /* CONFIG_HARD_SPI */
...	...	@@ -30,6 +30,7 @@
30	30
31	31	#include <asm/types.h>
32	32	#include <asm/fsl_i2c.h>
	33	+#include <asm/mpc8xxx_spi.h>
33	34
34	35	/*
35	36	* Local Access Window
...	...	@@ -627,7 +628,7 @@
627	628	u8 res3[0x900];
628	629	lbus83xx_t lbus; /* Local Bus Controller Registers */
629	630	u8 res4[0x1000];
630		- spi83xx_t spi; /* Serial Peripheral Interface */
	631	+ spi8xxx_t spi; /* Serial Peripheral Interface */
631	632	dma83xx_t dma; /* DMA */
632	633	pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
633	634	ios83xx_t ios; /* Sequencer */
...	...	@@ -661,7 +662,7 @@
661	662	u8 res2[0x900];
662	663	lbus83xx_t lbus; /* Local Bus Controller Registers */
663	664	u8 res3[0x1000];
664		- spi83xx_t spi; /* Serial Peripheral Interface */
	665	+ spi8xxx_t spi; /* Serial Peripheral Interface */
665	666	dma83xx_t dma; /* DMA */
666	667	pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
667	668	u8 res4[0x80];
...	...	@@ -696,7 +697,7 @@
696	697	u8 res2[0x900];
697	698	lbus83xx_t lbus; /* Local Bus Controller Registers */
698	699	u8 res3[0x1000];
699		- spi83xx_t spi; /* Serial Peripheral Interface */
	700	+ spi8xxx_t spi; /* Serial Peripheral Interface */
700	701	dma83xx_t dma; /* DMA */
701	702	pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
702	703	u8 res4[0x80];
...	...	@@ -741,7 +742,7 @@
741	742	u8 res2[0x900];
742	743	lbus83xx_t lbus; /* Local Bus Controller Registers */
743	744	u8 res3[0x1000];
744		- spi83xx_t spi; /* Serial Peripheral Interface */
	745	+ spi8xxx_t spi; /* Serial Peripheral Interface */
745	746	dma83xx_t dma; /* DMA */
746	747	pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
747	748	u8 res4[0x80];
	1	+/*
	2	+ * Freescale non-CPM SPI Controller
	3	+ *
	4	+ * Copyright 2008 Qstreams Networks, Inc.
	5	+ *
	6	+ * This software may be used and distributed according to the
	7	+ * terms of the GNU Public License, Version 2, incorporated
	8	+ * herein by reference.
	9	+ *
	10	+ * This program is free software; you can redistribute it and/or
	11	+ * modify it under the terms of the GNU General Public License
	12	+ * Version 2 as published by the Free Software Foundation.
	13	+ *
	14	+ * This program is distributed in the hope that it will be useful,
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ *
	19	+ * You should have received a copy of the GNU General Public License
	20	+ * along with this program; if not, write to the Free Software
	21	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	+ * MA 02111-1307 USA
	23	+ */
	24	+
	25	+#ifndef _ASM_MPC8XXX_SPI_H_
	26	+#define _ASM_MPC8XXX_SPI_H_
	27	+
	28	+#include <asm/types.h>
	29	+
	30	+#if defined(CONFIG_MPC834X) \|\| \
	31	+ defined(CONFIG_MPC8313) \|\| \
	32	+ defined(CONFIG_MPC8315) \|\| \
	33	+ defined(CONFIG_MPC837X)
	34	+
	35	+typedef struct spi8xxx
	36	+{
	37	+ u8 res0[0x20]; /* 0x0-0x01f reserved */
	38	+ u32 mode; /* mode register */
	39	+ u32 event; /* event register */
	40	+ u32 mask; /* mask register */
	41	+ u32 com; /* command register */
	42	+ u32 tx; /* transmit register */
	43	+ u32 rx; /* receive register */
	44	+ u8 res1[0xC8]; /* fill up to 0x100 */
	45	+} spi8xxx_t;
	46	+
	47	+#endif
	48	+
	49	+#endif /* _ASM_MPC8XXX_SPI_H_ */
...	...	@@ -87,6 +87,9 @@
87	87	defined(CONFIG_SOFT_I2C)
88	88	#include <i2c.h>
89	89	#endif
	90	+#if defined(CONFIG_HARD_SPI)
	91	+#include <spi.h>
	92	+#endif
90	93	#if defined(CONFIG_CMD_NAND)
91	94	void nand_init (void);
92	95	#endif
...	...	@@ -247,6 +250,16 @@
247	250	}
248	251	#endif
249	252
	253	+#if defined(CONFIG_HARD_SPI)
	254	+static int init_func_spi (void)
	255	+{
	256	+ puts ("SPI: ");
	257	+ spi_init ();
	258	+ puts ("ready\n");
	259	+ return (0);
	260	+}
	261	+#endif
	262	+
250	263	/***********************************************************************/
251	264
252	265	#if defined(CONFIG_WATCHDOG)
...	...	@@ -328,6 +341,9 @@
328	341	INIT_FUNC_WATCHDOG_RESET
329	342	#if defined(CONFIG_HARD_I2C) \|\| defined(CONFIG_SOFT_I2C)
330	343	init_func_i2c,
	344	+#endif
	345	+#if defined(CONFIG_HARD_SPI)
	346	+ init_func_spi,
331	347	#endif
332	348	#if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */
333	349	dtt_init,