Merge branch 'topic/arm/socfpga-20141006' of git://git.denx.de/u-boot-socfpga

Fix a trivial conflict in dw_mmc.c after talking with Marek. Conflicts: drivers/mmc/dw_mmc.c Signed-off-by: Tom Rini <trini@ti.com>

Merge branch 'topic/arm/socfpga-20141006' of git://git.denx.de/u-boot-socfpga
Fix a trivial conflict in dw_mmc.c after talking with Marek. Conflicts: drivers/mmc/dw_mmc.c Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini
2 parents 9169305599 2f210639c4
Showing 37 changed files Side-by-side Diff
arch/arm/cpu/armv7/socfpga/Makefile
arch/arm/cpu/armv7/socfpga/clock_manager.c
arch/arm/cpu/armv7/socfpga/fpga_manager.c
arch/arm/cpu/armv7/socfpga/misc.c
arch/arm/cpu/armv7/socfpga/reset_manager.c
arch/arm/cpu/armv7/socfpga/spl.c
arch/arm/cpu/armv7/socfpga/system_manager.c
arch/arm/cpu/armv7/socfpga/timer.c
arch/arm/include/asm/arch-socfpga/clock_manager.h
arch/arm/include/asm/arch-socfpga/fpga_manager.h
arch/arm/include/asm/arch-socfpga/nic301.h
arch/arm/include/asm/arch-socfpga/reset_manager.h
arch/arm/include/asm/arch-socfpga/scu.h
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
arch/arm/include/asm/arch-socfpga/system_manager.h
arch/arm/include/asm/system.h
arch/arm/lib/cache-cp15.c
board/altera/socfpga/pll_config.h
board/altera/socfpga/socfpga_cyclone5.c
common/image.c
@@ -8,6 +8,7 @@
 #
  
 obj-y	:= lowlevel_init.o
-obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o
+obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
+	   fpga_manager.o
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
@@ -8,38 +8,28 @@
 #include <asm/io.h>
 #include <asm/arch/clock_manager.h>
  
+DECLARE_GLOBAL_DATA_PTR;
+
 static const struct socfpga_clock_manager *clock_manager_base =
-		(void *)SOCFPGA_CLKMGR_ADDRESS;
+	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
  
-#define CLKMGR_BYPASS_ENABLE	1
-#define CLKMGR_BYPASS_DISABLE	0
-#define CLKMGR_STAT_IDLE	0
-#define CLKMGR_STAT_BUSY	1
-#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1		0
-#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX	1
-#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1		0
-#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX	1
-
-#define CLEAR_BGP_EN_PWRDN \
-	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
-	CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
-	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-
-#define VCO_EN_BASE \
-	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
-	CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
-	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-
-static inline void cm_wait_for_lock(uint32_t mask)
+static void cm_wait_for_lock(uint32_t mask)
 {
 	register uint32_t inter_val;
+	uint32_t retry = 0;
 	do {
 		inter_val = readl(&clock_manager_base->inter) & mask;
-	} while (inter_val != mask);
+		if (inter_val == mask)
+			retry++;
+		else
+			retry = 0;
+		if (retry >= 10)
+			break;
+	} while (1);
 }
  
 /* function to poll in the fsm busy bit */
-static inline void cm_wait_for_fsm(void)
+static void cm_wait_for_fsm(void)
 {
 	while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
 		;
  
  
@@ -49,22 +39,22 @@
  * function to write the bypass register which requires a poll of the
  * busy bit
  */
-static inline void cm_write_bypass(uint32_t val)
+static void cm_write_bypass(uint32_t val)
 {
 	writel(val, &clock_manager_base->bypass);
 	cm_wait_for_fsm();
 }
  
 /* function to write the ctrl register which requires a poll of the busy bit */
-static inline void cm_write_ctrl(uint32_t val)
+static void cm_write_ctrl(uint32_t val)
 {
 	writel(val, &clock_manager_base->ctrl);
 	cm_wait_for_fsm();
 }
  
 /* function to write a clock register that has phase information */
-static inline void cm_write_with_phase(uint32_t value,
-	uint32_t reg_address, uint32_t mask)
+static void cm_write_with_phase(uint32_t value,
+				uint32_t reg_address, uint32_t mask)
 {
 	/* poll until phase is zero */
 	while (readl(reg_address) & mask)
  
  
  
@@ -128,24 +118,18 @@
 	writel(0, &clock_manager_base->per_pll.en);
  
 	/* Put all plls in bypass */
-	cm_write_bypass(
-		CLKMGR_BYPASS_PERPLLSRC_SET(
-		CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
-		CLKMGR_BYPASS_SDRPLLSRC_SET(
-		CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
-		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
-		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
-		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
+	cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
+			CLKMGR_BYPASS_MAINPLL);
  
-	/*
-	 * Put all plls VCO registers back to reset value.
-	 * Some code might have messed with them.
-	 */
-	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
+	/* Put all plls VCO registers back to reset value. */
+	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
 	       &clock_manager_base->main_pll.vco);
-	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
+	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
 	       &clock_manager_base->per_pll.vco);
-	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
+	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
 	       &clock_manager_base->sdr_pll.vco);
  
 	/*
  
@@ -170,20 +154,10 @@
 	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
 	 * with numerator and denominator.
 	 */
-	writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
-		CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
-		&clock_manager_base->main_pll.vco);
+	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
+	writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
+	writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
  
-	writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
-		CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
-		&clock_manager_base->per_pll.vco);
-
-	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
-		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
-		cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
-		CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
-		&clock_manager_base->sdr_pll.vco);
-
 	/*
 	 * Time starts here
 	 * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
@@ -217,6 +191,9 @@
 	writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
  
 	/* Peri pernandsdmmcclk */
+	writel(cfg->mainnandsdmmcclk,
+	       &clock_manager_base->main_pll.mainnandsdmmcclk);
+
 	writel(cfg->pernandsdmmcclk,
 	       &clock_manager_base->per_pll.pernandsdmmcclk);
  
  
  
@@ -232,18 +209,16 @@
  
 	/* Enable vco */
 	/* main pll vco */
-	writel(cfg->main_vco_base | VCO_EN_BASE,
+	writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
 	       &clock_manager_base->main_pll.vco);
  
 	/* periferal pll */
-	writel(cfg->peri_vco_base | VCO_EN_BASE,
+	writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
 	       &clock_manager_base->per_pll.vco);
  
 	/* sdram pll vco */
-	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
-		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
-		cfg->sdram_vco_base | VCO_EN_BASE,
-		&clock_manager_base->sdr_pll.vco);
+	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+	       &clock_manager_base->sdr_pll.vco);
  
 	/* L3 MP and L3 SP */
 	writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
@@ -294,8 +269,8 @@
 	       &clock_manager_base->per_pll.vco);
  
 	/* assert sdram outresetall */
-	writel(cfg->sdram_vco_base | VCO_EN_BASE|
-		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
+	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
 		&clock_manager_base->sdr_pll.vco);
  
 	/* deassert main outresetall */
@@ -307,9 +282,8 @@
 	       &clock_manager_base->per_pll.vco);
  
 	/* deassert sdram outresetall */
-	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
-		cfg->sdram_vco_base | VCO_EN_BASE,
-		&clock_manager_base->sdr_pll.vco);
+	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+	       &clock_manager_base->sdr_pll.vco);
  
 	/*
 	 * now that we've toggled outreset all, all the clocks
  
@@ -333,18 +307,10 @@
 			    CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
  
 	/* Take all three PLLs out of bypass when safe mode is cleared. */
-	cm_write_bypass(
-		CLKMGR_BYPASS_PERPLLSRC_SET(
-			CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
-		CLKMGR_BYPASS_SDRPLLSRC_SET(
-			CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
-		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
-		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
-		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
+	cm_write_bypass(0);
  
 	/* clear safe mode */
-	cm_write_ctrl(readl(&clock_manager_base->ctrl) |
-			CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
+	cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
  
 	/*
 	 * now that safe mode is clear with clocks gated
  
@@ -357,5 +323,225 @@
 	writel(~0, &clock_manager_base->main_pll.en);
 	writel(~0, &clock_manager_base->per_pll.en);
 	writel(~0, &clock_manager_base->sdr_pll.en);
+
+	/* Clear the loss of lock bits (write 1 to clear) */
+	writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
+	       CLKMGR_INTER_MAINPLLLOST_MASK,
+	       &clock_manager_base->inter);
 }
+
+static unsigned int cm_get_main_vco_clk_hz(void)
+{
+	uint32_t reg, clock;
+
+	/* get the main VCO clock */
+	reg = readl(&clock_manager_base->main_pll.vco);
+	clock = CONFIG_HPS_CLK_OSC1_HZ;
+	clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
+		  CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
+	clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
+		  CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+	return clock;
+}
+
+static unsigned int cm_get_per_vco_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify PER PLL clock source */
+	reg = readl(&clock_manager_base->per_pll.vco);
+	reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
+	      CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
+	if (reg == CLKMGR_VCO_SSRC_EOSC1)
+		clock = CONFIG_HPS_CLK_OSC1_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+		clock = CONFIG_HPS_CLK_OSC2_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_F2S)
+		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+
+	/* get the PER VCO clock */
+	reg = readl(&clock_manager_base->per_pll.vco);
+	clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
+		  CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
+	clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
+		  CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+	return clock;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+	uint32_t reg, clock;
+
+	clock = cm_get_main_vco_clk_hz();
+
+	/* get the MPU clock */
+	reg = readl(&clock_manager_base->altera.mpuclk);
+	clock /= (reg + 1);
+	reg = readl(&clock_manager_base->main_pll.mpuclk);
+	clock /= (reg + 1);
+	return clock;
+}
+
+unsigned long cm_get_sdram_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify SDRAM PLL clock source */
+	reg = readl(&clock_manager_base->sdr_pll.vco);
+	reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
+	      CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
+	if (reg == CLKMGR_VCO_SSRC_EOSC1)
+		clock = CONFIG_HPS_CLK_OSC1_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+		clock = CONFIG_HPS_CLK_OSC2_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_F2S)
+		clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+
+	/* get the SDRAM VCO clock */
+	reg = readl(&clock_manager_base->sdr_pll.vco);
+	clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
+		  CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
+	clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
+		  CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+	/* get the SDRAM (DDR_DQS) clock */
+	reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
+	reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
+	      CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
+	clock /= (reg + 1);
+
+	return clock;
+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify the source of L4 SP clock */
+	reg = readl(&clock_manager_base->main_pll.l4src);
+	reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
+	      CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
+
+	if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
+		clock = cm_get_main_vco_clk_hz();
+
+		/* get the clock prior L4 SP divider (main clk) */
+		reg = readl(&clock_manager_base->altera.mainclk);
+		clock /= (reg + 1);
+		reg = readl(&clock_manager_base->main_pll.mainclk);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
+		clock = cm_get_per_vco_clk_hz();
+
+		/* get the clock prior L4 SP divider (periph_base_clk) */
+		reg = readl(&clock_manager_base->per_pll.perbaseclk);
+		clock /= (reg + 1);
+	}
+
+	/* get the L4 SP clock which supplied to UART */
+	reg = readl(&clock_manager_base->main_pll.maindiv);
+	reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
+	      CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
+	clock = clock / (1 << reg);
+
+	return clock;
+}
+
+unsigned int cm_get_mmc_controller_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify the source of MMC clock */
+	reg = readl(&clock_manager_base->per_pll.src);
+	reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
+	      CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
+
+	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
+		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
+		clock = cm_get_main_vco_clk_hz();
+
+		/* get the SDMMC clock */
+		reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
+		clock = cm_get_per_vco_clk_hz();
+
+		/* get the SDMMC clock */
+		reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
+		clock /= (reg + 1);
+	}
+
+	/* further divide by 4 as we have fixed divider at wrapper */
+	clock /= 4;
+	return clock;
+}
+
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify the source of QSPI clock */
+	reg = readl(&clock_manager_base->per_pll.src);
+	reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
+	      CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
+
+	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
+		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
+		clock = cm_get_main_vco_clk_hz();
+
+		/* get the qspi clock */
+		reg = readl(&clock_manager_base->main_pll.mainqspiclk);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
+		clock = cm_get_per_vco_clk_hz();
+
+		/* get the qspi clock */
+		reg = readl(&clock_manager_base->per_pll.perqspiclk);
+		clock /= (reg + 1);
+	}
+
+	return clock;
+}
+
+static void cm_print_clock_quick_summary(void)
+{
+	printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
+	printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
+	printf("EOSC1       %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
+	printf("EOSC2       %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
+	printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
+	printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
+	printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
+	printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
+	printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+}
+
+int set_cpu_clk_info(void)
+{
+	/* Calculate the clock frequencies required for drivers */
+	cm_get_l4_sp_clk_hz();
+	cm_get_mmc_controller_clk_hz();
+
+	gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
+	gd->bd->bi_dsp_freq = 0;
+	gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
+
+	return 0;
+}
+
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	cm_print_clock_quick_summary();
+	return 0;
+}
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_showclocks,
+	"display clocks",
+	""
+);
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * This file contains only support functions used also by the SoCFPGA
+ * platform code, the real meat is located in drivers/fpga/socfpga.c .
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timeout count */
+#define FPGA_TIMEOUT_CNT		0x1000000
+
+static struct socfpga_fpga_manager *fpgamgr_regs =
+	(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+/* Check whether FPGA Init_Done signal is high */
+static int is_fpgamgr_initdone_high(void)
+{
+	unsigned long val;
+
+	val = readl(&fpgamgr_regs->gpio_ext_porta);
+	return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
+}
+
+/* Get the FPGA mode */
+int fpgamgr_get_mode(void)
+{
+	unsigned long val;
+
+	val = readl(&fpgamgr_regs->stat);
+	return val & FPGAMGRREGS_STAT_MODE_MASK;
+}
+
+/* Check whether FPGA is ready to be accessed */
+int fpgamgr_test_fpga_ready(void)
+{
+	/* Check for init done signal */
+	if (!is_fpgamgr_initdone_high())
+		return 0;
+
+	/* Check again to avoid false glitches */
+	if (!is_fpgamgr_initdone_high())
+		return 0;
+
+	if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
+		return 0;
+
+	return 1;
+}
+
+/* Poll until FPGA is ready to be accessed or timeout occurred */
+int fpgamgr_poll_fpga_ready(void)
+{
+	unsigned long i;
+
+	/* If FPGA is blank, wait till WD invoke warm reset */
+	for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+		/* check for init done signal */
+		if (!is_fpgamgr_initdone_high())
+			continue;
+		/* check again to avoid false glitches */
+		if (!is_fpgamgr_initdone_high())
+			continue;
+		return 1;
+	}
+
+	return 0;
+}
@@ -6,24 +6,103 @@
  
 #include <common.h>
 #include <asm/io.h>
+#include <altera.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/nic301.h>
+#include <asm/arch/scu.h>
+#include <asm/pl310.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
+static struct pl310_regs *const pl310 =
+	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+static struct socfpga_reset_manager *reset_manager_base =
+	(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+static struct nic301_registers *nic301_regs =
+	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+static struct scu_registers *scu_regs =
+	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 	return 0;
 }
  
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_DESIGNWARE_ETH
+int cpu_eth_init(bd_t *bis)
+{
+#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
+	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
+#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
+	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
+#else
+#error "Incorrect CONFIG_EMAC_BASE value!"
+#endif
+
+	/* Initialize EMAC. This needs to be done at least once per boot. */
+
+	/*
+	 * Putting the EMAC controller to reset when configuring the PHY
+	 * interface select at System Manager
+	 */
+	socfpga_emac_reset(1);
+
+	/* Clearing emac0 PHY interface select to 0 */
+	clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
+		     SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
+
+	/* configure to PHY interface select choosed */
+	setbits_le32(&sysmgr_regs->emacgrp_ctrl,
+		     SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
+
+	/* Release the EMAC controller from reset */
+	socfpga_emac_reset(0);
+
+	/* initialize and register the emac */
+	return designware_initialize(CONFIG_EMAC_BASE,
+				     CONFIG_PHY_INTERFACE_MODE);
+}
+#endif
+
+#ifdef CONFIG_DWMMC
+/*
+ * Initializes MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+	return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
+				  CONFIG_HPS_SDMMC_BUSWIDTH, 0);
+}
+#endif
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 /*
  * Print CPU information
  */
 int print_cpuinfo(void)
 {
-	puts("CPU   : Altera SOCFPGA Platform\n");
+	puts("CPU:   Altera SoCFPGA Platform\n");
 	return 0;
 }
 #endif
  
  
  
  
  
  
  
  
@@ -36,23 +115,160 @@
 }
 #endif
  
-int misc_init_r(void)
+#ifdef CONFIG_FPGA
+/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Altera_SoCFPGA,
+		/* Interface type */
+		fast_passive_parallel,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+
+/* add device descriptor to FPGA device table */
+static void socfpga_fpga_add(void)
 {
+	int i;
+	fpga_init();
+	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
+		fpga_add(fpga_altera, &altera_fpga[i]);
+}
+#else
+static inline void socfpga_fpga_add(void) {}
+#endif
+
+int arch_cpu_init(void)
+{
+	/*
+	 * If the HW watchdog is NOT enabled, make sure it is not running,
+	 * for example because it was enabled in the preloader. This might
+	 * trigger a watchdog-triggered reboot of Linux kernel later.
+	 */
+#ifndef CONFIG_HW_WATCHDOG
+	socfpga_watchdog_reset();
+#endif
 	return 0;
 }
  
-
 /*
- * DesignWare Ethernet initialization
+ * Convert all NIC-301 AMBA slaves from secure to non-secure
  */
-int cpu_eth_init(bd_t *bis)
+static void socfpga_nic301_slave_ns(void)
 {
-#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
-       /* initialize and register the emac */
-	return designware_initialize(CONFIG_EMAC_BASE,
-				     CONFIG_PHY_INTERFACE_MODE);
+	writel(0x1, &nic301_regs->lwhps2fpgaregs);
+	writel(0x1, &nic301_regs->hps2fpgaregs);
+	writel(0x1, &nic301_regs->acp);
+	writel(0x1, &nic301_regs->rom);
+	writel(0x1, &nic301_regs->ocram);
+	writel(0x1, &nic301_regs->sdrdata);
+}
+
+static uint32_t iswgrp_handoff[8];
+
+int misc_init_r(void)
+{
+	int i;
+	for (i = 0; i < 8; i++)	/* Cache initial SW setting regs */
+		iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
+
+	socfpga_bridges_reset(1);
+	socfpga_nic301_slave_ns();
+
+	/*
+	 * Private components security:
+	 * U-Boot : configure private timer, global timer and cpu component
+	 * access as non secure for kernel stage (as required by Linux)
+	 */
+	setbits_le32(&scu_regs->sacr, 0xfff);
+
+	/* Configure the L2 controller to make SDRAM start at 0 */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+	writel(0x2, &nic301_regs->remap);
 #else
-	return 0;
+	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
+	writel(0x1, &pl310->pl310_addr_filter_start);
 #endif
+
+	/* Add device descriptor to FPGA device table */
+	socfpga_fpga_add();
+	return 0;
 }
+
+static void socfpga_sdram_apply_static_cfg(void)
+{
+	const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
+	const uint32_t applymask = 0x8;
+	uint32_t val = readl(staticcfg) | applymask;
+
+	/*
+	 * SDRAM staticcfg register specific:
+	 * When applying the register setting, the CPU must not access
+	 * SDRAM. Luckily for us, we can abuse i-cache here to help us
+	 * circumvent the SDRAM access issue. The idea is to make sure
+	 * that the code is in one full i-cache line by branching past
+	 * it and back. Once it is in the i-cache, we execute the core
+	 * of the code and apply the register settings.
+	 *
+	 * The code below uses 7 instructions, while the Cortex-A9 has
+	 * 32-byte cachelines, thus the limit is 8 instructions total.
+	 */
+	asm volatile(
+		".align	5			\n"
+		"	b	2f		\n"
+		"1:	str	%0,	[%1]	\n"
+		"	dsb			\n"
+		"	isb			\n"
+		"	b	3f		\n"
+		"2:	b	1b		\n"
+		"3:	nop			\n"
+	: : "r"(val), "r"(staticcfg) : "memory", "cc");
+}
+
+int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 2)
+		return CMD_RET_USAGE;
+
+	argv++;
+
+	switch (*argv[0]) {
+	case 'e':	/* Enable */
+		writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
+		socfpga_sdram_apply_static_cfg();
+		writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
+		writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
+		writel(iswgrp_handoff[1], &nic301_regs->remap);
+		break;
+	case 'd':	/* Disable */
+		writel(0, &sysmgr_regs->fpgaintfgrp_module);
+		writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
+		socfpga_sdram_apply_static_cfg();
+		writel(0, &reset_manager_base->brg_mod_reset);
+		writel(1, &nic301_regs->remap);
+		break;
+	default:
+		return CMD_RET_USAGE;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	bridge, 2, 1, do_bridge,
+	"SoCFPGA HPS FPGA bridge control",
+	"enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	""
+);
@@ -8,12 +8,25 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
+#include <asm/arch/fpga_manager.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
 static const struct socfpga_reset_manager *reset_manager_base =
 		(void *)SOCFPGA_RSTMGR_ADDRESS;
  
+/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
+void socfpga_watchdog_reset(void)
+{
+	/* assert reset for watchdog */
+	setbits_le32(&reset_manager_base->per_mod_reset,
+		     1 << RSTMGR_PERMODRST_L4WD0_LSB);
+
+	/* deassert watchdog from reset (watchdog in not running state) */
+	clrbits_le32(&reset_manager_base->per_mod_reset,
+		     1 << RSTMGR_PERMODRST_L4WD0_LSB);
+}
+
 /*
  * Write the reset manager register to cause reset
  */
@@ -36,5 +49,59 @@
 void reset_deassert_peripherals_handoff(void)
 {
 	writel(0, &reset_manager_base->per_mod_reset);
+}
+
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+void socfpga_bridges_reset(int enable)
+{
+	/* For SoCFPGA-VT, this is NOP. */
+}
+#else
+
+#define L3REGS_REMAP_LWHPS2FPGA_MASK	0x10
+#define L3REGS_REMAP_HPS2FPGA_MASK	0x08
+#define L3REGS_REMAP_OCRAM_MASK		0x01
+
+void socfpga_bridges_reset(int enable)
+{
+	const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
+				L3REGS_REMAP_HPS2FPGA_MASK |
+				L3REGS_REMAP_OCRAM_MASK;
+
+	if (enable) {
+		/* brdmodrst */
+		writel(0xffffffff, &reset_manager_base->brg_mod_reset);
+	} else {
+		/* Check signal from FPGA. */
+		if (fpgamgr_poll_fpga_ready()) {
+			/* FPGA not ready. Wait for watchdog timeout. */
+			printf("%s: fpga not ready, hanging.\n", __func__);
+			hang();
+		}
+
+		/* brdmodrst */
+		writel(0, &reset_manager_base->brg_mod_reset);
+
+		/* Remap the bridges into memory map */
+		writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
+	}
+}
+#endif
+
+/* Change the reset state for EMAC 0 and EMAC 1 */
+void socfpga_emac_reset(int enable)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	if (enable) {
+		setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
+		setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
+	} else {
+#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
+		clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
+#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
+		clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
+#endif
+	}
 }
@@ -19,6 +19,31 @@
  
 DECLARE_GLOBAL_DATA_PTR;
  
+#define MAIN_VCO_BASE (					\
+	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
+		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\
+		CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
+#define PERI_VCO_BASE (					\
+	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\
+		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\
+	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\
+		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\
+		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
+#define SDR_VCO_BASE (					\
+	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\
+		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\
+	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<		\
+		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\
+		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
 u32 spl_boot_device(void)
 {
 	return BOOT_DEVICE_RAM;
  
  
@@ -33,86 +58,87 @@
 	cm_config_t cm_default_cfg = {
 		/* main group */
 		MAIN_VCO_BASE,
-		CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
-			CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
-		CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
-		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
-			CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
-		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
-		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
-		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
-			CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
-		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
-		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
-		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
-		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
-			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
-		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
-			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
-		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
-			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
-		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
-			CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
-		CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
-			CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
-		CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
-			CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
+		(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
+			CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
+			CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
+			CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
+			CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
+			CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
+			CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
+			CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
+		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
+			CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
+		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
+			CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
+		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
+			CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
+			CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
+		(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
+			CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
+			CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
+		(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
+			CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
+		(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
+			CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
  
 		/* peripheral group */
 		PERI_VCO_BASE,
-		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
-			CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
-		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
-			CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
-		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
-			CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
-		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
-			CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
-		CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
-			CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
-		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
-			CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
-		CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
-			CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
-		CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
-			CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
-		CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
-			CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
-		CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
-			CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
-		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
-			CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
-		CLKMGR_PERPLLGRP_SRC_QSPI_SET(
-			CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
-		CLKMGR_PERPLLGRP_SRC_NAND_SET(
-			CONFIG_HPS_PERPLLGRP_SRC_NAND) |
-		CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
-			CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
+		(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
+			CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
+			CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
+			CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
+			CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
+			CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
+			CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
+			CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
+		(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
+			CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
+		(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
+			CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
+		(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
+			CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
+			CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
+		(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
+			CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
+		(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
+			CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
+		(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
+			CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
  
 		/* sdram pll group */
 		SDR_VCO_BASE,
-		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
-			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
-		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
-			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
-		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
-			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
-		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
-			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
-		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
-			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
-		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
-			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
-		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
-			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
-		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
-			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
+		(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
+			CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
+		(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
+			CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
+		(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
+			CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
+		(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
+			CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
+		(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
+			CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
+		(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
+			CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
+		(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
+			CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
+		(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
+			CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
+
 	};
  
 	debug("Freezing all I/O banks\n");
 /*
- *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
  
  
  
  
  
@@ -7,22 +7,63 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/system_manager.h>
+#include <asm/arch/fpga_manager.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
 /*
+ * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
+ * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
+ * CONFIG_SYSMGR_ISWGRP_HANDOFF.
+ */
+static void populate_sysmgr_fpgaintf_module(void)
+{
+	uint32_t handoff_val = 0;
+
+	/* ISWGRP_HANDOFF_FPGAINTF */
+	writel(0, &sysmgr_regs->iswgrp_handoff[2]);
+
+	/* Enable the signal for those HPS peripherals that use FPGA. */
+	if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_NAND;
+	if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC1;
+	if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SDMMC;
+	if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC0;
+	if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SPIM0;
+	if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SPIM1;
+
+	/* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
+	based on pinmux setting */
+	setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
+
+	handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
+	if (fpgamgr_test_fpga_ready()) {
+		/* Enable the required signals only */
+		writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
+	}
+}
+
+/*
  * Configure all the pin muxes
  */
 void sysmgr_pinmux_init(void)
 {
-	unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
+	uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0];
+	int i;
  
-	const unsigned long *pval = sys_mgr_init_table;
-	unsigned long i;
-
-	for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table);
-		i++, offset += sizeof(unsigned long)) {
-		writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+	for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); i++) {
+		writel(sys_mgr_init_table[i], regs);
+		regs += sizeof(regs);
 	}
+
+	populate_sysmgr_fpgaintf_module();
 }
@@ -8,6 +8,8 @@
 #include <asm/io.h>
 #include <asm/arch/timer.h>
  
+#define TIMER_LOAD_VAL		0xFFFFFFFF
+
 static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
  
 /*
@@ -7,6 +7,15 @@
 #ifndef	_CLOCK_MANAGER_H_
 #define	_CLOCK_MANAGER_H_
  
+#ifndef __ASSEMBLER__
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#endif
+
 typedef struct {
 	/* main group */
 	uint32_t main_vco_base;
@@ -89,6 +98,11 @@
 	u32	stat;
 };
  
+struct socfpga_clock_manager_altera {
+	u32	mpuclk;
+	u32	mainclk;
+};
+
 struct socfpga_clock_manager {
 	u32	ctrl;
 	u32	bypass;
  
  
  
  
@@ -100,113 +114,195 @@
 	struct socfpga_clock_manager_main_pll main_pll;
 	struct socfpga_clock_manager_per_pll per_pll;
 	struct socfpga_clock_manager_sdr_pll sdr_pll;
-	u32	_pad_0xe0_0x200[72];
+	struct socfpga_clock_manager_altera altera;
+	u32	_pad_0xe8_0x200[70];
 };
  
-#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
-#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
-#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
-#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
-#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
-#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
-#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
-#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
-#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x)  (((x) << 7) & 0x00000380)
-#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
-#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
-#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
-#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
-#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
-#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
-#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
-#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
-#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
-#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
-#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
-#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
-#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
-#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
-#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
-#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
-#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \
-	(((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \
-	(((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
-#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
-#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
-#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
-#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
-#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
-#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
-#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
-#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
-#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
-#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
-#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
-#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
-#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
-#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
-#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
-#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
-#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
-#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
-#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
-#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
-#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
-#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
-#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
-#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
+#define CLKMGR_CTRL_SAFEMODE				(1 << 0)
+#define CLKMGR_CTRL_SAFEMODE_OFFSET			0
  
-#define MAIN_VCO_BASE \
-	(CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
-	CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
+#define CLKMGR_BYPASS_PERPLLSRC				(1 << 4)
+#define CLKMGR_BYPASS_PERPLLSRC_OFFSET			4
+#define CLKMGR_BYPASS_PERPLL				(1 << 3)
+#define CLKMGR_BYPASS_PERPLL_OFFSET			3
+#define CLKMGR_BYPASS_SDRPLLSRC				(1 << 2)
+#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET			2
+#define CLKMGR_BYPASS_SDRPLL				(1 << 1)
+#define CLKMGR_BYPASS_SDRPLL_OFFSET			1
+#define CLKMGR_BYPASS_MAINPLL				(1 << 0)
+#define CLKMGR_BYPASS_MAINPLL_OFFSET			0
  
-#define PERI_VCO_BASE \
-	(CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
-	CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
-	CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
+#define CLKMGR_INTER_SDRPLLLOCKED_MASK			0x00000100
+#define CLKMGR_INTER_PERPLLLOCKED_MASK			0x00000080
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK			0x00000040
+#define CLKMGR_INTER_PERPLLLOST_MASK			0x00000010
+#define CLKMGR_INTER_SDRPLLLOST_MASK			0x00000020
+#define CLKMGR_INTER_MAINPLLLOST_MASK			0x00000008
  
-#define SDR_VCO_BASE \
-	(CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
-	CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
-	CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
+#define CLKMGR_STAT_BUSY				(1 << 0)
+
+/* Main PLL */
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN			(1 << 0)
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET		0
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET		16
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK		0x003f0000
+#define CLKMGR_MAINPLLGRP_VCO_EN			(1 << 1)
+#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET			1
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET		3
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK		0x0000fff8
+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK		0x01000000
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN			(1 << 2)
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET		2
+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE		0x8001000d
+
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET		0
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET		0
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET		0
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET	0
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET	0
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK	0x000001ff
+
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET	0
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK	0x000001ff
+
+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK		0x00000010
+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK		0x00000020
+#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK		0x00000080
+#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK		0x00000040
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK		0x00000004
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK		0x00000200
+
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET	0
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK		0x00000003
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET	2
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK		0x0000000c
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET	4
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK		0x00000070
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET	7
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK		0x00000380
+
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET	0
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK		0x00000003
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET		2
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK		0x0000000c
+
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET	0
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK	0x00000007
+
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP			(1 << 0)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET		0
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP			(1 << 1)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET		1
+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE		0x00000000
+#define CLKMGR_L4_SP_CLK_SRC_MAINPLL			0x0
+#define CLKMGR_L4_SP_CLK_SRC_PERPLL			0x1
+
+/* Per PLL */
+#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET		16
+#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK			0x003f0000
+#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET		3
+#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK			0x0000fff8
+#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK		0x01000000
+#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET		22
+#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK			0x00c00000
+#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
+#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE		0x8001000d
+#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET		22
+#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK			0x00c00000
+
+#define CLKMGR_VCO_SSRC_EOSC1				0x0
+#define CLKMGR_VCO_SSRC_EOSC2				0x1
+#define CLKMGR_VCO_SSRC_F2S				0x2
+
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET	0
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK	0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK		0x00000400
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000100
+
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET		6
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK		0x000001c0
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET		9
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK		0x00000e00
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET		3
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET		3
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET		0
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK		0x00000007
+
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET	0
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK		0x00ffffff
+
+#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET		2
+#define CLKMGR_PERPLLGRP_SRC_NAND_MASK			0x0000000c
+#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET		4
+#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK			0x00000030
+#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE		0x00000015
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET		0
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK			0x00000003
+#define CLKMGR_SDMMC_CLK_SRC_F2S			0x0
+#define CLKMGR_SDMMC_CLK_SRC_MAIN			0x1
+#define CLKMGR_SDMMC_CLK_SRC_PER			0x2
+#define CLKMGR_QSPI_CLK_SRC_F2S				0x0
+#define CLKMGR_QSPI_CLK_SRC_MAIN			0x1
+#define CLKMGR_QSPI_CLK_SRC_PER				0x2
+
+/* SDR PLL */
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET		16
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK			0x003f0000
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET		3
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK			0x0000fff8
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL		(1 << 24)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET		24
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET		25
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK		0x7e000000
+#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
+#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE		0x8001000d
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET		22
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK			0x00c00000
+
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET		9
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK		0x00000e00
+
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET	9
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK		0x00000e00
+
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET		9
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK		0x00000e00
+
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET	9
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK		0x00000e00
  
 #endif /* _CLOCK_MANAGER_H_ */
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ */
+
+#ifndef	_FPGA_MANAGER_H_
+#define	_FPGA_MANAGER_H_
+
+#include <altera.h>
+
+struct socfpga_fpga_manager {
+	/* FPGA Manager Module */
+	u32	stat;			/* 0x00 */
+	u32	ctrl;
+	u32	dclkcnt;
+	u32	dclkstat;
+	u32	gpo;			/* 0x10 */
+	u32	gpi;
+	u32	misci;			/* 0x18 */
+	u32	_pad_0x1c_0x82c[517];
+
+	/* Configuration Monitor (MON) Registers */
+	u32	gpio_inten;		/* 0x830 */
+	u32	gpio_intmask;
+	u32	gpio_inttype_level;
+	u32	gpio_int_polarity;
+	u32	gpio_intstatus;		/* 0x840 */
+	u32	gpio_raw_intstatus;
+	u32	_pad_0x848;
+	u32	gpio_porta_eoi;
+	u32	gpio_ext_porta;		/* 0x850 */
+	u32	_pad_0x854_0x85c[3];
+	u32	gpio_1s_sync;		/* 0x860 */
+	u32	_pad_0x864_0x868[2];
+	u32	gpio_ver_id_code;
+	u32	gpio_config_reg2;	/* 0x870 */
+	u32	gpio_config_reg1;
+};
+
+#define FPGAMGRREGS_STAT_MODE_MASK		0x7
+#define FPGAMGRREGS_STAT_MSEL_MASK		0xf8
+#define FPGAMGRREGS_STAT_MSEL_LSB		3
+
+#define FPGAMGRREGS_CTRL_CFGWDTH_MASK		0x200
+#define FPGAMGRREGS_CTRL_AXICFGEN_MASK		0x100
+#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK	0x4
+#define FPGAMGRREGS_CTRL_NCE_MASK		0x2
+#define FPGAMGRREGS_CTRL_EN_MASK		0x1
+#define FPGAMGRREGS_CTRL_CDRATIO_LSB		6
+
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK	0x8
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK	0x4
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK	0x2
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK	0x1
+
+/* FPGA Mode */
+#define FPGAMGRREGS_MODE_FPGAOFF		0x0
+#define FPGAMGRREGS_MODE_RESETPHASE		0x1
+#define FPGAMGRREGS_MODE_CFGPHASE		0x2
+#define FPGAMGRREGS_MODE_INITPHASE		0x3
+#define FPGAMGRREGS_MODE_USERMODE		0x4
+#define FPGAMGRREGS_MODE_UNKNOWN		0x5
+
+/* FPGA CD Ratio Value */
+#define CDRATIO_x1				0x0
+#define CDRATIO_x2				0x1
+#define CDRATIO_x4				0x2
+#define CDRATIO_x8				0x3
+
+/* SoCFPGA support functions */
+int fpgamgr_test_fpga_ready(void);
+int fpgamgr_poll_fpga_ready(void);
+int fpgamgr_get_mode(void);
+
+#endif /* _FPGA_MANAGER_H_ */
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_NIC301_REGISTERS_H_
+#define	_NIC301_REGISTERS_H_
+
+struct nic301_registers {
+	u32	remap;				/* 0x0 */
+	/* Security Register Group */
+	u32	_pad_0x4_0x8[1];
+	u32	l4main;
+	u32	l4sp;
+	u32	l4mp;				/* 0x10 */
+	u32	l4osc1;
+	u32	l4spim;
+	u32	stm;
+	u32	lwhps2fpgaregs;			/* 0x20 */
+	u32	_pad_0x24_0x28[1];
+	u32	usb1;
+	u32	nanddata;
+	u32	_pad_0x30_0x80[20];
+	u32	usb0;				/* 0x80 */
+	u32	nandregs;
+	u32	qspidata;
+	u32	fpgamgrdata;
+	u32	hps2fpgaregs;			/* 0x90 */
+	u32	acp;
+	u32	rom;
+	u32	ocram;
+	u32	sdrdata;			/* 0xA0 */
+	u32	_pad_0xa4_0x1fd0[1995];
+	/* ID Register Group */
+	u32	periph_id_4;			/* 0x1FD0 */
+	u32	_pad_0x1fd4_0x1fe0[3];
+	u32	periph_id_0;			/* 0x1FE0 */
+	u32	periph_id_1;
+	u32	periph_id_2;
+	u32	periph_id_3;
+	u32	comp_id_0;			/* 0x1FF0 */
+	u32	comp_id_1;
+	u32	comp_id_2;
+	u32	comp_id_3;
+	u32	_pad_0x2000_0x2008[2];
+	/* L4 MAIN */
+	u32	l4main_fn_mod_bm_iss;
+	u32	_pad_0x200c_0x3008[1023];
+	/* L4 SP */
+	u32	l4sp_fn_mod_bm_iss;
+	u32	_pad_0x300c_0x4008[1023];
+	/* L4 MP */
+	u32	l4mp_fn_mod_bm_iss;
+	u32	_pad_0x400c_0x5008[1023];
+	/* L4 OSC1 */
+	u32	l4osc_fn_mod_bm_iss;
+	u32	_pad_0x500c_0x6008[1023];
+	/* L4 SPIM */
+	u32	l4spim_fn_mod_bm_iss;
+	u32	_pad_0x600c_0x7008[1023];
+	/* STM */
+	u32	stm_fn_mod_bm_iss;
+	u32	_pad_0x700c_0x7108[63];
+	u32	stm_fn_mod;
+	u32	_pad_0x710c_0x8008[959];
+	/* LWHPS2FPGA */
+	u32	lwhps2fpga_fn_mod_bm_iss;
+	u32	_pad_0x800c_0x8108[63];
+	u32	lwhps2fpga_fn_mod;
+	u32	_pad_0x810c_0xa008[1983];
+	/* USB1 */
+	u32	usb1_fn_mod_bm_iss;
+	u32	_pad_0xa00c_0xa044[14];
+	u32	usb1_ahb_cntl;
+	u32	_pad_0xa048_0xb008[1008];
+	/* NANDDATA */
+	u32	nanddata_fn_mod_bm_iss;
+	u32	_pad_0xb00c_0xb108[63];
+	u32	nanddata_fn_mod;
+	u32	_pad_0xb10c_0x20008[21439];
+	/* USB0 */
+	u32	usb0_fn_mod_bm_iss;
+	u32	_pad_0x2000c_0x20044[14];
+	u32	usb0_ahb_cntl;
+	u32	_pad_0x20048_0x21008[1008];
+	/* NANDREGS */
+	u32	nandregs_fn_mod_bm_iss;
+	u32	_pad_0x2100c_0x21108[63];
+	u32	nandregs_fn_mod;
+	u32	_pad_0x2110c_0x22008[959];
+	/* QSPIDATA */
+	u32	qspidata_fn_mod_bm_iss;
+	u32	_pad_0x2200c_0x22044[14];
+	u32	qspidata_ahb_cntl;
+	u32	_pad_0x22048_0x23008[1008];
+	/* FPGAMGRDATA */
+	u32	fpgamgrdata_fn_mod_bm_iss;
+	u32	_pad_0x2300c_0x23040[13];
+	u32	fpgamgrdata_wr_tidemark;	/* 0x23040 */
+	u32	_pad_0x23044_0x23108[49];
+	u32	fn_mod;
+	u32	_pad_0x2310c_0x24008[959];
+	/* HPS2FPGA */
+	u32	hps2fpga_fn_mod_bm_iss;
+	u32	_pad_0x2400c_0x24040[13];
+	u32	hps2fpga_wr_tidemark;		/* 0x24040 */
+	u32	_pad_0x24044_0x24108[49];
+	u32	hps2fpga_fn_mod;
+	u32	_pad_0x2410c_0x25008[959];
+	/* ACP */
+	u32	acp_fn_mod_bm_iss;
+	u32	_pad_0x2500c_0x25108[63];
+	u32	acp_fn_mod;
+	u32	_pad_0x2510c_0x26008[959];
+	/* Boot ROM */
+	u32	bootrom_fn_mod_bm_iss;
+	u32	_pad_0x2600c_0x26108[63];
+	u32	bootrom_fn_mod;
+	u32	_pad_0x2610c_0x27008[959];
+	/* On-chip RAM */
+	u32	ocram_fn_mod_bm_iss;
+	u32	_pad_0x2700c_0x27040[13];
+	u32	ocram_wr_tidemark;		/* 0x27040 */
+	u32	_pad_0x27044_0x27108[49];
+	u32	ocram_fn_mod;
+	u32	_pad_0x2710c_0x42024[27590];
+	/* DAP */
+	u32	dap_fn_mod2;
+	u32	dap_fn_mod_ahb;
+	u32	_pad_0x4202c_0x42100[53];
+	u32	dap_read_qos;			/* 0x42100 */
+	u32	dap_write_qos;
+	u32	dap_fn_mod;
+	u32	_pad_0x4210c_0x43100[1021];
+	/* MPU */
+	u32	mpu_read_qos;			/* 0x43100 */
+	u32	mpu_write_qos;
+	u32	mpu_fn_mod;
+	u32	_pad_0x4310c_0x44028[967];
+	/* SDMMC */
+	u32	sdmmc_fn_mod_ahb;
+	u32	_pad_0x4402c_0x44100[53];
+	u32	sdmmc_read_qos;			/* 0x44100 */
+	u32	sdmmc_write_qos;
+	u32	sdmmc_fn_mod;
+	u32	_pad_0x4410c_0x45100[1021];
+	/* DMA */
+	u32	dma_read_qos;			/* 0x45100 */
+	u32	dma_write_qos;
+	u32	dma_fn_mod;
+	u32	_pad_0x4510c_0x46040[973];
+	/* FPGA2HPS */
+	u32	fpga2hps_wr_tidemark;		/* 0x46040 */
+	u32	_pad_0x46044_0x46100[47];
+	u32	fpga2hps_read_qos;		/* 0x46100 */
+	u32	fpga2hps_write_qos;
+	u32	fpga2hps_fn_mod;
+	u32	_pad_0x4610c_0x47100[1021];
+	/* ETR */
+	u32	etr_read_qos;			/* 0x47100 */
+	u32	etr_write_qos;
+	u32	etr_fn_mod;
+	u32	_pad_0x4710c_0x48100[1021];
+	/* EMAC0 */
+	u32	emac0_read_qos;			/* 0x48100 */
+	u32	emac0_write_qos;
+	u32	emac0_fn_mod;
+	u32	_pad_0x4810c_0x49100[1021];
+	/* EMAC1 */
+	u32	emac1_read_qos;			/* 0x49100 */
+	u32	emac1_write_qos;
+	u32	emac1_fn_mod;
+	u32	_pad_0x4910c_0x4a028[967];
+	/* USB0 */
+	u32	usb0_fn_mod_ahb;
+	u32	_pad_0x4a02c_0x4a100[53];
+	u32	usb0_read_qos;			/* 0x4A100 */
+	u32	usb0_write_qos;
+	u32	usb0_fn_mod;
+	u32	_pad_0x4a10c_0x4b100[1021];
+	/* NAND */
+	u32	nand_read_qos;			/* 0x4B100 */
+	u32	nand_write_qos;
+	u32	nand_fn_mod;
+	u32	_pad_0x4b10c_0x4c028[967];
+	/* USB1 */
+	u32	usb1_fn_mod_ahb;
+	u32	_pad_0x4c02c_0x4c100[53];
+	u32	usb1_read_qos;			/* 0x4C100 */
+	u32	usb1_write_qos;
+	u32	usb1_fn_mod;
+};
+
+#endif	/* _NIC301_REGISTERS_H_ */
@@ -10,6 +10,11 @@
 void reset_cpu(ulong addr);
 void reset_deassert_peripherals_handoff(void);
  
+void socfpga_bridges_reset(int enable);
+
+void socfpga_emac_reset(int enable);
+void socfpga_watchdog_reset(void);
+
 struct socfpga_reset_manager {
 	u32	status;
 	u32	ctrl;
@@ -26,6 +31,10 @@
 #else
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
 #endif
+
+#define RSTMGR_PERMODRST_EMAC0_LSB	0
+#define RSTMGR_PERMODRST_EMAC1_LSB	1
+#define RSTMGR_PERMODRST_L4WD0_LSB	6
  
 #endif /* _RESET_MANAGER_H_ */
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SOCFPGA_SCU_H__
+#define __SOCFPGA_SCU_H__
+
+struct scu_registers {
+	u32	ctrl;			/* 0x00 */
+	u32	cfg;
+	u32	cpsr;
+	u32	iassr;
+	u32	_pad_0x10_0x3c[12];	/* 0x10 */
+	u32	fsar;			/* 0x40 */
+	u32	fear;
+	u32	_pad_0x48_0x50[2];
+	u32	acr;			/* 0x54 */
+	u32	sacr;
+};
+
+#endif	/* __SOCFPGA_SCU_H__ */
@@ -7,17 +7,57 @@
 #ifndef _SOCFPGA_BASE_ADDRS_H_
 #define _SOCFPGA_BASE_ADDRS_H_
  
-#define SOCFPGA_L3REGS_ADDRESS 0xff800000
-#define SOCFPGA_UART0_ADDRESS 0xffc02000
-#define SOCFPGA_UART1_ADDRESS 0xffc03000
-#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
-#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
-#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
-#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
-#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
-#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000
-#define SOCFPGA_EMAC0_ADDRESS 0xff700000
-#define SOCFPGA_EMAC1_ADDRESS 0xff702000
+#define SOCFPGA_STM_ADDRESS		0xfc000000
+#define SOCFPGA_DAP_ADDRESS		0xff000000
+#define SOCFPGA_EMAC0_ADDRESS		0xff700000
+#define SOCFPGA_EMAC1_ADDRESS		0xff702000
+#define SOCFPGA_SDMMC_ADDRESS		0xff704000
+#define SOCFPGA_QSPI_ADDRESS		0xff705000
+#define SOCFPGA_GPIO0_ADDRESS		0xff708000
+#define SOCFPGA_GPIO1_ADDRESS		0xff709000
+#define SOCFPGA_GPIO2_ADDRESS		0xff70a000
+#define SOCFPGA_L3REGS_ADDRESS		0xff800000
+#define SOCFPGA_USB0_ADDRESS		0xffb00000
+#define SOCFPGA_USB1_ADDRESS		0xffb40000
+#define SOCFPGA_CAN0_ADDRESS		0xffc00000
+#define SOCFPGA_CAN1_ADDRESS		0xffc01000
+#define SOCFPGA_UART0_ADDRESS		0xffc02000
+#define SOCFPGA_UART1_ADDRESS		0xffc03000
+#define SOCFPGA_I2C0_ADDRESS		0xffc04000
+#define SOCFPGA_I2C1_ADDRESS		0xffc05000
+#define SOCFPGA_I2C2_ADDRESS		0xffc06000
+#define SOCFPGA_I2C3_ADDRESS		0xffc07000
+#define SOCFPGA_SDR_ADDRESS		0xffc20000
+#define SOCFPGA_L4WD0_ADDRESS		0xffd02000
+#define SOCFPGA_L4WD1_ADDRESS		0xffd03000
+#define SOCFPGA_CLKMGR_ADDRESS		0xffd04000
+#define SOCFPGA_RSTMGR_ADDRESS		0xffd05000
+#define SOCFPGA_SYSMGR_ADDRESS		0xffd08000
+#define SOCFPGA_SPIS0_ADDRESS		0xffe02000
+#define SOCFPGA_SPIS1_ADDRESS		0xffe03000
+#define SOCFPGA_SPIM0_ADDRESS		0xfff00000
+#define SOCFPGA_SPIM1_ADDRESS		0xfff01000
+#define SOCFPGA_SCANMGR_ADDRESS		0xfff02000
+#define SOCFPGA_ROM_ADDRESS		0xfffd0000
+#define SOCFPGA_MPUSCU_ADDRESS		0xfffec000
+#define SOCFPGA_MPUL2_ADDRESS		0xfffef000
+#define SOCFPGA_OCRAM_ADDRESS		0xffff0000
+#define SOCFPGA_LWFPGASLAVES_ADDRESS	0xff200000
+#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS	0xff400000
+#define SOCFPGA_HPS2FPGAREGS_ADDRESS	0xff500000
+#define SOCFPGA_FPGA2HPSREGS_ADDRESS	0xff600000
+#define SOCFPGA_FPGAMGRREGS_ADDRESS	0xff706000
+#define SOCFPGA_ACPIDMAP_ADDRESS	0xff707000
+#define SOCFPGA_NANDDATA_ADDRESS	0xff900000
+#define SOCFPGA_QSPIDATA_ADDRESS	0xffa00000
+#define SOCFPGA_NANDREGS_ADDRESS	0xffb80000
+#define SOCFPGA_FPGAMGRDATA_ADDRESS	0xffb90000
+#define SOCFPGA_SPTIMER0_ADDRESS	0xffc08000
+#define SOCFPGA_SPTIMER1_ADDRESS	0xffc09000
+#define SOCFPGA_OSC1TIMER0_ADDRESS	0xffd00000
+#define SOCFPGA_OSC1TIMER1_ADDRESS	0xffd01000
+#define SOCFPGA_DMANONSECURE_ADDRESS	0xffe00000
+#define SOCFPGA_DMASECURE_ADDRESS	0xffe01000
  
 #endif /* _SOCFPGA_BASE_ADDRS_H_ */
 /*
- *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
@@ -16,73 +16,132 @@
  
 #endif
  
-
-#define CONFIG_SYSMGR_PINMUXGRP_OFFSET	(0x400)
-
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)	\
-	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
-
 struct socfpga_system_manager {
-	u32	siliconid1;
+	/* System Manager Module */
+	u32	siliconid1;			/* 0x00 */
 	u32	siliconid2;
 	u32	_pad_0x8_0xf[2];
-	u32	wddbg;
+	u32	wddbg;				/* 0x10 */
 	u32	bootinfo;
 	u32	hpsinfo;
 	u32	parityinj;
-	u32	fpgaintfgrp_gbl;
+	/* FPGA Interface Group */
+	u32	fpgaintfgrp_gbl;		/* 0x20 */
 	u32	fpgaintfgrp_indiv;
 	u32	fpgaintfgrp_module;
 	u32	_pad_0x2c_0x2f;
-	u32	scanmgrgrp_ctrl;
+	/* Scan Manager Group */
+	u32	scanmgrgrp_ctrl;		/* 0x30 */
 	u32	_pad_0x34_0x3f[3];
-	u32	frzctrl_vioctrl;
+	/* Freeze Control Group */
+	u32	frzctrl_vioctrl;		/* 0x40 */
 	u32	_pad_0x44_0x4f[3];
-	u32	frzctrl_hioctrl;
+	u32	frzctrl_hioctrl;		/* 0x50 */
 	u32	frzctrl_src;
 	u32	frzctrl_hwctrl;
 	u32	_pad_0x5c_0x5f;
-	u32	emacgrp_ctrl;
+	/* EMAC Group */
+	u32	emacgrp_ctrl;			/* 0x60 */
 	u32	emacgrp_l3master;
 	u32	_pad_0x68_0x6f[2];
-	u32	dmagrp_ctrl;
+	/* DMA Controller Group */
+	u32	dmagrp_ctrl;			/* 0x70 */
 	u32	dmagrp_persecurity;
 	u32	_pad_0x78_0x7f[2];
-	u32	iswgrp_handoff[8];
-	u32	_pad_0xa0_0xbf[8];
-	u32	romcodegrp_ctrl;
+	/* Preloader (initial software) Group */
+	u32	iswgrp_handoff[8];		/* 0x80 */
+	u32	_pad_0xa0_0xbf[8];		/* 0xa0 */
+	/* Boot ROM Code Register Group */
+	u32	romcodegrp_ctrl;		/* 0xc0 */
 	u32	romcodegrp_cpu1startaddr;
 	u32	romcodegrp_initswstate;
 	u32	romcodegrp_initswlastld;
-	u32	romcodegrp_bootromswstate;
+	u32	romcodegrp_bootromswstate;	/* 0xd0 */
 	u32	__pad_0xd4_0xdf[3];
-	u32	romcodegrp_warmramgrp_enable;
+	/* Warm Boot from On-Chip RAM Group */
+	u32	romcodegrp_warmramgrp_enable;	/* 0xe0 */
 	u32	romcodegrp_warmramgrp_datastart;
 	u32	romcodegrp_warmramgrp_length;
 	u32	romcodegrp_warmramgrp_execution;
-	u32	romcodegrp_warmramgrp_crc;
+	u32	romcodegrp_warmramgrp_crc;	/* 0xf0 */
 	u32	__pad_0xf4_0xff[3];
-	u32	romhwgrp_ctrl;
+	/* Boot ROM Hardware Register Group */
+	u32	romhwgrp_ctrl;			/* 0x100 */
 	u32	_pad_0x104_0x107;
+	/* SDMMC Controller Group */
 	u32	sdmmcgrp_ctrl;
 	u32	sdmmcgrp_l3master;
-	u32	nandgrp_bootstrap;
+	/* NAND Flash Controller Register Group */
+	u32	nandgrp_bootstrap;		/* 0x110 */
 	u32	nandgrp_l3master;
+	/* USB Controller Group */
 	u32	usbgrp_l3master;
 	u32	_pad_0x11c_0x13f[9];
-	u32	eccgrp_l2;
+	/* ECC Management Register Group */
+	u32	eccgrp_l2;			/* 0x140 */
 	u32	eccgrp_ocram;
 	u32	eccgrp_usb0;
 	u32	eccgrp_usb1;
-	u32	eccgrp_emac0;
+	u32	eccgrp_emac0;			/* 0x150 */
 	u32	eccgrp_emac1;
 	u32	eccgrp_dma;
 	u32	eccgrp_can0;
-	u32	eccgrp_can1;
+	u32	eccgrp_can1;			/* 0x160 */
 	u32	eccgrp_nand;
 	u32	eccgrp_qspi;
 	u32	eccgrp_sdmmc;
+	u32	_pad_0x170_0x3ff[164];
+	/* Pin Mux Control Group */
+	u32	emacio[20];			/* 0x400 */
+	u32	flashio[12];			/* 0x450 */
+	u32	generalio[28];			/* 0x480 */
+	u32	_pad_0x4f0_0x4ff[4];
+	u32	mixed1io[22];			/* 0x500 */
+	u32	mixed2io[8];			/* 0x558 */
+	u32	gplinmux[23];			/* 0x578 */
+	u32	gplmux[71];			/* 0x5d4 */
+	u32	nandusefpga;			/* 0x6f0 */
+	u32	_pad_0x6f4;
+	u32	rgmii1usefpga;			/* 0x6f8 */
+	u32	_pad_0x6fc_0x700[2];
+	u32	i2c0usefpga;			/* 0x704 */
+	u32	sdmmcusefpga;			/* 0x708 */
+	u32	_pad_0x70c_0x710[2];
+	u32	rgmii0usefpga;			/* 0x714 */
+	u32	_pad_0x718_0x720[3];
+	u32	i2c3usefpga;			/* 0x724 */
+	u32	i2c2usefpga;			/* 0x728 */
+	u32	i2c1usefpga;			/* 0x72c */
+	u32	spim1usefpga;			/* 0x730 */
+	u32	_pad_0x734;
+	u32	spim0usefpga;			/* 0x738 */
 };
+
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	(1 << 0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	(1 << 1)
+#define SYSMGR_ECC_OCRAM_EN	(1 << 0)
+#define SYSMGR_ECC_OCRAM_SERR	(1 << 3)
+#define SYSMGR_ECC_OCRAM_DERR	(1 << 4)
+#define SYSMGR_FPGAINTF_USEFPGA	0x1
+#define SYSMGR_FPGAINTF_SPIM0	(1 << 0)
+#define SYSMGR_FPGAINTF_SPIM1	(1 << 1)
+#define SYSMGR_FPGAINTF_EMAC0	(1 << 2)
+#define SYSMGR_FPGAINTF_EMAC1	(1 << 3)
+#define SYSMGR_FPGAINTF_NAND	(1 << 4)
+#define SYSMGR_FPGAINTF_SDMMC	(1 << 5)
+
+/* FIXME: This is questionable macro. */
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)	\
+	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB			0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
  
 #endif /* _SYSTEM_MANAGER_H_ */
@@ -185,6 +185,7 @@
 	DCACHE_OFF = 0x12,
 	DCACHE_WRITETHROUGH = 0x1a,
 	DCACHE_WRITEBACK = 0x1e,
+	DCACHE_WRITEALLOC = 0x16,
 };
  
 /* Size of an MMU section */
@@ -73,6 +73,8 @@
 	     i++) {
 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
 		set_section_dcache(i, DCACHE_WRITETHROUGH);
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+		set_section_dcache(i, DCACHE_WRITEALLOC);
 #else
 		set_section_dcache(i, DCACHE_WRITEBACK);
 #endif
@@ -94,6 +94,9 @@
  
 /* Info for driver */
 #define CONFIG_HPS_CLK_OSC1_HZ			(25000000)
+#define CONFIG_HPS_CLK_OSC2_HZ			0
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ		0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ		0
 #define CONFIG_HPS_CLK_MAINVCO_HZ		(1600000000)
 #define CONFIG_HPS_CLK_PERVCO_HZ		(1000000000)
 #ifdef CONFIG_SOCFPGA_ARRIA5
@@ -17,7 +17,7 @@
  */
 int checkboard(void)
 {
-	puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
+	puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
 	return 0;
 }
  
@@ -34,7 +34,9 @@
  */
 int board_init(void)
 {
-	icache_enable();
+	/* Address of boot parameters for ATAG (if ATAG is used) */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
 	return 0;
 }
@@ -138,6 +138,7 @@
 	{	IH_TYPE_PBLIMAGE,   "pblimage",   "Freescale PBL Boot Image",},
 	{	IH_TYPE_RAMDISK,    "ramdisk",	  "RAMDisk Image",	},
 	{	IH_TYPE_SCRIPT,     "script",	  "Script",		},
+	{	IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SOCFPGA preloader",},
 	{	IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
 	{	IH_TYPE_UBLIMAGE,   "ublimage",   "Davinci UBL image",},
 	{	IH_TYPE_MXSIMAGE,   "mxsimage",   "Freescale MXS Boot Image",},
@@ -17,5 +17,6 @@
 obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
 obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
 obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
+obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
 endif
@@ -12,217 +12,163 @@
  *  Altera FPGA support
  */
 #include <common.h>
+#include <errno.h>
 #include <ACEX1K.h>
 #include <stratixII.h>
  
-/* Define FPGA_DEBUG to get debug printf's */
-/* #define FPGA_DEBUG */
+/* Define FPGA_DEBUG to 1 to get debug printf's */
+#define FPGA_DEBUG	0
  
-#ifdef	FPGA_DEBUG
-#define	PRINTF(fmt,args...)	printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-/* Local Static Functions */
-static int altera_validate (Altera_desc * desc, const char *fn);
-
-/* ------------------------------------------------------------------------- */
-int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
-{
-	int ret_val = FPGA_FAIL;	/* assume a failure */
-
-	if (!altera_validate (desc, (char *)__FUNCTION__)) {
-		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
-	} else {
-		switch (desc->family) {
-		case Altera_ACEX1K:
-		case Altera_CYC2:
+static const struct altera_fpga {
+	enum altera_family	family;
+	const char		*name;
+	int			(*load)(Altera_desc *, const void *, size_t);
+	int			(*dump)(Altera_desc *, const void *, size_t);
+	int			(*info)(Altera_desc *);
+} altera_fpga[] = {
 #if defined(CONFIG_FPGA_ACEX1K)
-			PRINTF ("%s: Launching the ACEX1K Loader...\n",
-					__FUNCTION__);
-			ret_val = ACEX1K_load (desc, buf, bsize);
+	{ Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
+	{ Altera_CYC2,   "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
 #elif defined(CONFIG_FPGA_CYCLON2)
-			PRINTF ("%s: Launching the CYCLONE II Loader...\n",
-					__FUNCTION__);
-			ret_val = CYC2_load (desc, buf, bsize);
-#else
-			printf ("%s: No support for ACEX1K devices.\n",
-					__FUNCTION__);
+	{ Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
+	{ Altera_CYC2,   "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
 #endif
-			break;
-
 #if defined(CONFIG_FPGA_STRATIX_II)
-		case Altera_StratixII:
-			PRINTF ("%s: Launching the Stratix II Loader...\n",
-				__FUNCTION__);
-			ret_val = StratixII_load (desc, buf, bsize);
-			break;
+	{ Altera_StratixII, "StratixII", StratixII_load,
+	  StratixII_dump, StratixII_info },
 #endif
-		default:
-			printf ("%s: Unsupported family type, %d\n",
-					__FUNCTION__, desc->family);
-		}
+#if defined(CONFIG_FPGA_SOCFPGA)
+	{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
+#endif
+};
+
+static int altera_validate(Altera_desc *desc, const char *fn)
+{
+	if (!desc) {
+		printf("%s: NULL descriptor!\n", fn);
+		return -EINVAL;
 	}
  
-	return ret_val;
+	if ((desc->family < min_altera_type) ||
+	    (desc->family > max_altera_type)) {
+		printf("%s: Invalid family type, %d\n", fn, desc->family);
+		return -EINVAL;
+	}
+
+	if ((desc->iface < min_altera_iface_type) ||
+	    (desc->iface > max_altera_iface_type)) {
+		printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
+		return -EINVAL;
+	}
+
+	if (!desc->size) {
+		printf("%s: NULL part size\n", fn);
+		return -EINVAL;
+	}
+
+	return 0;
 }
  
-int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
+static const struct altera_fpga *
+altera_desc_to_fpga(Altera_desc *desc, const char *fn)
 {
-	int ret_val = FPGA_FAIL;	/* assume a failure */
+	int i;
  
-	if (!altera_validate (desc, (char *)__FUNCTION__)) {
-		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
-	} else {
-		switch (desc->family) {
-		case Altera_ACEX1K:
-#if defined(CONFIG_FPGA_ACEX)
-			PRINTF ("%s: Launching the ACEX1K Reader...\n",
-					__FUNCTION__);
-			ret_val = ACEX1K_dump (desc, buf, bsize);
-#else
-			printf ("%s: No support for ACEX1K devices.\n",
-					__FUNCTION__);
-#endif
-			break;
+	if (altera_validate(desc, fn)) {
+		printf("%s: Invalid device descriptor\n", fn);
+		return NULL;
+	}
  
-#if defined(CONFIG_FPGA_STRATIX_II)
-		case Altera_StratixII:
-			PRINTF ("%s: Launching the Stratix II Reader...\n",
-				__FUNCTION__);
-			ret_val = StratixII_dump (desc, buf, bsize);
+	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) {
+		if (desc->family == altera_fpga[i].family)
 			break;
-#endif
-		default:
-			printf ("%s: Unsupported family type, %d\n",
-					__FUNCTION__, desc->family);
-		}
 	}
  
-	return ret_val;
+	if (i == ARRAY_SIZE(altera_fpga)) {
+		printf("%s: Unsupported family type, %d\n", fn, desc->family);
+		return NULL;
+	}
+
+	return &altera_fpga[i];
 }
  
-int altera_info( Altera_desc *desc )
+int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
 {
-	int ret_val = FPGA_FAIL;
+	const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
  
-	if (altera_validate (desc, (char *)__FUNCTION__)) {
-		printf ("Family:        \t");
-		switch (desc->family) {
-		case Altera_ACEX1K:
-			printf ("ACEX1K\n");
-			break;
-		case Altera_CYC2:
-			printf ("CYCLON II\n");
-			break;
-		case Altera_StratixII:
-			printf ("Stratix II\n");
-			break;
-			/* Add new family types here */
-		default:
-			printf ("Unknown family type, %d\n", desc->family);
-		}
+	if (!fpga)
+		return FPGA_FAIL;
  
-		printf ("Interface type:\t");
-		switch (desc->iface) {
-		case passive_serial:
-			printf ("Passive Serial (PS)\n");
-			break;
-		case passive_parallel_synchronous:
-			printf ("Passive Parallel Synchronous (PPS)\n");
-			break;
-		case passive_parallel_asynchronous:
-			printf ("Passive Parallel Asynchronous (PPA)\n");
-			break;
-		case passive_serial_asynchronous:
-			printf ("Passive Serial Asynchronous (PSA)\n");
-			break;
-		case altera_jtag_mode:		/* Not used */
-			printf ("JTAG Mode\n");
-			break;
-		case fast_passive_parallel:
-			printf ("Fast Passive Parallel (FPP)\n");
-			break;
-		case fast_passive_parallel_security:
-			printf
-			    ("Fast Passive Parallel with Security (FPPS) \n");
-			break;
-			/* Add new interface types here */
-		default:
-			printf ("Unsupported interface type, %d\n", desc->iface);
-		}
+	debug_cond(FPGA_DEBUG, "%s: Launching the %s Loader...\n",
+		   __func__, fpga->name);
+	if (fpga->load)
+		return fpga->load(desc, buf, bsize);
+	return 0;
+}
  
-		printf("Device Size:   \t%zd bytes\n"
-		      "Cookie:        \t0x%x (%d)\n",
-		      desc->size, desc->cookie, desc->cookie);
+int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
+{
+	const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
  
-		if (desc->iface_fns) {
-			printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
-			switch (desc->family) {
-			case Altera_ACEX1K:
-			case Altera_CYC2:
-#if defined(CONFIG_FPGA_ACEX1K)
-				ACEX1K_info (desc);
-#elif defined(CONFIG_FPGA_CYCLON2)
-				CYC2_info (desc);
-#else
-				/* just in case */
-				printf ("%s: No support for ACEX1K devices.\n",
-						__FUNCTION__);
-#endif
-				break;
-#if defined(CONFIG_FPGA_STRATIX_II)
-			case Altera_StratixII:
-				StratixII_info (desc);
-				break;
-#endif
-				/* Add new family types here */
-			default:
-				/* we don't need a message here - we give one up above */
-				break;
-			}
-		} else {
-			printf ("No Device Function Table.\n");
-		}
+	if (!fpga)
+		return FPGA_FAIL;
  
-		ret_val = FPGA_SUCCESS;
-	} else {
-		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
-	}
-
-	return ret_val;
+	debug_cond(FPGA_DEBUG, "%s: Launching the %s Reader...\n",
+		   __func__, fpga->name);
+	if (fpga->dump)
+		return fpga->dump(desc, buf, bsize);
+	return 0;
 }
  
-/* ------------------------------------------------------------------------- */
-
-static int altera_validate (Altera_desc * desc, const char *fn)
+int altera_info(Altera_desc *desc)
 {
-	int ret_val = false;
+	const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
  
-	if (desc) {
-		if ((desc->family > min_altera_type) &&
-			(desc->family < max_altera_type)) {
-			if ((desc->iface > min_altera_iface_type) &&
-				(desc->iface < max_altera_iface_type)) {
-				if (desc->size) {
-					ret_val = true;
-				} else {
-					printf ("%s: NULL part size\n", fn);
-				}
-			} else {
-				printf ("%s: Invalid Interface type, %d\n",
-					fn, desc->iface);
-			}
-		} else {
-			printf ("%s: Invalid family type, %d\n", fn, desc->family);
-		}
+	if (!fpga)
+		return FPGA_FAIL;
+
+	printf("Family:        \t%s\n", fpga->name);
+
+	printf("Interface type:\t");
+	switch (desc->iface) {
+	case passive_serial:
+		printf("Passive Serial (PS)\n");
+		break;
+	case passive_parallel_synchronous:
+		printf("Passive Parallel Synchronous (PPS)\n");
+		break;
+	case passive_parallel_asynchronous:
+		printf("Passive Parallel Asynchronous (PPA)\n");
+		break;
+	case passive_serial_asynchronous:
+		printf("Passive Serial Asynchronous (PSA)\n");
+		break;
+	case altera_jtag_mode:		/* Not used */
+		printf("JTAG Mode\n");
+		break;
+	case fast_passive_parallel:
+		printf("Fast Passive Parallel (FPP)\n");
+		break;
+	case fast_passive_parallel_security:
+		printf("Fast Passive Parallel with Security (FPPS)\n");
+		break;
+		/* Add new interface types here */
+	default:
+		printf("Unsupported interface type, %d\n", desc->iface);
+	}
+
+	printf("Device Size:   \t%zd bytes\n"
+	       "Cookie:        \t0x%x (%d)\n",
+	       desc->size, desc->cookie, desc->cookie);
+
+	if (desc->iface_fns) {
+		printf("Device Function Table @ 0x%p\n", desc->iface_fns);
+		if (fpga->info)
+			fpga->info(desc);
 	} else {
-		printf ("%s: NULL descriptor!\n", fn);
+		printf("No Device Function Table.\n");
 	}
  
-	return ret_val;
+	return FPGA_SUCCESS;
 }
-
-/* ------------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timeout count */
+#define FPGA_TIMEOUT_CNT		0x1000000
+
+static struct socfpga_fpga_manager *fpgamgr_regs =
+	(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/* Set CD ratio */
+static void fpgamgr_set_cd_ratio(unsigned long ratio)
+{
+	clrsetbits_le32(&fpgamgr_regs->ctrl,
+			0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
+			(ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
+}
+
+static int fpgamgr_dclkcnt_set(unsigned long cnt)
+{
+	unsigned long i;
+
+	/* Clear any existing done status */
+	if (readl(&fpgamgr_regs->dclkstat))
+		writel(0x1, &fpgamgr_regs->dclkstat);
+
+	/* Write the dclkcnt */
+	writel(cnt, &fpgamgr_regs->dclkcnt);
+
+	/* Wait till the dclkcnt done */
+	for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+		if (!readl(&fpgamgr_regs->dclkstat))
+			continue;
+
+		writel(0x1, &fpgamgr_regs->dclkstat);
+		return 0;
+	}
+
+	return -ETIMEDOUT;
+}
+
+/* Start the FPGA programming by initialize the FPGA Manager */
+static int fpgamgr_program_init(void)
+{
+	unsigned long msel, i;
+
+	/* Get the MSEL value */
+	msel = readl(&fpgamgr_regs->stat);
+	msel &= FPGAMGRREGS_STAT_MSEL_MASK;
+	msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
+
+	/*
+	 * Set the cfg width
+	 * If MSEL[3] = 1, cfg width = 32 bit
+	 */
+	if (msel & 0x8) {
+		setbits_le32(&fpgamgr_regs->ctrl,
+			     FPGAMGRREGS_CTRL_CFGWDTH_MASK);
+
+		/* To determine the CD ratio */
+		/* MSEL[1:0] = 0, CD Ratio = 1 */
+		if ((msel & 0x3) == 0x0)
+			fpgamgr_set_cd_ratio(CDRATIO_x1);
+		/* MSEL[1:0] = 1, CD Ratio = 4 */
+		else if ((msel & 0x3) == 0x1)
+			fpgamgr_set_cd_ratio(CDRATIO_x4);
+		/* MSEL[1:0] = 2, CD Ratio = 8 */
+		else if ((msel & 0x3) == 0x2)
+			fpgamgr_set_cd_ratio(CDRATIO_x8);
+
+	} else {	/* MSEL[3] = 0 */
+		clrbits_le32(&fpgamgr_regs->ctrl,
+			     FPGAMGRREGS_CTRL_CFGWDTH_MASK);
+
+		/* To determine the CD ratio */
+		/* MSEL[1:0] = 0, CD Ratio = 1 */
+		if ((msel & 0x3) == 0x0)
+			fpgamgr_set_cd_ratio(CDRATIO_x1);
+		/* MSEL[1:0] = 1, CD Ratio = 2 */
+		else if ((msel & 0x3) == 0x1)
+			fpgamgr_set_cd_ratio(CDRATIO_x2);
+		/* MSEL[1:0] = 2, CD Ratio = 4 */
+		else if ((msel & 0x3) == 0x2)
+			fpgamgr_set_cd_ratio(CDRATIO_x4);
+	}
+
+	/* To enable FPGA Manager configuration */
+	clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
+
+	/* To enable FPGA Manager drive over configuration line */
+	setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
+
+	/* Put FPGA into reset phase */
+	setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
+
+	/* (1) wait until FPGA enter reset phase */
+	for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+		if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
+			break;
+	}
+
+	/* If not in reset state, return error */
+	if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
+		puts("FPGA: Could not reset\n");
+		return -1;
+	}
+
+	/* Release FPGA from reset phase */
+	clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
+
+	/* (2) wait until FPGA enter configuration phase */
+	for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+		if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
+			break;
+	}
+
+	/* If not in configuration state, return error */
+	if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
+		puts("FPGA: Could not configure\n");
+		return -2;
+	}
+
+	/* Clear all interrupts in CB Monitor */
+	writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
+
+	/* Enable AXI configuration */
+	setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
+
+	return 0;
+}
+
+/* Write the RBF data to FPGA Manager */
+static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
+{
+	uint32_t src = (uint32_t)rbf_data;
+	uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
+
+	/* Number of loops for 32-byte long copying. */
+	uint32_t loops32 = rbf_size / 32;
+	/* Number of loops for 4-byte long copying + trailing bytes */
+	uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
+
+	asm volatile(
+		"1:	ldmia	%0!,	{r0-r7}\n"
+		"	stmia	%1!,	{r0-r7}\n"
+		"	sub	%1,	#32\n"
+		"	subs	%2,	#1\n"
+		"	bne	1b\n"
+		"2:	ldr	%2,	[%0],	#4\n"
+		"	str	%2,	[%1]\n"
+		"	subs	%3,	#1\n"
+		"	bne	2b\n"
+		: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
+		: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
+}
+
+/* Ensure the FPGA entering config done */
+static int fpgamgr_program_poll_cd(void)
+{
+	const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
+			      FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
+	unsigned long reg, i;
+
+	/* (3) wait until full config done */
+	for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+		reg = readl(&fpgamgr_regs->gpio_ext_porta);
+
+		/* Config error */
+		if (!(reg & mask)) {
+			printf("FPGA: Configuration error.\n");
+			return -3;
+		}
+
+		/* Config done without error */
+		if (reg & mask)
+			break;
+	}
+
+	/* Timeout happened, return error */
+	if (i == FPGA_TIMEOUT_CNT) {
+		printf("FPGA: Timeout waiting for program.\n");
+		return -4;
+	}
+
+	/* Disable AXI configuration */
+	clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
+
+	return 0;
+}
+
+/* Ensure the FPGA entering init phase */
+static int fpgamgr_program_poll_initphase(void)
+{
+	unsigned long i;
+
+	/* Additional clocks for the CB to enter initialization phase */
+	if (fpgamgr_dclkcnt_set(0x4))
+		return -5;
+
+	/* (4) wait until FPGA enter init phase or user mode */
+	for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+		if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
+			break;
+		if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
+			break;
+	}
+
+	/* If not in configuration state, return error */
+	if (i == FPGA_TIMEOUT_CNT)
+		return -6;
+
+	return 0;
+}
+
+/* Ensure the FPGA entering user mode */
+static int fpgamgr_program_poll_usermode(void)
+{
+	unsigned long i;
+
+	/* Additional clocks for the CB to exit initialization phase */
+	if (fpgamgr_dclkcnt_set(0x5000))
+		return -7;
+
+	/* (5) wait until FPGA enter user mode */
+	for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+		if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
+			break;
+	}
+	/* If not in configuration state, return error */
+	if (i == FPGA_TIMEOUT_CNT)
+		return -8;
+
+	/* To release FPGA Manager drive over configuration line */
+	clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
+
+	return 0;
+}
+
+/*
+ * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
+ * Return 0 for sucess, non-zero for error.
+ */
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+	unsigned long status;
+
+	if ((uint32_t)rbf_data & 0x3) {
+		puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
+		return -EINVAL;
+	}
+
+	/* Prior programming the FPGA, all bridges need to be shut off */
+
+	/* Disable all signals from hps peripheral controller to fpga */
+	writel(0, &sysmgr_regs->fpgaintfgrp_module);
+
+	/* Disable all signals from FPGA to HPS SDRAM */
+#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS	0x5080
+	writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
+
+	/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
+	socfpga_bridges_reset(1);
+
+	/* Unmap the bridges from NIC-301 */
+	writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+
+	/* Initialize the FPGA Manager */
+	status = fpgamgr_program_init();
+	if (status)
+		return status;
+
+	/* Write the RBF data to FPGA Manager */
+	fpgamgr_program_write(rbf_data, rbf_size);
+
+	/* Ensure the FPGA entering config done */
+	status = fpgamgr_program_poll_cd();
+	if (status)
+		return status;
+
+	/* Ensure the FPGA entering init phase */
+	status = fpgamgr_program_poll_initphase();
+	if (status)
+		return status;
+
+	/* Ensure the FPGA entering user mode */
+	return fpgamgr_program_poll_usermode();
+}
@@ -119,7 +119,7 @@
  
 	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
 		if (get_timer(start) > timeout) {
-			printf("Timeout on data busy\n");
+			printf("%s: Timeout on data busy\n", __func__);
 			return TIMEOUT;
 		}
 	}
  
  
@@ -178,15 +178,23 @@
 	}
  
 	if (i == retry) {
-		printf("dwmci_send_cmd: timeout..\n");
+		printf("%s: Timeout.\n", __func__);
 		return TIMEOUT;
 	}
  
 	if (mask & DWMCI_INTMSK_RTO) {
-		printf("dwmci_send_cmd: Response Timeout..\n");
+		/*
+		 * Timeout here is not necessarily fatal. (e)MMC cards
+		 * will splat here when they receive CMD55 as they do
+		 * not support this command and that is exactly the way
+		 * to tell them apart from SD cards. Thus, this output
+		 * below shall be debug(). eMMC cards also do not favor
+		 * CMD8, please keep that in mind.
+		 */
+		debug("%s: Response Timeout.\n", __func__);
 		return TIMEOUT;
 	} else if (mask & DWMCI_INTMSK_RE) {
-		printf("dwmci_send_cmd: Response Error..\n");
+		printf("%s: Response Error.\n", __func__);
 		return -1;
 	}
  
@@ -206,7 +214,7 @@
 		do {
 			mask = dwmci_readl(host, DWMCI_RINTSTS);
 			if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
-				printf("dwmci_send_cmd: DATA ERROR!\n");
+				printf("%s: DATA ERROR!\n", __func__);
 				return -1;
 			}
 		} while (!(mask & DWMCI_INTMSK_DTO));
@@ -243,7 +251,7 @@
 	else if (host->bus_hz)
 		sclk = host->bus_hz;
 	else {
-		printf("dwmci_setup_bus: Didn't get source clock value..\n");
+		printf("%s: Didn't get source clock value.\n", __func__);
 		return -EINVAL;
 	}
  
@@ -262,7 +270,7 @@
 	do {
 		status = dwmci_readl(host, DWMCI_CMD);
 		if (timeout-- < 0) {
-			printf("dwmci_setup_bus: timeout!\n");
+			printf("%s: Timeout!\n", __func__);
 			return -ETIMEDOUT;
 		}
 	} while (status & DWMCI_CMD_START);
@@ -277,7 +285,7 @@
 	do {
 		status = dwmci_readl(host, DWMCI_CMD);
 		if (timeout-- < 0) {
-			printf("dwmci_setup_bus: timeout!\n");
+			printf("%s: Timeout!\n", __func__);
 			return -ETIMEDOUT;
 		}
 	} while (status & DWMCI_CMD_START);
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <dwmmc.h>
+#include <errno.h>
 #include <asm/arch/dwmmc.h>
 #include <asm/arch/clock_manager.h>
 #include <asm/arch/system_manager.h>
  
  
  
@@ -44,12 +45,18 @@
 int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
 {
 	struct dwmci_host *host;
+	unsigned long clk = cm_get_mmc_controller_clk_hz();
  
+	if (clk == 0) {
+		printf("%s: MMC clock is zero!", __func__);
+		return -EINVAL;
+	}
+
 	/* calloc for zero init */
-	host = calloc(sizeof(struct dwmci_host), 1);
+	host = calloc(1, sizeof(struct dwmci_host));
 	if (!host) {
-		printf("dwmci_host calloc fail!\n");
-		return -1;
+		printf("%s: calloc() failed!\n", __func__);
+		return -ENOMEM;
 	}
  
 	host->name = "SOCFPGA DWMMC";
@@ -58,7 +65,7 @@
 	host->clksel = socfpga_dwmci_clksel;
 	host->dev_index = index;
 	/* fixed clock divide by 4 which due to the SDMMC wrapper */
-	host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ;
+	host->bus_hz = clk;
 	host->fifoth_val = MSIZE(0x2) |
 		RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) |
 		TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2);
@@ -279,19 +279,21 @@
 	struct eth_dma_regs *dma_p = priv->dma_regs_p;
 	u32 desc_num = priv->tx_currdescnum;
 	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
-
+	uint32_t desc_start = (uint32_t)desc_p;
+	uint32_t desc_end = desc_start +
+		roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
+	uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
+	uint32_t data_end = data_start +
+		roundup(length, ARCH_DMA_MINALIGN);
 	/*
 	 * Strictly we only need to invalidate the "txrx_status" field
 	 * for the following check, but on some platforms we cannot
-	 * invalidate only 4 bytes, so roundup to
-	 * ARCH_DMA_MINALIGN. This is safe because the individual
-	 * descriptors in the array are each aligned to
-	 * ARCH_DMA_MINALIGN.
+	 * invalidate only 4 bytes, so we flush the entire descriptor,
+	 * which is 16 bytes in total. This is safe because the
+	 * individual descriptors in the array are each aligned to
+	 * ARCH_DMA_MINALIGN and padded appropriately.
 	 */
-	invalidate_dcache_range(
-		(unsigned long)desc_p,
-		(unsigned long)desc_p +
-		roundup(sizeof(desc_p->txrx_status), ARCH_DMA_MINALIGN));
+	invalidate_dcache_range(desc_start, desc_end);
  
 	/* Check if the descriptor is owned by CPU */
 	if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
  
@@ -299,11 +301,10 @@
 		return -1;
 	}
  
-	memcpy((void *)desc_p->dmamac_addr, packet, length);
+	memcpy(desc_p->dmamac_addr, packet, length);
  
 	/* Flush data to be sent */
-	flush_dcache_range((unsigned long)desc_p->dmamac_addr,
-			   (unsigned long)desc_p->dmamac_addr + length);
+	flush_dcache_range(data_start, data_end);
  
 #if defined(CONFIG_DW_ALTDESCRIPTOR)
 	desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
@@ -321,8 +322,7 @@
 #endif
  
 	/* Flush modified buffer descriptor */
-	flush_dcache_range((unsigned long)desc_p,
-			   (unsigned long)desc_p + sizeof(struct dmamacdescr));
+	flush_dcache_range(desc_start, desc_end);
  
 	/* Test the wrap-around condition. */
 	if (++desc_num >= CONFIG_TX_DESCR_NUM)
  
@@ -342,11 +342,14 @@
 	u32 status, desc_num = priv->rx_currdescnum;
 	struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
 	int length = 0;
+	uint32_t desc_start = (uint32_t)desc_p;
+	uint32_t desc_end = desc_start +
+		roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
+	uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
+	uint32_t data_end;
  
 	/* Invalidate entire buffer descriptor */
-	invalidate_dcache_range((unsigned long)desc_p,
-				(unsigned long)desc_p +
-				sizeof(struct dmamacdescr));
+	invalidate_dcache_range(desc_start, desc_end);
  
 	status = desc_p->txrx_status;
  
@@ -357,9 +360,8 @@
 			 DESC_RXSTS_FRMLENSHFT;
  
 		/* Invalidate received data */
-		invalidate_dcache_range((unsigned long)desc_p->dmamac_addr,
-					(unsigned long)desc_p->dmamac_addr +
-					roundup(length, ARCH_DMA_MINALIGN));
+		data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
+		invalidate_dcache_range(data_start, data_end);
  
 		NetReceive(desc_p->dmamac_addr, length);
  
@@ -370,9 +372,7 @@
 		desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
  
 		/* Flush only status field - others weren't changed */
-		flush_dcache_range((unsigned long)&desc_p->txrx_status,
-				   (unsigned long)&desc_p->txrx_status +
-				   sizeof(desc_p->txrx_status));
+		flush_dcache_range(desc_start, desc_end);
  
 		/* Test the wrap-around condition. */
 		if (++desc_num >= CONFIG_RX_DESCR_NUM)
@@ -25,8 +25,7 @@
 #ifndef CONFIG_PHY_MICREL_KSZ9021
 /*
  * I can't believe Micrel used the exact same part number
- * for the KSZ9021
- * Shame Micrel, Shame!!!!!
+ * for the KSZ9021. Shame Micrel, Shame!
  */
 static struct phy_driver KS8721_driver = {
 	.name = "Micrel KS8721BL",
@@ -40,7 +39,7 @@
 #endif
  
  
-/**
+/*
  * KSZ9021 - KSZ9031 common
  */
  
  
@@ -69,8 +68,8 @@
 		phydev->speed = SPEED_10;
 	return 0;
 }
-#ifdef CONFIG_PHY_MICREL_KSZ9021
  
+#ifdef CONFIG_PHY_MICREL_KSZ9021
 /*
  * KSZ9021
  */
@@ -10,36 +10,60 @@
 #ifndef _ALTERA_H_
 #define _ALTERA_H_
  
-typedef enum {				/* typedef Altera_iface */
-	min_altera_iface_type,		/* insert all new types after this */
-	passive_serial,			/* serial data and external clock */
-	passive_parallel_synchronous,	/* parallel data */
-	passive_parallel_asynchronous,	/* parallel data */
-	passive_serial_asynchronous,	/* serial data w/ internal clock (not used)	*/
-	altera_jtag_mode,		/* jtag/tap serial (not used ) */
-	fast_passive_parallel,		/* fast passive parallel (FPP) */
-	fast_passive_parallel_security,	/* fast passive parallel with security (FPPS) */
-	max_altera_iface_type		/* insert all new types before this */
-} Altera_iface;				/* end, typedef Altera_iface */
+enum altera_iface {
+	/* insert all new types after this */
+	min_altera_iface_type,
+	/* serial data and external clock */
+	passive_serial,
+	/* parallel data */
+	passive_parallel_synchronous,
+	/* parallel data */
+	passive_parallel_asynchronous,
+	/* serial data w/ internal clock (not used) */
+	passive_serial_asynchronous,
+	/* jtag/tap serial (not used ) */
+	altera_jtag_mode,
+	/* fast passive parallel (FPP) */
+	fast_passive_parallel,
+	/* fast passive parallel with security (FPPS) */
+	fast_passive_parallel_security,
+	/* insert all new types before this */
+	max_altera_iface_type,
+};
  
-typedef enum {			/* typedef Altera_Family */
-	min_altera_type,	/* insert all new types after this */
-	Altera_ACEX1K,		/* ACEX1K Family */
-	Altera_CYC2,		/* CYCLONII Family */
-	Altera_StratixII,	/* StratixII Family */
-/* Add new models here */
-	max_altera_type		/* insert all new types before this */
-} Altera_Family;		/* end, typedef Altera_Family */
+enum altera_family {
+	/* insert all new types after this */
+	min_altera_type,
+	/* ACEX1K Family */
+	Altera_ACEX1K,
+	/* CYCLONII Family */
+	Altera_CYC2,
+	/* StratixII Family */
+	Altera_StratixII,
+	/* SoCFPGA Family */
+	Altera_SoCFPGA,
  
-typedef struct {		/* typedef Altera_desc */
-	Altera_Family	family;	/* part type */
-	Altera_iface	iface;	/* interface type */
-	size_t		size;	/* bytes of data part can accept */
-	void *		iface_fns;/* interface function table */
-	void *		base;	/* base interface address */
-	int		cookie;	/* implementation specific cookie */
-} Altera_desc;			/* end, typedef Altera_desc */
+	/* Add new models here */
  
+	/* insert all new types before this */
+	max_altera_type,
+};
+
+typedef struct {
+	/* part type */
+	enum altera_family	family;
+	/* interface type */
+	enum altera_iface	iface;
+	/* bytes of data part can accept */
+	size_t			size;
+	/* interface function table */
+	void			*iface_fns;
+	/* base interface address */
+	void			*base;
+	/* implementation specific cookie */
+	int			cookie;
+} Altera_desc;
+
 /* Generic Altera Functions
  *********************************************************************/
 extern int altera_load(Altera_desc *desc, const void *image, size_t size);
@@ -68,6 +92,10 @@
 	Altera_abort_fn abort;
 	Altera_post_fn post;
 } altera_board_specific_func;
+
+#ifdef CONFIG_FPGA_SOCFPGA
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+#endif
  
 #endif /* _ALTERA_H_ */
@@ -125,7 +125,6 @@
  */
 #define CONFIG_DESIGNWARE_ETH
 #define CONFIG_DW_AUTONEG
-#define CONFIG_DW_SEARCH_PHY
 #define CONFIG_NET_MULTI
  
 /*
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Virtual target or real hardware */
+#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
+
+#define CONFIG_ARMV7
+#define CONFIG_SYS_THUMB_BUILD
+
+#define CONFIG_SOCFPGA
+
+/*
+ * High level configuration
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CLOCKS
+
+#define CONFIG_FIT
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_BOOTMAPSZ		(64 * 1024 * 1024)
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x0
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
+#define CONFIG_SYS_INIT_SP_ADDR					\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE -	\
+	GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TEXT_BASE		0x08000040
+#else
+#define CONFIG_SYS_TEXT_BASE		0x01000040
+#endif
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
+#define CONFIG_CMDLINE_EDITING			/* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Cache
+ */
+#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
+
+/*
+ * Ethernet on SoC (EMAC)
+ */
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_NET_MULTI
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_MII
+#define CONFIG_AUTONEG_TIMEOUT		(15 * CONFIG_SYS_HZ)
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_GIGE
+#endif
+
+/*
+ * FPGA Driver
+ */
+#ifdef CONFIG_CMD_FPGA
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_SOCFPGA
+#define CONFIG_FPGA_COUNT		1
+#endif
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TIMER_RATE		2400000
+#else
+#define CONFIG_SYS_TIMER_RATE		25000000
+#endif
+
+/*
+ * L4 Watchdog
+ */
+#ifdef CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+#define CONFIG_DW_WDT_CLOCK_KHZ		25000
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	12000
+#endif
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH	1024
+#define CONFIG_SOCFPGA_DWMMC_DRVSEL	3
+#define CONFIG_SOCFPGA_DWMMC_SMPSEL	0
+/* FIXME */
+/* using smaller max blk cnt to avoid flooding the limited stack we have */
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
+#endif
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_NS16550_CLK		1000000
+#else
+#define CONFIG_SYS_NS16550_CLK		100000000
+#endif
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * U-Boot environment
+ */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			4096
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
+#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)	/* FIXME */
+#define CONFIG_SYS_SPL_MALLOC_START	((unsigned long) (&__malloc_start))
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(&__malloc_end - &__malloc_start)
+
+#define CHUNKSZ_CRC32			(1 * 1024)	/* FIXME: ewww */
+#define CONFIG_CRC32_VERIFY
+
+/* Linker script for SPL */
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_PARTITIONS
+#endif
+
+#endif	/* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
 /*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
+#define __CONFIG_SOCFPGA_CYCLONE5_H__
  
 #include <asm/arch/socfpga_base_addrs.h>
 #include "../../board/altera/socfpga/pinmux_config.h"
 #include "../../board/altera/socfpga/iocsr_config.h"
 #include "../../board/altera/socfpga/pll_config.h"
  
-/*
- * High level configuration
- */
-/* Virtual target or real hardware */
-#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
  
-#define CONFIG_ARMV7
-#define CONFIG_SYS_DCACHE_OFF
-#undef CONFIG_USE_IRQ
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
  
-#define CONFIG_MISC_INIT_R
-#define CONFIG_SINGLE_BOOTLOADER
-#define CONFIG_SOCFPGA
+#define CONFIG_REGEX			/* Enable regular expression support */
  
-/* base address for .text section */
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"zImage"
+#define CONFIG_BOOTARGS		"console=ttyS0" __stringify(CONFIG_BAUDRATE)
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TEXT_BASE		0x08000040
+#define CONFIG_BOOTCOMMAND	"run ramboot"
 #else
-#define CONFIG_SYS_TEXT_BASE		0x01000040
+#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
 #endif
-#define CONFIG_SYS_LOAD_ADDR		0x7fc0
+#define CONFIG_LOADADDR		0x8000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
  
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE		256
-/* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT		"SOCFPGA_CYCLONE5 # "
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_EMAC_BASE		SOCFPGA_EMAC0_ADDRESS
+#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
+#define CONFIG_EPHY0_PHY_ADDR		0
  
-/*
- * Display CPU and Board Info
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+/* PHY */
+#define CONFIG_EPHY1_PHY_ADDR		4
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0
  
-/*
- * Enable early stage initialization at C environment
- */
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/* flat device tree */
-#define CONFIG_OF_LIBFDT
-/* skip updating the FDT blob */
-#define CONFIG_FDT_BLOB_SKIP_UPDATE
-/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
-#define CONFIG_SYS_BOOTMAPSZ		((256*1024*1024) - (4*1024))
-
-#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
-#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
-
-/*
- * Memory allocation (MALLOC)
- */
-/* Room required on the stack for the environment data */
-#define CONFIG_ENV_SIZE			1024
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-
-/* SP location before relocation, must use scratch RAM */
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
-/* Reserving 0x100 space at back of scratch RAM for debug info */
-#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
-/* Stack pointer prior relocation, must situated at on-chip RAM */
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
-/* FAT file system support */
-#define CONFIG_CMD_FAT
-
-
-/*
- * Misc
- */
-#define CONFIG_DOS_PARTITION            1
-
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_PARTITIONS
 #endif
  
-/*
- * Environment setup
- */
+/* Extra Environment */
+#define CONFIG_HOSTNAME		socfpga_cyclone5
  
-/* Delay before automatically booting the default image */
-#define CONFIG_BOOTDELAY		3
-/* Enable auto completion of commands using TAB */
-#define CONFIG_AUTO_COMPLETE
-/* use "hush" command parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#define CONFIG_CMD_RUN
-
-#define CONFIG_BOOTCOMMAND "run ramboot"
-
-/*
- * arguments passed to the bootm command. The value of
- * CONFIG_BOOTARGS goes into the environment value "bootargs".
- * Do note the value will overide also the chosen node in FDT blob.
- */
-#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
 	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
 		"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"bootimage=uImageImage\0" \" \
+	"bootimage=zImageImage\0" \" \
 	"fdt_addr=100\0" \
-	"fsloadcmd=ext2load\0" \
-		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"fdtimage=socfpga.dtb\0" \
+		"fsloadcmd=ext2load\0" \
+	"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootimage};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
 	"qspiroot=/dev/mtdblock0\0" \
 	"qspirootfstype=jffs2\0" \
 	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
 		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
 		"bootm ${loadaddr} - ${fdt_addr}\0"
  
-/* using environment setting for stdin, stdout, stderr */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-/* Enable the call to overwrite_console() */
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-/* Enable overwrite of previous console environment settings */
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
  
-/* max number of command args	 */
-#define CONFIG_SYS_MAXARGS		16
-
-
-/*
- * Hardware drivers
- */
-
-/*
- * SDRAM Memory Map
- */
-/* We have 1 bank of DRAM */
-#define CONFIG_NR_DRAM_BANKS		1
-/* SDRAM Bank #1 */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE		0x40000000
-
-#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_START	0x00000000
-#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
-
-/*
- * NS16550 Configuration
- */
-#define UART0_BASE			SOCFPGA_UART0_ADDRESS
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
-#define CONFIG_CONS_INDEX               1
-#define CONFIG_SYS_NS16550_COM1		UART0_BASE
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define V_NS16550_CLK			1000000
-#else
-#define V_NS16550_CLK			100000000
-#endif
-#define CONFIG_BAUDRATE			115200
-
-/*
- * FLASH
- */
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * L4 OSC1 Timer 0
- */
-/* This timer use eosc1 where the clock frequency is fixed
- * throughout any condition */
-#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
-/* reload value when timer count to zero */
-#define TIMER_LOAD_VAL			0xFFFFFFFF
-/* Timer info */
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TIMER_RATE		2400000
-#else
-#define CONFIG_SYS_TIMER_RATE		25000000
-#endif
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
-
-#define CONFIG_ENV_IS_NOWHERE
-
-/*
- * network support
- */
-#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_DESIGNWARE_ETH          1
-#endif
-
-#ifdef CONFIG_DESIGNWARE_ETH
-#define CONFIG_EMAC0_BASE              SOCFPGA_EMAC0_ADDRESS
-#define CONFIG_EMAC1_BASE              SOCFPGA_EMAC1_ADDRESS
-/* console support for network */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-/* designware */
-#define CONFIG_NET_MULTI
-#define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_DW_SEARCH_PHY
-#define CONFIG_MII
-#define CONFIG_PHY_GIGE
-#define CONFIG_DW_AUTONEG
-#define CONFIG_AUTONEG_TIMEOUT         (15 * CONFIG_SYS_HZ)
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
-/* EMAC controller and PHY used */
-#define CONFIG_EMAC_BASE               CONFIG_EMAC1_BASE
-#define CONFIG_EPHY_PHY_ADDR           CONFIG_EPHY1_PHY_ADDR
-#define CONFIG_PHY_INTERFACE_MODE      PHY_INTERFACE_MODE_RGMII
-#endif /* CONFIG_DESIGNWARE_ETH */
-
-/*
- * L4 Watchdog
- */
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	2000
-#define CONFIG_DESIGNWARE_WATCHDOG
-#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
-/* Clocks source frequency to watchdog timer */
-#define CONFIG_DW_WDT_CLOCK_KHZ		25000
-
-
-/*
- * SPL "Second Program Loader" aka Initial Software
- */
-
-/* Enable building of SPL globally */
-#define CONFIG_SPL_FRAMEWORK
-
-/* TEXT_BASE for linking the SPL binary */
-#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
-
-/* Stack size for SPL */
-#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
-
-/* MALLOC size for SPL */
-#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)
-
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_BOARD_INIT
-
-#define CHUNKSZ_CRC32			(1 * 1024)
-
-#define CONFIG_CRC32_VERIFY
-
-/* Linker script for SPL */
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
-
-/* Support for common/libcommon.o in SPL binary */
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-/* Support for lib/libgeneric.o in SPL binary */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-
-/* Support for watchdog */
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-
-#endif	/* __CONFIG_H */
+#endif	/* __CONFIG_SOCFPGA_CYCLONE5_H__ */
@@ -157,7 +157,7 @@
 	u32 cnt;
 	u32 addr;
 	u32 next_addr;
-};
+} __aligned(ARCH_DMA_MINALIGN);
  
 static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
 {
@@ -232,6 +232,7 @@
 #define IH_TYPE_MXSIMAGE	16	/* Freescale MXSBoot Image	*/
 #define IH_TYPE_GPIMAGE		17	/* TI Keystone GPHeader Image	*/
 #define IH_TYPE_ATMELIMAGE	18	/* ATMEL ROM bootable Image	*/
+#define IH_TYPE_SOCFPGAIMAGE	19	/* Altera SOCFPGA Preloader	*/
  
 /*
  * Compression Types
@@ -87,6 +87,7 @@
 			os_support.o \
 			pblimage.o \
 			pbl_crc32.o \
+			socfpgaimage.o \
 			lib/sha1.o \
 			lib/sha256.o \
 			ublimage.o \
@@ -47,6 +47,8 @@
 	init_ubl_image_type();
 	/* Init Davinci AIS support */
 	init_ais_image_type();
+	/* Init Altera SOCFPGA support */
+	init_socfpga_image_type();
 	/* Init TI Keystone boot image generation/list support */
 	init_gpimage_type();
 }
@@ -168,6 +168,7 @@
 void init_fit_image_type(void);
 void init_ubl_image_type(void);
 void init_omap_image_type(void);
+void init_socfpga_image_type(void);
 void init_gpimage_type(void);
  
 void pbl_load_uboot(int fd, struct image_tool_params *mparams);
+/*
+ * Copyright (C) 2014 Charles Manning <cdhmanning@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Reference doc http://www.altera.com.cn/literature/hb/cyclone-v/cv_5400A.pdf
+ * Note this doc is not entirely accurate. Of particular interest to us is the
+ * "header" length field being in U32s and not bytes.
+ *
+ * "Header" is a structure of the following format.
+ * this is positioned at 0x40.
+ *
+ * Endian is LSB.
+ *
+ * Offset   Length   Usage
+ * -----------------------
+ *   0x40        4   Validation word 0x31305341
+ *   0x44        1   Version (whatever, zero is fine)
+ *   0x45        1   Flags   (unused, zero is fine)
+ *   0x46        2   Length  (in units of u32, including the end checksum).
+ *   0x48        2   Zero
+ *   0x4A        2   Checksum over the header. NB Not CRC32
+ *
+ * At the end of the code we have a 32-bit CRC checksum over whole binary
+ * excluding the CRC.
+ *
+ * Note that the CRC used here is **not** the zlib/Adler crc32. It is the
+ * CRC-32 used in bzip2, ethernet and elsewhere.
+ *
+ * The image is padded out to 64k, because that is what is
+ * typically used to write the image to the boot medium.
+ */
+
+#include "pbl_crc32.h"
+#include "imagetool.h"
+#include <image.h>
+
+#define HEADER_OFFSET	0x40
+#define VALIDATION_WORD	0x31305341
+#define PADDED_SIZE	0x10000
+
+/* To allow for adding CRC, the max input size is a bit smaller. */
+#define MAX_INPUT_SIZE	(PADDED_SIZE - sizeof(uint32_t))
+
+static uint8_t buffer[PADDED_SIZE];
+
+static struct socfpga_header {
+	uint32_t validation;
+	uint8_t  version;
+	uint8_t  flags;
+	uint16_t length_u32;
+	uint16_t zero;
+	uint16_t checksum;
+} header;
+
+/*
+ * The header checksum is just a very simple checksum over
+ * the header area.
+ * There is still a crc32 over the whole lot.
+ */
+static uint16_t hdr_checksum(struct socfpga_header *header)
+{
+	int len = sizeof(*header) - sizeof(header->checksum);
+	uint8_t *buf = (uint8_t *)header;
+	uint16_t ret = 0;
+
+	while (--len)
+		ret += *buf++;
+
+	return ret;
+}
+
+
+static void build_header(uint8_t *buf, uint8_t version, uint8_t flags,
+			 uint16_t length_bytes)
+{
+	header.validation = htole32(VALIDATION_WORD);
+	header.version = version;
+	header.flags = flags;
+	header.length_u32 = htole16(length_bytes/4);
+	header.zero = 0;
+	header.checksum = htole16(hdr_checksum(&header));
+
+	memcpy(buf, &header, sizeof(header));
+}
+
+/*
+ * Perform a rudimentary verification of header and return
+ * size of image.
+ */
+static int verify_header(const uint8_t *buf)
+{
+	memcpy(&header, buf, sizeof(header));
+
+	if (le32toh(header.validation) != VALIDATION_WORD)
+		return -1;
+	if (le16toh(header.checksum) != hdr_checksum(&header))
+		return -1;
+
+	return le16toh(header.length_u32) * 4;
+}
+
+/* Sign the buffer and return the signed buffer size */
+static int sign_buffer(uint8_t *buf,
+			uint8_t version, uint8_t flags,
+			int len, int pad_64k)
+{
+	uint32_t calc_crc;
+
+	/* Align the length up */
+	len = (len + 3) & (~3);
+
+	/* Build header, adding 4 bytes to length to hold the CRC32. */
+	build_header(buf + HEADER_OFFSET,  version, flags, len + 4);
+
+	/* Calculate and apply the CRC */
+	calc_crc = ~pbl_crc32(0, (char *)buf, len);
+
+	*((uint32_t *)(buf + len)) = htole32(calc_crc);
+
+	if (!pad_64k)
+		return len + 4;
+
+	return PADDED_SIZE;
+}
+
+/* Verify that the buffer looks sane */
+static int verify_buffer(const uint8_t *buf)
+{
+	int len; /* Including 32bit CRC */
+	uint32_t calc_crc;
+	uint32_t buf_crc;
+
+	len = verify_header(buf + HEADER_OFFSET);
+	if (len < 0) {
+		fprintf(stderr, "Invalid header\n");
+		return -1;
+	}
+
+	if (len < HEADER_OFFSET || len > PADDED_SIZE) {
+		fprintf(stderr, "Invalid header length (%i)\n", len);
+		return -1;
+	}
+
+	/*
+	 * Adjust length to the base of the CRC.
+	 * Check the CRC.
+	*/
+	len -= 4;
+
+	calc_crc = ~pbl_crc32(0, (const char *)buf, len);
+
+	buf_crc = le32toh(*((uint32_t *)(buf + len)));
+
+	if (buf_crc != calc_crc) {
+		fprintf(stderr, "CRC32 does not match (%08x != %08x)\n",
+			buf_crc, calc_crc);
+		return -1;
+	}
+
+	return 0;
+}
+
+/* mkimage glue functions */
+static int socfpgaimage_verify_header(unsigned char *ptr, int image_size,
+			struct image_tool_params *params)
+{
+	if (image_size != PADDED_SIZE)
+		return -1;
+
+	return verify_buffer(ptr);
+}
+
+static void socfpgaimage_print_header(const void *ptr)
+{
+	if (verify_buffer(ptr) == 0)
+		printf("Looks like a sane SOCFPGA preloader\n");
+	else
+		printf("Not a sane SOCFPGA preloader\n");
+}
+
+static int socfpgaimage_check_params(struct image_tool_params *params)
+{
+	/* Not sure if we should be accepting fflags */
+	return	(params->dflag && (params->fflag || params->lflag)) ||
+		(params->fflag && (params->dflag || params->lflag)) ||
+		(params->lflag && (params->dflag || params->fflag));
+}
+
+static int socfpgaimage_check_image_types(uint8_t type)
+{
+	if (type == IH_TYPE_SOCFPGAIMAGE)
+		return EXIT_SUCCESS;
+	return EXIT_FAILURE;
+}
+
+/*
+ * To work in with the mkimage framework, we do some ugly stuff...
+ *
+ * First, socfpgaimage_vrec_header() is called.
+ * We prepend a fake header big enough to make the file PADDED_SIZE.
+ * This gives us enough space to do what we want later.
+ *
+ * Next, socfpgaimage_set_header() is called.
+ * We fix up the buffer by moving the image to the start of the buffer.
+ * We now have some room to do what we need (add CRC and padding).
+ */
+
+static int data_size;
+#define FAKE_HEADER_SIZE (PADDED_SIZE - data_size)
+
+static int socfpgaimage_vrec_header(struct image_tool_params *params,
+				struct image_type_params *tparams)
+{
+	struct stat sbuf;
+
+	if (params->datafile &&
+	    stat(params->datafile, &sbuf) == 0 &&
+	    sbuf.st_size <= MAX_INPUT_SIZE) {
+		data_size = sbuf.st_size;
+		tparams->header_size = FAKE_HEADER_SIZE;
+	}
+	return 0;
+}
+
+static void socfpgaimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+				struct image_tool_params *params)
+{
+	uint8_t *buf = (uint8_t *)ptr;
+
+	/*
+	 * This function is called after vrec_header() has been called.
+	 * At this stage we have the FAKE_HEADER_SIZE dummy bytes followed by
+	 * data_size image bytes. Total = PADDED_SIZE.
+	 * We need to fix the buffer by moving the image bytes back to
+	 * the beginning of the buffer, then actually do the signing stuff...
+	 */
+	memmove(buf, buf + FAKE_HEADER_SIZE, data_size);
+	memset(buf + data_size, 0, FAKE_HEADER_SIZE);
+
+	sign_buffer(buf, 0, 0, data_size, 0);
+}
+
+static struct image_type_params socfpgaimage_params = {
+	.name		= "Altera SOCFPGA preloader support",
+	.vrec_header	= socfpgaimage_vrec_header,
+	.header_size	= 0, /* This will be modified by vrec_header() */
+	.hdr		= (void *)buffer,
+	.check_image_type = socfpgaimage_check_image_types,
+	.verify_header	= socfpgaimage_verify_header,
+	.print_header	= socfpgaimage_print_header,
+	.set_header	= socfpgaimage_set_header,
+	.check_params	= socfpgaimage_check_params,
+};
+
+void init_socfpga_image_type(void)
+{
+	register_image_type(&socfpgaimage_params);
+}
...	...	@@ -8,6 +8,7 @@
8	8	#
9	9
10	10	obj-y := lowlevel_init.o
11		-obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o
	11	+obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
	12	+ fpga_manager.o
12	13	obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
...	...	@@ -8,38 +8,28 @@
8	8	#include <asm/io.h>
9	9	#include <asm/arch/clock_manager.h>
10	10
	11	+DECLARE_GLOBAL_DATA_PTR;
	12	+
11	13	static const struct socfpga_clock_manager *clock_manager_base =
12		- (void *)SOCFPGA_CLKMGR_ADDRESS;
	14	+ (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
13	15
14		-#define CLKMGR_BYPASS_ENABLE 1
15		-#define CLKMGR_BYPASS_DISABLE 0
16		-#define CLKMGR_STAT_IDLE 0
17		-#define CLKMGR_STAT_BUSY 1
18		-#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
19		-#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
20		-#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
21		-#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
22		-
23		-#define CLEAR_BGP_EN_PWRDN \
24		- (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)\| \
25		- CLKMGR_MAINPLLGRP_VCO_EN_SET(0)\| \
26		- CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
27		-
28		-#define VCO_EN_BASE \
29		- (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)\| \
30		- CLKMGR_MAINPLLGRP_VCO_EN_SET(1)\| \
31		- CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
32		-
33		-static inline void cm_wait_for_lock(uint32_t mask)
	16	+static void cm_wait_for_lock(uint32_t mask)
34	17	{
35	18	register uint32_t inter_val;
	19	+ uint32_t retry = 0;
36	20	do {
37	21	inter_val = readl(&clock_manager_base->inter) & mask;
38		- } while (inter_val != mask);
	22	+ if (inter_val == mask)
	23	+ retry++;
	24	+ else
	25	+ retry = 0;
	26	+ if (retry >= 10)
	27	+ break;
	28	+ } while (1);
39	29	}
40	30
41	31	/* function to poll in the fsm busy bit */
42		-static inline void cm_wait_for_fsm(void)
	32	+static void cm_wait_for_fsm(void)
43	33	{
44	34	while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
45	35	;
46	36
47	37
...	...	@@ -49,22 +39,22 @@
49	39	* function to write the bypass register which requires a poll of the
50	40	* busy bit
51	41	*/
52		-static inline void cm_write_bypass(uint32_t val)
	42	+static void cm_write_bypass(uint32_t val)
53	43	{
54	44	writel(val, &clock_manager_base->bypass);
55	45	cm_wait_for_fsm();
56	46	}
57	47
58	48	/* function to write the ctrl register which requires a poll of the busy bit */
59		-static inline void cm_write_ctrl(uint32_t val)
	49	+static void cm_write_ctrl(uint32_t val)
60	50	{
61	51	writel(val, &clock_manager_base->ctrl);
62	52	cm_wait_for_fsm();
63	53	}
64	54
65	55	/* function to write a clock register that has phase information */
66		-static inline void cm_write_with_phase(uint32_t value,
67		- uint32_t reg_address, uint32_t mask)
	56	+static void cm_write_with_phase(uint32_t value,
	57	+ uint32_t reg_address, uint32_t mask)
68	58	{
69	59	/* poll until phase is zero */
70	60	while (readl(reg_address) & mask)
71	61
72	62
73	63
...	...	@@ -128,24 +118,18 @@
128	118	writel(0, &clock_manager_base->per_pll.en);
129	119
130	120	/* Put all plls in bypass */
131		- cm_write_bypass(
132		- CLKMGR_BYPASS_PERPLLSRC_SET(
133		- CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) \|
134		- CLKMGR_BYPASS_SDRPLLSRC_SET(
135		- CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) \|
136		- CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) \|
137		- CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) \|
138		- CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
	121	+ cm_write_bypass(CLKMGR_BYPASS_PERPLL \| CLKMGR_BYPASS_SDRPLL \|
	122	+ CLKMGR_BYPASS_MAINPLL);
139	123
140		- /*
141		- * Put all plls VCO registers back to reset value.
142		- * Some code might have messed with them.
143		- */
144		- writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
	124	+ /* Put all plls VCO registers back to reset value. */
	125	+ writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
	126	+ ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
145	127	&clock_manager_base->main_pll.vco);
146		- writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
	128	+ writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
	129	+ ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
147	130	&clock_manager_base->per_pll.vco);
148		- writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
	131	+ writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
	132	+ ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
149	133	&clock_manager_base->sdr_pll.vco);
150	134
151	135	/*
152	136
...	...	@@ -170,20 +154,10 @@
170	154	* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
171	155	* with numerator and denominator.
172	156	*/
173		- writel(cfg->main_vco_base \| CLEAR_BGP_EN_PWRDN \|
174		- CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
175		- &clock_manager_base->main_pll.vco);
	157	+ writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
	158	+ writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
	159	+ writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
176	160
177		- writel(cfg->peri_vco_base \| CLEAR_BGP_EN_PWRDN \|
178		- CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
179		- &clock_manager_base->per_pll.vco);
180		-
181		- writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) \|
182		- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) \|
183		- cfg->sdram_vco_base \| CLEAR_BGP_EN_PWRDN \|
184		- CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
185		- &clock_manager_base->sdr_pll.vco);
186		-
187	161	/*
188	162	* Time starts here
189	163	* must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
...	...	@@ -217,6 +191,9 @@
217	191	writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
218	192
219	193	/* Peri pernandsdmmcclk */
	194	+ writel(cfg->mainnandsdmmcclk,
	195	+ &clock_manager_base->main_pll.mainnandsdmmcclk);
	196	+
220	197	writel(cfg->pernandsdmmcclk,
221	198	&clock_manager_base->per_pll.pernandsdmmcclk);
222	199
223	200
224	201
...	...	@@ -232,18 +209,16 @@
232	209
233	210	/* Enable vco */
234	211	/* main pll vco */
235		- writel(cfg->main_vco_base \| VCO_EN_BASE,
	212	+ writel(cfg->main_vco_base \| CLKMGR_MAINPLLGRP_VCO_EN,
236	213	&clock_manager_base->main_pll.vco);
237	214
238	215	/* periferal pll */
239		- writel(cfg->peri_vco_base \| VCO_EN_BASE,
	216	+ writel(cfg->peri_vco_base \| CLKMGR_MAINPLLGRP_VCO_EN,
240	217	&clock_manager_base->per_pll.vco);
241	218
242	219	/* sdram pll vco */
243		- writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) \|
244		- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) \|
245		- cfg->sdram_vco_base \| VCO_EN_BASE,
246		- &clock_manager_base->sdr_pll.vco);
	220	+ writel(cfg->sdram_vco_base \| CLKMGR_MAINPLLGRP_VCO_EN,
	221	+ &clock_manager_base->sdr_pll.vco);
247	222
248	223	/* L3 MP and L3 SP */
249	224	writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
...	...	@@ -294,8 +269,8 @@
294	269	&clock_manager_base->per_pll.vco);
295	270
296	271	/* assert sdram outresetall */
297		- writel(cfg->sdram_vco_base \| VCO_EN_BASE\|
298		- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
	272	+ writel(cfg->sdram_vco_base \| CLKMGR_MAINPLLGRP_VCO_EN\|
	273	+ CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
299	274	&clock_manager_base->sdr_pll.vco);
300	275
301	276	/* deassert main outresetall */
...	...	@@ -307,9 +282,8 @@
307	282	&clock_manager_base->per_pll.vco);
308	283
309	284	/* deassert sdram outresetall */
310		- writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) \|
311		- cfg->sdram_vco_base \| VCO_EN_BASE,
312		- &clock_manager_base->sdr_pll.vco);
	285	+ writel(cfg->sdram_vco_base \| CLKMGR_MAINPLLGRP_VCO_EN,
	286	+ &clock_manager_base->sdr_pll.vco);
313	287
314	288	/*
315	289	* now that we've toggled outreset all, all the clocks
316	290
...	...	@@ -333,18 +307,10 @@
333	307	CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
334	308
335	309	/* Take all three PLLs out of bypass when safe mode is cleared. */
336		- cm_write_bypass(
337		- CLKMGR_BYPASS_PERPLLSRC_SET(
338		- CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) \|
339		- CLKMGR_BYPASS_SDRPLLSRC_SET(
340		- CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) \|
341		- CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) \|
342		- CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) \|
343		- CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
	310	+ cm_write_bypass(0);
344	311
345	312	/* clear safe mode */
346		- cm_write_ctrl(readl(&clock_manager_base->ctrl) \|
347		- CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
	313	+ cm_write_ctrl(readl(&clock_manager_base->ctrl) \| CLKMGR_CTRL_SAFEMODE);
348	314
349	315	/*
350	316	* now that safe mode is clear with clocks gated
351	317
...	...	@@ -357,5 +323,225 @@
357	323	writel(~0, &clock_manager_base->main_pll.en);
358	324	writel(~0, &clock_manager_base->per_pll.en);
359	325	writel(~0, &clock_manager_base->sdr_pll.en);
	326	+
	327	+ /* Clear the loss of lock bits (write 1 to clear) */
	328	+ writel(CLKMGR_INTER_SDRPLLLOST_MASK \| CLKMGR_INTER_PERPLLLOST_MASK \|
	329	+ CLKMGR_INTER_MAINPLLLOST_MASK,
	330	+ &clock_manager_base->inter);
360	331	}
	332	+
	333	+static unsigned int cm_get_main_vco_clk_hz(void)
	334	+{
	335	+ uint32_t reg, clock;
	336	+
	337	+ /* get the main VCO clock */
	338	+ reg = readl(&clock_manager_base->main_pll.vco);
	339	+ clock = CONFIG_HPS_CLK_OSC1_HZ;
	340	+ clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
	341	+ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
	342	+ clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
	343	+ CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
	344	+
	345	+ return clock;
	346	+}
	347	+
	348	+static unsigned int cm_get_per_vco_clk_hz(void)
	349	+{
	350	+ uint32_t reg, clock = 0;
	351	+
	352	+ /* identify PER PLL clock source */
	353	+ reg = readl(&clock_manager_base->per_pll.vco);
	354	+ reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
	355	+ CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
	356	+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
	357	+ clock = CONFIG_HPS_CLK_OSC1_HZ;
	358	+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
	359	+ clock = CONFIG_HPS_CLK_OSC2_HZ;
	360	+ else if (reg == CLKMGR_VCO_SSRC_F2S)
	361	+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
	362	+
	363	+ /* get the PER VCO clock */
	364	+ reg = readl(&clock_manager_base->per_pll.vco);
	365	+ clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
	366	+ CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
	367	+ clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
	368	+ CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
	369	+
	370	+ return clock;
	371	+}
	372	+
	373	+unsigned long cm_get_mpu_clk_hz(void)
	374	+{
	375	+ uint32_t reg, clock;
	376	+
	377	+ clock = cm_get_main_vco_clk_hz();
	378	+
	379	+ /* get the MPU clock */
	380	+ reg = readl(&clock_manager_base->altera.mpuclk);
	381	+ clock /= (reg + 1);
	382	+ reg = readl(&clock_manager_base->main_pll.mpuclk);
	383	+ clock /= (reg + 1);
	384	+ return clock;
	385	+}
	386	+
	387	+unsigned long cm_get_sdram_clk_hz(void)
	388	+{
	389	+ uint32_t reg, clock = 0;
	390	+
	391	+ /* identify SDRAM PLL clock source */
	392	+ reg = readl(&clock_manager_base->sdr_pll.vco);
	393	+ reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
	394	+ CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
	395	+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
	396	+ clock = CONFIG_HPS_CLK_OSC1_HZ;
	397	+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
	398	+ clock = CONFIG_HPS_CLK_OSC2_HZ;
	399	+ else if (reg == CLKMGR_VCO_SSRC_F2S)
	400	+ clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
	401	+
	402	+ /* get the SDRAM VCO clock */
	403	+ reg = readl(&clock_manager_base->sdr_pll.vco);
	404	+ clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
	405	+ CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
	406	+ clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
	407	+ CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
	408	+
	409	+ /* get the SDRAM (DDR_DQS) clock */
	410	+ reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
	411	+ reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
	412	+ CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
	413	+ clock /= (reg + 1);
	414	+
	415	+ return clock;
	416	+}
	417	+
	418	+unsigned int cm_get_l4_sp_clk_hz(void)
	419	+{
	420	+ uint32_t reg, clock = 0;
	421	+
	422	+ /* identify the source of L4 SP clock */
	423	+ reg = readl(&clock_manager_base->main_pll.l4src);
	424	+ reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
	425	+ CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
	426	+
	427	+ if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
	428	+ clock = cm_get_main_vco_clk_hz();
	429	+
	430	+ /* get the clock prior L4 SP divider (main clk) */
	431	+ reg = readl(&clock_manager_base->altera.mainclk);
	432	+ clock /= (reg + 1);
	433	+ reg = readl(&clock_manager_base->main_pll.mainclk);
	434	+ clock /= (reg + 1);
	435	+ } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
	436	+ clock = cm_get_per_vco_clk_hz();
	437	+
	438	+ /* get the clock prior L4 SP divider (periph_base_clk) */
	439	+ reg = readl(&clock_manager_base->per_pll.perbaseclk);
	440	+ clock /= (reg + 1);
	441	+ }
	442	+
	443	+ /* get the L4 SP clock which supplied to UART */
	444	+ reg = readl(&clock_manager_base->main_pll.maindiv);
	445	+ reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
	446	+ CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
	447	+ clock = clock / (1 << reg);
	448	+
	449	+ return clock;
	450	+}
	451	+
	452	+unsigned int cm_get_mmc_controller_clk_hz(void)
	453	+{
	454	+ uint32_t reg, clock = 0;
	455	+
	456	+ /* identify the source of MMC clock */
	457	+ reg = readl(&clock_manager_base->per_pll.src);
	458	+ reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
	459	+ CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
	460	+
	461	+ if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
	462	+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
	463	+ } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
	464	+ clock = cm_get_main_vco_clk_hz();
	465	+
	466	+ /* get the SDMMC clock */
	467	+ reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
	468	+ clock /= (reg + 1);
	469	+ } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
	470	+ clock = cm_get_per_vco_clk_hz();
	471	+
	472	+ /* get the SDMMC clock */
	473	+ reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
	474	+ clock /= (reg + 1);
	475	+ }
	476	+
	477	+ /* further divide by 4 as we have fixed divider at wrapper */
	478	+ clock /= 4;
	479	+ return clock;
	480	+}
	481	+
	482	+unsigned int cm_get_qspi_controller_clk_hz(void)
	483	+{
	484	+ uint32_t reg, clock = 0;
	485	+
	486	+ /* identify the source of QSPI clock */
	487	+ reg = readl(&clock_manager_base->per_pll.src);
	488	+ reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
	489	+ CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
	490	+
	491	+ if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
	492	+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
	493	+ } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
	494	+ clock = cm_get_main_vco_clk_hz();
	495	+
	496	+ /* get the qspi clock */
	497	+ reg = readl(&clock_manager_base->main_pll.mainqspiclk);
	498	+ clock /= (reg + 1);
	499	+ } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
	500	+ clock = cm_get_per_vco_clk_hz();
	501	+
	502	+ /* get the qspi clock */
	503	+ reg = readl(&clock_manager_base->per_pll.perqspiclk);
	504	+ clock /= (reg + 1);
	505	+ }
	506	+
	507	+ return clock;
	508	+}
	509	+
	510	+static void cm_print_clock_quick_summary(void)
	511	+{
	512	+ printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
	513	+ printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
	514	+ printf("EOSC1 %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
	515	+ printf("EOSC2 %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
	516	+ printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
	517	+ printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
	518	+ printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
	519	+ printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
	520	+ printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
	521	+}
	522	+
	523	+int set_cpu_clk_info(void)
	524	+{
	525	+ /* Calculate the clock frequencies required for drivers */
	526	+ cm_get_l4_sp_clk_hz();
	527	+ cm_get_mmc_controller_clk_hz();
	528	+
	529	+ gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
	530	+ gd->bd->bi_dsp_freq = 0;
	531	+ gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
	532	+
	533	+ return 0;
	534	+}
	535	+
	536	+int do_showclocks(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	537	+{
	538	+ cm_print_clock_quick_summary();
	539	+ return 0;
	540	+}
	541	+
	542	+U_BOOT_CMD(
	543	+ clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
	544	+ "display clocks",
	545	+ ""
	546	+);
	1	+/*
	2	+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
	3	+ * All rights reserved.
	4	+ *
	5	+ * This file contains only support functions used also by the SoCFPGA
	6	+ * platform code, the real meat is located in drivers/fpga/socfpga.c .
	7	+ *
	8	+ * SPDX-License-Identifier: BSD-3-Clause
	9	+ */
	10	+
	11	+#include <common.h>
	12	+#include <asm/io.h>
	13	+#include <asm/errno.h>
	14	+#include <asm/arch/fpga_manager.h>
	15	+#include <asm/arch/reset_manager.h>
	16	+#include <asm/arch/system_manager.h>
	17	+
	18	+DECLARE_GLOBAL_DATA_PTR;
	19	+
	20	+/* Timeout count */
	21	+#define FPGA_TIMEOUT_CNT 0x1000000
	22	+
	23	+static struct socfpga_fpga_manager *fpgamgr_regs =
	24	+ (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
	25	+
	26	+/* Check whether FPGA Init_Done signal is high */
	27	+static int is_fpgamgr_initdone_high(void)
	28	+{
	29	+ unsigned long val;
	30	+
	31	+ val = readl(&fpgamgr_regs->gpio_ext_porta);
	32	+ return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
	33	+}
	34	+
	35	+/* Get the FPGA mode */
	36	+int fpgamgr_get_mode(void)
	37	+{
	38	+ unsigned long val;
	39	+
	40	+ val = readl(&fpgamgr_regs->stat);
	41	+ return val & FPGAMGRREGS_STAT_MODE_MASK;
	42	+}
	43	+
	44	+/* Check whether FPGA is ready to be accessed */
	45	+int fpgamgr_test_fpga_ready(void)
	46	+{
	47	+ /* Check for init done signal */
	48	+ if (!is_fpgamgr_initdone_high())
	49	+ return 0;
	50	+
	51	+ /* Check again to avoid false glitches */
	52	+ if (!is_fpgamgr_initdone_high())
	53	+ return 0;
	54	+
	55	+ if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
	56	+ return 0;
	57	+
	58	+ return 1;
	59	+}
	60	+
	61	+/* Poll until FPGA is ready to be accessed or timeout occurred */
	62	+int fpgamgr_poll_fpga_ready(void)
	63	+{
	64	+ unsigned long i;
	65	+
	66	+ /* If FPGA is blank, wait till WD invoke warm reset */
	67	+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
	68	+ /* check for init done signal */
	69	+ if (!is_fpgamgr_initdone_high())
	70	+ continue;
	71	+ /* check again to avoid false glitches */
	72	+ if (!is_fpgamgr_initdone_high())
	73	+ continue;
	74	+ return 1;
	75	+ }
	76	+
	77	+ return 0;
	78	+}
...	...	@@ -6,24 +6,103 @@
6	6
7	7	#include <common.h>
8	8	#include <asm/io.h>
	9	+#include <altera.h>
9	10	#include <miiphy.h>
10	11	#include <netdev.h>
	12	+#include <asm/arch/reset_manager.h>
	13	+#include <asm/arch/system_manager.h>
	14	+#include <asm/arch/dwmmc.h>
	15	+#include <asm/arch/nic301.h>
	16	+#include <asm/arch/scu.h>
	17	+#include <asm/pl310.h>
11	18
12	19	DECLARE_GLOBAL_DATA_PTR;
13	20
	21	+static struct pl310_regs *const pl310 =
	22	+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
	23	+static struct socfpga_system_manager *sysmgr_regs =
	24	+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
	25	+static struct socfpga_reset_manager *reset_manager_base =
	26	+ (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
	27	+static struct nic301_registers *nic301_regs =
	28	+ (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
	29	+static struct scu_registers *scu_regs =
	30	+ (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
	31	+
14	32	int dram_init(void)
15	33	{
16	34	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
17	35	return 0;
18	36	}
19	37
	38	+void enable_caches(void)
	39	+{
	40	+#ifndef CONFIG_SYS_ICACHE_OFF
	41	+ icache_enable();
	42	+#endif
	43	+#ifndef CONFIG_SYS_DCACHE_OFF
	44	+ dcache_enable();
	45	+#endif
	46	+}
	47	+
	48	+/*
	49	+ * DesignWare Ethernet initialization
	50	+ */
	51	+#ifdef CONFIG_DESIGNWARE_ETH
	52	+int cpu_eth_init(bd_t *bis)
	53	+{
	54	+#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
	55	+ const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
	56	+#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
	57	+ const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
	58	+#else
	59	+#error "Incorrect CONFIG_EMAC_BASE value!"
	60	+#endif
	61	+
	62	+ /* Initialize EMAC. This needs to be done at least once per boot. */
	63	+
	64	+ /*
	65	+ * Putting the EMAC controller to reset when configuring the PHY
	66	+ * interface select at System Manager
	67	+ */
	68	+ socfpga_emac_reset(1);
	69	+
	70	+ /* Clearing emac0 PHY interface select to 0 */
	71	+ clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
	72	+ SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
	73	+
	74	+ /* configure to PHY interface select choosed */
	75	+ setbits_le32(&sysmgr_regs->emacgrp_ctrl,
	76	+ SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
	77	+
	78	+ /* Release the EMAC controller from reset */
	79	+ socfpga_emac_reset(0);
	80	+
	81	+ /* initialize and register the emac */
	82	+ return designware_initialize(CONFIG_EMAC_BASE,
	83	+ CONFIG_PHY_INTERFACE_MODE);
	84	+}
	85	+#endif
	86	+
	87	+#ifdef CONFIG_DWMMC
	88	+/*
	89	+ * Initializes MMC controllers.
	90	+ * to override, implement board_mmc_init()
	91	+ */
	92	+int cpu_mmc_init(bd_t *bis)
	93	+{
	94	+ return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
	95	+ CONFIG_HPS_SDMMC_BUSWIDTH, 0);
	96	+}
	97	+#endif
	98	+
20	99	#if defined(CONFIG_DISPLAY_CPUINFO)
21	100	/*
22	101	* Print CPU information
23	102	*/
24	103	int print_cpuinfo(void)
25	104	{
26		- puts("CPU : Altera SOCFPGA Platform\n");
	105	+ puts("CPU: Altera SoCFPGA Platform\n");
27	106	return 0;
28	107	}
29	108	#endif
30	109
31	110
32	111
33	112
34	113
35	114
36	115
37	116
...	...	@@ -36,23 +115,160 @@
36	115	}
37	116	#endif
38	117
39		-int misc_init_r(void)
	118	+#ifdef CONFIG_FPGA
	119	+/*
	120	+ * FPGA programming support for SoC FPGA Cyclone V
	121	+ */
	122	+static Altera_desc altera_fpga[] = {
	123	+ {
	124	+ /* Family */
	125	+ Altera_SoCFPGA,
	126	+ /* Interface type */
	127	+ fast_passive_parallel,
	128	+ /* No limitation as additional data will be ignored */
	129	+ -1,
	130	+ /* No device function table */
	131	+ NULL,
	132	+ /* Base interface address specified in driver */
	133	+ NULL,
	134	+ /* No cookie implementation */
	135	+ 0
	136	+ },
	137	+};
	138	+
	139	+/* add device descriptor to FPGA device table */
	140	+static void socfpga_fpga_add(void)
40	141	{
	142	+ int i;
	143	+ fpga_init();
	144	+ for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
	145	+ fpga_add(fpga_altera, &altera_fpga[i]);
	146	+}
	147	+#else
	148	+static inline void socfpga_fpga_add(void) {}
	149	+#endif
	150	+
	151	+int arch_cpu_init(void)
	152	+{
	153	+ /*
	154	+ * If the HW watchdog is NOT enabled, make sure it is not running,
	155	+ * for example because it was enabled in the preloader. This might
	156	+ * trigger a watchdog-triggered reboot of Linux kernel later.
	157	+ */
	158	+#ifndef CONFIG_HW_WATCHDOG
	159	+ socfpga_watchdog_reset();
	160	+#endif
41	161	return 0;
42	162	}
43	163
44		-
45	164	/*
46		- * DesignWare Ethernet initialization
	165	+ * Convert all NIC-301 AMBA slaves from secure to non-secure
47	166	*/
48		-int cpu_eth_init(bd_t *bis)
	167	+static void socfpga_nic301_slave_ns(void)
49	168	{
50		-#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
51		- /* initialize and register the emac */
52		- return designware_initialize(CONFIG_EMAC_BASE,
53		- CONFIG_PHY_INTERFACE_MODE);
	169	+ writel(0x1, &nic301_regs->lwhps2fpgaregs);
	170	+ writel(0x1, &nic301_regs->hps2fpgaregs);
	171	+ writel(0x1, &nic301_regs->acp);
	172	+ writel(0x1, &nic301_regs->rom);
	173	+ writel(0x1, &nic301_regs->ocram);
	174	+ writel(0x1, &nic301_regs->sdrdata);
	175	+}
	176	+
	177	+static uint32_t iswgrp_handoff[8];
	178	+
	179	+int misc_init_r(void)
	180	+{
	181	+ int i;
	182	+ for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
	183	+ iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
	184	+
	185	+ socfpga_bridges_reset(1);
	186	+ socfpga_nic301_slave_ns();
	187	+
	188	+ /*
	189	+ * Private components security:
	190	+ * U-Boot : configure private timer, global timer and cpu component
	191	+ * access as non secure for kernel stage (as required by Linux)
	192	+ */
	193	+ setbits_le32(&scu_regs->sacr, 0xfff);
	194	+
	195	+ /* Configure the L2 controller to make SDRAM start at 0 */
	196	+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	197	+ writel(0x2, &nic301_regs->remap);
54	198	#else
55		- return 0;
	199	+ writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
	200	+ writel(0x1, &pl310->pl310_addr_filter_start);
56	201	#endif
	202	+
	203	+ /* Add device descriptor to FPGA device table */
	204	+ socfpga_fpga_add();
	205	+ return 0;
57	206	}
	207	+
	208	+static void socfpga_sdram_apply_static_cfg(void)
	209	+{
	210	+ const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
	211	+ const uint32_t applymask = 0x8;
	212	+ uint32_t val = readl(staticcfg) \| applymask;
	213	+
	214	+ /*
	215	+ * SDRAM staticcfg register specific:
	216	+ * When applying the register setting, the CPU must not access
	217	+ * SDRAM. Luckily for us, we can abuse i-cache here to help us
	218	+ * circumvent the SDRAM access issue. The idea is to make sure
	219	+ * that the code is in one full i-cache line by branching past
	220	+ * it and back. Once it is in the i-cache, we execute the core
	221	+ * of the code and apply the register settings.
	222	+ *
	223	+ * The code below uses 7 instructions, while the Cortex-A9 has
	224	+ * 32-byte cachelines, thus the limit is 8 instructions total.
	225	+ */
	226	+ asm volatile(
	227	+ ".align 5 \n"
	228	+ " b 2f \n"
	229	+ "1: str %0, [%1] \n"
	230	+ " dsb \n"
	231	+ " isb \n"
	232	+ " b 3f \n"
	233	+ "2: b 1b \n"
	234	+ "3: nop \n"
	235	+ : : "r"(val), "r"(staticcfg) : "memory", "cc");
	236	+}
	237	+
	238	+int do_bridge(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	239	+{
	240	+ if (argc != 2)
	241	+ return CMD_RET_USAGE;
	242	+
	243	+ argv++;
	244	+
	245	+ switch (*argv[0]) {
	246	+ case 'e': /* Enable */
	247	+ writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
	248	+ socfpga_sdram_apply_static_cfg();
	249	+ writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
	250	+ writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
	251	+ writel(iswgrp_handoff[1], &nic301_regs->remap);
	252	+ break;
	253	+ case 'd': /* Disable */
	254	+ writel(0, &sysmgr_regs->fpgaintfgrp_module);
	255	+ writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
	256	+ socfpga_sdram_apply_static_cfg();
	257	+ writel(0, &reset_manager_base->brg_mod_reset);
	258	+ writel(1, &nic301_regs->remap);
	259	+ break;
	260	+ default:
	261	+ return CMD_RET_USAGE;
	262	+ }
	263	+
	264	+ return 0;
	265	+}
	266	+
	267	+U_BOOT_CMD(
	268	+ bridge, 2, 1, do_bridge,
	269	+ "SoCFPGA HPS FPGA bridge control",
	270	+ "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
	271	+ "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
	272	+ ""
	273	+);
...	...	@@ -8,12 +8,25 @@
8	8	#include <common.h>
9	9	#include <asm/io.h>
10	10	#include <asm/arch/reset_manager.h>
	11	+#include <asm/arch/fpga_manager.h>
11	12
12	13	DECLARE_GLOBAL_DATA_PTR;
13	14
14	15	static const struct socfpga_reset_manager *reset_manager_base =
15	16	(void *)SOCFPGA_RSTMGR_ADDRESS;
16	17
	18	+/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
	19	+void socfpga_watchdog_reset(void)
	20	+{
	21	+ /* assert reset for watchdog */
	22	+ setbits_le32(&reset_manager_base->per_mod_reset,
	23	+ 1 << RSTMGR_PERMODRST_L4WD0_LSB);
	24	+
	25	+ /* deassert watchdog from reset (watchdog in not running state) */
	26	+ clrbits_le32(&reset_manager_base->per_mod_reset,
	27	+ 1 << RSTMGR_PERMODRST_L4WD0_LSB);
	28	+}
	29	+
17	30	/*
18	31	* Write the reset manager register to cause reset
19	32	*/
...	...	@@ -36,5 +49,59 @@
36	49	void reset_deassert_peripherals_handoff(void)
37	50	{
38	51	writel(0, &reset_manager_base->per_mod_reset);
	52	+}
	53	+
	54	+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
	55	+void socfpga_bridges_reset(int enable)
	56	+{
	57	+ /* For SoCFPGA-VT, this is NOP. */
	58	+}
	59	+#else
	60	+
	61	+#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
	62	+#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
	63	+#define L3REGS_REMAP_OCRAM_MASK 0x01
	64	+
	65	+void socfpga_bridges_reset(int enable)
	66	+{
	67	+ const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK \|
	68	+ L3REGS_REMAP_HPS2FPGA_MASK \|
	69	+ L3REGS_REMAP_OCRAM_MASK;
	70	+
	71	+ if (enable) {
	72	+ /* brdmodrst */
	73	+ writel(0xffffffff, &reset_manager_base->brg_mod_reset);
	74	+ } else {
	75	+ /* Check signal from FPGA. */
	76	+ if (fpgamgr_poll_fpga_ready()) {
	77	+ /* FPGA not ready. Wait for watchdog timeout. */
	78	+ printf("%s: fpga not ready, hanging.\n", __func__);
	79	+ hang();
	80	+ }
	81	+
	82	+ /* brdmodrst */
	83	+ writel(0, &reset_manager_base->brg_mod_reset);
	84	+
	85	+ /* Remap the bridges into memory map */
	86	+ writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
	87	+ }
	88	+}
	89	+#endif
	90	+
	91	+/* Change the reset state for EMAC 0 and EMAC 1 */
	92	+void socfpga_emac_reset(int enable)
	93	+{
	94	+ const void *reset = &reset_manager_base->per_mod_reset;
	95	+
	96	+ if (enable) {
	97	+ setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
	98	+ setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
	99	+ } else {
	100	+#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
	101	+ clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
	102	+#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
	103	+ clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
	104	+#endif
	105	+ }
39	106	}
...	...	@@ -19,6 +19,31 @@
19	19
20	20	DECLARE_GLOBAL_DATA_PTR;
21	21
	22	+#define MAIN_VCO_BASE ( \
	23	+ (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
	24	+ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) \| \
	25	+ (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
	26	+ CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
	27	+ )
	28	+
	29	+#define PERI_VCO_BASE ( \
	30	+ (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
	31	+ CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) \| \
	32	+ (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
	33	+ CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) \| \
	34	+ (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
	35	+ CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
	36	+ )
	37	+
	38	+#define SDR_VCO_BASE ( \
	39	+ (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
	40	+ CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) \| \
	41	+ (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
	42	+ CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) \| \
	43	+ (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
	44	+ CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
	45	+ )
	46	+
22	47	u32 spl_boot_device(void)
23	48	{
24	49	return BOOT_DEVICE_RAM;
25	50
26	51
...	...	@@ -33,86 +58,87 @@
33	58	cm_config_t cm_default_cfg = {
34	59	/* main group */
35	60	MAIN_VCO_BASE,
36		- CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
37		- CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
38		- CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
39		- CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
40		- CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
41		- CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
42		- CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
43		- CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
44		- CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
45		- CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
46		- CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
47		- CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
48		- CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
49		- CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) \|
50		- CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
51		- CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) \|
52		- CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
53		- CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) \|
54		- CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
55		- CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
56		- CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
57		- CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) \|
58		- CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
59		- CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
60		- CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
61		- CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
62		- CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
63		- CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) \|
64		- CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
65		- CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
	61	+ (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
	62	+ CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
	63	+ (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
	64	+ CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
	65	+ (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
	66	+ CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
	67	+ (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
	68	+ CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
	69	+ (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
	70	+ CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
	71	+ (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
	72	+ CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
	73	+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
	74	+ CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) \|
	75	+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
	76	+ CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) \|
	77	+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
	78	+ CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) \|
	79	+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
	80	+ CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
	81	+ (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
	82	+ CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) \|
	83	+ (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
	84	+ CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
	85	+ (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
	86	+ CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
	87	+ (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
	88	+ CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) \|
	89	+ (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
	90	+ CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
66	91
67	92	/* peripheral group */
68	93	PERI_VCO_BASE,
69		- CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
70		- CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
71		- CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
72		- CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
73		- CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
74		- CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
75		- CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
76		- CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
77		- CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
78		- CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
79		- CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
80		- CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
81		- CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
82		- CONFIG_HPS_PERPLLGRP_DIV_USBCLK) \|
83		- CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
84		- CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) \|
85		- CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
86		- CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) \|
87		- CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
88		- CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
89		- CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
90		- CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
91		- CLKMGR_PERPLLGRP_SRC_QSPI_SET(
92		- CONFIG_HPS_PERPLLGRP_SRC_QSPI) \|
93		- CLKMGR_PERPLLGRP_SRC_NAND_SET(
94		- CONFIG_HPS_PERPLLGRP_SRC_NAND) \|
95		- CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
96		- CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
	94	+ (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
	95	+ CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
	96	+ (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
	97	+ CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
	98	+ (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
	99	+ CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
	100	+ (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
	101	+ CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
	102	+ (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
	103	+ CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
	104	+ (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
	105	+ CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
	106	+ (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
	107	+ CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) \|
	108	+ (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
	109	+ CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) \|
	110	+ (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
	111	+ CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) \|
	112	+ (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
	113	+ CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
	114	+ (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
	115	+ CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
	116	+ (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
	117	+ CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) \|
	118	+ (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
	119	+ CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) \|
	120	+ (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
	121	+ CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
97	122
98	123	/* sdram pll group */
99	124	SDR_VCO_BASE,
100		- CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
101		- CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) \|
102		- CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
103		- CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
104		- CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
105		- CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) \|
106		- CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
107		- CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
108		- CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
109		- CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) \|
110		- CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
111		- CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
112		- CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
113		- CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) \|
114		- CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
115		- CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
	125	+ (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
	126	+ CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) \|
	127	+ (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
	128	+ CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
	129	+ (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
	130	+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) \|
	131	+ (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
	132	+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
	133	+ (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
	134	+ CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) \|
	135	+ (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
	136	+ CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
	137	+ (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
	138	+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) \|
	139	+ (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
	140	+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
	141	+
116	142	};
117	143
118	144	debug("Freezing all I/O banks\n");
1	1	/*
2		- * Copyright (C) 2013 Altera Corporation <www.altera.com>
	2	+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
3	3	*
4	4	* SPDX-License-Identifier: GPL-2.0+
5	5	*/
6	6
7	7
8	8
9	9
10	10
...	...	@@ -7,22 +7,63 @@
7	7	#include <common.h>
8	8	#include <asm/io.h>
9	9	#include <asm/arch/system_manager.h>
	10	+#include <asm/arch/fpga_manager.h>
10	11
11	12	DECLARE_GLOBAL_DATA_PTR;
12	13
	14	+static struct socfpga_system_manager *sysmgr_regs =
	15	+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
	16	+
13	17	/*
	18	+ * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
	19	+ * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
	20	+ * CONFIG_SYSMGR_ISWGRP_HANDOFF.
	21	+ */
	22	+static void populate_sysmgr_fpgaintf_module(void)
	23	+{
	24	+ uint32_t handoff_val = 0;
	25	+
	26	+ /* ISWGRP_HANDOFF_FPGAINTF */
	27	+ writel(0, &sysmgr_regs->iswgrp_handoff[2]);
	28	+
	29	+ /* Enable the signal for those HPS peripherals that use FPGA. */
	30	+ if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
	31	+ handoff_val \|= SYSMGR_FPGAINTF_NAND;
	32	+ if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
	33	+ handoff_val \|= SYSMGR_FPGAINTF_EMAC1;
	34	+ if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
	35	+ handoff_val \|= SYSMGR_FPGAINTF_SDMMC;
	36	+ if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
	37	+ handoff_val \|= SYSMGR_FPGAINTF_EMAC0;
	38	+ if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
	39	+ handoff_val \|= SYSMGR_FPGAINTF_SPIM0;
	40	+ if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
	41	+ handoff_val \|= SYSMGR_FPGAINTF_SPIM1;
	42	+
	43	+ /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
	44	+ based on pinmux setting */
	45	+ setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
	46	+
	47	+ handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
	48	+ if (fpgamgr_test_fpga_ready()) {
	49	+ /* Enable the required signals only */
	50	+ writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
	51	+ }
	52	+}
	53	+
	54	+/*
14	55	* Configure all the pin muxes
15	56	*/
16	57	void sysmgr_pinmux_init(void)
17	58	{
18		- unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
	59	+ uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0];
	60	+ int i;
19	61
20		- const unsigned long *pval = sys_mgr_init_table;
21		- unsigned long i;
22		-
23		- for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table);
24		- i++, offset += sizeof(unsigned long)) {
25		- writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
	62	+ for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); i++) {
	63	+ writel(sys_mgr_init_table[i], regs);
	64	+ regs += sizeof(regs);
26	65	}
	66	+
	67	+ populate_sysmgr_fpgaintf_module();
27	68	}
...	...	@@ -8,6 +8,8 @@
8	8	#include <asm/io.h>
9	9	#include <asm/arch/timer.h>
10	10
	11	+#define TIMER_LOAD_VAL 0xFFFFFFFF
	12	+
11	13	static const struct socfpga_timer timer_base = (void )CONFIG_SYS_TIMERBASE;
12	14
13	15	/*
...	...	@@ -7,6 +7,15 @@
7	7	#ifndef _CLOCK_MANAGER_H_
8	8	#define _CLOCK_MANAGER_H_
9	9
	10	+#ifndef __ASSEMBLER__
	11	+/* Clock speed accessors */
	12	+unsigned long cm_get_mpu_clk_hz(void);
	13	+unsigned long cm_get_sdram_clk_hz(void);
	14	+unsigned int cm_get_l4_sp_clk_hz(void);
	15	+unsigned int cm_get_mmc_controller_clk_hz(void);
	16	+unsigned int cm_get_qspi_controller_clk_hz(void);
	17	+#endif
	18	+
10	19	typedef struct {
11	20	/* main group */
12	21	uint32_t main_vco_base;
...	...	@@ -89,6 +98,11 @@
89	98	u32 stat;
90	99	};
91	100
	101	+struct socfpga_clock_manager_altera {
	102	+ u32 mpuclk;
	103	+ u32 mainclk;
	104	+};
	105	+
92	106	struct socfpga_clock_manager {
93	107	u32 ctrl;
94	108	u32 bypass;
95	109
96	110
97	111
98	112
...	...	@@ -100,113 +114,195 @@
100	114	struct socfpga_clock_manager_main_pll main_pll;
101	115	struct socfpga_clock_manager_per_pll per_pll;
102	116	struct socfpga_clock_manager_sdr_pll sdr_pll;
103		- u32 _pad_0xe0_0x200[72];
	117	+ struct socfpga_clock_manager_altera altera;
	118	+ u32 _pad_0xe8_0x200[70];
104	119	};
105	120
106		-#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
107		-#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
108		-#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
109		-#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
110		-#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
111		-#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
112		-#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
113		-#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
114		-#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
115		-#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
116		-#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
117		-#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
118		-#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
119		-#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
120		-#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
121		-#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
122		-#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
123		-#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
124		-#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
125		-#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
126		-#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
127		-#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
128		-#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
129		-#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
130		-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
131		-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
132		-#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
133		-#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
134		-#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
135		-#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
136		-#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
137		-#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
138		-#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \
139		- (((x) << 0) & 0x000001ff)
140		-#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
141		-#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
142		-#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
143		-#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \
144		- (((x) << 0) & 0x000001ff)
145		-#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
146		-#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
147		-#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
148		-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
149		-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
150		-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
151		-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
152		-#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
153		-#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
154		-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
155		-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
156		-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
157		-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
158		-#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
159		-#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
160		-#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
161		-#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
162		-#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
163		-#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
164		-#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
165		-#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
166		-#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
167		-#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
168		-#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
169		-#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
170		-#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
171		-#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
172		-#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
173		-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
174		-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
175		-#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
176		-#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
177		-#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
178		-#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
179		-#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
180		-#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
181		-#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
182		-#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
183		-#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
184		-#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
185		-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
186		-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
187		-#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
188		-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
189		-#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
190		-#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
191		-#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
192		-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
193		-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
194		-#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
195		-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
	121	+#define CLKMGR_CTRL_SAFEMODE (1 << 0)
	122	+#define CLKMGR_CTRL_SAFEMODE_OFFSET 0
196	123
197		-#define MAIN_VCO_BASE \
198		- (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) \| \
199		- CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
	124	+#define CLKMGR_BYPASS_PERPLLSRC (1 << 4)
	125	+#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4
	126	+#define CLKMGR_BYPASS_PERPLL (1 << 3)
	127	+#define CLKMGR_BYPASS_PERPLL_OFFSET 3
	128	+#define CLKMGR_BYPASS_SDRPLLSRC (1 << 2)
	129	+#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2
	130	+#define CLKMGR_BYPASS_SDRPLL (1 << 1)
	131	+#define CLKMGR_BYPASS_SDRPLL_OFFSET 1
	132	+#define CLKMGR_BYPASS_MAINPLL (1 << 0)
	133	+#define CLKMGR_BYPASS_MAINPLL_OFFSET 0
200	134
201		-#define PERI_VCO_BASE \
202		- (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) \| \
203		- CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) \| \
204		- CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
	135	+#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
	136	+#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
	137	+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
	138	+#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010
	139	+#define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020
	140	+#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008
205	141
206		-#define SDR_VCO_BASE \
207		- (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) \| \
208		- CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) \| \
209		- CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
	142	+#define CLKMGR_STAT_BUSY (1 << 0)
	143	+
	144	+/* Main PLL */
	145	+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0)
	146	+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
	147	+#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16
	148	+#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
	149	+#define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1)
	150	+#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1
	151	+#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3
	152	+#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
	153	+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
	154	+#define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2)
	155	+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2
	156	+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
	157	+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
	158	+
	159	+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0
	160	+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff
	161	+
	162	+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0
	163	+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff
	164	+
	165	+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0
	166	+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff
	167	+
	168	+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0
	169	+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff
	170	+
	171	+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0
	172	+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff
	173	+
	174	+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0
	175	+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff
	176	+
	177	+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
	178	+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
	179	+#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
	180	+#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
	181	+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
	182	+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
	183	+
	184	+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0
	185	+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003
	186	+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2
	187	+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c
	188	+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4
	189	+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070
	190	+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7
	191	+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380
	192	+
	193	+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0
	194	+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003
	195	+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2
	196	+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c
	197	+
	198	+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0
	199	+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007
	200	+
	201	+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0)
	202	+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0
	203	+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1)
	204	+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1
	205	+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
	206	+#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
	207	+#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
	208	+
	209	+/* Per PLL */
	210	+#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16
	211	+#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000
	212	+#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3
	213	+#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8
	214	+#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
	215	+#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22
	216	+#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000
	217	+#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
	218	+#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
	219	+#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22
	220	+#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000
	221	+
	222	+#define CLKMGR_VCO_SSRC_EOSC1 0x0
	223	+#define CLKMGR_VCO_SSRC_EOSC2 0x1
	224	+#define CLKMGR_VCO_SSRC_F2S 0x2
	225	+
	226	+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0
	227	+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff
	228	+
	229	+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0
	230	+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff
	231	+
	232	+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0
	233	+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff
	234	+
	235	+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0
	236	+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff
	237	+
	238	+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0
	239	+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff
	240	+
	241	+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0
	242	+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff
	243	+
	244	+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
	245	+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
	246	+
	247	+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6
	248	+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0
	249	+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9
	250	+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00
	251	+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
	252	+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
	253	+#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0
	254	+#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007
	255	+
	256	+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0
	257	+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff
	258	+
	259	+#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2
	260	+#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c
	261	+#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4
	262	+#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030
	263	+#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
	264	+#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0
	265	+#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003
	266	+#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
	267	+#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
	268	+#define CLKMGR_SDMMC_CLK_SRC_PER 0x2
	269	+#define CLKMGR_QSPI_CLK_SRC_F2S 0x0
	270	+#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
	271	+#define CLKMGR_QSPI_CLK_SRC_PER 0x2
	272	+
	273	+/* SDR PLL */
	274	+#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16
	275	+#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000
	276	+#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3
	277	+#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8
	278	+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24)
	279	+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24
	280	+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25
	281	+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
	282	+#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
	283	+#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
	284	+#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22
	285	+#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000
	286	+
	287	+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0
	288	+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
	289	+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9
	290	+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00
	291	+
	292	+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0
	293	+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
	294	+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9
	295	+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00
	296	+
	297	+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0
	298	+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
	299	+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9
	300	+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00
	301	+
	302	+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0
	303	+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
	304	+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9
	305	+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00
210	306
211	307	#endif /* _CLOCK_MANAGER_H_ */
	1	+/*
	2	+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#ifndef _NIC301_REGISTERS_H_
	8	+#define _NIC301_REGISTERS_H_
	9	+
	10	+struct nic301_registers {
	11	+ u32 remap; /* 0x0 */
	12	+ /* Security Register Group */
	13	+ u32 _pad_0x4_0x8[1];
	14	+ u32 l4main;
	15	+ u32 l4sp;
	16	+ u32 l4mp; /* 0x10 */
	17	+ u32 l4osc1;
	18	+ u32 l4spim;
	19	+ u32 stm;
	20	+ u32 lwhps2fpgaregs; /* 0x20 */
	21	+ u32 _pad_0x24_0x28[1];
	22	+ u32 usb1;
	23	+ u32 nanddata;
	24	+ u32 _pad_0x30_0x80[20];
	25	+ u32 usb0; /* 0x80 */
	26	+ u32 nandregs;
	27	+ u32 qspidata;
	28	+ u32 fpgamgrdata;
	29	+ u32 hps2fpgaregs; /* 0x90 */
	30	+ u32 acp;
	31	+ u32 rom;
	32	+ u32 ocram;
	33	+ u32 sdrdata; /* 0xA0 */
	34	+ u32 _pad_0xa4_0x1fd0[1995];
	35	+ /* ID Register Group */
	36	+ u32 periph_id_4; /* 0x1FD0 */
	37	+ u32 _pad_0x1fd4_0x1fe0[3];
	38	+ u32 periph_id_0; /* 0x1FE0 */
	39	+ u32 periph_id_1;
	40	+ u32 periph_id_2;
	41	+ u32 periph_id_3;
	42	+ u32 comp_id_0; /* 0x1FF0 */
	43	+ u32 comp_id_1;
	44	+ u32 comp_id_2;
	45	+ u32 comp_id_3;
	46	+ u32 _pad_0x2000_0x2008[2];
	47	+ /* L4 MAIN */
	48	+ u32 l4main_fn_mod_bm_iss;
	49	+ u32 _pad_0x200c_0x3008[1023];
	50	+ /* L4 SP */
	51	+ u32 l4sp_fn_mod_bm_iss;
	52	+ u32 _pad_0x300c_0x4008[1023];
	53	+ /* L4 MP */
	54	+ u32 l4mp_fn_mod_bm_iss;
	55	+ u32 _pad_0x400c_0x5008[1023];
	56	+ /* L4 OSC1 */
	57	+ u32 l4osc_fn_mod_bm_iss;
	58	+ u32 _pad_0x500c_0x6008[1023];
	59	+ /* L4 SPIM */
	60	+ u32 l4spim_fn_mod_bm_iss;
	61	+ u32 _pad_0x600c_0x7008[1023];
	62	+ /* STM */
	63	+ u32 stm_fn_mod_bm_iss;
	64	+ u32 _pad_0x700c_0x7108[63];
	65	+ u32 stm_fn_mod;
	66	+ u32 _pad_0x710c_0x8008[959];
	67	+ /* LWHPS2FPGA */
	68	+ u32 lwhps2fpga_fn_mod_bm_iss;
	69	+ u32 _pad_0x800c_0x8108[63];
	70	+ u32 lwhps2fpga_fn_mod;
	71	+ u32 _pad_0x810c_0xa008[1983];
	72	+ /* USB1 */
	73	+ u32 usb1_fn_mod_bm_iss;
	74	+ u32 _pad_0xa00c_0xa044[14];
	75	+ u32 usb1_ahb_cntl;
	76	+ u32 _pad_0xa048_0xb008[1008];
	77	+ /* NANDDATA */
	78	+ u32 nanddata_fn_mod_bm_iss;
	79	+ u32 _pad_0xb00c_0xb108[63];
	80	+ u32 nanddata_fn_mod;
	81	+ u32 _pad_0xb10c_0x20008[21439];
	82	+ /* USB0 */
	83	+ u32 usb0_fn_mod_bm_iss;
	84	+ u32 _pad_0x2000c_0x20044[14];
	85	+ u32 usb0_ahb_cntl;
	86	+ u32 _pad_0x20048_0x21008[1008];
	87	+ /* NANDREGS */
	88	+ u32 nandregs_fn_mod_bm_iss;
	89	+ u32 _pad_0x2100c_0x21108[63];
	90	+ u32 nandregs_fn_mod;
	91	+ u32 _pad_0x2110c_0x22008[959];
	92	+ /* QSPIDATA */
	93	+ u32 qspidata_fn_mod_bm_iss;
	94	+ u32 _pad_0x2200c_0x22044[14];
	95	+ u32 qspidata_ahb_cntl;
	96	+ u32 _pad_0x22048_0x23008[1008];
	97	+ /* FPGAMGRDATA */
	98	+ u32 fpgamgrdata_fn_mod_bm_iss;
	99	+ u32 _pad_0x2300c_0x23040[13];
	100	+ u32 fpgamgrdata_wr_tidemark; /* 0x23040 */
	101	+ u32 _pad_0x23044_0x23108[49];
	102	+ u32 fn_mod;
	103	+ u32 _pad_0x2310c_0x24008[959];
	104	+ /* HPS2FPGA */
	105	+ u32 hps2fpga_fn_mod_bm_iss;
	106	+ u32 _pad_0x2400c_0x24040[13];
	107	+ u32 hps2fpga_wr_tidemark; /* 0x24040 */
	108	+ u32 _pad_0x24044_0x24108[49];
	109	+ u32 hps2fpga_fn_mod;
	110	+ u32 _pad_0x2410c_0x25008[959];
	111	+ /* ACP */
	112	+ u32 acp_fn_mod_bm_iss;
	113	+ u32 _pad_0x2500c_0x25108[63];
	114	+ u32 acp_fn_mod;
	115	+ u32 _pad_0x2510c_0x26008[959];
	116	+ /* Boot ROM */
	117	+ u32 bootrom_fn_mod_bm_iss;
	118	+ u32 _pad_0x2600c_0x26108[63];
	119	+ u32 bootrom_fn_mod;
	120	+ u32 _pad_0x2610c_0x27008[959];
	121	+ /* On-chip RAM */
	122	+ u32 ocram_fn_mod_bm_iss;
	123	+ u32 _pad_0x2700c_0x27040[13];
	124	+ u32 ocram_wr_tidemark; /* 0x27040 */
	125	+ u32 _pad_0x27044_0x27108[49];
	126	+ u32 ocram_fn_mod;
	127	+ u32 _pad_0x2710c_0x42024[27590];
	128	+ /* DAP */
	129	+ u32 dap_fn_mod2;
	130	+ u32 dap_fn_mod_ahb;
	131	+ u32 _pad_0x4202c_0x42100[53];
	132	+ u32 dap_read_qos; /* 0x42100 */
	133	+ u32 dap_write_qos;
	134	+ u32 dap_fn_mod;
	135	+ u32 _pad_0x4210c_0x43100[1021];
	136	+ /* MPU */
	137	+ u32 mpu_read_qos; /* 0x43100 */
	138	+ u32 mpu_write_qos;
	139	+ u32 mpu_fn_mod;
	140	+ u32 _pad_0x4310c_0x44028[967];
	141	+ /* SDMMC */
	142	+ u32 sdmmc_fn_mod_ahb;
	143	+ u32 _pad_0x4402c_0x44100[53];
	144	+ u32 sdmmc_read_qos; /* 0x44100 */
	145	+ u32 sdmmc_write_qos;
	146	+ u32 sdmmc_fn_mod;
	147	+ u32 _pad_0x4410c_0x45100[1021];
	148	+ /* DMA */
	149	+ u32 dma_read_qos; /* 0x45100 */
	150	+ u32 dma_write_qos;
	151	+ u32 dma_fn_mod;
	152	+ u32 _pad_0x4510c_0x46040[973];
	153	+ /* FPGA2HPS */
	154	+ u32 fpga2hps_wr_tidemark; /* 0x46040 */
	155	+ u32 _pad_0x46044_0x46100[47];
	156	+ u32 fpga2hps_read_qos; /* 0x46100 */
	157	+ u32 fpga2hps_write_qos;
	158	+ u32 fpga2hps_fn_mod;
	159	+ u32 _pad_0x4610c_0x47100[1021];
	160	+ /* ETR */
	161	+ u32 etr_read_qos; /* 0x47100 */
	162	+ u32 etr_write_qos;
	163	+ u32 etr_fn_mod;
	164	+ u32 _pad_0x4710c_0x48100[1021];
	165	+ /* EMAC0 */
	166	+ u32 emac0_read_qos; /* 0x48100 */
	167	+ u32 emac0_write_qos;
	168	+ u32 emac0_fn_mod;
	169	+ u32 _pad_0x4810c_0x49100[1021];
	170	+ /* EMAC1 */
	171	+ u32 emac1_read_qos; /* 0x49100 */
	172	+ u32 emac1_write_qos;
	173	+ u32 emac1_fn_mod;
	174	+ u32 _pad_0x4910c_0x4a028[967];
	175	+ /* USB0 */
	176	+ u32 usb0_fn_mod_ahb;
	177	+ u32 _pad_0x4a02c_0x4a100[53];
	178	+ u32 usb0_read_qos; /* 0x4A100 */
	179	+ u32 usb0_write_qos;
	180	+ u32 usb0_fn_mod;
	181	+ u32 _pad_0x4a10c_0x4b100[1021];
	182	+ /* NAND */
	183	+ u32 nand_read_qos; /* 0x4B100 */
	184	+ u32 nand_write_qos;
	185	+ u32 nand_fn_mod;
	186	+ u32 _pad_0x4b10c_0x4c028[967];
	187	+ /* USB1 */
	188	+ u32 usb1_fn_mod_ahb;
	189	+ u32 _pad_0x4c02c_0x4c100[53];
	190	+ u32 usb1_read_qos; /* 0x4C100 */
	191	+ u32 usb1_write_qos;
	192	+ u32 usb1_fn_mod;
	193	+};
	194	+
	195	+#endif /* _NIC301_REGISTERS_H_ */