Eric Lee / smarc-uboot

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Commit 0528ba0e1c4f879278d597b1aeaf1bf31a943f75

Authored by Peng Fan
Committed by Stefano Babic
1 parent b3cf0a8f03
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

imx8m: soc: enable SCTR clock before timer init 

To i.MX8MM SCTR clock is disabled by ROM, so before timer init
need to enable it.
To i.MX8MQ, it does not hurt the clock is enabled again.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Showing 1 changed file with 6 additions and 0 deletions Side-by-side Diff

arch/arm/mach-imx/imx8m/soc.c
Diff comments   View file @ 0528ba0
... ... @@ -232,6 +232,12 @@
232 232 {
233 233 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
234 234 /*
  235 + * ROM might disable clock for SCTR,
  236 + * enable the clock before timer_init.
  237 + */
  238 + if (IS_ENABLED(CONFIG_SPL_BUILD))
  239 + clock_enable(CCGR_SCTR, 1);
  240 + /*
235 241 * Init timer at very early state, because sscg pll setting
236 242 * will use it
237 243 */