Eric Lee / smarc-uboot

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Commit 058d23168752c2a2ec0a6c3b50296cb5b91ec6d0

Authored by Boris BREZILLON
Committed by Stefano Babic
1 parent a05a6045d5
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

board/seco: Add mx6q-uq7 basic board support 

Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported).
It also adds a Kconfig skeleton to later add more SECO board (supporting
SoC and board variants).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

Showing 11 changed files with 744 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx6/Kconfig
Diff comments   View file @ 058d231
... ... @@ -25,8 +25,19 @@
25 25 config MX6SX
26 26 bool
27 27  
  28 +choice
  29 + prompt "MX6 board select"
  30 +
  31 +config TARGET_SECOMX6
  32 + bool "Support secomx6 boards"
  33 + select CPU_V7
  34 +
  35 +endchoice
  36 +
28 37 config SYS_SOC
29 38 default "mx6"
  39 +
  40 +source "board/seco/Kconfig"
30 41  
31 42 endif
  1 +if TARGET_SECOMX6
  2 +
  3 +choice
  4 + prompt "SECO i.MX6 Board variant"
  5 +
  6 +config SECOMX6_Q7
  7 + bool "Q7"
  8 +
  9 +config SECOMX6_UQ7
  10 + bool "uQ7"
  11 +
  12 +config SECOMX6_USBC
  13 + bool "uSBC"
  14 +
  15 +endchoice
  16 +
  17 +choice
  18 + prompt "SECO i.MX6 SoC variant"
  19 +
  20 +config SECOMX6Q
  21 + bool "i.MX6Q"
  22 + select MX6Q
  23 +
  24 +config SECOMX6DL
  25 + bool "i.MX6DL"
  26 + select MX6DL
  27 +
  28 +config SECOMX6S
  29 + bool "i.MX6S"
  30 + select MX6S
  31 +
  32 +endchoice
  33 +
  34 +choice
  35 + prompt "DDR size"
  36 +
  37 +config SECOMX6_512MB
  38 + bool "512MB"
  39 +
  40 +config SECOMX6_1GB
  41 + bool "1GB"
  42 +
  43 +config SECOMX6_2GB
  44 + bool "2GB"
  45 +
  46 +config SECOMX6_4GB
  47 + bool "4GB"
  48 +
  49 +endchoice
  50 +
  51 +config IMX_CONFIG
  52 + default "board/seco/mx6quq7/mx6quq7-2g.cfg" if SECOMX6_UQ7 && SECOMX6Q && SECOMX6_2GB
  53 +
  54 +config SYS_BOARD
  55 + default "mx6quq7" if SECOMX6_UQ7 && SECOMX6Q
  56 +
  57 +config SYS_VENDOR
  58 + default "seco"
  59 +
  60 +config SYS_CONFIG_NAME
  61 + default "secomx6quq7" if SECOMX6_UQ7 && SECOMX6Q
  62 +
  63 +endif
board/seco/common/Makefile
Diff comments   View file @ 058d231
  1 +
  2 +obj-$(CONFIG_TARGET_SECOMX6) += mx6.o
board/seco/common/mx6.c
Diff comments   View file @ 058d231
  1 +/*
  2 + * Copyright (C) 2013 Freescale Semiconductor, Inc.
  3 + * Copyright (C) 2015 ECA Sinters
  4 + *
  5 + * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6 + * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com>
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <asm/arch/clock.h>
  12 +#include <asm/arch/imx-regs.h>
  13 +#include <asm/arch/iomux.h>
  14 +#include <asm/arch/mx6-pins.h>
  15 +#include <asm/errno.h>
  16 +#include <asm/gpio.h>
  17 +#include <asm/imx-common/iomux-v3.h>
  18 +#include <asm/imx-common/boot_mode.h>
  19 +#include <mmc.h>
  20 +#include <fsl_esdhc.h>
  21 +#include <miiphy.h>
  22 +#include <netdev.h>
  23 +#include <asm/arch/mxc_hdmi.h>
  24 +#include <asm/arch/crm_regs.h>
  25 +#include <linux/fb.h>
  26 +#include <ipu_pixfmt.h>
  27 +#include <asm/io.h>
  28 +#include <asm/arch/sys_proto.h>
  29 +#include <micrel.h>
  30 +#include <asm/imx-common/mxc_i2c.h>
  31 +#include <i2c.h>
  32 +
  33 +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  34 + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  35 + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  36 +
  37 +static iomux_v3_cfg_t const uart2_pads[] = {
  38 + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  39 + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  40 +};
  41 +
  42 +void seco_mx6_setup_uart_iomux(void)
  43 +{
  44 + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  45 +}
  46 +
  47 +#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  48 + PAD_CTL_SPEED_MED | \
  49 + PAD_CTL_DSE_40ohm | \
  50 + PAD_CTL_HYS)
  51 +
  52 +static iomux_v3_cfg_t const enet_pads[] = {
  53 + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  54 + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  55 + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  56 + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  57 + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  58 + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  59 + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  60 + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61 + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62 + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63 + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64 + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  65 + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66 + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67 + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68 +};
  69 +
  70 +void seco_mx6_setup_enet_iomux(void)
  71 +{
  72 + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  73 +}
  74 +
  75 +int seco_mx6_rgmii_rework(struct phy_device *phydev)
  76 +{
  77 + /* control data pad skew - devaddr = 0x02, register = 0x04 */
  78 + ksz9031_phy_extended_write(phydev, 0x02,
  79 + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  80 + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  81 + /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  82 + ksz9031_phy_extended_write(phydev, 0x02,
  83 + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  84 + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  85 + /* tx data pad skew - devaddr = 0x02, register = 0x05 */
  86 + ksz9031_phy_extended_write(phydev, 0x02,
  87 + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  88 + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  89 +
  90 + /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  91 + ksz9031_phy_extended_write(phydev, 0x02,
  92 + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  93 + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  94 + return 0;
  95 +}
  96 +
  97 +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  98 + PAD_CTL_SPEED_LOW | \
  99 + PAD_CTL_DSE_80ohm | \
  100 + PAD_CTL_SRE_FAST | \
  101 + PAD_CTL_HYS)
  102 +
  103 +static iomux_v3_cfg_t const usdhc3_pads[] = {
  104 + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  105 + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  106 + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  107 + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  108 + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  109 + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  110 +};
  111 +
  112 +static iomux_v3_cfg_t const usdhc4_pads[] = {
  113 + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  114 + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  115 + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  116 + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117 + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118 + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  119 +};
  120 +
  121 +void seco_mx6_setup_usdhc_iomux(int id)
  122 +{
  123 + switch (id) {
  124 + case 3:
  125 + imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
  126 + ARRAY_SIZE(usdhc3_pads));
  127 + break;
  128 +
  129 + case 4:
  130 + imx_iomux_v3_setup_multiple_pads(usdhc4_pads,
  131 + ARRAY_SIZE(usdhc4_pads));
  132 + break;
  133 +
  134 + default:
  135 + printf("Warning: invalid usdhc id (%d)\n", id);
  136 + break;
  137 + }
  138 +}
board/seco/common/mx6.h
Diff comments   View file @ 058d231
  1 +#ifndef __SECO_COMMON_MX6_H
  2 +#define __SECO_COMMON_MX6_H
  3 +
  4 +void seco_mx6_setup_uart_iomux(void);
  5 +void seco_mx6_setup_enet_iomux(void);
  6 +int seco_mx6_rgmii_rework(struct phy_device *phydev);
  7 +void seco_mx6_setup_usdhc_iomux(int id);
  8 +
  9 +#endif /* __SECO_COMMON_MX6_H */
board/seco/mx6quq7/MAINTAINERS
Diff comments   View file @ 058d231
  1 +MX6QUQ7 BOARD
  2 +M: Boris Brezillon <boris.brezillon@free-electrons.com>
  3 +S: Maintained
  4 +F: board/seco/mx6quq7/
  5 +F: include/configs/secomx6quq7.h
  6 +F: configs/secomx6quq7_defconfig
board/seco/mx6quq7/Makefile
Diff comments   View file @ 058d231
  1 +#
  2 +# (C) Copyright 2015 ECA Sinters
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y := mx6quq7.o
board/seco/mx6quq7/mx6quq7-2g.cfg
Diff comments   View file @ 058d231
  1 +/*
  2 + * Copyright (C) 2013 Seco USA Inc
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0
  5 + *
  6 + * Refer doc/README.imximage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +/* image version */
  13 +IMAGE_VERSION 2
  14 +
  15 +/*
  16 + * Boot Device : one of
  17 + * spi, sd (the board has no nand neither onenand)
  18 + */
  19 +BOOT_FROM sd
  20 +
  21 +#define __ASSEMBLY__
  22 +#include <config.h>
  23 +#include "asm/arch/mx6-ddr.h"
  24 +#include "asm/arch/iomux.h"
  25 +#include "asm/arch/crm_regs.h"
  26 +
  27 +/* DDR IO TYPE */
  28 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
  29 +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
  30 +
  31 +/* DATA STROBE */
  32 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
  33 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
  34 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
  35 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
  36 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
  37 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028
  38 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028
  39 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028
  40 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028
  41 +
  42 +/* DATA */
  43 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
  44 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
  45 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
  46 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
  47 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
  48 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000028
  49 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000028
  50 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000028
  51 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000028
  52 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
  53 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
  54 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
  55 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
  56 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028
  57 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028
  58 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028
  59 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028
  60 +/* ADDRESS */
  61 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000028
  62 +DATA 4, MX6_IOM_DRAM_CAS, 0x00000028
  63 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000028
  64 +
  65 +/* CONTROL */
  66 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
  67 +DATA 4, MX6_IOM_DRAM_RESET, 0x00000028
  68 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
  69 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000028
  70 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000028
  71 +
  72 +/* CLOCK */
  73 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
  74 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
  75 +
  76 +/*
  77 + * DDR3 SETTINGS
  78 + * Read Data Bit Delay
  79 + */
  80 +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
  81 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
  82 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
  83 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
  84 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
  85 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
  86 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
  87 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
  88 +
  89 +
  90 +/* Write Leveling */
  91 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
  92 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
  93 +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F0001
  94 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
  95 +
  96 +/* DQS gating, read delay, write delay calibration values */
  97 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x431A0326
  98 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0323031B
  99 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x433F0340
  100 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0345031C
  101 +
  102 +/* Read calibration */
  103 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40343137
  104 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x40372F45
  105 +
  106 +/* write calibration */
  107 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x32414741
  108 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4731473C
  109 +
  110 +/* Complete calibration by forced measurement: */
  111 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
  112 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
  113 +
  114 +/*
  115 + * MMDC init:
  116 + * in DDR3, 64-bit mode, only MMDC0 is init
  117 + */
  118 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
  119 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
  120 +
  121 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7955
  122 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
  123 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
  124 +
  125 +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
  126 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
  127 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
  128 +DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
  129 +
  130 +/* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */
  131 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
  132 +
  133 +/* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */
  134 +DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
  135 +
  136 +/* Initialize DDR3 on CS_0 and CS_1 */
  137 +DATA 4, MX6_MMDC_P0_MDSCR, 0x02088032
  138 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
  139 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
  140 +
  141 +/* P0 01c */
  142 +/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */
  143 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
  144 +
  145 +/*ZQ - Calibrationi */
  146 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
  147 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
  148 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
  149 +
  150 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
  151 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
  152 +
  153 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
  154 +
  155 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
  156 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
  157 +
  158 +/* set the default clock gate to save power */
  159 +DATA 4, CCM_CCGR0, 0x00C03F3F
  160 +DATA 4, CCM_CCGR1, 0x0030FC03
  161 +DATA 4, CCM_CCGR2, 0x0FFFC000
  162 +DATA 4, CCM_CCGR3, 0x3FF00000
  163 +DATA 4, CCM_CCGR4, 0x00FFF300
  164 +DATA 4, CCM_CCGR5, 0x0F0000C3
  165 +DATA 4, CCM_CCGR6, 0x000003FF
  166 +
  167 +/* enable AXI cache for VDOA/VPU/IPU */
  168 +DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
  169 +
  170 +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  171 +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
  172 +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
board/seco/mx6quq7/mx6quq7.c
Diff comments   View file @ 058d231
  1 +/*
  2 + * Copyright (C) 2013 Freescale Semiconductor, Inc.
  3 + * Copyright (C) 2015 ECA Sinters
  4 + *
  5 + * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6 + * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com>
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <asm/arch/clock.h>
  12 +#include <asm/arch/imx-regs.h>
  13 +#include <asm/arch/iomux.h>
  14 +#include <asm/arch/mx6-pins.h>
  15 +#include <asm/errno.h>
  16 +#include <asm/gpio.h>
  17 +#include <asm/imx-common/iomux-v3.h>
  18 +#include <asm/imx-common/boot_mode.h>
  19 +#include <malloc.h>
  20 +#include <mmc.h>
  21 +#include <fsl_esdhc.h>
  22 +#include <miiphy.h>
  23 +#include <netdev.h>
  24 +#include <asm/arch/mxc_hdmi.h>
  25 +#include <asm/arch/crm_regs.h>
  26 +#include <linux/fb.h>
  27 +#include <ipu_pixfmt.h>
  28 +#include <asm/io.h>
  29 +#include <asm/arch/sys_proto.h>
  30 +#include <micrel.h>
  31 +#include <asm/imx-common/mxc_i2c.h>
  32 +#include <i2c.h>
  33 +
  34 +#include "../common/mx6.h"
  35 +
  36 +DECLARE_GLOBAL_DATA_PTR;
  37 +
  38 +int dram_init(void)
  39 +{
  40 + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  41 +
  42 + return 0;
  43 +}
  44 +
  45 +int board_early_init_f(void)
  46 +{
  47 + seco_mx6_setup_uart_iomux();
  48 +
  49 + return 0;
  50 +}
  51 +
  52 +int board_phy_config(struct phy_device *phydev)
  53 +{
  54 + seco_mx6_rgmii_rework(phydev);
  55 + if (phydev->drv->config)
  56 + phydev->drv->config(phydev);
  57 +
  58 + return 0;
  59 +}
  60 +
  61 +int board_eth_init(bd_t *bis)
  62 +{
  63 + uint32_t base = IMX_FEC_BASE;
  64 + struct mii_dev *bus = NULL;
  65 + struct phy_device *phydev = NULL;
  66 + int ret = 0;
  67 +
  68 + seco_mx6_setup_enet_iomux();
  69 +
  70 +#ifdef CONFIG_FEC_MXC
  71 + bus = fec_get_miibus(base, -1);
  72 + if (!bus)
  73 + return -ENOMEM;
  74 +
  75 + /* scan phy 4,5,6,7 */
  76 + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
  77 + if (!phydev) {
  78 + free(bus);
  79 + return -ENOMEM;
  80 + }
  81 +
  82 + printf("using phy at %d\n", phydev->addr);
  83 + ret = fec_probe(bis, -1, base, bus, phydev);
  84 + if (ret) {
  85 + free(phydev);
  86 + free(bus);
  87 + printf("FEC MXC: %s:failed\n", __func__);
  88 + }
  89 +#endif
  90 +
  91 + return ret;
  92 +}
  93 +
  94 +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  95 + {USDHC3_BASE_ADDR},
  96 + {USDHC2_BASE_ADDR},
  97 +};
  98 +
  99 +int board_mmc_init(bd_t *bis)
  100 +{
  101 + u32 index = 0;
  102 + int ret;
  103 +
  104 + /*
  105 + * Following map is done:
  106 + * (U-boot device node) (Physical Port)
  107 + * mmc0 eMMC on Board
  108 + * mmc1 Ext SD
  109 + */
  110 + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  111 + switch (index) {
  112 + case 0:
  113 + seco_mx6_setup_usdhc_iomux(3);
  114 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  115 + usdhc_cfg[0].max_bus_width = 4;
  116 + break;
  117 + case 1:
  118 + seco_mx6_setup_usdhc_iomux(4);
  119 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  120 + usdhc_cfg[1].max_bus_width = 4;
  121 + break;
  122 +
  123 + default:
  124 + printf("Warning: %d exceed maximum number of SD ports %d\n",
  125 + index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  126 + return -EINVAL;
  127 + }
  128 +
  129 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  130 + if (ret)
  131 + return ret;
  132 + }
  133 +
  134 + return 0;
  135 +}
  136 +
  137 +int board_init(void)
  138 +{
  139 + /* address of boot parameters */
  140 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  141 +
  142 + imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D4__GPIO2_IO04 |
  143 + MUX_PAD_CTRL(NO_PAD_CTRL));
  144 +
  145 + gpio_direction_output(IMX_GPIO_NR(2, 4), 0);
  146 +
  147 + /* Set Low */
  148 + gpio_set_value(IMX_GPIO_NR(2, 4), 0);
  149 + udelay(1000);
  150 +
  151 + /* Set High */
  152 + gpio_set_value(IMX_GPIO_NR(2, 4), 1);
  153 +
  154 + return 0;
  155 +}
  156 +
  157 +int checkboard(void)
  158 +{
  159 + puts("Board: SECO uQ7\n");
  160 +
  161 + return 0;
  162 +}
configs/secomx6quq7_defconfig
Diff comments   View file @ 058d231
  1 +CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_TARGET_SECOMX6=y
  5 +CONFIG_SECOMX6_UQ7=y
  6 +CONFIG_SECOMX6Q=y
  7 +CONFIG_SECOMX6_2GB=y
include/configs/secomx6quq7.h
Diff comments   View file @ 058d231
  1 +/*
  2 + * Copyright (C) 2013 Seco S.r.l
  3 + *
  4 + * Configuration settings for the Seco Boards.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __CONFIG_H
  10 +#define __CONFIG_H
  11 +
  12 +#include "mx6_common.h"
  13 +#include <asm/arch/imx-regs.h>
  14 +#include <asm/imx-common/gpio.h>
  15 +#include <linux/sizes.h>
  16 +
  17 +#define CONFIG_SYS_GENERIC_BOARD
  18 +#define CONFIG_DISPLAY_CPUINFO
  19 +#define CONFIG_DISPLAY_BOARDINFO
  20 +
  21 +#define CONFIG_CMDLINE_TAG
  22 +#define CONFIG_SETUP_MEMORY_TAGS
  23 +#define CONFIG_INITRD_TAG
  24 +#define CONFIG_REVISION_TAG
  25 +#define CONFIG_BOARD_REVISION_TAG
  26 +
  27 +/* Size of malloc() pool */
  28 +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
  29 +
  30 +#define CONFIG_BOARD_EARLY_INIT_F
  31 +#define CONFIG_MXC_GPIO
  32 +
  33 +#define CONFIG_MXC_UART
  34 +#define CONFIG_MXC_UART_BASE UART2_BASE
  35 +
  36 +/* allow to overwrite serial and ethaddr */
  37 +#define CONFIG_ENV_OVERWRITE
  38 +#define CONFIG_CONS_INDEX 1
  39 +#define CONFIG_BAUDRATE 115200
  40 +
  41 +/* Command definition */
  42 +#include <config_cmd_default.h>
  43 +
  44 +#undef CONFIG_CMD_IMLS
  45 +
  46 +#define CONFIG_CMD_BMODE
  47 +#define CONFIG_CMD_SETEXPR
  48 +
  49 +#define CONFIG_BOOTDELAY 3
  50 +
  51 +#define CONFIG_SYS_MEMTEST_START 0x10000000
  52 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
  53 +#define CONFIG_LOADADDR 0x12000000
  54 +#define CONFIG_SYS_TEXT_BASE 0x17800000
  55 +
  56 +/* MMC Configuration */
  57 +#define CONFIG_FSL_ESDHC
  58 +#define CONFIG_FSL_USDHC
  59 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  60 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  61 +
  62 +#define CONFIG_MMC
  63 +#define CONFIG_CMD_MMC
  64 +#define CONFIG_GENERIC_MMC
  65 +#define CONFIG_BOUNCE_BUFFER
  66 +#define CONFIG_CMD_EXT2
  67 +#define CONFIG_CMD_FAT
  68 +#define CONFIG_DOS_PARTITION
  69 +
  70 +/* Ethernet Configuration */
  71 +#define CONFIG_CMD_PING
  72 +#define CONFIG_CMD_DHCP
  73 +#define CONFIG_CMD_MII
  74 +#define CONFIG_CMD_NET
  75 +#define CONFIG_FEC_MXC
  76 +#define CONFIG_MII
  77 +#define IMX_FEC_BASE ENET_BASE_ADDR
  78 +#define CONFIG_FEC_XCV_TYPE RGMII
  79 +#define CONFIG_ETHPRIME "FEC"
  80 +#define CONFIG_FEC_MXC_PHYADDR 6
  81 +#define CONFIG_PHYLIB
  82 +#define CONFIG_PHY_MICREL
  83 +
  84 +#define CONFIG_EXTRA_ENV_SETTINGS \
  85 + "netdev=eth0\0" \
  86 + "ethprime=FEC0\0" \
  87 + "netdev=eth0\0" \
  88 + "ethprime=FEC0\0" \
  89 + "uboot=u-boot.bin\0" \
  90 + "kernel=uImage\0" \
  91 + "nfsroot=/opt/eldk/arm\0" \
  92 + "ip_local=10.0.0.5::10.0.0.1:255.255.255.0::eth0:off\0" \
  93 + "ip_server=10.0.0.1\0" \
  94 + "nfs_path=/targetfs \0" \
  95 + "memory=mem=1024M\0" \
  96 + "bootdev=mmc dev 0; ext2load mmc 0:1\0" \
  97 + "root=root=/dev/mmcblk0p1\0" \
  98 + "option=rootwait rw fixrtc rootflags=barrier=1\0" \
  99 + "cpu_freq=arm_freq=996\0" \
  100 + "setbootargs=setenv bootargs console=ttymxc1,115200 ${root}" \
  101 + " ${option} ${memory} ${cpu_freq}\0" \
  102 + "setbootargs_nfs=setenv bootargs console=ttymxc1,115200" \
  103 + " root=/dev/nfs nfsroot=${ip_server}:${nfs_path}" \
  104 + " nolock,wsize=4096,rsize=4096 ip=:::::eth0:dhcp" \
  105 + " ${memory} ${cpu_freq}\0" \
  106 + "setbootdev=setenv boot_dev ${bootdev} 10800000 /boot/uImage\0" \
  107 + "bootcmd=run setbootargs; run setbootdev; run boot_dev;" \
  108 + " bootm 0x10800000\0" \
  109 + "stdin=serial\0" \
  110 + "stdout=serial\0" \
  111 + "stderr=serial\0"
  112 +
  113 +
  114 +/* Miscellaneous configurable options */
  115 +#define CONFIG_SYS_LONGHELP
  116 +#define CONFIG_SYS_HUSH_PARSER
  117 +#define CONFIG_SYS_PROMPT "SECO MX6Q uQ7 U-Boot > "
  118 +
  119 +#define CONFIG_AUTO_COMPLETE
  120 +#define CONFIG_SYS_CBSIZE 256
  121 +
  122 +/* Print Buffer Size */
  123 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  124 + sizeof(CONFIG_SYS_PROMPT) + 16)
  125 +#define CONFIG_SYS_MAXARGS 16
  126 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  127 +
  128 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  129 +#define CONFIG_SYS_HZ 1000
  130 +
  131 +#define CONFIG_CMDLINE_EDITING
  132 +
  133 +
  134 +/* Physical Memory Map */
  135 +#define CONFIG_NR_DRAM_BANKS 1
  136 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
  137 +#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
  138 +
  139 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
  140 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
  141 +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
  142 +
  143 +#define CONFIG_SYS_INIT_SP_OFFSET \
  144 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  145 +#define CONFIG_SYS_INIT_SP_ADDR \
  146 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  147 +
  148 +/* FLASH and environment organization */
  149 +#define CONFIG_SYS_NO_FLASH
  150 +
  151 +#define CONFIG_ENV_SIZE (8 * 1024)
  152 +
  153 +#if defined(CONFIG_ENV_IS_IN_MMC)
  154 + #define CONFIG_ENV_OFFSET (6 * 128 * 1024)
  155 + #define CONFIG_SYS_MMC_ENV_DEV 0
  156 + #define CONFIG_DYNAMIC_MMC_DEVNO
  157 +#endif
  158 +
  159 +#define CONFIG_OF_LIBFDT
  160 +#define CONFIG_CMD_BOOTZ
  161 +
  162 +#ifndef CONFIG_SYS_DCACHE_OFF
  163 +#define CONFIG_CMD_CACHE
  164 +#endif
  165 +
  166 +#endif /* __CONFIG_H */