Eric Lee / smarc-uboot

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Commit 05922b0abf848949df778c19312cb1cf7fdfbe6a

Authored by Peng Fan
1 parent 5fb09cab9b
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-12767 imx6ull: fix runtime checking for i.MX6ULL 

Fix runtime checking for i.MX6ULL. Add is_cpu_type(MXC_CPU_MX6ULL)
to avoid using wrong code path.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Showing 5 changed files with 34 additions and 24 deletions Inline Diff

arch/arm/cpu/armv7/mx6/clock.c
Diff comments   View file @ 05922b0
1 /* 1 /*
2 * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2010-2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <div64.h> 8 #include <div64.h>
9 #include <asm/io.h> 9 #include <asm/io.h>
10 #include <asm/errno.h> 10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h> 13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h> 14 #include <asm/arch/sys_proto.h>
15 15
16 enum pll_clocks { 16 enum pll_clocks {
17 PLL_SYS, /* System PLL */ 17 PLL_SYS, /* System PLL */
18 PLL_BUS, /* System Bus PLL*/ 18 PLL_BUS, /* System Bus PLL*/
19 PLL_USBOTG, /* OTG USB PLL */ 19 PLL_USBOTG, /* OTG USB PLL */
20 PLL_ENET, /* ENET PLL */ 20 PLL_ENET, /* ENET PLL */
21 PLL_AUDIO, /* AUDIO PLL */ 21 PLL_AUDIO, /* AUDIO PLL */
22 PLL_VIDEO, /* AUDIO PLL */ 22 PLL_VIDEO, /* AUDIO PLL */
23 }; 23 };
24 24
25 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 25 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
26 26
27 #ifdef CONFIG_MXC_OCOTP 27 #ifdef CONFIG_MXC_OCOTP
28 void enable_ocotp_clk(unsigned char enable) 28 void enable_ocotp_clk(unsigned char enable)
29 { 29 {
30 u32 reg; 30 u32 reg;
31 31
32 reg = __raw_readl(&imx_ccm->CCGR2); 32 reg = __raw_readl(&imx_ccm->CCGR2);
33 if (enable) 33 if (enable)
34 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK; 34 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
35 else 35 else
36 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK; 36 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
37 __raw_writel(reg, &imx_ccm->CCGR2); 37 __raw_writel(reg, &imx_ccm->CCGR2);
38 } 38 }
39 #endif 39 #endif
40 40
41 #ifdef CONFIG_NAND_MXS 41 #ifdef CONFIG_NAND_MXS
42 void setup_gpmi_io_clk(u32 cfg) 42 void setup_gpmi_io_clk(u32 cfg)
43 { 43 {
44 /* Disable clocks per ERR007177 from MX6 errata */ 44 /* Disable clocks per ERR007177 from MX6 errata */
45 clrbits_le32(&imx_ccm->CCGR4, 45 clrbits_le32(&imx_ccm->CCGR4,
46 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 46 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
48 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 48 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
49 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 49 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
50 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); 50 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
51 51
52 #if defined(CONFIG_MX6SX) 52 #if defined(CONFIG_MX6SX)
53 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); 53 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
54 54
55 clrsetbits_le32(&imx_ccm->cs2cdr, 55 clrsetbits_le32(&imx_ccm->cs2cdr,
56 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | 56 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
57 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | 57 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
58 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK, 58 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
59 cfg); 59 cfg);
60 60
61 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); 61 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
62 #elif defined(CONFIG_MX6UL) 62 #elif defined(CONFIG_MX6UL)
63 /* 63 /*
64 * config gpmi and bch clock to 100 MHz 64 * config gpmi and bch clock to 100 MHz
65 * bch/gpmi select PLL2 PFD2 400M 65 * bch/gpmi select PLL2 PFD2 400M
66 * 100M = 400M / 4 66 * 100M = 400M / 4
67 */ 67 */
68 clrbits_le32(&imx_ccm->cscmr1, 68 clrbits_le32(&imx_ccm->cscmr1,
69 MXC_CCM_CSCMR1_BCH_CLK_SEL | 69 MXC_CCM_CSCMR1_BCH_CLK_SEL |
70 MXC_CCM_CSCMR1_GPMI_CLK_SEL); 70 MXC_CCM_CSCMR1_GPMI_CLK_SEL);
71 clrsetbits_le32(&imx_ccm->cscdr1, 71 clrsetbits_le32(&imx_ccm->cscdr1,
72 MXC_CCM_CSCDR1_BCH_PODF_MASK | 72 MXC_CCM_CSCDR1_BCH_PODF_MASK |
73 MXC_CCM_CSCDR1_GPMI_PODF_MASK, 73 MXC_CCM_CSCDR1_GPMI_PODF_MASK,
74 cfg); 74 cfg);
75 #else 75 #else
76 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); 76 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
77 77
78 clrsetbits_le32(&imx_ccm->cs2cdr, 78 clrsetbits_le32(&imx_ccm->cs2cdr,
79 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 79 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
80 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 80 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
81 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 81 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
82 cfg); 82 cfg);
83 83
84 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); 84 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
85 #endif 85 #endif
86 setbits_le32(&imx_ccm->CCGR4, 86 setbits_le32(&imx_ccm->CCGR4,
87 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 87 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
88 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 88 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
89 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 89 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
90 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 90 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
91 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); 91 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
92 } 92 }
93 #endif 93 #endif
94 94
95 void enable_usboh3_clk(unsigned char enable) 95 void enable_usboh3_clk(unsigned char enable)
96 { 96 {
97 u32 reg; 97 u32 reg;
98 98
99 reg = __raw_readl(&imx_ccm->CCGR6); 99 reg = __raw_readl(&imx_ccm->CCGR6);
100 if (enable) 100 if (enable)
101 reg |= MXC_CCM_CCGR6_USBOH3_MASK; 101 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
102 else 102 else
103 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK); 103 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
104 __raw_writel(reg, &imx_ccm->CCGR6); 104 __raw_writel(reg, &imx_ccm->CCGR6);
105 105
106 } 106 }
107 107
108 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX) 108 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
109 void enable_enet_clk(unsigned char enable) 109 void enable_enet_clk(unsigned char enable)
110 { 110 {
111 u32 mask, *addr; 111 u32 mask, *addr;
112 112
113 if (is_cpu_type(MXC_CPU_MX6ULL)) { 113 if (is_cpu_type(MXC_CPU_MX6ULL)) {
114 mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK; 114 mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
115 addr = &imx_ccm->CCGR0; 115 addr = &imx_ccm->CCGR0;
116 } else if (is_cpu_type(MXC_CPU_MX6UL)) { 116 } else if (is_cpu_type(MXC_CPU_MX6UL)) {
117 mask = MXC_CCM_CCGR3_ENET_MASK; 117 mask = MXC_CCM_CCGR3_ENET_MASK;
118 addr = &imx_ccm->CCGR3; 118 addr = &imx_ccm->CCGR3;
119 } else { 119 } else {
120 mask = MXC_CCM_CCGR1_ENET_MASK; 120 mask = MXC_CCM_CCGR1_ENET_MASK;
121 addr = &imx_ccm->CCGR1; 121 addr = &imx_ccm->CCGR1;
122 } 122 }
123 123
124 if (enable) 124 if (enable)
125 setbits_le32(addr, mask); 125 setbits_le32(addr, mask);
126 else 126 else
127 clrbits_le32(addr, mask); 127 clrbits_le32(addr, mask);
128 } 128 }
129 #endif 129 #endif
130 130
131 #ifdef CONFIG_MXC_UART 131 #ifdef CONFIG_MXC_UART
132 void enable_uart_clk(unsigned char enable) 132 void enable_uart_clk(unsigned char enable)
133 { 133 {
134 u32 mask; 134 u32 mask;
135 135
136 if (is_cpu_type(MXC_CPU_MX6UL)) 136 if (is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL))
137 mask = MXC_CCM_CCGR5_UART_MASK; 137 mask = MXC_CCM_CCGR5_UART_MASK;
138 else 138 else
139 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK; 139 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
140 140
141 if (enable) 141 if (enable)
142 setbits_le32(&imx_ccm->CCGR5, mask); 142 setbits_le32(&imx_ccm->CCGR5, mask);
143 else 143 else
144 clrbits_le32(&imx_ccm->CCGR5, mask); 144 clrbits_le32(&imx_ccm->CCGR5, mask);
145 } 145 }
146 #endif 146 #endif
147 147
148 #ifdef CONFIG_MMC 148 #ifdef CONFIG_MMC
149 int enable_usdhc_clk(unsigned char enable, unsigned bus_num) 149 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
150 { 150 {
151 u32 mask; 151 u32 mask;
152 152
153 if (bus_num > 3) 153 if (bus_num > 3)
154 return -EINVAL; 154 return -EINVAL;
155 155
156 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2); 156 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
157 if (enable) 157 if (enable)
158 setbits_le32(&imx_ccm->CCGR6, mask); 158 setbits_le32(&imx_ccm->CCGR6, mask);
159 else 159 else
160 clrbits_le32(&imx_ccm->CCGR6, mask); 160 clrbits_le32(&imx_ccm->CCGR6, mask);
161 161
162 return 0; 162 return 0;
163 } 163 }
164 #endif 164 #endif
165 165
166 #ifdef CONFIG_SYS_I2C_MXC 166 #ifdef CONFIG_SYS_I2C_MXC
167 /* i2c_num can be from 0 - 3 */ 167 /* i2c_num can be from 0 - 3 */
168 int enable_i2c_clk(unsigned char enable, unsigned i2c_num) 168 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
169 { 169 {
170 u32 reg; 170 u32 reg;
171 u32 mask; 171 u32 mask;
172 u32 *addr; 172 u32 *addr;
173 173
174 if (i2c_num > 3) 174 if (i2c_num > 3)
175 return -EINVAL; 175 return -EINVAL;
176 if (i2c_num < 3) { 176 if (i2c_num < 3) {
177 mask = MXC_CCM_CCGR_CG_MASK 177 mask = MXC_CCM_CCGR_CG_MASK
178 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 178 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
179 + (i2c_num << 1)); 179 + (i2c_num << 1));
180 reg = __raw_readl(&imx_ccm->CCGR2); 180 reg = __raw_readl(&imx_ccm->CCGR2);
181 if (enable) 181 if (enable)
182 reg |= mask; 182 reg |= mask;
183 else 183 else
184 reg &= ~mask; 184 reg &= ~mask;
185 __raw_writel(reg, &imx_ccm->CCGR2); 185 __raw_writel(reg, &imx_ccm->CCGR2);
186 } else { 186 } else {
187 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) { 187 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
188 is_cpu_type(MXC_CPU_MX6ULL)) {
188 mask = MXC_CCM_CCGR6_I2C4_MASK; 189 mask = MXC_CCM_CCGR6_I2C4_MASK;
189 addr = &imx_ccm->CCGR6; 190 addr = &imx_ccm->CCGR6;
190 } else { 191 } else {
191 mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK; 192 mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
192 addr = &imx_ccm->CCGR1; 193 addr = &imx_ccm->CCGR1;
193 } 194 }
194 reg = __raw_readl(addr); 195 reg = __raw_readl(addr);
195 if (enable) 196 if (enable)
196 reg |= mask; 197 reg |= mask;
197 else 198 else
198 reg &= ~mask; 199 reg &= ~mask;
199 __raw_writel(reg, addr); 200 __raw_writel(reg, addr);
200 } 201 }
201 return 0; 202 return 0;
202 } 203 }
203 #endif 204 #endif
204 205
205 /* spi_num can be from 0 - SPI_MAX_NUM */ 206 /* spi_num can be from 0 - SPI_MAX_NUM */
206 int enable_spi_clk(unsigned char enable, unsigned spi_num) 207 int enable_spi_clk(unsigned char enable, unsigned spi_num)
207 { 208 {
208 u32 reg; 209 u32 reg;
209 u32 mask; 210 u32 mask;
210 211
211 if (spi_num > SPI_MAX_NUM) 212 if (spi_num > SPI_MAX_NUM)
212 return -EINVAL; 213 return -EINVAL;
213 214
214 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1); 215 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
215 reg = __raw_readl(&imx_ccm->CCGR1); 216 reg = __raw_readl(&imx_ccm->CCGR1);
216 if (enable) 217 if (enable)
217 reg |= mask; 218 reg |= mask;
218 else 219 else
219 reg &= ~mask; 220 reg &= ~mask;
220 __raw_writel(reg, &imx_ccm->CCGR1); 221 __raw_writel(reg, &imx_ccm->CCGR1);
221 return 0; 222 return 0;
222 } 223 }
223 static u32 decode_pll(enum pll_clocks pll, u32 infreq) 224 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
224 { 225 {
225 u32 div, test_div, pll_num, pll_denom; 226 u32 div, test_div, pll_num, pll_denom;
226 227
227 switch (pll) { 228 switch (pll) {
228 case PLL_SYS: 229 case PLL_SYS:
229 div = __raw_readl(&imx_ccm->analog_pll_sys); 230 div = __raw_readl(&imx_ccm->analog_pll_sys);
230 div &= BM_ANADIG_PLL_SYS_DIV_SELECT; 231 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
231 232
232 return (infreq * div) >> 1; 233 return (infreq * div) >> 1;
233 case PLL_BUS: 234 case PLL_BUS:
234 div = __raw_readl(&imx_ccm->analog_pll_528); 235 div = __raw_readl(&imx_ccm->analog_pll_528);
235 div &= BM_ANADIG_PLL_528_DIV_SELECT; 236 div &= BM_ANADIG_PLL_528_DIV_SELECT;
236 237
237 return infreq * (20 + (div << 1)); 238 return infreq * (20 + (div << 1));
238 case PLL_USBOTG: 239 case PLL_USBOTG:
239 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); 240 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
240 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT; 241 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
241 242
242 return infreq * (20 + (div << 1)); 243 return infreq * (20 + (div << 1));
243 case PLL_ENET: 244 case PLL_ENET:
244 div = __raw_readl(&imx_ccm->analog_pll_enet); 245 div = __raw_readl(&imx_ccm->analog_pll_enet);
245 div &= BM_ANADIG_PLL_ENET_DIV_SELECT; 246 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
246 247
247 return 25000000 * (div + (div >> 1) + 1); 248 return 25000000 * (div + (div >> 1) + 1);
248 case PLL_AUDIO: 249 case PLL_AUDIO:
249 div = __raw_readl(&imx_ccm->analog_pll_audio); 250 div = __raw_readl(&imx_ccm->analog_pll_audio);
250 if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE)) 251 if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
251 return 0; 252 return 0;
252 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */ 253 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
253 if (div & BM_ANADIG_PLL_AUDIO_BYPASS) 254 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
254 return MXC_HCLK; 255 return MXC_HCLK;
255 pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num); 256 pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
256 pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom); 257 pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
257 test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >> 258 test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
258 BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT; 259 BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
259 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT; 260 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
260 if (test_div == 3) { 261 if (test_div == 3) {
261 debug("Error test_div\n"); 262 debug("Error test_div\n");
262 return 0; 263 return 0;
263 } 264 }
264 test_div = 1 << (2 - test_div); 265 test_div = 1 << (2 - test_div);
265 266
266 return infreq * (div + pll_num / pll_denom) / test_div; 267 return infreq * (div + pll_num / pll_denom) / test_div;
267 case PLL_VIDEO: 268 case PLL_VIDEO:
268 div = __raw_readl(&imx_ccm->analog_pll_video); 269 div = __raw_readl(&imx_ccm->analog_pll_video);
269 if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE)) 270 if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
270 return 0; 271 return 0;
271 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */ 272 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
272 if (div & BM_ANADIG_PLL_VIDEO_BYPASS) 273 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
273 return MXC_HCLK; 274 return MXC_HCLK;
274 pll_num = __raw_readl(&imx_ccm->analog_pll_video_num); 275 pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
275 pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom); 276 pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
276 test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >> 277 test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
277 BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT; 278 BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
278 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT; 279 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
279 if (test_div == 3) { 280 if (test_div == 3) {
280 debug("Error test_div\n"); 281 debug("Error test_div\n");
281 return 0; 282 return 0;
282 } 283 }
283 test_div = 1 << (2 - test_div); 284 test_div = 1 << (2 - test_div);
284 285
285 return infreq * (div + pll_num / pll_denom) / test_div; 286 return infreq * (div + pll_num / pll_denom) / test_div;
286 default: 287 default:
287 return 0; 288 return 0;
288 } 289 }
289 /* NOTREACHED */ 290 /* NOTREACHED */
290 } 291 }
291 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) 292 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
292 { 293 {
293 u32 div; 294 u32 div;
294 u64 freq; 295 u64 freq;
295 296
296 switch (pll) { 297 switch (pll) {
297 case PLL_BUS: 298 case PLL_BUS:
298 if (!is_cpu_type(MXC_CPU_MX6UL)) { 299 if (!is_cpu_type(MXC_CPU_MX6UL) &&
300 !is_cpu_type(MXC_CPU_MX6ULL)) {
299 if (pfd_num == 3) { 301 if (pfd_num == 3) {
300 /* No PFD3 on PPL2 */ 302 /* No PFD3 on PPL2 */
301 return 0; 303 return 0;
302 } 304 }
303 } 305 }
304 div = __raw_readl(&imx_ccm->analog_pfd_528); 306 div = __raw_readl(&imx_ccm->analog_pfd_528);
305 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK); 307 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
306 break; 308 break;
307 case PLL_USBOTG: 309 case PLL_USBOTG:
308 div = __raw_readl(&imx_ccm->analog_pfd_480); 310 div = __raw_readl(&imx_ccm->analog_pfd_480);
309 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK); 311 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
310 break; 312 break;
311 default: 313 default:
312 /* No PFD on other PLL */ 314 /* No PFD on other PLL */
313 return 0; 315 return 0;
314 } 316 }
315 317
316 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >> 318 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
317 ANATOP_PFD_FRAC_SHIFT(pfd_num)); 319 ANATOP_PFD_FRAC_SHIFT(pfd_num));
318 } 320 }
319 321
320 static u32 get_mcu_main_clk(void) 322 static u32 get_mcu_main_clk(void)
321 { 323 {
322 u32 reg, freq; 324 u32 reg, freq;
323 325
324 reg = __raw_readl(&imx_ccm->cacrr); 326 reg = __raw_readl(&imx_ccm->cacrr);
325 reg &= MXC_CCM_CACRR_ARM_PODF_MASK; 327 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
326 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET; 328 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
327 freq = decode_pll(PLL_SYS, MXC_HCLK); 329 freq = decode_pll(PLL_SYS, MXC_HCLK);
328 330
329 return freq / (reg + 1); 331 return freq / (reg + 1);
330 } 332 }
331 333
332 u32 get_periph_clk(void) 334 u32 get_periph_clk(void)
333 { 335 {
334 u32 reg, div = 0, freq = 0; 336 u32 reg, div = 0, freq = 0;
335 337
336 reg = __raw_readl(&imx_ccm->cbcdr); 338 reg = __raw_readl(&imx_ccm->cbcdr);
337 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { 339 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
338 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> 340 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
339 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET; 341 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
340 reg = __raw_readl(&imx_ccm->cbcmr); 342 reg = __raw_readl(&imx_ccm->cbcmr);
341 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK; 343 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
342 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET; 344 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
343 345
344 switch (reg) { 346 switch (reg) {
345 case 0: 347 case 0:
346 freq = decode_pll(PLL_USBOTG, MXC_HCLK); 348 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
347 break; 349 break;
348 case 1: 350 case 1:
349 case 2: 351 case 2:
350 freq = MXC_HCLK; 352 freq = MXC_HCLK;
351 break; 353 break;
352 default: 354 default:
353 break; 355 break;
354 } 356 }
355 } else { 357 } else {
356 reg = __raw_readl(&imx_ccm->cbcmr); 358 reg = __raw_readl(&imx_ccm->cbcmr);
357 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK; 359 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
358 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET; 360 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
359 361
360 switch (reg) { 362 switch (reg) {
361 case 0: 363 case 0:
362 freq = decode_pll(PLL_BUS, MXC_HCLK); 364 freq = decode_pll(PLL_BUS, MXC_HCLK);
363 break; 365 break;
364 case 1: 366 case 1:
365 freq = mxc_get_pll_pfd(PLL_BUS, 2); 367 freq = mxc_get_pll_pfd(PLL_BUS, 2);
366 break; 368 break;
367 case 2: 369 case 2:
368 freq = mxc_get_pll_pfd(PLL_BUS, 0); 370 freq = mxc_get_pll_pfd(PLL_BUS, 0);
369 break; 371 break;
370 case 3: 372 case 3:
371 /* static / 2 divider */ 373 /* static / 2 divider */
372 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; 374 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
373 break; 375 break;
374 default: 376 default:
375 break; 377 break;
376 } 378 }
377 } 379 }
378 380
379 return freq / (div + 1); 381 return freq / (div + 1);
380 } 382 }
381 383
382 static u32 get_ipg_clk(void) 384 static u32 get_ipg_clk(void)
383 { 385 {
384 u32 reg, ipg_podf; 386 u32 reg, ipg_podf;
385 387
386 reg = __raw_readl(&imx_ccm->cbcdr); 388 reg = __raw_readl(&imx_ccm->cbcdr);
387 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK; 389 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
388 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET; 390 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
389 391
390 return get_ahb_clk() / (ipg_podf + 1); 392 return get_ahb_clk() / (ipg_podf + 1);
391 } 393 }
392 394
393 static u32 get_ipg_per_clk(void) 395 static u32 get_ipg_per_clk(void)
394 { 396 {
395 u32 reg, perclk_podf; 397 u32 reg, perclk_podf;
396 398
397 reg = __raw_readl(&imx_ccm->cscmr1); 399 reg = __raw_readl(&imx_ccm->cscmr1);
398 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || 400 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
399 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) { 401 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) ||
402 is_cpu_type(MXC_CPU_MX6ULL)) {
400 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) 403 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
401 return MXC_HCLK; /* OSC 24Mhz */ 404 return MXC_HCLK; /* OSC 24Mhz */
402 } 405 }
403 406
404 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; 407 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
405 408
406 return get_ipg_clk() / (perclk_podf + 1); 409 return get_ipg_clk() / (perclk_podf + 1);
407 } 410 }
408 411
409 static u32 get_uart_clk(void) 412 static u32 get_uart_clk(void)
410 { 413 {
411 u32 reg, uart_podf; 414 u32 reg, uart_podf;
412 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ 415 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
413 reg = __raw_readl(&imx_ccm->cscdr1); 416 reg = __raw_readl(&imx_ccm->cscdr1);
414 417
415 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || 418 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
416 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) { 419 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) ||
420 is_cpu_type(MXC_CPU_MX6ULL)) {
417 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) 421 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
418 freq = MXC_HCLK; 422 freq = MXC_HCLK;
419 } 423 }
420 424
421 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; 425 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
422 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; 426 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
423 427
424 return freq / (uart_podf + 1); 428 return freq / (uart_podf + 1);
425 } 429 }
426 430
427 static u32 get_cspi_clk(void) 431 static u32 get_cspi_clk(void)
428 { 432 {
429 u32 reg, cspi_podf; 433 u32 reg, cspi_podf;
430 434
431 reg = __raw_readl(&imx_ccm->cscdr2); 435 reg = __raw_readl(&imx_ccm->cscdr2);
432 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >> 436 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
433 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; 437 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
434 438
435 if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) || 439 if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
436 is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) { 440 is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
441 is_cpu_type(MXC_CPU_MX6ULL)) {
437 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK) 442 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
438 return MXC_HCLK / (cspi_podf + 1); 443 return MXC_HCLK / (cspi_podf + 1);
439 } 444 }
440 445
441 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1)); 446 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
442 } 447 }
443 448
444 static u32 get_axi_clk(void) 449 static u32 get_axi_clk(void)
445 { 450 {
446 u32 root_freq, axi_podf; 451 u32 root_freq, axi_podf;
447 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); 452 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
448 453
449 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK; 454 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
450 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET; 455 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
451 456
452 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { 457 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
453 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) 458 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
454 root_freq = mxc_get_pll_pfd(PLL_BUS, 2); 459 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
455 else 460 else
456 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); 461 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
457 } else 462 } else
458 root_freq = get_periph_clk(); 463 root_freq = get_periph_clk();
459 464
460 return root_freq / (axi_podf + 1); 465 return root_freq / (axi_podf + 1);
461 } 466 }
462 467
463 static u32 get_emi_slow_clk(void) 468 static u32 get_emi_slow_clk(void)
464 { 469 {
465 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0; 470 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
466 471
467 cscmr1 = __raw_readl(&imx_ccm->cscmr1); 472 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
468 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK; 473 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
469 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET; 474 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
470 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; 475 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
471 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET; 476 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
472 477
473 switch (emi_clk_sel) { 478 switch (emi_clk_sel) {
474 case 0: 479 case 0:
475 root_freq = get_axi_clk(); 480 root_freq = get_axi_clk();
476 break; 481 break;
477 case 1: 482 case 1:
478 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); 483 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
479 break; 484 break;
480 case 2: 485 case 2:
481 root_freq = mxc_get_pll_pfd(PLL_BUS, 2); 486 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
482 break; 487 break;
483 case 3: 488 case 3:
484 root_freq = mxc_get_pll_pfd(PLL_BUS, 0); 489 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
485 break; 490 break;
486 } 491 }
487 492
488 return root_freq / (emi_slow_podf + 1); 493 return root_freq / (emi_slow_podf + 1);
489 } 494 }
490 495
491 static u32 get_mmdc_ch0_clk(void) 496 static u32 get_mmdc_ch0_clk(void)
492 { 497 {
493 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr); 498 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
494 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); 499 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
495 500
496 u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div; 501 u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
497 502
498 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || 503 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
499 is_cpu_type(MXC_CPU_MX6SL)) { 504 is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6ULL)) {
500 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >> 505 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
501 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET; 506 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
502 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { 507 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
503 per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >> 508 per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
504 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET; 509 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
505 if (is_cpu_type(MXC_CPU_MX6SL)) { 510 if (is_cpu_type(MXC_CPU_MX6SL)) {
506 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL) 511 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
507 freq = MXC_HCLK; 512 freq = MXC_HCLK;
508 else 513 else
509 freq = decode_pll(PLL_USBOTG, MXC_HCLK); 514 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
510 } else { 515 } else {
511 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL) 516 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
512 freq = decode_pll(PLL_BUS, MXC_HCLK); 517 freq = decode_pll(PLL_BUS, MXC_HCLK);
513 else 518 else
514 freq = decode_pll(PLL_USBOTG, MXC_HCLK); 519 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
515 } 520 }
516 } else { 521 } else {
517 per2_clk2_podf = 0; 522 per2_clk2_podf = 0;
518 switch ((cbcmr & 523 switch ((cbcmr &
519 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >> 524 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
520 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) { 525 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
521 case 0: 526 case 0:
522 freq = decode_pll(PLL_BUS, MXC_HCLK); 527 freq = decode_pll(PLL_BUS, MXC_HCLK);
523 break; 528 break;
524 case 1: 529 case 1:
525 freq = mxc_get_pll_pfd(PLL_BUS, 2); 530 freq = mxc_get_pll_pfd(PLL_BUS, 2);
526 break; 531 break;
527 case 2: 532 case 2:
528 freq = mxc_get_pll_pfd(PLL_BUS, 0); 533 freq = mxc_get_pll_pfd(PLL_BUS, 0);
529 break; 534 break;
530 case 3: 535 case 3:
531 pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2)); 536 pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
532 switch (pmu_misc2_audio_div) { 537 switch (pmu_misc2_audio_div) {
533 case 0: 538 case 0:
534 case 2: 539 case 2:
535 pmu_misc2_audio_div = 1; 540 pmu_misc2_audio_div = 1;
536 break; 541 break;
537 case 1: 542 case 1:
538 pmu_misc2_audio_div = 2; 543 pmu_misc2_audio_div = 2;
539 break; 544 break;
540 case 3: 545 case 3:
541 pmu_misc2_audio_div = 4; 546 pmu_misc2_audio_div = 4;
542 break; 547 break;
543 } 548 }
544 freq = decode_pll(PLL_AUDIO, MXC_HCLK) / 549 freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
545 pmu_misc2_audio_div; 550 pmu_misc2_audio_div;
546 break; 551 break;
547 } 552 }
548 } 553 }
549 return freq / (podf + 1) / (per2_clk2_podf + 1); 554 return freq / (podf + 1) / (per2_clk2_podf + 1);
550 } else { 555 } else {
551 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >> 556 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
552 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET; 557 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
553 return get_periph_clk() / (podf + 1); 558 return get_periph_clk() / (podf + 1);
554 } 559 }
555 } 560 }
556 561
557 #if defined(CONFIG_VIDEO_MXS) 562 #if defined(CONFIG_VIDEO_MXS)
558 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, 563 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
559 u32 post_div) 564 u32 post_div)
560 { 565 {
561 u32 reg = 0; 566 u32 reg = 0;
562 ulong start; 567 ulong start;
563 568
564 debug("pll5 div = %d, num = %d, denom = %d\n", 569 debug("pll5 div = %d, num = %d, denom = %d\n",
565 pll_div, pll_num, pll_denom); 570 pll_div, pll_num, pll_denom);
566 571
567 /* Power up PLL5 video */ 572 /* Power up PLL5 video */
568 writel(BM_ANADIG_PLL_VIDEO_POWERDOWN | 573 writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
569 BM_ANADIG_PLL_VIDEO_BYPASS | 574 BM_ANADIG_PLL_VIDEO_BYPASS |
570 BM_ANADIG_PLL_VIDEO_DIV_SELECT | 575 BM_ANADIG_PLL_VIDEO_DIV_SELECT |
571 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT, 576 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
572 &imx_ccm->analog_pll_video_clr); 577 &imx_ccm->analog_pll_video_clr);
573 578
574 /* Set div, num and denom */ 579 /* Set div, num and denom */
575 switch (post_div) { 580 switch (post_div) {
576 case 1: 581 case 1:
577 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | 582 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
578 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2), 583 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
579 &imx_ccm->analog_pll_video_set); 584 &imx_ccm->analog_pll_video_set);
580 break; 585 break;
581 case 2: 586 case 2:
582 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | 587 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
583 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1), 588 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
584 &imx_ccm->analog_pll_video_set); 589 &imx_ccm->analog_pll_video_set);
585 break; 590 break;
586 case 4: 591 case 4:
587 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | 592 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
588 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0), 593 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
589 &imx_ccm->analog_pll_video_set); 594 &imx_ccm->analog_pll_video_set);
590 break; 595 break;
591 default: 596 default:
592 puts("Wrong test_div!\n"); 597 puts("Wrong test_div!\n");
593 return -EINVAL; 598 return -EINVAL;
594 } 599 }
595 600
596 writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num), 601 writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
597 &imx_ccm->analog_pll_video_num); 602 &imx_ccm->analog_pll_video_num);
598 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom), 603 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
599 &imx_ccm->analog_pll_video_denom); 604 &imx_ccm->analog_pll_video_denom);
600 605
601 /* Wait PLL5 lock */ 606 /* Wait PLL5 lock */
602 start = get_timer(0); /* Get current timestamp */ 607 start = get_timer(0); /* Get current timestamp */
603 608
604 do { 609 do {
605 reg = readl(&imx_ccm->analog_pll_video); 610 reg = readl(&imx_ccm->analog_pll_video);
606 if (reg & BM_ANADIG_PLL_VIDEO_LOCK) { 611 if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
607 /* Enable PLL out */ 612 /* Enable PLL out */
608 writel(BM_ANADIG_PLL_VIDEO_ENABLE, 613 writel(BM_ANADIG_PLL_VIDEO_ENABLE,
609 &imx_ccm->analog_pll_video_set); 614 &imx_ccm->analog_pll_video_set);
610 return 0; 615 return 0;
611 } 616 }
612 } while (get_timer(0) < (start + 10)); /* Wait 10ms */ 617 } while (get_timer(0) < (start + 10)); /* Wait 10ms */
613 618
614 puts("Lock PLL5 timeout\n"); 619 puts("Lock PLL5 timeout\n");
615 620
616 return -ETIME; 621 return -ETIME;
617 } 622 }
618 623
619 /* 624 /*
620 * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD 625 * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
621 * 626 *
622 * 'freq' using KHz as unit, see driver/video/mxsfb.c. 627 * 'freq' using KHz as unit, see driver/video/mxsfb.c.
623 */ 628 */
624 void mxs_set_lcdclk(u32 base_addr, u32 freq) 629 void mxs_set_lcdclk(u32 base_addr, u32 freq)
625 { 630 {
626 u32 reg = 0; 631 u32 reg = 0;
627 u32 hck = MXC_HCLK / 1000; 632 u32 hck = MXC_HCLK / 1000;
628 /* DIV_SELECT ranges from 27 to 54 */ 633 /* DIV_SELECT ranges from 27 to 54 */
629 u32 min = hck * 27; 634 u32 min = hck * 27;
630 u32 max = hck * 54; 635 u32 max = hck * 54;
631 u32 temp, best = 0; 636 u32 temp, best = 0;
632 u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1; 637 u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
633 u32 pll_div, pll_num, pll_denom, post_div = 1; 638 u32 pll_div, pll_num, pll_denom, post_div = 1;
634 639
635 debug("mxs_set_lcdclk, freq = %dKHz\n", freq); 640 debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
636 641
637 if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) { 642 if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL) &&
643 !is_cpu_type(MXC_CPU_MX6ULL)) {
638 debug("This chip not support lcd!\n"); 644 debug("This chip not support lcd!\n");
639 return; 645 return;
640 } 646 }
641 647
642 if (base_addr == LCDIF1_BASE_ADDR) { 648 if (base_addr == LCDIF1_BASE_ADDR) {
643 reg = readl(&imx_ccm->cscdr2); 649 reg = readl(&imx_ccm->cscdr2);
644 /* Can't change clocks when clock not from pre-mux */ 650 /* Can't change clocks when clock not from pre-mux */
645 if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0) 651 if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
646 return; 652 return;
647 } 653 }
648 654
649 if (is_cpu_type(MXC_CPU_MX6SX)) { 655 if (is_cpu_type(MXC_CPU_MX6SX)) {
650 reg = readl(&imx_ccm->cscdr2); 656 reg = readl(&imx_ccm->cscdr2);
651 /* Can't change clocks when clock not from pre-mux */ 657 /* Can't change clocks when clock not from pre-mux */
652 if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0) 658 if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
653 return; 659 return;
654 } 660 }
655 661
656 temp = freq * max_pred * max_postd; 662 temp = freq * max_pred * max_postd;
657 if (temp < min) { 663 if (temp < min) {
658 /* 664 /*
659 * Register: PLL_VIDEO 665 * Register: PLL_VIDEO
660 * Bit Field: POST_DIV_SELECT 666 * Bit Field: POST_DIV_SELECT
661 * 00 — Divide by 4. 667 * 00 — Divide by 4.
662 * 01 — Divide by 2. 668 * 01 — Divide by 2.
663 * 10 — Divide by 1. 669 * 10 — Divide by 1.
664 * 11 — Reserved 670 * 11 — Reserved
665 * No need to check post_div(1) 671 * No need to check post_div(1)
666 */ 672 */
667 for (post_div = 2; post_div <= 4; post_div <<= 1) { 673 for (post_div = 2; post_div <= 4; post_div <<= 1) {
668 if ((temp * post_div) > min) { 674 if ((temp * post_div) > min) {
669 freq *= post_div; 675 freq *= post_div;
670 break; 676 break;
671 } 677 }
672 } 678 }
673 679
674 if (post_div > 4) { 680 if (post_div > 4) {
675 printf("Fail to set rate to %dkhz", freq); 681 printf("Fail to set rate to %dkhz", freq);
676 return; 682 return;
677 } 683 }
678 } 684 }
679 685
680 /* Choose the best pred and postd to match freq for lcd */ 686 /* Choose the best pred and postd to match freq for lcd */
681 for (i = 1; i <= max_pred; i++) { 687 for (i = 1; i <= max_pred; i++) {
682 for (j = 1; j <= max_postd; j++) { 688 for (j = 1; j <= max_postd; j++) {
683 temp = freq * i * j; 689 temp = freq * i * j;
684 if (temp > max || temp < min) 690 if (temp > max || temp < min)
685 continue; 691 continue;
686 if (best == 0 || temp < best) { 692 if (best == 0 || temp < best) {
687 best = temp; 693 best = temp;
688 pred = i; 694 pred = i;
689 postd = j; 695 postd = j;
690 } 696 }
691 } 697 }
692 } 698 }
693 699
694 if (best == 0) { 700 if (best == 0) {
695 printf("Fail to set rate to %dKHz", freq); 701 printf("Fail to set rate to %dKHz", freq);
696 return; 702 return;
697 } 703 }
698 704
699 debug("best %d, pred = %d, postd = %d\n", best, pred, postd); 705 debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
700 706
701 pll_div = best / hck; 707 pll_div = best / hck;
702 pll_denom = 1000000; 708 pll_denom = 1000000;
703 pll_num = (best - hck * pll_div) * pll_denom / hck; 709 pll_num = (best - hck * pll_div) * pll_denom / hck;
704 710
705 /* 711 /*
706 * pll_num 712 * pll_num
707 * (24MHz * (pll_div + --------- )) 713 * (24MHz * (pll_div + --------- ))
708 * pll_denom 714 * pll_denom
709 *freq KHz = -------------------------------- 715 *freq KHz = --------------------------------
710 * post_div * pred * postd * 1000 716 * post_div * pred * postd * 1000
711 */ 717 */
712 718
713 if (base_addr == LCDIF1_BASE_ADDR) { 719 if (base_addr == LCDIF1_BASE_ADDR) {
714 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) 720 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
715 return; 721 return;
716 722
717 /* Select pre-lcd clock to PLL5 and set pre divider */ 723 /* Select pre-lcd clock to PLL5 and set pre divider */
718 clrsetbits_le32(&imx_ccm->cscdr2, 724 clrsetbits_le32(&imx_ccm->cscdr2,
719 MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK | 725 MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
720 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK, 726 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
721 (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) | 727 (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
722 ((pred - 1) << 728 ((pred - 1) <<
723 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET)); 729 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
724 730
725 /* Set the post divider */ 731 /* Set the post divider */
726 clrsetbits_le32(&imx_ccm->cbcmr, 732 clrsetbits_le32(&imx_ccm->cbcmr,
727 MXC_CCM_CBCMR_LCDIF1_PODF_MASK, 733 MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
728 ((postd - 1) << 734 ((postd - 1) <<
729 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET)); 735 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
730 } else if (is_cpu_type(MXC_CPU_MX6SX)) { 736 } else if (is_cpu_type(MXC_CPU_MX6SX)) {
731 /* Setting LCDIF2 for i.MX6SX */ 737 /* Setting LCDIF2 for i.MX6SX */
732 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) 738 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
733 return; 739 return;
734 740
735 /* Select pre-lcd clock to PLL5 and set pre divider */ 741 /* Select pre-lcd clock to PLL5 and set pre divider */
736 clrsetbits_le32(&imx_ccm->cscdr2, 742 clrsetbits_le32(&imx_ccm->cscdr2,
737 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK | 743 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
738 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK, 744 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
739 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) | 745 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
740 ((pred - 1) << 746 ((pred - 1) <<
741 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET)); 747 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
742 748
743 /* Set the post divider */ 749 /* Set the post divider */
744 clrsetbits_le32(&imx_ccm->cscmr1, 750 clrsetbits_le32(&imx_ccm->cscmr1,
745 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK, 751 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
746 ((postd - 1) << 752 ((postd - 1) <<
747 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET)); 753 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
748 } 754 }
749 } 755 }
750 756
751 int enable_lcdif_clock(u32 base_addr) 757 int enable_lcdif_clock(u32 base_addr)
752 { 758 {
753 u32 reg = 0; 759 u32 reg = 0;
754 u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask; 760 u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
755 761
756 if (is_cpu_type(MXC_CPU_MX6SX)) { 762 if (is_cpu_type(MXC_CPU_MX6SX)) {
757 if ((base_addr != LCDIF1_BASE_ADDR) && 763 if ((base_addr != LCDIF1_BASE_ADDR) &&
758 (base_addr != LCDIF2_BASE_ADDR)) { 764 (base_addr != LCDIF2_BASE_ADDR)) {
759 puts("Wrong LCD interface!\n"); 765 puts("Wrong LCD interface!\n");
760 return -EINVAL; 766 return -EINVAL;
761 } 767 }
762 /* Set to pre-mux clock at default */ 768 /* Set to pre-mux clock at default */
763 lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ? 769 lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
764 MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK : 770 MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
765 MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK; 771 MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
766 lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ? 772 lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
767 (MXC_CCM_CCGR3_LCDIF2_PIX_MASK | 773 (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
768 MXC_CCM_CCGR3_DISP_AXI_MASK) : 774 MXC_CCM_CCGR3_DISP_AXI_MASK) :
769 (MXC_CCM_CCGR3_LCDIF1_PIX_MASK | 775 (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
770 MXC_CCM_CCGR3_DISP_AXI_MASK); 776 MXC_CCM_CCGR3_DISP_AXI_MASK);
771 } else if (is_cpu_type(MXC_CPU_MX6UL)) { 777 } else if (is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) {
772 if (base_addr != LCDIF1_BASE_ADDR) { 778 if (base_addr != LCDIF1_BASE_ADDR) {
773 puts("Wrong LCD interface!\n"); 779 puts("Wrong LCD interface!\n");
774 return -EINVAL; 780 return -EINVAL;
775 } 781 }
776 /* Set to pre-mux clock at default */ 782 /* Set to pre-mux clock at default */
777 lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK; 783 lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
778 lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK; 784 lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
779 } else { 785 } else {
780 return 0; 786 return 0;
781 } 787 }
782 788
783 reg = readl(&imx_ccm->cscdr2); 789 reg = readl(&imx_ccm->cscdr2);
784 reg &= ~lcdif_clk_sel_mask; 790 reg &= ~lcdif_clk_sel_mask;
785 writel(reg, &imx_ccm->cscdr2); 791 writel(reg, &imx_ccm->cscdr2);
786 792
787 /* Enable the LCDIF pix clock */ 793 /* Enable the LCDIF pix clock */
788 reg = readl(&imx_ccm->CCGR3); 794 reg = readl(&imx_ccm->CCGR3);
789 reg |= lcdif_ccgr3_mask; 795 reg |= lcdif_ccgr3_mask;
790 writel(reg, &imx_ccm->CCGR3); 796 writel(reg, &imx_ccm->CCGR3);
791 797
792 reg = readl(&imx_ccm->CCGR2); 798 reg = readl(&imx_ccm->CCGR2);
793 reg |= MXC_CCM_CCGR2_LCD_MASK; 799 reg |= MXC_CCM_CCGR2_LCD_MASK;
794 writel(reg, &imx_ccm->CCGR2); 800 writel(reg, &imx_ccm->CCGR2);
795 801
796 return 0; 802 return 0;
797 } 803 }
798 804
799 int enable_lvds_bridge(u32 lcd_base_addr) 805 int enable_lvds_bridge(u32 lcd_base_addr)
800 { 806 {
801 u32 reg = 0; 807 u32 reg = 0;
802 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 808 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
803 809
804 if (is_cpu_type(MXC_CPU_MX6SX)) { 810 if (is_cpu_type(MXC_CPU_MX6SX)) {
805 if ((lcd_base_addr != LCDIF1_BASE_ADDR) && 811 if ((lcd_base_addr != LCDIF1_BASE_ADDR) &&
806 (lcd_base_addr != LCDIF2_BASE_ADDR)) { 812 (lcd_base_addr != LCDIF2_BASE_ADDR)) {
807 puts("Wrong LCD interface!\n"); 813 puts("Wrong LCD interface!\n");
808 return -EINVAL; 814 return -EINVAL;
809 } 815 }
810 } else { 816 } else {
811 debug("This chip not support lvds bridge!\n"); 817 debug("This chip not support lvds bridge!\n");
812 return 0; 818 return 0;
813 } 819 }
814 820
815 /* Turn on LDB DI0 clocks */ 821 /* Turn on LDB DI0 clocks */
816 reg = readl(&imx_ccm->CCGR3); 822 reg = readl(&imx_ccm->CCGR3);
817 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; 823 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
818 writel(reg, &imx_ccm->CCGR3); 824 writel(reg, &imx_ccm->CCGR3);
819 825
820 /* set LDB DI0 clk select to 011 PLL2 PFD3 200M*/ 826 /* set LDB DI0 clk select to 011 PLL2 PFD3 200M*/
821 reg = readl(&imx_ccm->cs2cdr); 827 reg = readl(&imx_ccm->cs2cdr);
822 reg &= ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK; 828 reg &= ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
823 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET); 829 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
824 writel(reg, &imx_ccm->cs2cdr); 830 writel(reg, &imx_ccm->cs2cdr);
825 831
826 reg = readl(&imx_ccm->cscmr2); 832 reg = readl(&imx_ccm->cscmr2);
827 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 833 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
828 writel(reg, &imx_ccm->cscmr2); 834 writel(reg, &imx_ccm->cscmr2);
829 835
830 /* set LDB DI0 clock for LCDIF PIX clock */ 836 /* set LDB DI0 clock for LCDIF PIX clock */
831 reg = readl(&imx_ccm->cscdr2); 837 reg = readl(&imx_ccm->cscdr2);
832 if (lcd_base_addr == LCDIF1_BASE_ADDR) { 838 if (lcd_base_addr == LCDIF1_BASE_ADDR) {
833 reg &= ~MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK; 839 reg &= ~MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
834 reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET); 840 reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET);
835 } else { 841 } else {
836 reg &= ~MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK; 842 reg &= ~MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK;
837 reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET); 843 reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET);
838 } 844 }
839 writel(reg, &imx_ccm->cscdr2); 845 writel(reg, &imx_ccm->cscdr2);
840 846
841 reg = IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 847 reg = IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
842 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 848 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
843 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 849 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
844 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 850 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
845 writel(reg, &iomux->gpr[6]); 851 writel(reg, &iomux->gpr[6]);
846 852
847 reg = readl(&iomux->gpr[5]); 853 reg = readl(&iomux->gpr[5]);
848 if (lcd_base_addr == LCDIF1_BASE_ADDR) 854 if (lcd_base_addr == LCDIF1_BASE_ADDR)
849 reg &= ~0x8; /* MUX LVDS to LCDIF1 */ 855 reg &= ~0x8; /* MUX LVDS to LCDIF1 */
850 else 856 else
851 reg |= 0x8; /* MUX LVDS to LCDIF2 */ 857 reg |= 0x8; /* MUX LVDS to LCDIF2 */
852 writel(reg, &iomux->gpr[5]); 858 writel(reg, &iomux->gpr[5]);
853 859
854 return 0; 860 return 0;
855 } 861 }
856 862
857 #endif 863 #endif
858 864
859 #ifdef CONFIG_FSL_QSPI 865 #ifdef CONFIG_FSL_QSPI
860 /* qspi_num can be from 0 - 1 */ 866 /* qspi_num can be from 0 - 1 */
861 void enable_qspi_clk(int qspi_num) 867 void enable_qspi_clk(int qspi_num)
862 { 868 {
863 u32 reg = 0; 869 u32 reg = 0;
864 /* Enable QuadSPI clock */ 870 /* Enable QuadSPI clock */
865 switch (qspi_num) { 871 switch (qspi_num) {
866 case 0: 872 case 0:
867 /* disable the clock gate */ 873 /* disable the clock gate */
868 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); 874 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
869 875
870 /* set 50M : (50 = 396 / 2 / 4) */ 876 /* set 50M : (50 = 396 / 2 / 4) */
871 reg = readl(&imx_ccm->cscmr1); 877 reg = readl(&imx_ccm->cscmr1);
872 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK | 878 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
873 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK); 879 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
874 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) | 880 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
875 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)); 881 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
876 writel(reg, &imx_ccm->cscmr1); 882 writel(reg, &imx_ccm->cscmr1);
877 883
878 /* enable the clock gate */ 884 /* enable the clock gate */
879 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); 885 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
880 break; 886 break;
881 case 1: 887 case 1:
882 /* 888 /*
883 * disable the clock gate 889 * disable the clock gate
884 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, 890 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
885 * disable both of them. 891 * disable both of them.
886 */ 892 */
887 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | 893 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
888 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); 894 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
889 895
890 /* set 50M : (50 = 396 / 2 / 4) */ 896 /* set 50M : (50 = 396 / 2 / 4) */
891 reg = readl(&imx_ccm->cs2cdr); 897 reg = readl(&imx_ccm->cs2cdr);
892 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | 898 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
893 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | 899 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
894 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK); 900 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
895 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) | 901 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
896 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3)); 902 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
897 writel(reg, &imx_ccm->cs2cdr); 903 writel(reg, &imx_ccm->cs2cdr);
898 904
899 /*enable the clock gate*/ 905 /*enable the clock gate*/
900 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | 906 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
901 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); 907 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
902 break; 908 break;
903 default: 909 default:
904 break; 910 break;
905 } 911 }
906 } 912 }
907 #endif 913 #endif
908 914
909 #if defined(CONFIG_VIDEO_GIS) 915 #if defined(CONFIG_VIDEO_GIS)
910 void mxs_set_vadcclk() 916 void mxs_set_vadcclk()
911 { 917 {
912 u32 reg = 0; 918 u32 reg = 0;
913 919
914 reg = readl(&imx_ccm->cscmr2); 920 reg = readl(&imx_ccm->cscmr2);
915 reg &= ~MXC_CCM_CSCMR2_VID_CLK_SEL_MASK; 921 reg &= ~MXC_CCM_CSCMR2_VID_CLK_SEL_MASK;
916 reg |= 0x19 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET; 922 reg |= 0x19 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET;
917 writel(reg, &imx_ccm->cscmr2); 923 writel(reg, &imx_ccm->cscmr2);
918 } 924 }
919 #endif 925 #endif
920 926
921 #ifdef CONFIG_FEC_MXC 927 #ifdef CONFIG_FEC_MXC
922 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) 928 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
923 { 929 {
924 u32 reg = 0; 930 u32 reg = 0;
925 s32 timeout = 100000; 931 s32 timeout = 100000;
926 932
927 struct anatop_regs __iomem *anatop = 933 struct anatop_regs __iomem *anatop =
928 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; 934 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
929 935
930 if (freq < ENET_25MHZ || freq > ENET_125MHZ) 936 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
931 return -EINVAL; 937 return -EINVAL;
932 938
933 reg = readl(&anatop->pll_enet); 939 reg = readl(&anatop->pll_enet);
934 940
935 if (fec_id == 0) { 941 if (fec_id == 0) {
936 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; 942 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
937 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); 943 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
938 } else if (fec_id == 1) { 944 } else if (fec_id == 1) {
939 /* Only i.MX6SX/UL support ENET2 */ 945 /* Only i.MX6SX/UL support ENET2 */
940 if (!(is_cpu_type(MXC_CPU_MX6SX) || 946 if (!(is_cpu_type(MXC_CPU_MX6SX) ||
941 is_cpu_type(MXC_CPU_MX6UL))) 947 is_cpu_type(MXC_CPU_MX6UL) ||
948 is_cpu_type(MXC_CPU_MX6ULL)))
942 return -EINVAL; 949 return -EINVAL;
943 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; 950 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
944 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); 951 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
945 } else { 952 } else {
946 return -EINVAL; 953 return -EINVAL;
947 } 954 }
948 955
949 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || 956 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
950 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { 957 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
951 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; 958 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
952 writel(reg, &anatop->pll_enet); 959 writel(reg, &anatop->pll_enet);
953 while (timeout--) { 960 while (timeout--) {
954 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) 961 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
955 break; 962 break;
956 } 963 }
957 if (timeout < 0) 964 if (timeout < 0)
958 return -ETIMEDOUT; 965 return -ETIMEDOUT;
959 } 966 }
960 967
961 /* Enable FEC clock */ 968 /* Enable FEC clock */
962 if (fec_id == 0) 969 if (fec_id == 0)
963 reg |= BM_ANADIG_PLL_ENET_ENABLE; 970 reg |= BM_ANADIG_PLL_ENET_ENABLE;
964 else 971 else
965 reg |= BM_ANADIG_PLL_ENET2_ENABLE; 972 reg |= BM_ANADIG_PLL_ENET2_ENABLE;
966 reg &= ~BM_ANADIG_PLL_ENET_BYPASS; 973 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
967 writel(reg, &anatop->pll_enet); 974 writel(reg, &anatop->pll_enet);
968 975
969 #ifdef CONFIG_MX6SX 976 #ifdef CONFIG_MX6SX
970 /* 977 /*
971 * Set enet ahb clock to 200MHz 978 * Set enet ahb clock to 200MHz
972 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB 979 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
973 */ 980 */
974 reg = readl(&imx_ccm->chsccdr); 981 reg = readl(&imx_ccm->chsccdr);
975 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK 982 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
976 | MXC_CCM_CHSCCDR_ENET_PODF_MASK 983 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
977 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK); 984 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
978 /* PLL2 PFD2 */ 985 /* PLL2 PFD2 */
979 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET); 986 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
980 /* Div = 2*/ 987 /* Div = 2*/
981 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET); 988 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
982 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET); 989 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
983 writel(reg, &imx_ccm->chsccdr); 990 writel(reg, &imx_ccm->chsccdr);
984 991
985 /* Enable enet system clock */ 992 /* Enable enet system clock */
986 reg = readl(&imx_ccm->CCGR3); 993 reg = readl(&imx_ccm->CCGR3);
987 reg |= MXC_CCM_CCGR3_ENET_MASK; 994 reg |= MXC_CCM_CCGR3_ENET_MASK;
988 writel(reg, &imx_ccm->CCGR3); 995 writel(reg, &imx_ccm->CCGR3);
989 #endif 996 #endif
990 return 0; 997 return 0;
991 } 998 }
992 #endif 999 #endif
993 1000
994 static u32 get_usdhc_clk(u32 port) 1001 static u32 get_usdhc_clk(u32 port)
995 { 1002 {
996 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0; 1003 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
997 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1); 1004 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
998 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1); 1005 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
999 1006
1000 switch (port) { 1007 switch (port) {
1001 case 0: 1008 case 0:
1002 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >> 1009 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
1003 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET; 1010 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
1004 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL; 1011 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
1005 1012
1006 break; 1013 break;
1007 case 1: 1014 case 1:
1008 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >> 1015 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
1009 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET; 1016 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
1010 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL; 1017 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
1011 1018
1012 break; 1019 break;
1013 case 2: 1020 case 2:
1014 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >> 1021 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
1015 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET; 1022 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
1016 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL; 1023 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
1017 1024
1018 break; 1025 break;
1019 case 3: 1026 case 3:
1020 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >> 1027 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
1021 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET; 1028 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
1022 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL; 1029 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
1023 1030
1024 break; 1031 break;
1025 default: 1032 default:
1026 break; 1033 break;
1027 } 1034 }
1028 1035
1029 if (clk_sel) 1036 if (clk_sel)
1030 root_freq = mxc_get_pll_pfd(PLL_BUS, 0); 1037 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
1031 else 1038 else
1032 root_freq = mxc_get_pll_pfd(PLL_BUS, 2); 1039 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
1033 1040
1034 return root_freq / (usdhc_podf + 1); 1041 return root_freq / (usdhc_podf + 1);
1035 } 1042 }
1036 1043
1037 u32 imx_get_uartclk(void) 1044 u32 imx_get_uartclk(void)
1038 { 1045 {
1039 return get_uart_clk(); 1046 return get_uart_clk();
1040 } 1047 }
1041 1048
1042 u32 imx_get_fecclk(void) 1049 u32 imx_get_fecclk(void)
1043 { 1050 {
1044 return mxc_get_clock(MXC_IPG_CLK); 1051 return mxc_get_clock(MXC_IPG_CLK);
1045 } 1052 }
1046 1053
1047 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX) 1054 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
1048 static int enable_enet_pll(uint32_t en) 1055 static int enable_enet_pll(uint32_t en)
1049 { 1056 {
1050 struct mxc_ccm_reg *const imx_ccm 1057 struct mxc_ccm_reg *const imx_ccm
1051 = (struct mxc_ccm_reg *) CCM_BASE_ADDR; 1058 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
1052 s32 timeout = 100000; 1059 s32 timeout = 100000;
1053 u32 reg = 0; 1060 u32 reg = 0;
1054 1061
1055 /* Enable PLLs */ 1062 /* Enable PLLs */
1056 reg = readl(&imx_ccm->analog_pll_enet); 1063 reg = readl(&imx_ccm->analog_pll_enet);
1057 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; 1064 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
1058 writel(reg, &imx_ccm->analog_pll_enet); 1065 writel(reg, &imx_ccm->analog_pll_enet);
1059 reg |= BM_ANADIG_PLL_SYS_ENABLE; 1066 reg |= BM_ANADIG_PLL_SYS_ENABLE;
1060 while (timeout--) { 1067 while (timeout--) {
1061 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK) 1068 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
1062 break; 1069 break;
1063 } 1070 }
1064 if (timeout <= 0) 1071 if (timeout <= 0)
1065 return -EIO; 1072 return -EIO;
1066 reg &= ~BM_ANADIG_PLL_SYS_BYPASS; 1073 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
1067 writel(reg, &imx_ccm->analog_pll_enet); 1074 writel(reg, &imx_ccm->analog_pll_enet);
1068 reg |= en; 1075 reg |= en;
1069 writel(reg, &imx_ccm->analog_pll_enet); 1076 writel(reg, &imx_ccm->analog_pll_enet);
1070 return 0; 1077 return 0;
1071 } 1078 }
1072 #endif 1079 #endif
1073 1080
1074 #ifdef CONFIG_CMD_SATA 1081 #ifdef CONFIG_CMD_SATA
1075 static void ungate_sata_clock(void) 1082 static void ungate_sata_clock(void)
1076 { 1083 {
1077 struct mxc_ccm_reg *const imx_ccm = 1084 struct mxc_ccm_reg *const imx_ccm =
1078 (struct mxc_ccm_reg *)CCM_BASE_ADDR; 1085 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1079 1086
1080 /* Enable SATA clock. */ 1087 /* Enable SATA clock. */
1081 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); 1088 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
1082 } 1089 }
1083 1090
1084 int enable_sata_clock(void) 1091 int enable_sata_clock(void)
1085 { 1092 {
1086 ungate_sata_clock(); 1093 ungate_sata_clock();
1087 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); 1094 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
1088 } 1095 }
1089 1096
1090 void disable_sata_clock(void) 1097 void disable_sata_clock(void)
1091 { 1098 {
1092 struct mxc_ccm_reg *const imx_ccm = 1099 struct mxc_ccm_reg *const imx_ccm =
1093 (struct mxc_ccm_reg *)CCM_BASE_ADDR; 1100 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1094 1101
1095 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); 1102 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
1096 } 1103 }
1097 #endif 1104 #endif
1098 1105
1099 #ifdef CONFIG_PCIE_IMX 1106 #ifdef CONFIG_PCIE_IMX
1100 static void ungate_disp_axi_clock(void) 1107 static void ungate_disp_axi_clock(void)
1101 { 1108 {
1102 struct mxc_ccm_reg *const imx_ccm = 1109 struct mxc_ccm_reg *const imx_ccm =
1103 (struct mxc_ccm_reg *)CCM_BASE_ADDR; 1110 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1104 1111
1105 /* Enable display axi clock. */ 1112 /* Enable display axi clock. */
1106 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_DISP_AXI_MASK); 1113 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_DISP_AXI_MASK);
1107 } 1114 }
1108 1115
1109 static void ungate_pcie_clock(void) 1116 static void ungate_pcie_clock(void)
1110 { 1117 {
1111 struct mxc_ccm_reg *const imx_ccm = 1118 struct mxc_ccm_reg *const imx_ccm =
1112 (struct mxc_ccm_reg *)CCM_BASE_ADDR; 1119 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1113 1120
1114 /* Enable PCIe clock. */ 1121 /* Enable PCIe clock. */
1115 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); 1122 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
1116 } 1123 }
1117 1124
1118 int enable_pcie_clock(void) 1125 int enable_pcie_clock(void)
1119 { 1126 {
1120 struct anatop_regs *anatop_regs = 1127 struct anatop_regs *anatop_regs =
1121 (struct anatop_regs *)ANATOP_BASE_ADDR; 1128 (struct anatop_regs *)ANATOP_BASE_ADDR;
1122 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 1129 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1123 u32 lvds1_clk_sel; 1130 u32 lvds1_clk_sel;
1124 1131
1125 /* 1132 /*
1126 * Here be dragons! 1133 * Here be dragons!
1127 * 1134 *
1128 * The register ANATOP_MISC1 is not documented in the Freescale 1135 * The register ANATOP_MISC1 is not documented in the Freescale
1129 * MX6RM. The register that is mapped in the ANATOP space and 1136 * MX6RM. The register that is mapped in the ANATOP space and
1130 * marked as ANATOP_MISC1 is actually documented in the PMU section 1137 * marked as ANATOP_MISC1 is actually documented in the PMU section
1131 * of the datasheet as PMU_MISC1. 1138 * of the datasheet as PMU_MISC1.
1132 * 1139 *
1133 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on 1140 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
1134 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important 1141 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
1135 * for PCI express link that is clocked from the i.MX6. 1142 * for PCI express link that is clocked from the i.MX6.
1136 */ 1143 */
1137 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) 1144 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
1138 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) 1145 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
1139 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F 1146 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
1140 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa 1147 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1141 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb 1148 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1142 1149
1143 if (is_cpu_type(MXC_CPU_MX6SX)) 1150 if (is_cpu_type(MXC_CPU_MX6SX))
1144 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF; 1151 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
1145 else 1152 else
1146 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF; 1153 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
1147 1154
1148 clrsetbits_le32(&anatop_regs->ana_misc1, 1155 clrsetbits_le32(&anatop_regs->ana_misc1,
1149 ANADIG_ANA_MISC1_LVDSCLK1_IBEN | 1156 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1150 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, 1157 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1151 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel); 1158 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
1152 1159
1153 /* PCIe reference clock sourced from AXI. */ 1160 /* PCIe reference clock sourced from AXI. */
1154 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); 1161 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1155 1162
1156 if (!is_cpu_type(MXC_CPU_MX6SX)) { 1163 if (!is_cpu_type(MXC_CPU_MX6SX)) {
1157 /* Party time! Ungate the clock to the PCIe. */ 1164 /* Party time! Ungate the clock to the PCIe. */
1158 #ifdef CONFIG_CMD_SATA 1165 #ifdef CONFIG_CMD_SATA
1159 ungate_sata_clock(); 1166 ungate_sata_clock();
1160 #endif 1167 #endif
1161 ungate_pcie_clock(); 1168 ungate_pcie_clock();
1162 1169
1163 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | 1170 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1164 BM_ANADIG_PLL_ENET_ENABLE_PCIE); 1171 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1165 } else { 1172 } else {
1166 /* Party time! Ungate the clock to the PCIe. */ 1173 /* Party time! Ungate the clock to the PCIe. */
1167 ungate_disp_axi_clock(); 1174 ungate_disp_axi_clock();
1168 ungate_pcie_clock(); 1175 ungate_pcie_clock();
1169 1176
1170 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_PCIE); 1177 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1171 } 1178 }
1172 } 1179 }
1173 #endif 1180 #endif
1174 1181
1175 #ifdef CONFIG_SECURE_BOOT 1182 #ifdef CONFIG_SECURE_BOOT
1176 void hab_caam_clock_enable(unsigned char enable) 1183 void hab_caam_clock_enable(unsigned char enable)
1177 { 1184 {
1178 u32 reg; 1185 u32 reg;
1179 1186
1180 if (is_cpu_type(MXC_CPU_MX6ULL)) { 1187 if (is_cpu_type(MXC_CPU_MX6ULL)) {
1181 /* CG5, DCP clock */ 1188 /* CG5, DCP clock */
1182 reg = __raw_readl(&imx_ccm->CCGR0); 1189 reg = __raw_readl(&imx_ccm->CCGR0);
1183 if (enable) 1190 if (enable)
1184 reg |= MXC_CCM_CCGR0_DCP_CLK_MASK; 1191 reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
1185 else 1192 else
1186 reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK; 1193 reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
1187 __raw_writel(reg, &imx_ccm->CCGR0); 1194 __raw_writel(reg, &imx_ccm->CCGR0);
1188 } else { 1195 } else {
1189 /* CG4 ~ CG6, CAAM clocks */ 1196 /* CG4 ~ CG6, CAAM clocks */
1190 reg = __raw_readl(&imx_ccm->CCGR0); 1197 reg = __raw_readl(&imx_ccm->CCGR0);
1191 if (enable) 1198 if (enable)
1192 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | 1199 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1193 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | 1200 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1194 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); 1201 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1195 else 1202 else
1196 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | 1203 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1197 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | 1204 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1198 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); 1205 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1199 __raw_writel(reg, &imx_ccm->CCGR0); 1206 __raw_writel(reg, &imx_ccm->CCGR0);
1200 } 1207 }
1201 1208
1202 /* EMI slow clk */ 1209 /* EMI slow clk */
1203 reg = __raw_readl(&imx_ccm->CCGR6); 1210 reg = __raw_readl(&imx_ccm->CCGR6);
1204 if (enable) 1211 if (enable)
1205 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; 1212 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1206 else 1213 else
1207 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK; 1214 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1208 __raw_writel(reg, &imx_ccm->CCGR6); 1215 __raw_writel(reg, &imx_ccm->CCGR6);
1209 } 1216 }
1210 #endif 1217 #endif
1211 1218
1212 static void enable_pll3(void) 1219 static void enable_pll3(void)
1213 { 1220 {
1214 struct anatop_regs __iomem *anatop = 1221 struct anatop_regs __iomem *anatop =
1215 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; 1222 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
1216 1223
1217 /* make sure pll3 is enabled */ 1224 /* make sure pll3 is enabled */
1218 if ((readl(&anatop->usb1_pll_480_ctrl) & 1225 if ((readl(&anatop->usb1_pll_480_ctrl) &
1219 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) { 1226 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1220 /* enable pll's power */ 1227 /* enable pll's power */
1221 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER, 1228 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1222 &anatop->usb1_pll_480_ctrl_set); 1229 &anatop->usb1_pll_480_ctrl_set);
1223 writel(0x80, &anatop->ana_misc2_clr); 1230 writel(0x80, &anatop->ana_misc2_clr);
1224 /* wait for pll lock */ 1231 /* wait for pll lock */
1225 while ((readl(&anatop->usb1_pll_480_ctrl) & 1232 while ((readl(&anatop->usb1_pll_480_ctrl) &
1226 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) 1233 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1227 ; 1234 ;
1228 /* disable bypass */ 1235 /* disable bypass */
1229 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS, 1236 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1230 &anatop->usb1_pll_480_ctrl_clr); 1237 &anatop->usb1_pll_480_ctrl_clr);
1231 /* enable pll output */ 1238 /* enable pll output */
1232 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE, 1239 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1233 &anatop->usb1_pll_480_ctrl_set); 1240 &anatop->usb1_pll_480_ctrl_set);
1234 } 1241 }
1235 } 1242 }
1236 1243
1237 void enable_thermal_clk(void) 1244 void enable_thermal_clk(void)
1238 { 1245 {
1239 enable_pll3(); 1246 enable_pll3();
1240 } 1247 }
1241 1248
1242 unsigned int mxc_get_clock(enum mxc_clock clk) 1249 unsigned int mxc_get_clock(enum mxc_clock clk)
1243 { 1250 {
1244 switch (clk) { 1251 switch (clk) {
1245 case MXC_ARM_CLK: 1252 case MXC_ARM_CLK:
1246 return get_mcu_main_clk(); 1253 return get_mcu_main_clk();
1247 case MXC_PER_CLK: 1254 case MXC_PER_CLK:
1248 return get_periph_clk(); 1255 return get_periph_clk();
1249 case MXC_AHB_CLK: 1256 case MXC_AHB_CLK:
1250 return get_ahb_clk(); 1257 return get_ahb_clk();
1251 case MXC_IPG_CLK: 1258 case MXC_IPG_CLK:
1252 return get_ipg_clk(); 1259 return get_ipg_clk();
1253 case MXC_IPG_PERCLK: 1260 case MXC_IPG_PERCLK:
1254 case MXC_I2C_CLK: 1261 case MXC_I2C_CLK:
1255 return get_ipg_per_clk(); 1262 return get_ipg_per_clk();
1256 case MXC_UART_CLK: 1263 case MXC_UART_CLK:
1257 return get_uart_clk(); 1264 return get_uart_clk();
1258 case MXC_CSPI_CLK: 1265 case MXC_CSPI_CLK:
1259 return get_cspi_clk(); 1266 return get_cspi_clk();
1260 case MXC_AXI_CLK: 1267 case MXC_AXI_CLK:
1261 return get_axi_clk(); 1268 return get_axi_clk();
1262 case MXC_EMI_SLOW_CLK: 1269 case MXC_EMI_SLOW_CLK:
1263 return get_emi_slow_clk(); 1270 return get_emi_slow_clk();
1264 case MXC_DDR_CLK: 1271 case MXC_DDR_CLK:
1265 return get_mmdc_ch0_clk(); 1272 return get_mmdc_ch0_clk();
1266 case MXC_ESDHC_CLK: 1273 case MXC_ESDHC_CLK:
1267 return get_usdhc_clk(0); 1274 return get_usdhc_clk(0);
1268 case MXC_ESDHC2_CLK: 1275 case MXC_ESDHC2_CLK:
1269 return get_usdhc_clk(1); 1276 return get_usdhc_clk(1);
1270 case MXC_ESDHC3_CLK: 1277 case MXC_ESDHC3_CLK:
1271 return get_usdhc_clk(2); 1278 return get_usdhc_clk(2);
1272 case MXC_ESDHC4_CLK: 1279 case MXC_ESDHC4_CLK:
1273 return get_usdhc_clk(3); 1280 return get_usdhc_clk(3);
1274 case MXC_SATA_CLK: 1281 case MXC_SATA_CLK:
1275 return get_ahb_clk(); 1282 return get_ahb_clk();
1276 default: 1283 default:
1277 printf("Unsupported MXC CLK: %d\n", clk); 1284 printf("Unsupported MXC CLK: %d\n", clk);
1278 break; 1285 break;
1279 } 1286 }
1280 1287
1281 return 0; 1288 return 0;
1282 } 1289 }
1283 1290
1284 /* 1291 /*
1285 * Dump some core clockes. 1292 * Dump some core clockes.
1286 */ 1293 */
1287 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 1294 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1288 { 1295 {
1289 u32 freq; 1296 u32 freq;
1290 freq = decode_pll(PLL_SYS, MXC_HCLK); 1297 freq = decode_pll(PLL_SYS, MXC_HCLK);
1291 printf("PLL_SYS %8d MHz\n", freq / 1000000); 1298 printf("PLL_SYS %8d MHz\n", freq / 1000000);
1292 freq = decode_pll(PLL_BUS, MXC_HCLK); 1299 freq = decode_pll(PLL_BUS, MXC_HCLK);
1293 printf("PLL_BUS %8d MHz\n", freq / 1000000); 1300 printf("PLL_BUS %8d MHz\n", freq / 1000000);
1294 freq = decode_pll(PLL_USBOTG, MXC_HCLK); 1301 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1295 printf("PLL_OTG %8d MHz\n", freq / 1000000); 1302 printf("PLL_OTG %8d MHz\n", freq / 1000000);
1296 freq = decode_pll(PLL_ENET, MXC_HCLK); 1303 freq = decode_pll(PLL_ENET, MXC_HCLK);
1297 printf("PLL_NET %8d MHz\n", freq / 1000000); 1304 printf("PLL_NET %8d MHz\n", freq / 1000000);
1298 1305
1299 printf("\n"); 1306 printf("\n");
1300 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); 1307 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1301 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); 1308 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
1302 #ifdef CONFIG_MXC_SPI 1309 #ifdef CONFIG_MXC_SPI
1303 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); 1310 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
1304 #endif 1311 #endif
1305 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); 1312 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1306 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); 1313 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1307 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); 1314 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1308 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); 1315 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1309 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); 1316 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1310 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); 1317 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1311 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000); 1318 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
1312 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000); 1319 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
1313 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); 1320 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
1314 1321
1315 return 0; 1322 return 0;
1316 } 1323 }
1317 1324
1318 static void pre_misc_setting(void) 1325 static void pre_misc_setting(void)
1319 { 1326 {
1320 /* Bypass IPU1 QoS generator */ 1327 /* Bypass IPU1 QoS generator */
1321 writel(0x00000002, 0x00bb048c); 1328 writel(0x00000002, 0x00bb048c);
1322 /* Bypass IPU2 QoS generator */ 1329 /* Bypass IPU2 QoS generator */
1323 writel(0x00000002, 0x00bb050c); 1330 writel(0x00000002, 0x00bb050c);
1324 /* Bandwidth THR for of PRE0 */ 1331 /* Bandwidth THR for of PRE0 */
1325 writel(0x00000200, 0x00bb0690); 1332 writel(0x00000200, 0x00bb0690);
1326 /* Bandwidth THR for of PRE1 */ 1333 /* Bandwidth THR for of PRE1 */
1327 writel(0x00000200, 0x00bb0710); 1334 writel(0x00000200, 0x00bb0710);
1328 /* Bandwidth THR for of PRE2 */ 1335 /* Bandwidth THR for of PRE2 */
1329 writel(0x00000200, 0x00bb0790); 1336 writel(0x00000200, 0x00bb0790);
1330 /* Bandwidth THR for of PRE3 */ 1337 /* Bandwidth THR for of PRE3 */
1331 writel(0x00000200, 0x00bb0810); 1338 writel(0x00000200, 0x00bb0810);
1332 /* Saturation THR for of PRE0 */ 1339 /* Saturation THR for of PRE0 */
1333 writel(0x00000010, 0x00bb0694); 1340 writel(0x00000010, 0x00bb0694);
1334 /* Saturation THR for of PRE1 */ 1341 /* Saturation THR for of PRE1 */
1335 writel(0x00000010, 0x00bb0714); 1342 writel(0x00000010, 0x00bb0714);
1336 /* Saturation THR for of PRE2 */ 1343 /* Saturation THR for of PRE2 */
1337 writel(0x00000010, 0x00bb0794); 1344 writel(0x00000010, 0x00bb0794);
1338 /* Saturation THR for of PRE */ 1345 /* Saturation THR for of PRE */
1339 writel(0x00000010, 0x00bb0814); 1346 writel(0x00000010, 0x00bb0814);
1340 } 1347 }
1341 1348
1342 void enable_ipu_clock(void) 1349 void enable_ipu_clock(void)
1343 { 1350 {
1344 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 1351 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1345 int reg; 1352 int reg;
1346 reg = readl(&mxc_ccm->CCGR3); 1353 reg = readl(&mxc_ccm->CCGR3);
1347 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; 1354 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1348 writel(reg, &mxc_ccm->CCGR3); 1355 writel(reg, &mxc_ccm->CCGR3);
1349 1356
1350 if (is_mx6dqp()) { 1357 if (is_mx6dqp()) {
1351 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); 1358 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1352 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); 1359 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1353 1360
1354 /* 1361 /*
1355 * Since CONFIG_VIDEO_IPUV3 is always set in mx6sabre_common.h and 1362 * Since CONFIG_VIDEO_IPUV3 is always set in mx6sabre_common.h and
1356 * this misc setting is a must for mx6qp, this position is ok 1363 * this misc setting is a must for mx6qp, this position is ok
1357 * to do such settings. 1364 * to do such settings.
1358 */ 1365 */
1359 pre_misc_setting(); 1366 pre_misc_setting();
1360 } 1367 }
1361 } 1368 }
1362 1369
1363 /***************************************************/ 1370 /***************************************************/
1364 1371
1365 U_BOOT_CMD( 1372 U_BOOT_CMD(
1366 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks, 1373 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
1367 "display clocks", 1374 "display clocks",
1368 "" 1375 ""
1369 ); 1376 );
1370 1377
arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ 05922b0
1 /* 1 /*
2 * (C) Copyright 2007 2 * (C) Copyright 2007
3 * Sascha Hauer, Pengutronix 3 * Sascha Hauer, Pengutronix
4 * 4 *
5 * (C) Copyright 2009-2016 Freescale Semiconductor, Inc. 5 * (C) Copyright 2009-2016 Freescale Semiconductor, Inc.
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #include <common.h> 10 #include <common.h>
11 #include <asm/errno.h> 11 #include <asm/errno.h>
12 #include <asm/io.h> 12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h> 14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h> 15 #include <asm/arch/sys_proto.h>
16 #include <asm/imx-common/boot_mode.h> 16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/dma.h> 17 #include <asm/imx-common/dma.h>
18 #include <asm/imx-common/hab.h> 18 #include <asm/imx-common/hab.h>
19 #include <stdbool.h> 19 #include <stdbool.h>
20 #include <asm/arch/mxc_hdmi.h> 20 #include <asm/arch/mxc_hdmi.h>
21 #include <asm/arch/crm_regs.h> 21 #include <asm/arch/crm_regs.h>
22 #include <dm.h> 22 #include <dm.h>
23 #include <imx_thermal.h> 23 #include <imx_thermal.h>
24 #include <mmc.h> 24 #include <mmc.h>
25 #if defined(CONFIG_FSL_FASTBOOT) && defined(CONFIG_ANDROID_RECOVERY) 25 #if defined(CONFIG_FSL_FASTBOOT) && defined(CONFIG_ANDROID_RECOVERY)
26 #include <recovery.h> 26 #include <recovery.h>
27 #endif 27 #endif
28 28
29 29
30 enum ldo_reg { 30 enum ldo_reg {
31 LDO_ARM, 31 LDO_ARM,
32 LDO_SOC, 32 LDO_SOC,
33 LDO_PU, 33 LDO_PU,
34 }; 34 };
35 35
36 struct scu_regs { 36 struct scu_regs {
37 u32 ctrl; 37 u32 ctrl;
38 u32 config; 38 u32 config;
39 u32 status; 39 u32 status;
40 u32 invalidate; 40 u32 invalidate;
41 u32 fpga_rev; 41 u32 fpga_rev;
42 }; 42 };
43 43
44 #if defined(CONFIG_IMX_THERMAL) 44 #if defined(CONFIG_IMX_THERMAL)
45 static const struct imx_thermal_plat imx6_thermal_plat = { 45 static const struct imx_thermal_plat imx6_thermal_plat = {
46 .regs = (void *)ANATOP_BASE_ADDR, 46 .regs = (void *)ANATOP_BASE_ADDR,
47 .fuse_bank = 1, 47 .fuse_bank = 1,
48 .fuse_word = 6, 48 .fuse_word = 6,
49 }; 49 };
50 50
51 U_BOOT_DEVICE(imx6_thermal) = { 51 U_BOOT_DEVICE(imx6_thermal) = {
52 .name = "imx_thermal", 52 .name = "imx_thermal",
53 .platdata = &imx6_thermal_plat, 53 .platdata = &imx6_thermal_plat,
54 }; 54 };
55 #endif 55 #endif
56 56
57 #if defined(CONFIG_SECURE_BOOT) 57 #if defined(CONFIG_SECURE_BOOT)
58 struct imx_sec_config_fuse_t const imx_sec_config_fuse = { 58 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
59 .bank = 0, 59 .bank = 0,
60 .word = 6, 60 .word = 6,
61 }; 61 };
62 #endif 62 #endif
63 63
64 u32 get_nr_cpus(void) 64 u32 get_nr_cpus(void)
65 { 65 {
66 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; 66 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
67 return readl(&scu->config) & 3; 67 return readl(&scu->config) & 3;
68 } 68 }
69 69
70 u32 get_cpu_rev(void) 70 u32 get_cpu_rev(void)
71 { 71 {
72 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 72 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
73 u32 reg = readl(&anatop->digprog_sololite); 73 u32 reg = readl(&anatop->digprog_sololite);
74 u32 type = ((reg >> 16) & 0xff); 74 u32 type = ((reg >> 16) & 0xff);
75 u32 major, cfg = 0; 75 u32 major, cfg = 0;
76 76
77 if (type != MXC_CPU_MX6SL) { 77 if (type != MXC_CPU_MX6SL) {
78 reg = readl(&anatop->digprog); 78 reg = readl(&anatop->digprog);
79 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; 79 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
80 cfg = readl(&scu->config) & 3; 80 cfg = readl(&scu->config) & 3;
81 type = ((reg >> 16) & 0xff); 81 type = ((reg >> 16) & 0xff);
82 if (type == MXC_CPU_MX6DL) { 82 if (type == MXC_CPU_MX6DL) {
83 if (!cfg) 83 if (!cfg)
84 type = MXC_CPU_MX6SOLO; 84 type = MXC_CPU_MX6SOLO;
85 } 85 }
86 86
87 if (type == MXC_CPU_MX6Q) { 87 if (type == MXC_CPU_MX6Q) {
88 if (cfg == 1) 88 if (cfg == 1)
89 type = MXC_CPU_MX6D; 89 type = MXC_CPU_MX6D;
90 } 90 }
91 91
92 } 92 }
93 major = ((reg >> 8) & 0xff); 93 major = ((reg >> 8) & 0xff);
94 if ((major >= 1) && 94 if ((major >= 1) &&
95 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) { 95 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
96 major--; 96 major--;
97 type = MXC_CPU_MX6QP; 97 type = MXC_CPU_MX6QP;
98 if (cfg == 1) 98 if (cfg == 1)
99 type = MXC_CPU_MX6DP; 99 type = MXC_CPU_MX6DP;
100 } 100 }
101 reg &= 0xff; /* mx6 silicon revision */ 101 reg &= 0xff; /* mx6 silicon revision */
102 return (type << 12) | (reg + (0x10 * (major + 1))); 102 return (type << 12) | (reg + (0x10 * (major + 1)));
103 } 103 }
104 104
105 /* 105 /*
106 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440) 106 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
107 * defines a 2-bit SPEED_GRADING 107 * defines a 2-bit SPEED_GRADING
108 */ 108 */
109 #define OCOTP_CFG3_SPEED_SHIFT 16 109 #define OCOTP_CFG3_SPEED_SHIFT 16
110 #define OCOTP_CFG3_SPEED_800MHZ 0 110 #define OCOTP_CFG3_SPEED_800MHZ 0
111 #define OCOTP_CFG3_SPEED_850MHZ 1 111 #define OCOTP_CFG3_SPEED_850MHZ 1
112 #define OCOTP_CFG3_SPEED_1GHZ 2 112 #define OCOTP_CFG3_SPEED_1GHZ 2
113 #define OCOTP_CFG3_SPEED_1P2GHZ 3 113 #define OCOTP_CFG3_SPEED_1P2GHZ 3
114 114
115 /* 115 /*
116 * For i.MX6UL 116 * For i.MX6UL
117 */ 117 */
118 #define OCOTP_CFG3_SPEED_528MHZ 1 118 #define OCOTP_CFG3_SPEED_528MHZ 1
119 #define OCOTP_CFG3_SPEED_696MHZ 2 119 #define OCOTP_CFG3_SPEED_696MHZ 2
120 120
121 u32 get_cpu_speed_grade_hz(void) 121 u32 get_cpu_speed_grade_hz(void)
122 { 122 {
123 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 123 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
124 struct fuse_bank *bank = &ocotp->bank[0]; 124 struct fuse_bank *bank = &ocotp->bank[0];
125 struct fuse_bank0_regs *fuse = 125 struct fuse_bank0_regs *fuse =
126 (struct fuse_bank0_regs *)bank->fuse_regs; 126 (struct fuse_bank0_regs *)bank->fuse_regs;
127 uint32_t val; 127 uint32_t val;
128 128
129 val = readl(&fuse->cfg3); 129 val = readl(&fuse->cfg3);
130 val >>= OCOTP_CFG3_SPEED_SHIFT; 130 val >>= OCOTP_CFG3_SPEED_SHIFT;
131 val &= 0x3; 131 val &= 0x3;
132 132
133 if (is_cpu_type(MXC_CPU_MX6UL)) { 133 if (is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) {
134 if (val == OCOTP_CFG3_SPEED_528MHZ) 134 if (val == OCOTP_CFG3_SPEED_528MHZ)
135 return 528000000; 135 return 528000000;
136 else if (val == OCOTP_CFG3_SPEED_696MHZ) 136 else if (val == OCOTP_CFG3_SPEED_696MHZ)
137 return 69600000; 137 return 69600000;
138 else 138 else
139 return 0; 139 return 0;
140 } 140 }
141 141
142 switch (val) { 142 switch (val) {
143 /* Valid for IMX6DQ */ 143 /* Valid for IMX6DQ */
144 case OCOTP_CFG3_SPEED_1P2GHZ: 144 case OCOTP_CFG3_SPEED_1P2GHZ:
145 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) || 145 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) ||
146 is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) 146 is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
147 return 1200000000; 147 return 1200000000;
148 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ 148 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
149 case OCOTP_CFG3_SPEED_1GHZ: 149 case OCOTP_CFG3_SPEED_1GHZ:
150 return 996000000; 150 return 996000000;
151 /* Valid for IMX6DQ */ 151 /* Valid for IMX6DQ */
152 case OCOTP_CFG3_SPEED_850MHZ: 152 case OCOTP_CFG3_SPEED_850MHZ:
153 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) || 153 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) ||
154 is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) 154 is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
155 return 852000000; 155 return 852000000;
156 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ 156 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
157 case OCOTP_CFG3_SPEED_800MHZ: 157 case OCOTP_CFG3_SPEED_800MHZ:
158 return 792000000; 158 return 792000000;
159 } 159 }
160 return 0; 160 return 0;
161 } 161 }
162 162
163 /* 163 /*
164 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480) 164 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
165 * defines a 2-bit Temperature Grade 165 * defines a 2-bit Temperature Grade
166 * 166 *
167 * return temperature grade and min/max temperature in celcius 167 * return temperature grade and min/max temperature in celcius
168 */ 168 */
169 #define OCOTP_MEM0_TEMP_SHIFT 6 169 #define OCOTP_MEM0_TEMP_SHIFT 6
170 170
171 u32 get_cpu_temp_grade(int *minc, int *maxc) 171 u32 get_cpu_temp_grade(int *minc, int *maxc)
172 { 172 {
173 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 173 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
174 struct fuse_bank *bank = &ocotp->bank[1]; 174 struct fuse_bank *bank = &ocotp->bank[1];
175 struct fuse_bank1_regs *fuse = 175 struct fuse_bank1_regs *fuse =
176 (struct fuse_bank1_regs *)bank->fuse_regs; 176 (struct fuse_bank1_regs *)bank->fuse_regs;
177 uint32_t val; 177 uint32_t val;
178 178
179 val = readl(&fuse->mem0); 179 val = readl(&fuse->mem0);
180 val >>= OCOTP_MEM0_TEMP_SHIFT; 180 val >>= OCOTP_MEM0_TEMP_SHIFT;
181 val &= 0x3; 181 val &= 0x3;
182 182
183 if (minc && maxc) { 183 if (minc && maxc) {
184 if (val == TEMP_AUTOMOTIVE) { 184 if (val == TEMP_AUTOMOTIVE) {
185 *minc = -40; 185 *minc = -40;
186 *maxc = 125; 186 *maxc = 125;
187 } else if (val == TEMP_INDUSTRIAL) { 187 } else if (val == TEMP_INDUSTRIAL) {
188 *minc = -40; 188 *minc = -40;
189 *maxc = 105; 189 *maxc = 105;
190 } else if (val == TEMP_EXTCOMMERCIAL) { 190 } else if (val == TEMP_EXTCOMMERCIAL) {
191 *minc = -20; 191 *minc = -20;
192 *maxc = 105; 192 *maxc = 105;
193 } else { 193 } else {
194 *minc = 0; 194 *minc = 0;
195 *maxc = 95; 195 *maxc = 95;
196 } 196 }
197 } 197 }
198 return val; 198 return val;
199 } 199 }
200 200
201 #ifdef CONFIG_REVISION_TAG 201 #ifdef CONFIG_REVISION_TAG
202 u32 __weak get_board_rev(void) 202 u32 __weak get_board_rev(void)
203 { 203 {
204 u32 cpurev = get_cpu_rev(); 204 u32 cpurev = get_cpu_rev();
205 u32 type = ((cpurev >> 12) & 0xff); 205 u32 type = ((cpurev >> 12) & 0xff);
206 if (type == MXC_CPU_MX6SOLO) 206 if (type == MXC_CPU_MX6SOLO)
207 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); 207 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
208 208
209 if (type == MXC_CPU_MX6D) 209 if (type == MXC_CPU_MX6D)
210 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); 210 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
211 211
212 if (type == MXC_CPU_MX6QP || type == MXC_CPU_MX6DP) 212 if (type == MXC_CPU_MX6QP || type == MXC_CPU_MX6DP)
213 cpurev = (MXC_CPU_MX6Q) << 12 | ((cpurev + 0x10) & 0xFFF); 213 cpurev = (MXC_CPU_MX6Q) << 12 | ((cpurev + 0x10) & 0xFFF);
214 214
215 return cpurev; 215 return cpurev;
216 } 216 }
217 #endif 217 #endif
218 218
219 static void clear_ldo_ramp(void) 219 static void clear_ldo_ramp(void)
220 { 220 {
221 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 221 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
222 int reg; 222 int reg;
223 223
224 /* ROM may modify LDO ramp up time according to fuse setting, so in 224 /* ROM may modify LDO ramp up time according to fuse setting, so in
225 * order to be in the safe side we neeed to reset these settings to 225 * order to be in the safe side we neeed to reset these settings to
226 * match the reset value: 0'b00 226 * match the reset value: 0'b00
227 */ 227 */
228 reg = readl(&anatop->ana_misc2); 228 reg = readl(&anatop->ana_misc2);
229 reg &= ~(0x3f << 24); 229 reg &= ~(0x3f << 24);
230 writel(reg, &anatop->ana_misc2); 230 writel(reg, &anatop->ana_misc2);
231 } 231 }
232 232
233 /* 233 /*
234 * Set the PMU_REG_CORE register 234 * Set the PMU_REG_CORE register
235 * 235 *
236 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level. 236 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
237 * Possible values are from 0.725V to 1.450V in steps of 237 * Possible values are from 0.725V to 1.450V in steps of
238 * 0.025V (25mV). 238 * 0.025V (25mV).
239 */ 239 */
240 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) 240 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
241 { 241 {
242 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 242 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
243 u32 val, step, old, reg = readl(&anatop->reg_core); 243 u32 val, step, old, reg = readl(&anatop->reg_core);
244 u8 shift; 244 u8 shift;
245 245
246 if (mv < 725) 246 if (mv < 725)
247 val = 0x00; /* Power gated off */ 247 val = 0x00; /* Power gated off */
248 else if (mv > 1450) 248 else if (mv > 1450)
249 val = 0x1F; /* Power FET switched full on. No regulation */ 249 val = 0x1F; /* Power FET switched full on. No regulation */
250 else 250 else
251 val = (mv - 700) / 25; 251 val = (mv - 700) / 25;
252 252
253 clear_ldo_ramp(); 253 clear_ldo_ramp();
254 254
255 switch (ldo) { 255 switch (ldo) {
256 case LDO_SOC: 256 case LDO_SOC:
257 shift = 18; 257 shift = 18;
258 break; 258 break;
259 case LDO_PU: 259 case LDO_PU:
260 shift = 9; 260 shift = 9;
261 break; 261 break;
262 case LDO_ARM: 262 case LDO_ARM:
263 shift = 0; 263 shift = 0;
264 break; 264 break;
265 default: 265 default:
266 return -EINVAL; 266 return -EINVAL;
267 } 267 }
268 268
269 old = (reg & (0x1F << shift)) >> shift; 269 old = (reg & (0x1F << shift)) >> shift;
270 step = abs(val - old); 270 step = abs(val - old);
271 if (step == 0) 271 if (step == 0)
272 return 0; 272 return 0;
273 273
274 reg = (reg & ~(0x1F << shift)) | (val << shift); 274 reg = (reg & ~(0x1F << shift)) | (val << shift);
275 writel(reg, &anatop->reg_core); 275 writel(reg, &anatop->reg_core);
276 276
277 /* 277 /*
278 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per 278 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
279 * step 279 * step
280 */ 280 */
281 udelay(3 * step); 281 udelay(3 * step);
282 282
283 return 0; 283 return 0;
284 } 284 }
285 285
286 static void set_ahb_rate(u32 val) 286 static void set_ahb_rate(u32 val)
287 { 287 {
288 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 288 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
289 u32 reg, div; 289 u32 reg, div;
290 290
291 div = get_periph_clk() / val - 1; 291 div = get_periph_clk() / val - 1;
292 reg = readl(&mxc_ccm->cbcdr); 292 reg = readl(&mxc_ccm->cbcdr);
293 293
294 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | 294 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
295 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); 295 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
296 } 296 }
297 297
298 static void clear_mmdc_ch_mask(void) 298 static void clear_mmdc_ch_mask(void)
299 { 299 {
300 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 300 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
301 u32 reg; 301 u32 reg;
302 reg = readl(&mxc_ccm->ccdr); 302 reg = readl(&mxc_ccm->ccdr);
303 303
304 /* Clear MMDC channel mask */ 304 /* Clear MMDC channel mask */
305 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) 305 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
306 is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6ULL))
306 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); 307 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
307 else 308 else
308 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); 309 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
309 writel(reg, &mxc_ccm->ccdr); 310 writel(reg, &mxc_ccm->ccdr);
310 } 311 }
311 312
312 static void init_bandgap(void) 313 static void init_bandgap(void)
313 { 314 {
314 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 315 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
315 /* 316 /*
316 * Ensure the bandgap has stabilized. 317 * Ensure the bandgap has stabilized.
317 */ 318 */
318 while (!(readl(&anatop->ana_misc0) & 0x80)) 319 while (!(readl(&anatop->ana_misc0) & 0x80))
319 ; 320 ;
320 /* 321 /*
321 * For best noise performance of the analog blocks using the 322 * For best noise performance of the analog blocks using the
322 * outputs of the bandgap, the reftop_selfbiasoff bit should 323 * outputs of the bandgap, the reftop_selfbiasoff bit should
323 * be set. 324 * be set.
324 */ 325 */
325 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); 326 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
326 } 327 }
327 328
328 329
329 #ifdef CONFIG_MX6SL 330 #ifdef CONFIG_MX6SL
330 static void set_preclk_from_osc(void) 331 static void set_preclk_from_osc(void)
331 { 332 {
332 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 333 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
333 u32 reg; 334 u32 reg;
334 335
335 reg = readl(&mxc_ccm->cscmr1); 336 reg = readl(&mxc_ccm->cscmr1);
336 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; 337 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
337 writel(reg, &mxc_ccm->cscmr1); 338 writel(reg, &mxc_ccm->cscmr1);
338 } 339 }
339 #endif 340 #endif
340 341
341 #ifdef CONFIG_MX6SX 342 #ifdef CONFIG_MX6SX
342 void vadc_power_up(void) 343 void vadc_power_up(void)
343 { 344 {
344 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 345 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
345 u32 val; 346 u32 val;
346 347
347 /* csi0 */ 348 /* csi0 */
348 val = readl(&iomux->gpr[5]); 349 val = readl(&iomux->gpr[5]);
349 val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, 350 val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
350 val |= IMX6SX_GPR5_CSI1_MUX_CTRL_CVD; 351 val |= IMX6SX_GPR5_CSI1_MUX_CTRL_CVD;
351 writel(val, &iomux->gpr[5]); 352 writel(val, &iomux->gpr[5]);
352 353
353 /* Power on vadc analog 354 /* Power on vadc analog
354 * Power down vadc ext power */ 355 * Power down vadc ext power */
355 val = readl(GPC_BASE_ADDR + 0); 356 val = readl(GPC_BASE_ADDR + 0);
356 val &= ~0x60000; 357 val &= ~0x60000;
357 writel(val, GPC_BASE_ADDR + 0); 358 writel(val, GPC_BASE_ADDR + 0);
358 359
359 /* software reset afe */ 360 /* software reset afe */
360 val = readl(&iomux->gpr[1]); 361 val = readl(&iomux->gpr[1]);
361 writel(val | 0x80000, &iomux->gpr[1]); 362 writel(val | 0x80000, &iomux->gpr[1]);
362 363
363 udelay(10*1000); 364 udelay(10*1000);
364 365
365 /* Release reset bit */ 366 /* Release reset bit */
366 writel(val & ~0x80000, &iomux->gpr[1]); 367 writel(val & ~0x80000, &iomux->gpr[1]);
367 368
368 /* Power on vadc ext power */ 369 /* Power on vadc ext power */
369 val = readl(GPC_BASE_ADDR + 0); 370 val = readl(GPC_BASE_ADDR + 0);
370 val |= 0x40000; 371 val |= 0x40000;
371 writel(val, GPC_BASE_ADDR + 0); 372 writel(val, GPC_BASE_ADDR + 0);
372 } 373 }
373 374
374 void vadc_power_down(void) 375 void vadc_power_down(void)
375 { 376 {
376 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 377 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
377 u32 val; 378 u32 val;
378 379
379 /* Power down vadc ext power 380 /* Power down vadc ext power
380 * Power off vadc analog */ 381 * Power off vadc analog */
381 val = readl(GPC_BASE_ADDR + 0); 382 val = readl(GPC_BASE_ADDR + 0);
382 val &= ~0x40000; 383 val &= ~0x40000;
383 val |= 0x20000; 384 val |= 0x20000;
384 writel(val, GPC_BASE_ADDR + 0); 385 writel(val, GPC_BASE_ADDR + 0);
385 386
386 /* clean csi0 connect to vadc */ 387 /* clean csi0 connect to vadc */
387 val = readl(&iomux->gpr[5]); 388 val = readl(&iomux->gpr[5]);
388 val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, 389 val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
389 writel(val, &iomux->gpr[5]); 390 writel(val, &iomux->gpr[5]);
390 } 391 }
391 392
392 void pcie_power_up(void) 393 void pcie_power_up(void)
393 { 394 {
394 set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */ 395 set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */
395 } 396 }
396 397
397 void pcie_power_off(void) 398 void pcie_power_off(void)
398 { 399 {
399 set_ldo_voltage(LDO_PU, 0); /* Set VDDPU to 1.1V */ 400 set_ldo_voltage(LDO_PU, 0); /* Set VDDPU to 1.1V */
400 } 401 }
401 #endif 402 #endif
402 403
403 static void set_uart_from_osc(void) 404 static void set_uart_from_osc(void)
404 { 405 {
405 u32 reg; 406 u32 reg;
406 407
407 /* set uart clk to OSC */ 408 /* set uart clk to OSC */
408 reg = readl(CCM_BASE_ADDR + 0x24); 409 reg = readl(CCM_BASE_ADDR + 0x24);
409 reg |= MXC_CCM_CSCDR1_UART_CLK_SEL; 410 reg |= MXC_CCM_CSCDR1_UART_CLK_SEL;
410 writel(reg, CCM_BASE_ADDR + 0x24); 411 writel(reg, CCM_BASE_ADDR + 0x24);
411 } 412 }
412 413
413 static void imx_set_vddpu_power_down(void) 414 static void imx_set_vddpu_power_down(void)
414 { 415 {
415 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 416 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
416 u32 val; 417 u32 val;
417 418
418 /* need to power down xPU in GPC before turn off PU LDO */ 419 /* need to power down xPU in GPC before turn off PU LDO */
419 val = readl(GPC_BASE_ADDR + 0x260); 420 val = readl(GPC_BASE_ADDR + 0x260);
420 writel(val | 0x1, GPC_BASE_ADDR + 0x260); 421 writel(val | 0x1, GPC_BASE_ADDR + 0x260);
421 422
422 val = readl(GPC_BASE_ADDR + 0x0); 423 val = readl(GPC_BASE_ADDR + 0x0);
423 writel(val | 0x1, GPC_BASE_ADDR + 0x0); 424 writel(val | 0x1, GPC_BASE_ADDR + 0x0);
424 while (readl(GPC_BASE_ADDR + 0x0) & 0x1) 425 while (readl(GPC_BASE_ADDR + 0x0) & 0x1)
425 ; 426 ;
426 427
427 /* disable VDDPU */ 428 /* disable VDDPU */
428 val = 0x3e00; 429 val = 0x3e00;
429 writel(val, &anatop->reg_core_clr); 430 writel(val, &anatop->reg_core_clr);
430 } 431 }
431 432
432 static void imx_set_pcie_phy_power_down(void) 433 static void imx_set_pcie_phy_power_down(void)
433 { 434 {
434 u32 val; 435 u32 val;
435 436
436 if (!is_cpu_type(MXC_CPU_MX6SX)) { 437 if (!is_cpu_type(MXC_CPU_MX6SX)) {
437 val = readl(IOMUXC_BASE_ADDR + 0x4); 438 val = readl(IOMUXC_BASE_ADDR + 0x4);
438 val |= 0x1 << 18; 439 val |= 0x1 << 18;
439 writel(val, IOMUXC_BASE_ADDR + 0x4); 440 writel(val, IOMUXC_BASE_ADDR + 0x4);
440 } else { 441 } else {
441 val = readl(IOMUXC_GPR_BASE_ADDR + 0x30); 442 val = readl(IOMUXC_GPR_BASE_ADDR + 0x30);
442 val |= 0x1 << 30; 443 val |= 0x1 << 30;
443 writel(val, IOMUXC_GPR_BASE_ADDR + 0x30); 444 writel(val, IOMUXC_GPR_BASE_ADDR + 0x30);
444 } 445 }
445 } 446 }
446 447
447 int arch_cpu_init(void) 448 int arch_cpu_init(void)
448 { 449 {
449 if (!is_cpu_type(MXC_CPU_MX6SL) && !!is_cpu_type(MXC_CPU_MX6SX) 450 if (!is_cpu_type(MXC_CPU_MX6SL) && !is_cpu_type(MXC_CPU_MX6SX)
450 && !is_cpu_type(MXC_CPU_MX6UL)) { 451 && !is_cpu_type(MXC_CPU_MX6UL) && !is_cpu_type(MXC_CPU_MX6ULL)) {
451 /* 452 /*
452 * imx6sl doesn't have pcie at all. 453 * imx6sl doesn't have pcie at all.
453 * this bit is not used by imx6sx anymore 454 * this bit is not used by imx6sx anymore
454 */ 455 */
455 u32 val; 456 u32 val;
456 457
457 /* 458 /*
458 * There are about 0.02% percentage, random pcie link down 459 * There are about 0.02% percentage, random pcie link down
459 * when warm-reset is used. 460 * when warm-reset is used.
460 * clear the ref_ssp_en bit16 of gpr1 to workaround it. 461 * clear the ref_ssp_en bit16 of gpr1 to workaround it.
461 * then warm-reset imx6q/dl/solo again. 462 * then warm-reset imx6q/dl/solo again.
462 */ 463 */
463 val = readl(IOMUXC_BASE_ADDR + 0x4); 464 val = readl(IOMUXC_BASE_ADDR + 0x4);
464 if (val & (0x1 << 16)) { 465 if (val & (0x1 << 16)) {
465 val &= ~(0x1 << 16); 466 val &= ~(0x1 << 16);
466 writel(val, IOMUXC_BASE_ADDR + 0x4); 467 writel(val, IOMUXC_BASE_ADDR + 0x4);
467 reset_cpu(0); 468 reset_cpu(0);
468 } 469 }
469 } 470 }
470 471
471 init_aips(); 472 init_aips();
472 473
473 /* Need to clear MMDC_CHx_MASK to make warm reset work. */ 474 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
474 clear_mmdc_ch_mask(); 475 clear_mmdc_ch_mask();
475 476
476 /* 477 /*
477 * Disable self-bias circuit in the analog bandap. 478 * Disable self-bias circuit in the analog bandap.
478 * The self-bias circuit is used by the bandgap during startup. 479 * The self-bias circuit is used by the bandgap during startup.
479 * This bit should be set after the bandgap has initialized. 480 * This bit should be set after the bandgap has initialized.
480 */ 481 */
481 init_bandgap(); 482 init_bandgap();
482 483
483 if (!is_cpu_type(MXC_CPU_MX6UL) && !is_cpu_type(MXC_CPU_MX6ULL)) { 484 if (!is_cpu_type(MXC_CPU_MX6UL) && !is_cpu_type(MXC_CPU_MX6ULL)) {
484 /* 485 /*
485 * When low freq boot is enabled, ROM will not set AHB 486 * When low freq boot is enabled, ROM will not set AHB
486 * freq, so we need to ensure AHB freq is 132MHz in such 487 * freq, so we need to ensure AHB freq is 132MHz in such
487 * scenario. 488 * scenario.
488 */ 489 */
489 if (mxc_get_clock(MXC_ARM_CLK) == 396000000) 490 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
490 set_ahb_rate(132000000); 491 set_ahb_rate(132000000);
491 } 492 }
492 493
493 if (is_cpu_type(MXC_CPU_MX6UL)) { 494 if (is_cpu_type(MXC_CPU_MX6UL)) {
494 if (is_soc_rev(CHIP_REV_1_0)) { 495 if (is_soc_rev(CHIP_REV_1_0)) {
495 /* 496 /*
496 * According to the design team's requirement on i.MX6UL, 497 * According to the design team's requirement on i.MX6UL,
497 * the PMIC_STBY_REQ PAD should be configured as open 498 * the PMIC_STBY_REQ PAD should be configured as open
498 * drain 100K (0x0000b8a0). 499 * drain 100K (0x0000b8a0).
499 */ 500 */
500 writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); 501 writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
501 } else { 502 } else {
502 /* 503 /*
503 * From TO1.1, SNVS adds internal pull up control for POR_B, 504 * From TO1.1, SNVS adds internal pull up control for POR_B,
504 * the register filed is GPBIT[1:0], after system boot up, 505 * the register filed is GPBIT[1:0], after system boot up,
505 * it can be set to 2b'01 to disable internal pull up. 506 * it can be set to 2b'01 to disable internal pull up.
506 * It can save about 30uA power in SNVS mode. 507 * It can save about 30uA power in SNVS mode.
507 */ 508 */
508 writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) & (~0x1400)) | 0x400, 509 writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) & (~0x1400)) | 0x400,
509 MX6UL_SNVS_LP_BASE_ADDR + 0x10); 510 MX6UL_SNVS_LP_BASE_ADDR + 0x10);
510 } 511 }
511 } 512 }
512 513
513 if (is_cpu_type(MXC_CPU_MX6ULL)) { 514 if (is_cpu_type(MXC_CPU_MX6ULL)) {
514 /* 515 /*
515 * GPBIT[1:0] is suggested to set to 2'b11: 516 * GPBIT[1:0] is suggested to set to 2'b11:
516 * 2'b00 : always PUP100K 517 * 2'b00 : always PUP100K
517 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL 518 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
518 * 2'b10 : always disable PUP100K 519 * 2'b10 : always disable PUP100K
519 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL 520 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
520 * register offset is different from i.MX6UL, since 521 * register offset is different from i.MX6UL, since
521 * i.MX6UL is fixed by ECO. 522 * i.MX6UL is fixed by ECO.
522 */ 523 */
523 writel(readl(MX6UL_SNVS_LP_BASE_ADDR) | 524 writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
524 0x3, MX6UL_SNVS_LP_BASE_ADDR); 525 0x3, MX6UL_SNVS_LP_BASE_ADDR);
525 } 526 }
526 527
527 /* Set perclk to source from OSC 24MHz */ 528 /* Set perclk to source from OSC 24MHz */
528 #if defined(CONFIG_MX6SL) 529 #if defined(CONFIG_MX6SL)
529 set_preclk_from_osc(); 530 set_preclk_from_osc();
530 #endif 531 #endif
531 532
532 if (is_cpu_type(MXC_CPU_MX6SX)) 533 if (is_cpu_type(MXC_CPU_MX6SX))
533 set_uart_from_osc(); 534 set_uart_from_osc();
534 535
535 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ 536 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
536 537
537 if (!is_cpu_type(MXC_CPU_MX6SL) && !is_cpu_type(MXC_CPU_MX6UL)) 538 if (!is_cpu_type(MXC_CPU_MX6SL) && !is_cpu_type(MXC_CPU_MX6UL) &&
539 !is_cpu_type(MXC_CPU_MX6ULL))
538 imx_set_pcie_phy_power_down(); 540 imx_set_pcie_phy_power_down();
539 541
540 if (!is_mx6dqp() && !is_cpu_type(MXC_CPU_MX6UL)) 542 if (!is_mx6dqp() && !is_cpu_type(MXC_CPU_MX6UL) &&
543 !is_cpu_type(MXC_CPU_MX6ULL))
541 imx_set_vddpu_power_down(); 544 imx_set_vddpu_power_down();
542 545
543 #ifdef CONFIG_APBH_DMA 546 #ifdef CONFIG_APBH_DMA
544 /* Start APBH DMA */ 547 /* Start APBH DMA */
545 mxs_dma_init(); 548 mxs_dma_init();
546 #endif 549 #endif
547 550
548 init_src(); 551 init_src();
549 552
550 if (is_mx6dqp()) 553 if (is_mx6dqp())
551 writel(0x80000201, 0xbb0608); 554 writel(0x80000201, 0xbb0608);
552 555
553 return 0; 556 return 0;
554 } 557 }
555 558
556 #ifdef CONFIG_ENV_IS_IN_MMC 559 #ifdef CONFIG_ENV_IS_IN_MMC
557 __weak int board_mmc_get_env_dev(int devno) 560 __weak int board_mmc_get_env_dev(int devno)
558 { 561 {
559 return CONFIG_SYS_MMC_ENV_DEV; 562 return CONFIG_SYS_MMC_ENV_DEV;
560 } 563 }
561 564
562 static int mmc_get_boot_dev(void) 565 static int mmc_get_boot_dev(void)
563 { 566 {
564 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 567 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
565 u32 soc_sbmr = readl(&src_regs->sbmr1); 568 u32 soc_sbmr = readl(&src_regs->sbmr1);
566 u32 bootsel; 569 u32 bootsel;
567 int devno; 570 int devno;
568 571
569 /* 572 /*
570 * Refer to 573 * Refer to
571 * "i.MX 6Dual/6Quad Applications Processor Reference Manual" 574 * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
572 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration" 575 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
573 * i.MX6SL/SX/UL has same layout. 576 * i.MX6SL/SX/UL has same layout.
574 */ 577 */
575 bootsel = (soc_sbmr & 0x000000FF) >> 6; 578 bootsel = (soc_sbmr & 0x000000FF) >> 6;
576 579
577 /* No boot from sd/mmc */ 580 /* No boot from sd/mmc */
578 if (bootsel != 1) 581 if (bootsel != 1)
579 return -1; 582 return -1;
580 583
581 /* BOOT_CFG2[3] and BOOT_CFG2[4] */ 584 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
582 devno = (soc_sbmr & 0x00001800) >> 11; 585 devno = (soc_sbmr & 0x00001800) >> 11;
583 586
584 return devno; 587 return devno;
585 } 588 }
586 589
587 int mmc_get_env_dev(void) 590 int mmc_get_env_dev(void)
588 { 591 {
589 int devno = mmc_get_boot_dev(); 592 int devno = mmc_get_boot_dev();
590 593
591 /* If not boot from sd/mmc, use default value */ 594 /* If not boot from sd/mmc, use default value */
592 if (devno < 0) 595 if (devno < 0)
593 return CONFIG_SYS_MMC_ENV_DEV; 596 return CONFIG_SYS_MMC_ENV_DEV;
594 597
595 return board_mmc_get_env_dev(devno); 598 return board_mmc_get_env_dev(devno);
596 } 599 }
597 600
598 #ifdef CONFIG_SYS_MMC_ENV_PART 601 #ifdef CONFIG_SYS_MMC_ENV_PART
599 __weak int board_mmc_get_env_part(int devno) 602 __weak int board_mmc_get_env_part(int devno)
600 { 603 {
601 return CONFIG_SYS_MMC_ENV_PART; 604 return CONFIG_SYS_MMC_ENV_PART;
602 } 605 }
603 606
604 uint mmc_get_env_part(struct mmc *mmc) 607 uint mmc_get_env_part(struct mmc *mmc)
605 { 608 {
606 int devno = mmc_get_boot_dev(); 609 int devno = mmc_get_boot_dev();
607 610
608 /* If not boot from sd/mmc, use default value */ 611 /* If not boot from sd/mmc, use default value */
609 if (devno < 0) 612 if (devno < 0)
610 return CONFIG_SYS_MMC_ENV_PART; 613 return CONFIG_SYS_MMC_ENV_PART;
611 614
612 return board_mmc_get_env_part(devno); 615 return board_mmc_get_env_part(devno);
613 } 616 }
614 #endif 617 #endif
615 #endif 618 #endif
616 619
617 int board_postclk_init(void) 620 int board_postclk_init(void)
618 { 621 {
619 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ 622 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
620 623
621 return 0; 624 return 0;
622 } 625 }
623 626
624 #ifdef CONFIG_SERIAL_TAG 627 #ifdef CONFIG_SERIAL_TAG
625 void get_board_serial(struct tag_serialnr *serialnr) 628 void get_board_serial(struct tag_serialnr *serialnr)
626 { 629 {
627 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 630 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
628 struct fuse_bank *bank = &ocotp->bank[0]; 631 struct fuse_bank *bank = &ocotp->bank[0];
629 struct fuse_bank0_regs *fuse = 632 struct fuse_bank0_regs *fuse =
630 (struct fuse_bank0_regs *)bank->fuse_regs; 633 (struct fuse_bank0_regs *)bank->fuse_regs;
631 634
632 serialnr->low = fuse->uid_low; 635 serialnr->low = fuse->uid_low;
633 serialnr->high = fuse->uid_high; 636 serialnr->high = fuse->uid_high;
634 } 637 }
635 #endif 638 #endif
636 639
637 #if defined(CONFIG_FEC_MXC) 640 #if defined(CONFIG_FEC_MXC)
638 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 641 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
639 { 642 {
640 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 643 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
641 struct fuse_bank *bank = &ocotp->bank[4]; 644 struct fuse_bank *bank = &ocotp->bank[4];
642 struct fuse_bank4_regs *fuse = 645 struct fuse_bank4_regs *fuse =
643 (struct fuse_bank4_regs *)bank->fuse_regs; 646 (struct fuse_bank4_regs *)bank->fuse_regs;
644 647
645 if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) && 648 if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
646 dev_id == 1) { 649 is_cpu_type(MXC_CPU_MX6ULL)) && dev_id == 1) {
647 u32 value = readl(&fuse->mac_addr2); 650 u32 value = readl(&fuse->mac_addr2);
648 mac[0] = value >> 24 ; 651 mac[0] = value >> 24 ;
649 mac[1] = value >> 16 ; 652 mac[1] = value >> 16 ;
650 mac[2] = value >> 8 ; 653 mac[2] = value >> 8 ;
651 mac[3] = value ; 654 mac[3] = value ;
652 655
653 value = readl(&fuse->mac_addr1); 656 value = readl(&fuse->mac_addr1);
654 mac[4] = value >> 24 ; 657 mac[4] = value >> 24 ;
655 mac[5] = value >> 16 ; 658 mac[5] = value >> 16 ;
656 659
657 } else { 660 } else {
658 u32 value = readl(&fuse->mac_addr1); 661 u32 value = readl(&fuse->mac_addr1);
659 mac[0] = (value >> 8); 662 mac[0] = (value >> 8);
660 mac[1] = value ; 663 mac[1] = value ;
661 664
662 value = readl(&fuse->mac_addr0); 665 value = readl(&fuse->mac_addr0);
663 mac[2] = value >> 24 ; 666 mac[2] = value >> 24 ;
664 mac[3] = value >> 16 ; 667 mac[3] = value >> 16 ;
665 mac[4] = value >> 8 ; 668 mac[4] = value >> 8 ;
666 mac[5] = value ; 669 mac[5] = value ;
667 } 670 }
668 671
669 } 672 }
670 #endif 673 #endif
671 674
672 /* 675 /*
673 * cfg_val will be used for 676 * cfg_val will be used for
674 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] 677 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
675 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0] 678 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
676 * instead of SBMR1 to determine the boot device. 679 * instead of SBMR1 to determine the boot device.
677 */ 680 */
678 const struct boot_mode soc_boot_modes[] = { 681 const struct boot_mode soc_boot_modes[] = {
679 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, 682 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
680 /* reserved value should start rom usb */ 683 /* reserved value should start rom usb */
681 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, 684 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
682 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, 685 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
683 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, 686 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
684 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, 687 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
685 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, 688 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
686 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, 689 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
687 /* 4 bit bus width */ 690 /* 4 bit bus width */
688 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, 691 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
689 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 692 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
690 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 693 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
691 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 694 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
692 {NULL, 0}, 695 {NULL, 0},
693 }; 696 };
694 697
695 enum boot_device get_boot_device(void) 698 enum boot_device get_boot_device(void)
696 { 699 {
697 enum boot_device boot_dev = UNKNOWN_BOOT; 700 enum boot_device boot_dev = UNKNOWN_BOOT;
698 uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); 701 uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
699 uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ; 702 uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
700 uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; 703 uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
701 uint bt_dev_port = (soc_sbmr & 0x00001800) >> 11; 704 uint bt_dev_port = (soc_sbmr & 0x00001800) >> 11;
702 705
703 switch (bt_mem_ctl) { 706 switch (bt_mem_ctl) {
704 case 0x0: 707 case 0x0:
705 if (bt_mem_type) 708 if (bt_mem_type)
706 boot_dev = ONE_NAND_BOOT; 709 boot_dev = ONE_NAND_BOOT;
707 else 710 else
708 boot_dev = WEIM_NOR_BOOT; 711 boot_dev = WEIM_NOR_BOOT;
709 break; 712 break;
710 case 0x2: 713 case 0x2:
711 boot_dev = SATA_BOOT; 714 boot_dev = SATA_BOOT;
712 break; 715 break;
713 case 0x3: 716 case 0x3:
714 if (bt_mem_type) 717 if (bt_mem_type)
715 boot_dev = I2C_BOOT; 718 boot_dev = I2C_BOOT;
716 else 719 else
717 boot_dev = SPI_NOR_BOOT; 720 boot_dev = SPI_NOR_BOOT;
718 break; 721 break;
719 case 0x4: 722 case 0x4:
720 case 0x5: 723 case 0x5:
721 boot_dev = bt_dev_port + SD1_BOOT; 724 boot_dev = bt_dev_port + SD1_BOOT;
722 break; 725 break;
723 case 0x6: 726 case 0x6:
724 case 0x7: 727 case 0x7:
725 boot_dev = bt_dev_port + MMC1_BOOT; 728 boot_dev = bt_dev_port + MMC1_BOOT;
726 break; 729 break;
727 case 0x8 ... 0xf: 730 case 0x8 ... 0xf:
728 boot_dev = NAND_BOOT; 731 boot_dev = NAND_BOOT;
729 break; 732 break;
730 default: 733 default:
731 boot_dev = UNKNOWN_BOOT; 734 boot_dev = UNKNOWN_BOOT;
732 break; 735 break;
733 } 736 }
734 737
735 return boot_dev; 738 return boot_dev;
736 } 739 }
737 740
738 void set_wdog_reset(struct wdog_regs *wdog) 741 void set_wdog_reset(struct wdog_regs *wdog)
739 { 742 {
740 u32 reg = readw(&wdog->wcr); 743 u32 reg = readw(&wdog->wcr);
741 /* 744 /*
742 * use WDOG_B mode to reset external pmic because it's risky for the 745 * use WDOG_B mode to reset external pmic because it's risky for the
743 * following watchdog reboot in case of cpu freq at lowest 400Mhz with 746 * following watchdog reboot in case of cpu freq at lowest 400Mhz with
744 * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So 747 * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So
745 * in ldo-bypass mode watchdog reset will only triger POR reset, not 748 * in ldo-bypass mode watchdog reset will only triger POR reset, not
746 * WDOG reset. But below code depends on hardware design, if HW didn't 749 * WDOG reset. But below code depends on hardware design, if HW didn't
747 * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip 750 * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip
748 * these code since it assumed boot from 400Mhz always. 751 * these code since it assumed boot from 400Mhz always.
749 */ 752 */
750 reg = readw(&wdog->wcr); 753 reg = readw(&wdog->wcr);
751 reg |= 1 << 3; 754 reg |= 1 << 3;
752 /* 755 /*
753 * WDZST bit is write-once only bit. Align this bit in kernel, 756 * WDZST bit is write-once only bit. Align this bit in kernel,
754 * otherwise kernel code will have no chance to set this bit. 757 * otherwise kernel code will have no chance to set this bit.
755 */ 758 */
756 reg |= 1 << 0; 759 reg |= 1 << 0;
757 writew(reg, &wdog->wcr); 760 writew(reg, &wdog->wcr);
758 } 761 }
759 762
760 void reset_misc(void) 763 void reset_misc(void)
761 { 764 {
762 #ifdef CONFIG_VIDEO_MXS 765 #ifdef CONFIG_VIDEO_MXS
763 lcdif_power_down(); 766 lcdif_power_down();
764 #endif 767 #endif
765 } 768 }
766 769
767 void s_init(void) 770 void s_init(void)
768 { 771 {
769 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 772 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
770 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 773 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
771 u32 mask480; 774 u32 mask480;
772 u32 mask528; 775 u32 mask528;
773 u32 reg, periph1, periph2; 776 u32 reg, periph1, periph2;
774 777
775 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || 778 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
776 is_cpu_type(MXC_CPU_MX6ULL)) 779 is_cpu_type(MXC_CPU_MX6ULL))
777 return; 780 return;
778 781
779 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs 782 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
780 * to make sure PFD is working right, otherwise, PFDs may 783 * to make sure PFD is working right, otherwise, PFDs may
781 * not output clock after reset, MX6DL and MX6SL have added 396M pfd 784 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
782 * workaround in ROM code, as bus clock need it 785 * workaround in ROM code, as bus clock need it
783 */ 786 */
784 787
785 mask480 = ANATOP_PFD_CLKGATE_MASK(0) | 788 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
786 ANATOP_PFD_CLKGATE_MASK(1) | 789 ANATOP_PFD_CLKGATE_MASK(1) |
787 ANATOP_PFD_CLKGATE_MASK(2) | 790 ANATOP_PFD_CLKGATE_MASK(2) |
788 ANATOP_PFD_CLKGATE_MASK(3); 791 ANATOP_PFD_CLKGATE_MASK(3);
789 mask528 = ANATOP_PFD_CLKGATE_MASK(1) | 792 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
790 ANATOP_PFD_CLKGATE_MASK(3); 793 ANATOP_PFD_CLKGATE_MASK(3);
791 794
792 reg = readl(&ccm->cbcmr); 795 reg = readl(&ccm->cbcmr);
793 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) 796 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
794 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET); 797 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
795 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) 798 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
796 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET); 799 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
797 800
798 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */ 801 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
799 if ((periph2 != 0x2) && (periph1 != 0x2)) 802 if ((periph2 != 0x2) && (periph1 != 0x2))
800 mask528 |= ANATOP_PFD_CLKGATE_MASK(0); 803 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
801 804
802 if ((periph2 != 0x1) && (periph1 != 0x1) && 805 if ((periph2 != 0x1) && (periph1 != 0x1) &&
803 (periph2 != 0x3) && (periph1 != 0x3)) 806 (periph2 != 0x3) && (periph1 != 0x3))
804 mask528 |= ANATOP_PFD_CLKGATE_MASK(2); 807 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
805 808
806 writel(mask480, &anatop->pfd_480_set); 809 writel(mask480, &anatop->pfd_480_set);
807 writel(mask528, &anatop->pfd_528_set); 810 writel(mask528, &anatop->pfd_528_set);
808 writel(mask480, &anatop->pfd_480_clr); 811 writel(mask480, &anatop->pfd_480_clr);
809 writel(mask528, &anatop->pfd_528_clr); 812 writel(mask528, &anatop->pfd_528_clr);
810 } 813 }
811 814
812 #ifdef CONFIG_IMX_HDMI 815 #ifdef CONFIG_IMX_HDMI
813 void imx_enable_hdmi_phy(void) 816 void imx_enable_hdmi_phy(void)
814 { 817 {
815 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; 818 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
816 u8 reg; 819 u8 reg;
817 reg = readb(&hdmi->phy_conf0); 820 reg = readb(&hdmi->phy_conf0);
818 reg |= HDMI_PHY_CONF0_PDZ_MASK; 821 reg |= HDMI_PHY_CONF0_PDZ_MASK;
819 writeb(reg, &hdmi->phy_conf0); 822 writeb(reg, &hdmi->phy_conf0);
820 udelay(3000); 823 udelay(3000);
821 reg |= HDMI_PHY_CONF0_ENTMDS_MASK; 824 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
822 writeb(reg, &hdmi->phy_conf0); 825 writeb(reg, &hdmi->phy_conf0);
823 udelay(3000); 826 udelay(3000);
824 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; 827 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
825 writeb(reg, &hdmi->phy_conf0); 828 writeb(reg, &hdmi->phy_conf0);
826 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); 829 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
827 } 830 }
828 831
829 void imx_setup_hdmi(void) 832 void imx_setup_hdmi(void)
830 { 833 {
831 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 834 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
832 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; 835 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
833 int reg, count; 836 int reg, count;
834 u8 val; 837 u8 val;
835 838
836 /* Turn on HDMI PHY clock */ 839 /* Turn on HDMI PHY clock */
837 reg = readl(&mxc_ccm->CCGR2); 840 reg = readl(&mxc_ccm->CCGR2);
838 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| 841 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
839 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; 842 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
840 writel(reg, &mxc_ccm->CCGR2); 843 writel(reg, &mxc_ccm->CCGR2);
841 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); 844 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
842 reg = readl(&mxc_ccm->chsccdr); 845 reg = readl(&mxc_ccm->chsccdr);
843 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| 846 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
844 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| 847 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
845 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); 848 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
846 reg |= (CHSCCDR_PODF_DIVIDE_BY_3 849 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
847 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) 850 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
848 |(CHSCCDR_IPU_PRE_CLK_540M_PFD 851 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
849 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); 852 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
850 writel(reg, &mxc_ccm->chsccdr); 853 writel(reg, &mxc_ccm->chsccdr);
851 854
852 /* Workaround to clear the overflow condition */ 855 /* Workaround to clear the overflow condition */
853 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) { 856 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
854 /* TMDS software reset */ 857 /* TMDS software reset */
855 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz); 858 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
856 val = readb(&hdmi->fc_invidconf); 859 val = readb(&hdmi->fc_invidconf);
857 for (count = 0 ; count < 5 ; count++) 860 for (count = 0 ; count < 5 ; count++)
858 writeb(val, &hdmi->fc_invidconf); 861 writeb(val, &hdmi->fc_invidconf);
859 } 862 }
860 } 863 }
861 #endif 864 #endif
862 865
863 #ifdef CONFIG_IMX_BOOTAUX 866 #ifdef CONFIG_IMX_BOOTAUX
864 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) 867 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
865 { 868 {
866 struct src *src_reg; 869 struct src *src_reg;
867 u32 stack, pc; 870 u32 stack, pc;
868 871
869 if (!boot_private_data) 872 if (!boot_private_data)
870 return -EINVAL; 873 return -EINVAL;
871 874
872 stack = *(u32 *)boot_private_data; 875 stack = *(u32 *)boot_private_data;
873 pc = *(u32 *)(boot_private_data + 4); 876 pc = *(u32 *)(boot_private_data + 4);
874 877
875 /* Set the stack and pc to M4 bootROM */ 878 /* Set the stack and pc to M4 bootROM */
876 writel(stack, M4_BOOTROM_BASE_ADDR); 879 writel(stack, M4_BOOTROM_BASE_ADDR);
877 writel(pc, M4_BOOTROM_BASE_ADDR + 4); 880 writel(pc, M4_BOOTROM_BASE_ADDR + 4);
878 881
879 /* Enable M4 */ 882 /* Enable M4 */
880 src_reg = (struct src *)SRC_BASE_ADDR; 883 src_reg = (struct src *)SRC_BASE_ADDR;
881 clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK, 884 clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
882 SRC_SCR_M4_ENABLE_MASK); 885 SRC_SCR_M4_ENABLE_MASK);
883 886
884 return 0; 887 return 0;
885 } 888 }
886 889
887 int arch_auxiliary_core_check_up(u32 core_id) 890 int arch_auxiliary_core_check_up(u32 core_id)
888 { 891 {
889 struct src *src_reg = (struct src *)SRC_BASE_ADDR; 892 struct src *src_reg = (struct src *)SRC_BASE_ADDR;
890 unsigned val; 893 unsigned val;
891 894
892 val = readl(&src_reg->scr); 895 val = readl(&src_reg->scr);
893 896
894 if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK) 897 if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
895 return 0; /* assert in reset */ 898 return 0; /* assert in reset */
896 899
897 return 1; 900 return 1;
898 } 901 }
899 #endif 902 #endif
900 903
901 #ifdef CONFIG_LDO_BYPASS_CHECK 904 #ifdef CONFIG_LDO_BYPASS_CHECK
902 DECLARE_GLOBAL_DATA_PTR; 905 DECLARE_GLOBAL_DATA_PTR;
903 static int ldo_bypass; 906 static int ldo_bypass;
904 907
905 int check_ldo_bypass(void) 908 int check_ldo_bypass(void)
906 { 909 {
907 const int *ldo_mode; 910 const int *ldo_mode;
908 int node; 911 int node;
909 912
910 /* get the right fdt_blob from the global working_fdt */ 913 /* get the right fdt_blob from the global working_fdt */
911 gd->fdt_blob = working_fdt; 914 gd->fdt_blob = working_fdt;
912 /* Get the node from FDT for anatop ldo-bypass */ 915 /* Get the node from FDT for anatop ldo-bypass */
913 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 916 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
914 "fsl,imx6q-gpc"); 917 "fsl,imx6q-gpc");
915 if (node < 0) { 918 if (node < 0) {
916 printf("No gpc device node %d, force to ldo-enable.\n", node); 919 printf("No gpc device node %d, force to ldo-enable.\n", node);
917 return 0; 920 return 0;
918 } 921 }
919 ldo_mode = fdt_getprop(gd->fdt_blob, node, "fsl,ldo-bypass", NULL); 922 ldo_mode = fdt_getprop(gd->fdt_blob, node, "fsl,ldo-bypass", NULL);
920 /* 923 /*
921 * return 1 if "fsl,ldo-bypass = <1>", else return 0 if 924 * return 1 if "fsl,ldo-bypass = <1>", else return 0 if
922 * "fsl,ldo-bypass = <0>" or no "fsl,ldo-bypass" property 925 * "fsl,ldo-bypass = <0>" or no "fsl,ldo-bypass" property
923 */ 926 */
924 ldo_bypass = fdt32_to_cpu(*ldo_mode) == 1 ? 1 : 0; 927 ldo_bypass = fdt32_to_cpu(*ldo_mode) == 1 ? 1 : 0;
925 928
926 return ldo_bypass; 929 return ldo_bypass;
927 } 930 }
928 931
929 int check_1_2G(void) 932 int check_1_2G(void)
930 { 933 {
931 u32 reg; 934 u32 reg;
932 int result = 0; 935 int result = 0;
933 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 936 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
934 struct fuse_bank *bank = &ocotp->bank[0]; 937 struct fuse_bank *bank = &ocotp->bank[0];
935 struct fuse_bank0_regs *fuse_bank0 = 938 struct fuse_bank0_regs *fuse_bank0 =
936 (struct fuse_bank0_regs *)bank->fuse_regs; 939 (struct fuse_bank0_regs *)bank->fuse_regs;
937 940
938 reg = readl(&fuse_bank0->cfg3); 941 reg = readl(&fuse_bank0->cfg3);
939 if (((reg >> 16) & 0x3) == 0x3) { 942 if (((reg >> 16) & 0x3) == 0x3) {
940 if (ldo_bypass) { 943 if (ldo_bypass) {
941 printf("Wrong dtb file used! i.MX6Q@1.2Ghz only " 944 printf("Wrong dtb file used! i.MX6Q@1.2Ghz only "
942 "works with ldo-enable mode!\n"); 945 "works with ldo-enable mode!\n");
943 /* 946 /*
944 * Currently, only imx6q-sabresd board might be here, 947 * Currently, only imx6q-sabresd board might be here,
945 * since only i.MX6Q support 1.2G and only Sabresd board 948 * since only i.MX6Q support 1.2G and only Sabresd board
946 * support ldo-bypass mode. So hardcode here. 949 * support ldo-bypass mode. So hardcode here.
947 * You can also modify your board(i.MX6Q) dtb name if it 950 * You can also modify your board(i.MX6Q) dtb name if it
948 * supports both ldo-bypass and ldo-enable mode. 951 * supports both ldo-bypass and ldo-enable mode.
949 */ 952 */
950 printf("Please use imx6q-sabresd-ldo.dtb!\n"); 953 printf("Please use imx6q-sabresd-ldo.dtb!\n");
951 hang(); 954 hang();
952 } 955 }
953 result = 1; 956 result = 1;
954 } 957 }
955 958
956 return result; 959 return result;
957 } 960 }
958 961
959 static int arm_orig_podf; 962 static int arm_orig_podf;
960 void set_arm_freq_400M(bool is_400M) 963 void set_arm_freq_400M(bool is_400M)
961 { 964 {
962 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 965 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
963 966
964 if (is_400M) 967 if (is_400M)
965 writel(0x1, &mxc_ccm->cacrr); 968 writel(0x1, &mxc_ccm->cacrr);
966 else 969 else
967 writel(arm_orig_podf, &mxc_ccm->cacrr); 970 writel(arm_orig_podf, &mxc_ccm->cacrr);
968 } 971 }
969 972
970 void prep_anatop_bypass(void) 973 void prep_anatop_bypass(void)
971 { 974 {
972 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 975 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
973 976
974 arm_orig_podf = readl(&mxc_ccm->cacrr); 977 arm_orig_podf = readl(&mxc_ccm->cacrr);
975 /* 978 /*
976 * Downgrade ARM speed to 400Mhz as half of boot 800Mhz before ldo 979 * Downgrade ARM speed to 400Mhz as half of boot 800Mhz before ldo
977 * bypassed, also downgrade internal vddarm ldo to 0.975V. 980 * bypassed, also downgrade internal vddarm ldo to 0.975V.
978 * VDDARM_IN 0.975V + 125mV = 1.1V < Max(1.3V) 981 * VDDARM_IN 0.975V + 125mV = 1.1V < Max(1.3V)
979 * otherwise at 800Mhz(i.mx6dl): 982 * otherwise at 800Mhz(i.mx6dl):
980 * VDDARM_IN 1.175V + 125mV = 1.3V = Max(1.3V) 983 * VDDARM_IN 1.175V + 125mV = 1.3V = Max(1.3V)
981 * We need provide enough gap in this case. 984 * We need provide enough gap in this case.
982 * skip if boot from 400M. 985 * skip if boot from 400M.
983 */ 986 */
984 if (!arm_orig_podf) 987 if (!arm_orig_podf)
985 set_arm_freq_400M(true); 988 set_arm_freq_400M(true);
986 989
987 if (!is_cpu_type(MXC_CPU_MX6DL) && !is_cpu_type(MXC_CPU_MX6SX)) 990 if (!is_cpu_type(MXC_CPU_MX6DL) && !is_cpu_type(MXC_CPU_MX6SX))
988 set_ldo_voltage(LDO_ARM, 975); 991 set_ldo_voltage(LDO_ARM, 975);
989 else 992 else
990 set_ldo_voltage(LDO_ARM, 1150); 993 set_ldo_voltage(LDO_ARM, 1150);
991 } 994 }
992 995
993 int set_anatop_bypass(int wdog_reset_pin) 996 int set_anatop_bypass(int wdog_reset_pin)
994 { 997 {
995 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 998 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
996 struct wdog_regs *wdog; 999 struct wdog_regs *wdog;
997 u32 reg = readl(&anatop->reg_core); 1000 u32 reg = readl(&anatop->reg_core);
998 1001
999 /* bypass VDDARM/VDDSOC */ 1002 /* bypass VDDARM/VDDSOC */
1000 reg = reg | (0x1F << 18) | 0x1F; 1003 reg = reg | (0x1F << 18) | 0x1F;
1001 writel(reg, &anatop->reg_core); 1004 writel(reg, &anatop->reg_core);
1002 1005
1003 if (wdog_reset_pin == 2) 1006 if (wdog_reset_pin == 2)
1004 wdog = (struct wdog_regs *) WDOG2_BASE_ADDR; 1007 wdog = (struct wdog_regs *) WDOG2_BASE_ADDR;
1005 else if (wdog_reset_pin == 1) 1008 else if (wdog_reset_pin == 1)
1006 wdog = (struct wdog_regs *) WDOG1_BASE_ADDR; 1009 wdog = (struct wdog_regs *) WDOG1_BASE_ADDR;
1007 else 1010 else
1008 return arm_orig_podf; 1011 return arm_orig_podf;
1009 set_wdog_reset(wdog); 1012 set_wdog_reset(wdog);
1010 return arm_orig_podf; 1013 return arm_orig_podf;
1011 } 1014 }
1012 1015
1013 void finish_anatop_bypass(void) 1016 void finish_anatop_bypass(void)
1014 { 1017 {
1015 if (!arm_orig_podf) 1018 if (!arm_orig_podf)
1016 set_arm_freq_400M(false); 1019 set_arm_freq_400M(false);
1017 } 1020 }
1018 #endif 1021 #endif
1019 1022
1020 #ifdef CONFIG_FSL_FASTBOOT 1023 #ifdef CONFIG_FSL_FASTBOOT
1021 1024
1022 #ifdef CONFIG_ANDROID_RECOVERY 1025 #ifdef CONFIG_ANDROID_RECOVERY
1023 #define ANDROID_RECOVERY_BOOT (1 << 7) 1026 #define ANDROID_RECOVERY_BOOT (1 << 7)
1024 /* check if the recovery bit is set by kernel, it can be set by kernel 1027 /* check if the recovery bit is set by kernel, it can be set by kernel
1025 * issue a command '# reboot recovery' */ 1028 * issue a command '# reboot recovery' */
1026 int recovery_check_and_clean_flag(void) 1029 int recovery_check_and_clean_flag(void)
1027 { 1030 {
1028 int flag_set = 0; 1031 int flag_set = 0;
1029 u32 reg; 1032 u32 reg;
1030 reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR); 1033 reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR);
1031 1034
1032 flag_set = !!(reg & ANDROID_RECOVERY_BOOT); 1035 flag_set = !!(reg & ANDROID_RECOVERY_BOOT);
1033 printf("check_and_clean: reg %x, flag_set %d\n", reg, flag_set); 1036 printf("check_and_clean: reg %x, flag_set %d\n", reg, flag_set);
1034 /* clean it in case looping infinite here.... */ 1037 /* clean it in case looping infinite here.... */
1035 if (flag_set) { 1038 if (flag_set) {
1036 reg &= ~ANDROID_RECOVERY_BOOT; 1039 reg &= ~ANDROID_RECOVERY_BOOT;
1037 writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR); 1040 writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR);
1038 } 1041 }
1039 1042
1040 return flag_set; 1043 return flag_set;
1041 } 1044 }
1042 #endif /*CONFIG_ANDROID_RECOVERY*/ 1045 #endif /*CONFIG_ANDROID_RECOVERY*/
1043 1046
1044 #define ANDROID_FASTBOOT_BOOT (1 << 8) 1047 #define ANDROID_FASTBOOT_BOOT (1 << 8)
1045 /* check if the recovery bit is set by kernel, it can be set by kernel 1048 /* check if the recovery bit is set by kernel, it can be set by kernel
1046 * issue a command '# reboot fastboot' */ 1049 * issue a command '# reboot fastboot' */
1047 int fastboot_check_and_clean_flag(void) 1050 int fastboot_check_and_clean_flag(void)
1048 { 1051 {
1049 int flag_set = 0; 1052 int flag_set = 0;
1050 u32 reg; 1053 u32 reg;
1051 1054
1052 reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR); 1055 reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR);
1053 1056
1054 flag_set = !!(reg & ANDROID_FASTBOOT_BOOT); 1057 flag_set = !!(reg & ANDROID_FASTBOOT_BOOT);
1055 1058
1056 /* clean it in case looping infinite here.... */ 1059 /* clean it in case looping infinite here.... */
1057 if (flag_set) { 1060 if (flag_set) {
1058 reg &= ~ANDROID_FASTBOOT_BOOT; 1061 reg &= ~ANDROID_FASTBOOT_BOOT;
1059 writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR); 1062 writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR);
1060 } 1063 }
1061 1064
1062 return flag_set; 1065 return flag_set;
1063 } 1066 }
1064 1067
1065 void fastboot_enable_flag(void) 1068 void fastboot_enable_flag(void)
1066 { 1069 {
1067 setbits_le32(SNVS_BASE_ADDR + SNVS_LPGPR, 1070 setbits_le32(SNVS_BASE_ADDR + SNVS_LPGPR,
1068 ANDROID_FASTBOOT_BOOT); 1071 ANDROID_FASTBOOT_BOOT);
1069 } 1072 }
1070 #endif /*CONFIG_FSL_FASTBOOT*/ 1073 #endif /*CONFIG_FSL_FASTBOOT*/
1071 1074
1072 1075
arch/arm/imx-common/init.c
Diff comments   View file @ 05922b0
1 /* 1 /*
2 * Copyright 2015-2016 Freescale Semiconductor, Inc. 2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <asm/io.h> 7 #include <asm/io.h>
8 #include <asm/arch/imx-regs.h> 8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/clock.h> 9 #include <asm/arch/clock.h>
10 #include <asm/arch/sys_proto.h> 10 #include <asm/arch/sys_proto.h>
11 #include <asm/imx-common/boot_mode.h> 11 #include <asm/imx-common/boot_mode.h>
12 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/crm_regs.h>
13 13
14 void init_aips(void) 14 void init_aips(void)
15 { 15 {
16 struct aipstz_regs *aips1, *aips2, *aips3; 16 struct aipstz_regs *aips1, *aips2, *aips3;
17 17
18 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; 18 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
19 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; 19 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
20 aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR; 20 aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
21 21
22 /* 22 /*
23 * Set all MPROTx to be non-bufferable, trusted for R/W, 23 * Set all MPROTx to be non-bufferable, trusted for R/W,
24 * not forced to user-mode. 24 * not forced to user-mode.
25 */ 25 */
26 writel(0x77777777, &aips1->mprot0); 26 writel(0x77777777, &aips1->mprot0);
27 writel(0x77777777, &aips1->mprot1); 27 writel(0x77777777, &aips1->mprot1);
28 writel(0x77777777, &aips2->mprot0); 28 writel(0x77777777, &aips2->mprot0);
29 writel(0x77777777, &aips2->mprot1); 29 writel(0x77777777, &aips2->mprot1);
30 30
31 /* 31 /*
32 * Set all OPACRx to be non-bufferable, not require 32 * Set all OPACRx to be non-bufferable, not require
33 * supervisor privilege level for access,allow for 33 * supervisor privilege level for access,allow for
34 * write access and untrusted master access. 34 * write access and untrusted master access.
35 */ 35 */
36 writel(0x00000000, &aips1->opacr0); 36 writel(0x00000000, &aips1->opacr0);
37 writel(0x00000000, &aips1->opacr1); 37 writel(0x00000000, &aips1->opacr1);
38 writel(0x00000000, &aips1->opacr2); 38 writel(0x00000000, &aips1->opacr2);
39 writel(0x00000000, &aips1->opacr3); 39 writel(0x00000000, &aips1->opacr3);
40 writel(0x00000000, &aips1->opacr4); 40 writel(0x00000000, &aips1->opacr4);
41 writel(0x00000000, &aips2->opacr0); 41 writel(0x00000000, &aips2->opacr0);
42 writel(0x00000000, &aips2->opacr1); 42 writel(0x00000000, &aips2->opacr1);
43 writel(0x00000000, &aips2->opacr2); 43 writel(0x00000000, &aips2->opacr2);
44 writel(0x00000000, &aips2->opacr3); 44 writel(0x00000000, &aips2->opacr3);
45 writel(0x00000000, &aips2->opacr4); 45 writel(0x00000000, &aips2->opacr4);
46 46
47 if (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6SX) || 47 if (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6SX) ||
48 is_soc_type(MXC_SOC_MX7)) { 48 is_soc_type(MXC_SOC_MX7)) {
49 /* 49 /*
50 * Set all MPROTx to be non-bufferable, trusted for R/W, 50 * Set all MPROTx to be non-bufferable, trusted for R/W,
51 * not forced to user-mode. 51 * not forced to user-mode.
52 */ 52 */
53 writel(0x77777777, &aips3->mprot0); 53 writel(0x77777777, &aips3->mprot0);
54 writel(0x77777777, &aips3->mprot1); 54 writel(0x77777777, &aips3->mprot1);
55 55
56 /* 56 /*
57 * Set all OPACRx to be non-bufferable, not require 57 * Set all OPACRx to be non-bufferable, not require
58 * supervisor privilege level for access,allow for 58 * supervisor privilege level for access,allow for
59 * write access and untrusted master access. 59 * write access and untrusted master access.
60 */ 60 */
61 writel(0x00000000, &aips3->opacr0); 61 writel(0x00000000, &aips3->opacr0);
62 writel(0x00000000, &aips3->opacr1); 62 writel(0x00000000, &aips3->opacr1);
63 writel(0x00000000, &aips3->opacr2); 63 writel(0x00000000, &aips3->opacr2);
64 writel(0x00000000, &aips3->opacr3); 64 writel(0x00000000, &aips3->opacr3);
65 writel(0x00000000, &aips3->opacr4); 65 writel(0x00000000, &aips3->opacr4);
66 } 66 }
67 } 67 }
68 68
69 void imx_set_wdog_powerdown(bool enable) 69 void imx_set_wdog_powerdown(bool enable)
70 { 70 {
71 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; 71 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
72 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; 72 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
73 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; 73 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
74 #ifdef CONFIG_MX7D 74 #ifdef CONFIG_MX7D
75 struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR; 75 struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
76 #endif 76 #endif
77 77
78 /* Write to the PDE (Power Down Enable) bit */ 78 /* Write to the PDE (Power Down Enable) bit */
79 writew(enable, &wdog1->wmcr); 79 writew(enable, &wdog1->wmcr);
80 writew(enable, &wdog2->wmcr); 80 writew(enable, &wdog2->wmcr);
81 81
82 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || 82 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
83 is_soc_type(MXC_SOC_MX7)) 83 is_cpu_type(MXC_CPU_MX6ULL) || is_soc_type(MXC_SOC_MX7))
84 writew(enable, &wdog3->wmcr); 84 writew(enable, &wdog3->wmcr);
85 #ifdef CONFIG_MX7D 85 #ifdef CONFIG_MX7D
86 writew(enable, &wdog4->wmcr); 86 writew(enable, &wdog4->wmcr);
87 #endif 87 #endif
88 } 88 }
89 89
90 #define SRC_SCR_WARM_RESET_ENABLE 0 90 #define SRC_SCR_WARM_RESET_ENABLE 0
91 91
92 void init_src(void) 92 void init_src(void)
93 { 93 {
94 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 94 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
95 u32 val; 95 u32 val;
96 96
97 /* 97 /*
98 * force warm reset sources to generate cold reset 98 * force warm reset sources to generate cold reset
99 * for a more reliable restart 99 * for a more reliable restart
100 */ 100 */
101 val = readl(&src_regs->scr); 101 val = readl(&src_regs->scr);
102 val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE); 102 val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
103 writel(val, &src_regs->scr); 103 writel(val, &src_regs->scr);
104 } 104 }
105 105
106 #ifdef CONFIG_CMD_BMODE 106 #ifdef CONFIG_CMD_BMODE
107 void boot_mode_apply(unsigned cfg_val) 107 void boot_mode_apply(unsigned cfg_val)
108 { 108 {
109 unsigned reg; 109 unsigned reg;
110 struct src *psrc = (struct src *)SRC_BASE_ADDR; 110 struct src *psrc = (struct src *)SRC_BASE_ADDR;
111 writel(cfg_val, &psrc->gpr9); 111 writel(cfg_val, &psrc->gpr9);
112 reg = readl(&psrc->gpr10); 112 reg = readl(&psrc->gpr10);
113 if (cfg_val) 113 if (cfg_val)
114 reg |= 1 << 28; 114 reg |= 1 << 28;
115 else 115 else
116 reg &= ~(1 << 28); 116 reg &= ~(1 << 28);
117 writel(reg, &psrc->gpr10); 117 writel(reg, &psrc->gpr10);
118 } 118 }
119 #endif 119 #endif
120 120
arch/arm/include/asm/arch-mx6/crm_regs.h
Diff comments   View file @ 05922b0
1 /* 1 /*
2 * Copyright 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
9 9
10 #define CCM_CCOSR 0x020c4060 10 #define CCM_CCOSR 0x020c4060
11 #define CCM_CCGR0 0x020C4068 11 #define CCM_CCGR0 0x020C4068
12 #define CCM_CCGR1 0x020C406c 12 #define CCM_CCGR1 0x020C406c
13 #define CCM_CCGR2 0x020C4070 13 #define CCM_CCGR2 0x020C4070
14 #define CCM_CCGR3 0x020C4074 14 #define CCM_CCGR3 0x020C4074
15 #define CCM_CCGR4 0x020C4078 15 #define CCM_CCGR4 0x020C4078
16 #define CCM_CCGR5 0x020C407c 16 #define CCM_CCGR5 0x020C407c
17 #define CCM_CCGR6 0x020C4080 17 #define CCM_CCGR6 0x020C4080
18 18
19 #define PMU_MISC2 0x020C8170 19 #define PMU_MISC2 0x020C8170
20 20
21 #ifndef __ASSEMBLY__ 21 #ifndef __ASSEMBLY__
22 struct mxc_ccm_reg { 22 struct mxc_ccm_reg {
23 u32 ccr; /* 0x0000 */ 23 u32 ccr; /* 0x0000 */
24 u32 ccdr; 24 u32 ccdr;
25 u32 csr; 25 u32 csr;
26 u32 ccsr; 26 u32 ccsr;
27 u32 cacrr; /* 0x0010*/ 27 u32 cacrr; /* 0x0010*/
28 u32 cbcdr; 28 u32 cbcdr;
29 u32 cbcmr; 29 u32 cbcmr;
30 u32 cscmr1; 30 u32 cscmr1;
31 u32 cscmr2; /* 0x0020 */ 31 u32 cscmr2; /* 0x0020 */
32 u32 cscdr1; 32 u32 cscdr1;
33 u32 cs1cdr; 33 u32 cs1cdr;
34 u32 cs2cdr; 34 u32 cs2cdr;
35 u32 cdcdr; /* 0x0030 */ 35 u32 cdcdr; /* 0x0030 */
36 u32 chsccdr; 36 u32 chsccdr;
37 u32 cscdr2; 37 u32 cscdr2;
38 u32 cscdr3; 38 u32 cscdr3;
39 u32 cscdr4; /* 0x0040 */ 39 u32 cscdr4; /* 0x0040 */
40 u32 resv0; 40 u32 resv0;
41 u32 cdhipr; 41 u32 cdhipr;
42 u32 cdcr; 42 u32 cdcr;
43 u32 ctor; /* 0x0050 */ 43 u32 ctor; /* 0x0050 */
44 u32 clpcr; 44 u32 clpcr;
45 u32 cisr; 45 u32 cisr;
46 u32 cimr; 46 u32 cimr;
47 u32 ccosr; /* 0x0060 */ 47 u32 ccosr; /* 0x0060 */
48 u32 cgpr; 48 u32 cgpr;
49 u32 CCGR0; 49 u32 CCGR0;
50 u32 CCGR1; 50 u32 CCGR1;
51 u32 CCGR2; /* 0x0070 */ 51 u32 CCGR2; /* 0x0070 */
52 u32 CCGR3; 52 u32 CCGR3;
53 u32 CCGR4; 53 u32 CCGR4;
54 u32 CCGR5; 54 u32 CCGR5;
55 u32 CCGR6; /* 0x0080 */ 55 u32 CCGR6; /* 0x0080 */
56 u32 CCGR7; 56 u32 CCGR7;
57 u32 cmeor; 57 u32 cmeor;
58 u32 resv[0xfdd]; 58 u32 resv[0xfdd];
59 u32 analog_pll_sys; /* 0x4000 */ 59 u32 analog_pll_sys; /* 0x4000 */
60 u32 analog_pll_sys_set; 60 u32 analog_pll_sys_set;
61 u32 analog_pll_sys_clr; 61 u32 analog_pll_sys_clr;
62 u32 analog_pll_sys_tog; 62 u32 analog_pll_sys_tog;
63 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ 63 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
64 u32 analog_usb1_pll_480_ctrl_set; 64 u32 analog_usb1_pll_480_ctrl_set;
65 u32 analog_usb1_pll_480_ctrl_clr; 65 u32 analog_usb1_pll_480_ctrl_clr;
66 u32 analog_usb1_pll_480_ctrl_tog; 66 u32 analog_usb1_pll_480_ctrl_tog;
67 u32 analog_reserved0[4]; 67 u32 analog_reserved0[4];
68 u32 analog_pll_528; /* 0x4030 */ 68 u32 analog_pll_528; /* 0x4030 */
69 u32 analog_pll_528_set; 69 u32 analog_pll_528_set;
70 u32 analog_pll_528_clr; 70 u32 analog_pll_528_clr;
71 u32 analog_pll_528_tog; 71 u32 analog_pll_528_tog;
72 u32 analog_pll_528_ss; /* 0x4040 */ 72 u32 analog_pll_528_ss; /* 0x4040 */
73 u32 analog_reserved1[3]; 73 u32 analog_reserved1[3];
74 u32 analog_pll_528_num; /* 0x4050 */ 74 u32 analog_pll_528_num; /* 0x4050 */
75 u32 analog_reserved2[3]; 75 u32 analog_reserved2[3];
76 u32 analog_pll_528_denom; /* 0x4060 */ 76 u32 analog_pll_528_denom; /* 0x4060 */
77 u32 analog_reserved3[3]; 77 u32 analog_reserved3[3];
78 u32 analog_pll_audio; /* 0x4070 */ 78 u32 analog_pll_audio; /* 0x4070 */
79 u32 analog_pll_audio_set; 79 u32 analog_pll_audio_set;
80 u32 analog_pll_audio_clr; 80 u32 analog_pll_audio_clr;
81 u32 analog_pll_audio_tog; 81 u32 analog_pll_audio_tog;
82 u32 analog_pll_audio_num; /* 0x4080*/ 82 u32 analog_pll_audio_num; /* 0x4080*/
83 u32 analog_reserved4[3]; 83 u32 analog_reserved4[3];
84 u32 analog_pll_audio_denom; /* 0x4090 */ 84 u32 analog_pll_audio_denom; /* 0x4090 */
85 u32 analog_reserved5[3]; 85 u32 analog_reserved5[3];
86 u32 analog_pll_video; /* 0x40a0 */ 86 u32 analog_pll_video; /* 0x40a0 */
87 u32 analog_pll_video_set; 87 u32 analog_pll_video_set;
88 u32 analog_pll_video_clr; 88 u32 analog_pll_video_clr;
89 u32 analog_pll_video_tog; 89 u32 analog_pll_video_tog;
90 u32 analog_pll_video_num; /* 0x40b0 */ 90 u32 analog_pll_video_num; /* 0x40b0 */
91 u32 analog_reserved6[3]; 91 u32 analog_reserved6[3];
92 u32 analog_pll_video_denom; /* 0x40c0 */ 92 u32 analog_pll_video_denom; /* 0x40c0 */
93 u32 analog_reserved7[7]; 93 u32 analog_reserved7[7];
94 u32 analog_pll_enet; /* 0x40e0 */ 94 u32 analog_pll_enet; /* 0x40e0 */
95 u32 analog_pll_enet_set; 95 u32 analog_pll_enet_set;
96 u32 analog_pll_enet_clr; 96 u32 analog_pll_enet_clr;
97 u32 analog_pll_enet_tog; 97 u32 analog_pll_enet_tog;
98 u32 analog_pfd_480; /* 0x40f0 */ 98 u32 analog_pfd_480; /* 0x40f0 */
99 u32 analog_pfd_480_set; 99 u32 analog_pfd_480_set;
100 u32 analog_pfd_480_clr; 100 u32 analog_pfd_480_clr;
101 u32 analog_pfd_480_tog; 101 u32 analog_pfd_480_tog;
102 u32 analog_pfd_528; /* 0x4100 */ 102 u32 analog_pfd_528; /* 0x4100 */
103 u32 analog_pfd_528_set; 103 u32 analog_pfd_528_set;
104 u32 analog_pfd_528_clr; 104 u32 analog_pfd_528_clr;
105 u32 analog_pfd_528_tog; 105 u32 analog_pfd_528_tog;
106 /* PMU Memory Map/Register Definition */ 106 /* PMU Memory Map/Register Definition */
107 u32 pmu_reg_1p1; 107 u32 pmu_reg_1p1;
108 u32 pmu_reg_1p1_set; 108 u32 pmu_reg_1p1_set;
109 u32 pmu_reg_1p1_clr; 109 u32 pmu_reg_1p1_clr;
110 u32 pmu_reg_1p1_tog; 110 u32 pmu_reg_1p1_tog;
111 u32 pmu_reg_3p0; 111 u32 pmu_reg_3p0;
112 u32 pmu_reg_3p0_set; 112 u32 pmu_reg_3p0_set;
113 u32 pmu_reg_3p0_clr; 113 u32 pmu_reg_3p0_clr;
114 u32 pmu_reg_3p0_tog; 114 u32 pmu_reg_3p0_tog;
115 u32 pmu_reg_2p5; 115 u32 pmu_reg_2p5;
116 u32 pmu_reg_2p5_set; 116 u32 pmu_reg_2p5_set;
117 u32 pmu_reg_2p5_clr; 117 u32 pmu_reg_2p5_clr;
118 u32 pmu_reg_2p5_tog; 118 u32 pmu_reg_2p5_tog;
119 u32 pmu_reg_core; 119 u32 pmu_reg_core;
120 u32 pmu_reg_core_set; 120 u32 pmu_reg_core_set;
121 u32 pmu_reg_core_clr; 121 u32 pmu_reg_core_clr;
122 u32 pmu_reg_core_tog; 122 u32 pmu_reg_core_tog;
123 u32 pmu_misc0; 123 u32 pmu_misc0;
124 u32 pmu_misc0_set; 124 u32 pmu_misc0_set;
125 u32 pmu_misc0_clr; 125 u32 pmu_misc0_clr;
126 u32 pmu_misc0_tog; 126 u32 pmu_misc0_tog;
127 u32 pmu_misc1; 127 u32 pmu_misc1;
128 u32 pmu_misc1_set; 128 u32 pmu_misc1_set;
129 u32 pmu_misc1_clr; 129 u32 pmu_misc1_clr;
130 u32 pmu_misc1_tog; 130 u32 pmu_misc1_tog;
131 u32 pmu_misc2; 131 u32 pmu_misc2;
132 u32 pmu_misc2_set; 132 u32 pmu_misc2_set;
133 u32 pmu_misc2_clr; 133 u32 pmu_misc2_clr;
134 u32 pmu_misc2_tog; 134 u32 pmu_misc2_tog;
135 /* TEMPMON Memory Map/Register Definition */ 135 /* TEMPMON Memory Map/Register Definition */
136 u32 tempsense0; 136 u32 tempsense0;
137 u32 tempsense0_set; 137 u32 tempsense0_set;
138 u32 tempsense0_clr; 138 u32 tempsense0_clr;
139 u32 tempsense0_tog; 139 u32 tempsense0_tog;
140 u32 tempsense1; 140 u32 tempsense1;
141 u32 tempsense1_set; 141 u32 tempsense1_set;
142 u32 tempsense1_clr; 142 u32 tempsense1_clr;
143 u32 tempsense1_tog; 143 u32 tempsense1_tog;
144 /* USB Analog Memory Map/Register Definition */ 144 /* USB Analog Memory Map/Register Definition */
145 u32 usb1_vbus_detect; 145 u32 usb1_vbus_detect;
146 u32 usb1_vbus_detect_set; 146 u32 usb1_vbus_detect_set;
147 u32 usb1_vbus_detect_clr; 147 u32 usb1_vbus_detect_clr;
148 u32 usb1_vbus_detect_tog; 148 u32 usb1_vbus_detect_tog;
149 u32 usb1_chrg_detect; 149 u32 usb1_chrg_detect;
150 u32 usb1_chrg_detect_set; 150 u32 usb1_chrg_detect_set;
151 u32 usb1_chrg_detect_clr; 151 u32 usb1_chrg_detect_clr;
152 u32 usb1_chrg_detect_tog; 152 u32 usb1_chrg_detect_tog;
153 u32 usb1_vbus_det_stat; 153 u32 usb1_vbus_det_stat;
154 u32 usb1_vbus_det_stat_set; 154 u32 usb1_vbus_det_stat_set;
155 u32 usb1_vbus_det_stat_clr; 155 u32 usb1_vbus_det_stat_clr;
156 u32 usb1_vbus_det_stat_tog; 156 u32 usb1_vbus_det_stat_tog;
157 u32 usb1_chrg_det_stat; 157 u32 usb1_chrg_det_stat;
158 u32 usb1_chrg_det_stat_set; 158 u32 usb1_chrg_det_stat_set;
159 u32 usb1_chrg_det_stat_clr; 159 u32 usb1_chrg_det_stat_clr;
160 u32 usb1_chrg_det_stat_tog; 160 u32 usb1_chrg_det_stat_tog;
161 u32 usb1_loopback; 161 u32 usb1_loopback;
162 u32 usb1_loopback_set; 162 u32 usb1_loopback_set;
163 u32 usb1_loopback_clr; 163 u32 usb1_loopback_clr;
164 u32 usb1_loopback_tog; 164 u32 usb1_loopback_tog;
165 u32 usb1_misc; 165 u32 usb1_misc;
166 u32 usb1_misc_set; 166 u32 usb1_misc_set;
167 u32 usb1_misc_clr; 167 u32 usb1_misc_clr;
168 u32 usb1_misc_tog; 168 u32 usb1_misc_tog;
169 u32 usb2_vbus_detect; 169 u32 usb2_vbus_detect;
170 u32 usb2_vbus_detect_set; 170 u32 usb2_vbus_detect_set;
171 u32 usb2_vbus_detect_clr; 171 u32 usb2_vbus_detect_clr;
172 u32 usb2_vbus_detect_tog; 172 u32 usb2_vbus_detect_tog;
173 u32 usb2_chrg_detect; 173 u32 usb2_chrg_detect;
174 u32 usb2_chrg_detect_set; 174 u32 usb2_chrg_detect_set;
175 u32 usb2_chrg_detect_clr; 175 u32 usb2_chrg_detect_clr;
176 u32 usb2_chrg_detect_tog; 176 u32 usb2_chrg_detect_tog;
177 u32 usb2_vbus_det_stat; 177 u32 usb2_vbus_det_stat;
178 u32 usb2_vbus_det_stat_set; 178 u32 usb2_vbus_det_stat_set;
179 u32 usb2_vbus_det_stat_clr; 179 u32 usb2_vbus_det_stat_clr;
180 u32 usb2_vbus_det_stat_tog; 180 u32 usb2_vbus_det_stat_tog;
181 u32 usb2_chrg_det_stat; 181 u32 usb2_chrg_det_stat;
182 u32 usb2_chrg_det_stat_set; 182 u32 usb2_chrg_det_stat_set;
183 u32 usb2_chrg_det_stat_clr; 183 u32 usb2_chrg_det_stat_clr;
184 u32 usb2_chrg_det_stat_tog; 184 u32 usb2_chrg_det_stat_tog;
185 u32 usb2_loopback; 185 u32 usb2_loopback;
186 u32 usb2_loopback_set; 186 u32 usb2_loopback_set;
187 u32 usb2_loopback_clr; 187 u32 usb2_loopback_clr;
188 u32 usb2_loopback_tog; 188 u32 usb2_loopback_tog;
189 u32 usb2_misc; 189 u32 usb2_misc;
190 u32 usb2_misc_set; 190 u32 usb2_misc_set;
191 u32 usb2_misc_clr; 191 u32 usb2_misc_clr;
192 u32 usb2_misc_tog; 192 u32 usb2_misc_tog;
193 u32 digprog; 193 u32 digprog;
194 u32 reserved1[7]; 194 u32 reserved1[7];
195 /* For i.MX 6SoloLite */ 195 /* For i.MX 6SoloLite */
196 u32 digprog_sololite; 196 u32 digprog_sololite;
197 }; 197 };
198 #endif 198 #endif
199 199
200 /* Define the bits in register CCR */ 200 /* Define the bits in register CCR */
201 #define MXC_CCM_CCR_RBC_EN (1 << 27) 201 #define MXC_CCM_CCR_RBC_EN (1 << 27)
202 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) 202 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
203 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 203 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
204 /* CCR_WB does not exist on i.MX6SX/UL */ 204 /* CCR_WB does not exist on i.MX6SX/UL */
205 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 205 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
206 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) 206 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
207 #define MXC_CCM_CCR_COSC_EN (1 << 12) 207 #define MXC_CCM_CCR_COSC_EN (1 << 12)
208 #ifdef CONFIG_MX6SX 208 #ifdef CONFIG_MX6SX
209 #define MXC_CCM_CCR_OSCNT_MASK 0x7F 209 #define MXC_CCM_CCR_OSCNT_MASK 0x7F
210 #else 210 #else
211 #define MXC_CCM_CCR_OSCNT_MASK 0xFF 211 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
212 #endif 212 #endif
213 #define MXC_CCM_CCR_OSCNT_OFFSET 0 213 #define MXC_CCM_CCR_OSCNT_OFFSET 0
214 214
215 /* Define the bits in register CCDR */ 215 /* Define the bits in register CCDR */
216 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) 216 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
217 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) 217 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
218 /* Exists on i.MX6QP */ 218 /* Exists on i.MX6QP */
219 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18) 219 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
220 220
221 /* Define the bits in register CSR */ 221 /* Define the bits in register CSR */
222 #define MXC_CCM_CSR_COSC_READY (1 << 5) 222 #define MXC_CCM_CSR_COSC_READY (1 << 5)
223 #define MXC_CCM_CSR_REF_EN_B (1 << 0) 223 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
224 224
225 /* Define the bits in register CCSR */ 225 /* Define the bits in register CCSR */
226 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) 226 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
227 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) 227 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
228 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) 228 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
229 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) 229 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
230 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) 230 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
231 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) 231 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
232 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) 232 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
233 #define MXC_CCM_CCSR_STEP_SEL (1 << 8) 233 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
234 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) 234 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
235 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) 235 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
236 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) 236 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
237 237
238 /* Define the bits in register CACRR */ 238 /* Define the bits in register CACRR */
239 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 239 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
240 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 240 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
241 241
242 /* Define the bits in register CBCDR */ 242 /* Define the bits in register CBCDR */
243 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) 243 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
244 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 244 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
245 #define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26) 245 #define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26)
246 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) 246 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
247 /* MMDC_CH0 not exists on i.MX6SX */ 247 /* MMDC_CH0 not exists on i.MX6SX */
248 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) 248 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
249 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 249 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
250 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) 250 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
251 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 251 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
252 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 252 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
253 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 253 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
254 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 254 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
255 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 255 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
256 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) 256 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
257 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6) 257 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
258 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) 258 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
259 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 259 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
260 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) 260 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
261 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 261 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
262 262
263 /* Define the bits in register CBCMR */ 263 /* Define the bits in register CBCMR */
264 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) 264 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
265 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 265 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
266 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) 266 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
267 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 267 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
268 /* LCDIF on i.MX6SX/UL */ 268 /* LCDIF on i.MX6SX/UL */
269 #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23) 269 #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23)
270 #define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23 270 #define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23
271 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) 271 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
272 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 272 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
273 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) 273 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
274 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 274 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
275 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) 275 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20)
276 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) 276 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
277 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 277 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
278 #ifndef CONFIG_MX6SX 278 #ifndef CONFIG_MX6SX
279 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) 279 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
280 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 280 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
281 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 281 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
282 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 282 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
283 #endif 283 #endif
284 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) 284 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
285 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 285 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
286 #ifndef CONFIG_MX6SX 286 #ifndef CONFIG_MX6SX
287 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) 287 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
288 #endif 288 #endif
289 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) 289 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
290 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) 290 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
291 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 291 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
292 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) 292 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
293 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 293 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
294 /* Exists on i.MX6QP */ 294 /* Exists on i.MX6QP */
295 #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) 295 #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
296 296
297 /* Define the bits in register CSCMR1 */ 297 /* Define the bits in register CSCMR1 */
298 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) 298 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
299 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 299 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
300 /* QSPI1 exist on i.MX6SX/UL */ 300 /* QSPI1 exist on i.MX6SX/UL */
301 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26) 301 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
302 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26 302 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
303 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) 303 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
304 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 304 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
305 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) 305 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
306 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 306 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
307 /* LCFIF2_PODF on i.MX6SX */ 307 /* LCFIF2_PODF on i.MX6SX */
308 #define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20) 308 #define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20)
309 #define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20 309 #define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20
310 /* ACLK_EMI on i.MX6DQ/SDL/DQP */ 310 /* ACLK_EMI on i.MX6DQ/SDL/DQP */
311 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) 311 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
312 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 312 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
313 /* CSCMR1_GPMI/BCH exist on i.MX6UL */ 313 /* CSCMR1_GPMI/BCH exist on i.MX6UL */
314 #define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19) 314 #define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19)
315 #define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18) 315 #define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18)
316 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) 316 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
317 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) 317 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
318 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) 318 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
319 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) 319 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
320 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) 320 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
321 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 321 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
322 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 322 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
323 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 323 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
324 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) 324 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
325 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 325 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
326 /* QSPI1 exist on i.MX6SX/UL */ 326 /* QSPI1 exist on i.MX6SX/UL */
327 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7) 327 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
328 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 328 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
329 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */ 329 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
330 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) 330 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
331 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 331 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
332 332
333 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F 333 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
334 334
335 /* Define the bits in register CSCMR2 */ 335 /* Define the bits in register CSCMR2 */
336 #ifdef CONFIG_MX6SX 336 #ifdef CONFIG_MX6SX
337 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21) 337 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21)
338 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21 338 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
339 #endif 339 #endif
340 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) 340 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
341 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 341 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
342 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) 342 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
343 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) 343 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
344 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */ 344 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
345 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) 345 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
346 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 346 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
347 347
348 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2) 348 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
349 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 349 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
350 350
351 /* Define the bits in register CSCDR1 */ 351 /* Define the bits in register CSCDR1 */
352 #ifndef CONFIG_MX6SX 352 #ifndef CONFIG_MX6SX
353 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) 353 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
354 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 354 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
355 #endif 355 #endif
356 /* CSCDR1_GPMI/BCH exist on i.MX6UL */ 356 /* CSCDR1_GPMI/BCH exist on i.MX6UL */
357 #define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22) 357 #define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22)
358 #define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22 358 #define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22
359 #define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19) 359 #define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19)
360 #define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19 360 #define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19
361 361
362 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) 362 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
363 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 363 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
364 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) 364 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
365 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 365 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
366 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) 366 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
367 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 367 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
368 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) 368 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
369 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 369 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
370 #ifndef CONFIG_MX6SX 370 #ifndef CONFIG_MX6SX
371 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 371 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
372 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 372 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
373 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 373 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
374 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 374 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
375 #endif 375 #endif
376 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F 376 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
377 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 377 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
378 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */ 378 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */
379 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) 379 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
380 380
381 /* Define the bits in register CS1CDR */ 381 /* Define the bits in register CS1CDR */
382 /* MX6UL, !MX6ULL */ 382 /* MX6UL, !MX6ULL */
383 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << 22) 383 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << 22)
384 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET 22 384 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET 22
385 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F << 16) 385 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F << 16)
386 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET 16 386 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET 16
387 #define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << 6) 387 #define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << 6)
388 #define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET 6 388 #define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET 6
389 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK 0x3F 389 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK 0x3F
390 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET 0 390 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET 0
391 391
392 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) 392 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
393 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 393 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
394 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22) 394 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
395 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22 395 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
396 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) 396 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
397 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 397 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
398 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) 398 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
399 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 399 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
400 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) 400 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
401 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 401 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
402 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F 402 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
403 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 403 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
404 404
405 /* Define the bits in register CS2CDR */ 405 /* Define the bits in register CS2CDR */
406 /* QSPI2 on i.MX6SX */ 406 /* QSPI2 on i.MX6SX */
407 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21) 407 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
408 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21 408 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
409 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) 409 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
410 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18) 410 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18)
411 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18 411 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
412 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) 412 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18)
413 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15) 413 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
414 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15 414 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
415 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) 415 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
416 416
417 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) 417 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
418 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 418 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
419 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) 419 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
420 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) 420 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
421 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 421 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
422 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) 422 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
423 423
424 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15) 424 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15)
425 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15 425 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15
426 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) 426 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15)
427 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16) 427 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16)
428 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16 428 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16
429 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) 429 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
430 430
431 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ 431 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
432 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ 432 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \
433 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ 433 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \
434 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) 434 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
435 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ 435 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
436 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ 436 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \
437 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ 437 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \
438 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) 438 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
439 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ 439 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
440 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ 440 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \
441 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ 441 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
442 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) 442 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
443 443
444 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) 444 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
445 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 445 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
446 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) 446 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
447 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 447 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
448 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) 448 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
449 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 449 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
450 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F 450 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
451 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 451 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
452 452
453 /* Define the bits in register CDCDR */ 453 /* Define the bits in register CDCDR */
454 #ifndef CONFIG_MX6SX 454 #ifndef CONFIG_MX6SX
455 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) 455 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
456 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 456 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
457 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) 457 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
458 #endif 458 #endif
459 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) 459 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
460 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 460 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
461 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22) 461 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22)
462 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22 462 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
463 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) 463 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
464 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 464 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
465 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) 465 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
466 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 466 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
467 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) 467 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
468 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 468 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
469 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) 469 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
470 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 470 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
471 471
472 /* Define the bits in register CHSCCDR */ 472 /* Define the bits in register CHSCCDR */
473 /* i.MX 6SX */ 473 /* i.MX 6SX */
474 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15) 474 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
475 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15 475 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
476 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12) 476 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
477 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12 477 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
478 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9) 478 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9)
479 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9 479 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
480 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6) 480 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6)
481 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6 481 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
482 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3) 482 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
483 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3 483 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
484 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7) 484 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
485 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0 485 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
486 486
487 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 487 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
488 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 488 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
489 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) 489 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
490 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 490 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
491 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) 491 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
492 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 492 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
493 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 493 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
494 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 494 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
495 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) 495 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
496 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 496 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
497 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) 497 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
498 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 498 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
499 499
500 /* i.MX6ULL */ 500 /* i.MX6ULL */
501 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15) 501 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15)
502 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15 502 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15
503 #define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12) 503 #define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12)
504 #define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET 12 504 #define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET 12
505 #define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0x7 << 9) 505 #define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0x7 << 9)
506 #define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET 9 506 #define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET 9
507 507
508 #define CHSCCDR_CLK_SEL_LDB_DI0 3 508 #define CHSCCDR_CLK_SEL_LDB_DI0 3
509 #define CHSCCDR_PODF_DIVIDE_BY_3 2 509 #define CHSCCDR_PODF_DIVIDE_BY_3 2
510 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 510 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
511 511
512 /* Define the bits in register CSCDR2 */ 512 /* Define the bits in register CSCDR2 */
513 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) 513 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
514 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 514 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
515 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ 515 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
516 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) 516 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
517 /* LCDIF1 on i.MX6SX/UL */ 517 /* LCDIF1 on i.MX6SX/UL */
518 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15) 518 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15)
519 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15 519 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15
520 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12) 520 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12)
521 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12 521 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12
522 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9) 522 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9)
523 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9 523 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9
524 /* LCDIF2 on i.MX6SX */ 524 /* LCDIF2 on i.MX6SX */
525 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6) 525 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6)
526 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6 526 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6
527 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3) 527 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3)
528 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3 528 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3
529 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0) 529 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0)
530 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0 530 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0
531 531
532 /* All IPU2_DI1 are LCDIF1 on MX6SX */ 532 /* All IPU2_DI1 are LCDIF1 on MX6SX */
533 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 533 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
534 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 534 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
535 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) 535 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
536 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 536 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
537 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) 537 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
538 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 538 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
539 /* All IPU2_DI0 are LCDIF2 on MX6SX */ 539 /* All IPU2_DI0 are LCDIF2 on MX6SX */
540 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 540 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
541 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 541 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
542 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) 542 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
543 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 543 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
544 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 544 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
545 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 545 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
546 546
547 /* Define the bits in register CSCDR3 */ 547 /* Define the bits in register CSCDR3 */
548 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) 548 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
549 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 549 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
550 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) 550 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
551 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 551 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
552 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) 552 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
553 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 553 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
554 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) 554 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
555 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 555 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
556 556
557 /* Define the bits in register CDHIPR */ 557 /* Define the bits in register CDHIPR */
558 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) 558 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
559 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) 559 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
560 #ifndef CONFIG_MX6SX 560 #ifndef CONFIG_MX6SX
561 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) 561 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
562 #endif 562 #endif
563 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) 563 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
564 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) 564 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
565 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) 565 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
566 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 566 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
567 567
568 /* Define the bits in register CLPCR */ 568 /* Define the bits in register CLPCR */
569 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) 569 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
570 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) 570 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
571 #ifndef CONFIG_MX6SX 571 #ifndef CONFIG_MX6SX
572 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) 572 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
573 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) 573 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
574 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) 574 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
575 #endif 575 #endif
576 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) 576 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
577 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) 577 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
578 #ifndef CONFIG_MX6SX 578 #ifndef CONFIG_MX6SX
579 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) 579 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
580 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) 580 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
581 #endif 581 #endif
582 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16) 582 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
583 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) 583 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
584 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) 584 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
585 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 585 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
586 #define MXC_CCM_CLPCR_VSTBY (1 << 8) 586 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
587 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) 587 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
588 #define MXC_CCM_CLPCR_SBYOS (1 << 6) 588 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
589 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) 589 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
590 #ifndef CONFIG_MX6SX 590 #ifndef CONFIG_MX6SX
591 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) 591 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
592 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 592 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
593 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) 593 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
594 #endif 594 #endif
595 #define MXC_CCM_CLPCR_LPM_MASK 0x3 595 #define MXC_CCM_CLPCR_LPM_MASK 0x3
596 #define MXC_CCM_CLPCR_LPM_OFFSET 0 596 #define MXC_CCM_CLPCR_LPM_OFFSET 0
597 597
598 /* Define the bits in register CISR */ 598 /* Define the bits in register CISR */
599 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) 599 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
600 #ifndef CONFIG_MX6SX 600 #ifndef CONFIG_MX6SX
601 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) 601 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
602 #endif 602 #endif
603 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) 603 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
604 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) 604 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
605 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) 605 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
606 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) 606 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
607 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) 607 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
608 #define MXC_CCM_CISR_COSC_READY (1 << 6) 608 #define MXC_CCM_CISR_COSC_READY (1 << 6)
609 #define MXC_CCM_CISR_LRF_PLL 1 609 #define MXC_CCM_CISR_LRF_PLL 1
610 610
611 /* Define the bits in register CIMR */ 611 /* Define the bits in register CIMR */
612 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) 612 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
613 #ifndef CONFIG_MX6SX 613 #ifndef CONFIG_MX6SX
614 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) 614 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
615 #endif 615 #endif
616 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) 616 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
617 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) 617 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
618 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) 618 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
619 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) 619 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
620 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) 620 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
621 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) 621 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
622 #define MXC_CCM_CIMR_MASK_LRF_PLL 1 622 #define MXC_CCM_CIMR_MASK_LRF_PLL 1
623 623
624 /* Define the bits in register CCOSR */ 624 /* Define the bits in register CCOSR */
625 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) 625 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
626 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) 626 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
627 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 627 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
628 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 628 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
629 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) 629 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
630 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8) 630 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
631 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) 631 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
632 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) 632 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
633 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 633 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
634 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF 634 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
635 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 635 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
636 636
637 /* Define the bits in registers CGPR */ 637 /* Define the bits in registers CGPR */
638 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16) 638 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
639 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) 639 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
640 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) 640 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
641 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 641 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
642 642
643 /* Define the bits in registers CCGRx */ 643 /* Define the bits in registers CCGRx */
644 #define MXC_CCM_CCGR_CG_MASK 3 644 #define MXC_CCM_CCGR_CG_MASK 3
645 645
646 /* i.MX 6ULL */ 646 /* i.MX 6ULL */
647 #define MXC_CCM_CCGR0_DCP_CLK_OFFSET 10 647 #define MXC_CCM_CCGR0_DCP_CLK_OFFSET 10
648 #define MXC_CCM_CCGR0_DCP_CLK_MASK (3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET) 648 #define MXC_CCM_CCGR0_DCP_CLK_MASK (3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET)
649 #define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET 12 649 #define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET 12
650 #define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET) 650 #define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET)
651 651
652 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 652 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
653 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) 653 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
654 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 654 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
655 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) 655 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
656 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4 656 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
657 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET) 657 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
658 #define MXC_CCM_CCGR0_ASRC_OFFSET 6 658 #define MXC_CCM_CCGR0_ASRC_OFFSET 6
659 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET) 659 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
660 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 660 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
661 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) 661 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
662 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 662 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
663 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) 663 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
664 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 664 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
665 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) 665 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
666 #define MXC_CCM_CCGR0_CAN1_OFFSET 14 666 #define MXC_CCM_CCGR0_CAN1_OFFSET 14
667 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET) 667 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
668 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 668 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
669 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) 669 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
670 #define MXC_CCM_CCGR0_CAN2_OFFSET 18 670 #define MXC_CCM_CCGR0_CAN2_OFFSET 18
671 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET) 671 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
672 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 672 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
673 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) 673 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
674 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 674 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
675 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) 675 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
676 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24 676 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
677 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) 677 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
678 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26 678 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
679 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) 679 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
680 #ifdef CONFIG_MX6SX 680 #ifdef CONFIG_MX6SX
681 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30 681 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
682 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET) 682 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
683 #else 683 #else
684 #define MXC_CCM_CCGR0_DTCP_OFFSET 28 684 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
685 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) 685 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
686 #endif 686 #endif
687 687
688 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 688 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
689 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) 689 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
690 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 690 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
691 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET) 691 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
692 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 692 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
693 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET) 693 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
694 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 694 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
695 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) 695 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
696 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 696 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
697 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) 697 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
698 /* CCGR1_ENET does not exist on i.MX6SX/UL */ 698 /* CCGR1_ENET does not exist on i.MX6SX/UL */
699 #define MXC_CCM_CCGR1_ENET_OFFSET 10 699 #define MXC_CCM_CCGR1_ENET_OFFSET 10
700 #define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET) 700 #define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET)
701 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 701 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
702 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) 702 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
703 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 703 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
704 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) 704 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
705 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16 705 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
706 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) 706 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
707 #ifdef CONFIG_MX6SX 707 #ifdef CONFIG_MX6SX
708 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18 708 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
709 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET) 709 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
710 #endif 710 #endif
711 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 711 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
712 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) 712 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
713 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 713 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
714 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) 714 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
715 #ifndef CONFIG_MX6SX 715 #ifndef CONFIG_MX6SX
716 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24 716 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
717 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) 717 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
718 #endif 718 #endif
719 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26 719 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
720 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) 720 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
721 #ifdef CONFIG_MX6SX 721 #ifdef CONFIG_MX6SX
722 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28 722 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
723 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET) 723 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
724 #define MXC_CCM_CCGR1_CANFD_OFFSET 30 724 #define MXC_CCM_CCGR1_CANFD_OFFSET 30
725 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET) 725 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
726 #endif 726 #endif
727 727
728 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 728 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
729 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) 729 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
730 730
731 /* i.MX6SX/UL */ 731 /* i.MX6SX/UL */
732 #define MXC_CCM_CCGR2_CSI_OFFSET 2 732 #define MXC_CCM_CCGR2_CSI_OFFSET 2
733 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET) 733 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
734 734
735 #ifndef CONFIG_MX6SX 735 #ifndef CONFIG_MX6SX
736 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 736 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
737 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) 737 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
738 #endif 738 #endif
739 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 739 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
740 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) 740 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
741 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 741 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
742 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) 742 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
743 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 743 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
744 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) 744 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
745 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8 745 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8
746 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET) 746 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
747 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 747 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
748 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) 748 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
749 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 749 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
750 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) 750 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
751 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 751 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
752 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET) 752 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
753 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 753 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
754 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET) 754 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
755 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 755 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
756 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) 756 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
757 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 757 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
758 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) 758 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
759 /* i.MX6SX/UL LCD and PXP */ 759 /* i.MX6SX/UL LCD and PXP */
760 #define MXC_CCM_CCGR2_LCD_OFFSET 28 760 #define MXC_CCM_CCGR2_LCD_OFFSET 28
761 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) 761 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
762 #define MXC_CCM_CCGR2_PXP_OFFSET 30 762 #define MXC_CCM_CCGR2_PXP_OFFSET 30
763 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET) 763 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
764 764
765 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 765 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
766 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) 766 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
767 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 767 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
768 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) 768 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
769 769
770 /* i.MX6ULL */ 770 /* i.MX6ULL */
771 #define MXC_CCM_CCGR2_ESAI_CLK_OFFSET 0 771 #define MXC_CCM_CCGR2_ESAI_CLK_OFFSET 0
772 #define MXC_CCM_CCGR2_ESAI_CLK_MASK (3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET) 772 #define MXC_CCM_CCGR2_ESAI_CLK_MASK (3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET)
773 #define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET 4 773 #define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET 4
774 #define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK (3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET) 774 #define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK (3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET)
775 775
776 /* Exist on i.MX6SX */ 776 /* Exist on i.MX6SX */
777 #define MXC_CCM_CCGR3_M4_OFFSET 2 777 #define MXC_CCM_CCGR3_M4_OFFSET 2
778 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET) 778 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
779 /* i.MX6ULL */ 779 /* i.MX6ULL */
780 #define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET 4 780 #define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET 4
781 #define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET) 781 #define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET)
782 #define MXC_CCM_CCGR3_ENET_OFFSET 4 782 #define MXC_CCM_CCGR3_ENET_OFFSET 4
783 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET) 783 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
784 #define MXC_CCM_CCGR3_QSPI_OFFSET 14 784 #define MXC_CCM_CCGR3_QSPI_OFFSET 14
785 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) 785 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
786 786
787 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 787 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
788 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) 788 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
789 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 789 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
790 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) 790 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
791 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 791 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
792 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) 792 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
793 793
794 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 794 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
795 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) 795 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
796 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 796 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
797 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) 797 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
798 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 798 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
799 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) 799 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
800 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 800 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
801 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) 801 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
802 802
803 /* QSPI1 exists on i.MX6SX/UL */ 803 /* QSPI1 exists on i.MX6SX/UL */
804 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14 804 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14
805 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET) 805 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
806 806
807 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 807 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
808 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) 808 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
809 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 809 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
810 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) 810 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
811 811
812 /* A7_CLKDIV/WDOG1 on i.MX6UL */ 812 /* A7_CLKDIV/WDOG1 on i.MX6UL */
813 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16 813 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16
814 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET) 814 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
815 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18 815 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18
816 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET) 816 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
817 817
818 #define MXC_CCM_CCGR3_MLB_OFFSET 18 818 #define MXC_CCM_CCGR3_MLB_OFFSET 18
819 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) 819 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
820 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 820 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
821 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) 821 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
822 #ifndef CONFIG_MX6SX 822 #ifndef CONFIG_MX6SX
823 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 823 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
824 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) 824 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
825 #endif 825 #endif
826 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 826 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
827 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) 827 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
828 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 828 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
829 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) 829 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
830 830
831 #define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6 831 #define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6
832 #define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET) 832 #define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET)
833 #define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8 833 #define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8
834 #define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET) 834 #define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET)
835 #define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10 835 #define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10
836 #define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET) 836 #define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET)
837 /* AXI on i.MX6UL */ 837 /* AXI on i.MX6UL */
838 #define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28 838 #define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28
839 #define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET) 839 #define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
840 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 840 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
841 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) 841 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
842 842
843 /* GPIO4 on i.MX6UL/ULL */ 843 /* GPIO4 on i.MX6UL/ULL */
844 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30 844 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30
845 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET) 845 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
846 846
847 #ifndef CONFIG_MX6SX 847 #ifndef CONFIG_MX6SX
848 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 848 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
849 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) 849 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
850 #endif 850 #endif
851 851
852 /* i.MX6ULL */ 852 /* i.MX6ULL */
853 #define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET 30 853 #define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET 30
854 #define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK (3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET) 854 #define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK (3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET)
855 855
856 #define MXC_CCM_CCGR4_PCIE_OFFSET 0 856 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
857 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) 857 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
858 /* QSPI2 on i.MX6SX */ 858 /* QSPI2 on i.MX6SX */
859 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10 859 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
860 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET) 860 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
861 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 861 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
862 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) 862 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
863 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 863 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
864 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) 864 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
865 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 865 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
866 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) 866 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
867 #define MXC_CCM_CCGR4_PWM1_OFFSET 16 867 #define MXC_CCM_CCGR4_PWM1_OFFSET 16
868 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET) 868 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
869 #define MXC_CCM_CCGR4_PWM2_OFFSET 18 869 #define MXC_CCM_CCGR4_PWM2_OFFSET 18
870 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET) 870 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
871 #define MXC_CCM_CCGR4_PWM3_OFFSET 20 871 #define MXC_CCM_CCGR4_PWM3_OFFSET 20
872 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET) 872 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
873 #define MXC_CCM_CCGR4_PWM4_OFFSET 22 873 #define MXC_CCM_CCGR4_PWM4_OFFSET 22
874 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET) 874 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
875 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 875 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
876 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) 876 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
877 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 877 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
878 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) 878 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
879 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 879 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
880 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) 880 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
881 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 881 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
882 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) 882 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
883 883
884 #define MXC_CCM_CCGR5_ROM_OFFSET 0 884 #define MXC_CCM_CCGR5_ROM_OFFSET 0
885 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) 885 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
886 #ifndef CONFIG_MX6SX 886 #ifndef CONFIG_MX6SX
887 #define MXC_CCM_CCGR5_SATA_OFFSET 4 887 #define MXC_CCM_CCGR5_SATA_OFFSET 4
888 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) 888 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
889 #endif 889 #endif
890 #define MXC_CCM_CCGR5_SDMA_OFFSET 6 890 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
891 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) 891 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
892 #define MXC_CCM_CCGR5_SPBA_OFFSET 12 892 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
893 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET) 893 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
894 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14 894 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
895 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET) 895 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
896 #define MXC_CCM_CCGR5_SSI1_OFFSET 18 896 #define MXC_CCM_CCGR5_SSI1_OFFSET 18
897 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET) 897 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
898 #define MXC_CCM_CCGR5_SSI2_OFFSET 20 898 #define MXC_CCM_CCGR5_SSI2_OFFSET 20
899 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET) 899 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
900 #define MXC_CCM_CCGR5_SSI3_OFFSET 22 900 #define MXC_CCM_CCGR5_SSI3_OFFSET 22
901 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET) 901 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
902 #define MXC_CCM_CCGR5_UART_OFFSET 24 902 #define MXC_CCM_CCGR5_UART_OFFSET 24
903 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) 903 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
904 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 904 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
905 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) 905 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
906 #ifdef CONFIG_MX6SX 906 #ifdef CONFIG_MX6SX
907 #define MXC_CCM_CCGR5_SAI1_OFFSET 20 907 #define MXC_CCM_CCGR5_SAI1_OFFSET 20
908 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET) 908 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
909 #define MXC_CCM_CCGR5_SAI2_OFFSET 30 909 #define MXC_CCM_CCGR5_SAI2_OFFSET 30
910 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET) 910 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
911 #endif 911 #endif
912 912
913 /* PRG_CLK0 exists on i.MX6QP */ 913 /* PRG_CLK0 exists on i.MX6QP */
914 #define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24) 914 #define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24)
915 915
916 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0 916 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
917 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) 917 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
918 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2 918 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
919 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) 919 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
920 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4 920 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
921 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) 921 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
922 #define MXC_CCM_CCGR6_SIM1_CLK_OFFSET 6 922 #define MXC_CCM_CCGR6_SIM1_CLK_OFFSET 6
923 #define MXC_CCM_CCGR6_SIM1_CLK_MASK (3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET) 923 #define MXC_CCM_CCGR6_SIM1_CLK_MASK (3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET)
924 #define MXC_CCM_CCGR6_SIM2_CLK_OFFSET 8 924 #define MXC_CCM_CCGR6_SIM2_CLK_OFFSET 8
925 #define MXC_CCM_CCGR6_SIM2_CLK_MASK (3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET) 925 #define MXC_CCM_CCGR6_SIM2_CLK_MASK (3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET)
926 /* i.MX6ULL */ 926 /* i.MX6ULL */
927 #define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET 8 927 #define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET 8
928 #define MXC_CCM_CCGR6_IPMUX4_CLK_MASK (3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET) 928 #define MXC_CCM_CCGR6_IPMUX4_CLK_MASK (3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET)
929 /* GPMI/BCH on i.MX6UL */ 929 /* GPMI/BCH on i.MX6UL */
930 #define MXC_CCM_CCGR6_BCH_OFFSET 6 930 #define MXC_CCM_CCGR6_BCH_OFFSET 6
931 #define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET) 931 #define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET)
932 #define MXC_CCM_CCGR6_GPMI_OFFSET 8 932 #define MXC_CCM_CCGR6_GPMI_OFFSET 8
933 #define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET) 933 #define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
934 934
935 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6 935 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
936 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) 936 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
937 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8 937 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
938 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) 938 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
939 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 939 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
940 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) 940 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
941 /* i.MX6ULL */ 941 /* i.MX6ULL */
942 #define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET 18 942 #define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET 18
943 #define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK (3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET) 943 #define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK (3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET)
944 /* The following *CCGR6* exist only i.MX6SX */ 944 /* The following *CCGR6* exist only i.MX6SX */
945 #define MXC_CCM_CCGR6_PWM8_OFFSET 16 945 #define MXC_CCM_CCGR6_PWM8_OFFSET 16
946 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET) 946 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
947 #define MXC_CCM_CCGR6_VADC_OFFSET 20 947 #define MXC_CCM_CCGR6_VADC_OFFSET 20
948 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET) 948 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
949 #define MXC_CCM_CCGR6_GIS_OFFSET 22 949 #define MXC_CCM_CCGR6_GIS_OFFSET 22
950 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET) 950 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
951 #define MXC_CCM_CCGR6_I2C4_OFFSET 24 951 #define MXC_CCM_CCGR6_I2C4_OFFSET 24
952 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET) 952 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
953 #define MXC_CCM_CCGR6_PWM5_OFFSET 26 953 #define MXC_CCM_CCGR6_PWM5_OFFSET 26
954 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET) 954 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
955 #define MXC_CCM_CCGR6_PWM6_OFFSET 28 955 #define MXC_CCM_CCGR6_PWM6_OFFSET 28
956 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET) 956 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
957 #define MXC_CCM_CCGR6_PWM7_OFFSET 30 957 #define MXC_CCM_CCGR6_PWM7_OFFSET 30
958 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET) 958 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
959 /* The two does not exist on i.MX6SX */ 959 /* The two does not exist on i.MX6SX */
960 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 960 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
961 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) 961 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
962 962
963 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000 963 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
964 #define BP_ANADIG_PLL_SYS_RSVD0 20 964 #define BP_ANADIG_PLL_SYS_RSVD0 20
965 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 965 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
966 #define BF_ANADIG_PLL_SYS_RSVD0(v) \ 966 #define BF_ANADIG_PLL_SYS_RSVD0(v) \
967 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) 967 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
968 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 968 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
969 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 969 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
970 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 970 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
971 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 971 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
972 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 972 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
973 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 973 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
974 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ 974 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
975 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) 975 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
976 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 976 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
977 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 977 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
978 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 978 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
979 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 979 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
980 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 980 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
981 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 981 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
982 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 982 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
983 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 983 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
984 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 984 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
985 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 985 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
986 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 986 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
987 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0 987 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0
988 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F 988 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
989 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ 989 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
990 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) 990 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
991 991
992 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 992 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
993 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 993 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
994 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 994 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
995 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ 995 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
996 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) 996 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
997 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 997 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
998 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 998 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
999 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 999 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
1000 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ 1000 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
1001 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) 1001 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
1002 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 1002 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
1003 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 1003 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
1004 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 1004 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
1005 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 1005 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
1006 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 1006 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
1007 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 1007 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
1008 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 1008 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
1009 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 1009 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
1010 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 1010 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
1011 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 1011 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
1012 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 1012 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
1013 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 1013 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
1014 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 1014 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
1015 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 1015 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
1016 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C 1016 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
1017 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ 1017 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
1018 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) 1018 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
1019 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 1019 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
1020 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 1020 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
1021 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ 1021 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
1022 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) 1022 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
1023 1023
1024 #define BM_ANADIG_PLL_528_LOCK 0x80000000 1024 #define BM_ANADIG_PLL_528_LOCK 0x80000000
1025 #define BP_ANADIG_PLL_528_RSVD1 19 1025 #define BP_ANADIG_PLL_528_RSVD1 19
1026 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 1026 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
1027 #define BF_ANADIG_PLL_528_RSVD1(v) \ 1027 #define BF_ANADIG_PLL_528_RSVD1(v) \
1028 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) 1028 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
1029 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 1029 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
1030 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 1030 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
1031 #define BM_ANADIG_PLL_528_BYPASS 0x00010000 1031 #define BM_ANADIG_PLL_528_BYPASS 0x00010000
1032 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 1032 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
1033 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 1033 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
1034 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ 1034 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
1035 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) 1035 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
1036 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 1036 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
1037 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 1037 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
1038 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 1038 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
1039 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 1039 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
1040 #define BM_ANADIG_PLL_528_ENABLE 0x00002000 1040 #define BM_ANADIG_PLL_528_ENABLE 0x00002000
1041 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 1041 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
1042 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 1042 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
1043 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 1043 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
1044 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200 1044 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200
1045 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 1045 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
1046 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080 1046 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080
1047 #define BP_ANADIG_PLL_528_RSVD0 1 1047 #define BP_ANADIG_PLL_528_RSVD0 1
1048 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E 1048 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E
1049 #define BF_ANADIG_PLL_528_RSVD0(v) \ 1049 #define BF_ANADIG_PLL_528_RSVD0(v) \
1050 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) 1050 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
1051 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 1051 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
1052 1052
1053 #define BP_ANADIG_PLL_528_SS_STOP 16 1053 #define BP_ANADIG_PLL_528_SS_STOP 16
1054 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 1054 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
1055 #define BF_ANADIG_PLL_528_SS_STOP(v) \ 1055 #define BF_ANADIG_PLL_528_SS_STOP(v) \
1056 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) 1056 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
1057 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 1057 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
1058 #define BP_ANADIG_PLL_528_SS_STEP 0 1058 #define BP_ANADIG_PLL_528_SS_STEP 0
1059 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF 1059 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
1060 #define BF_ANADIG_PLL_528_SS_STEP(v) \ 1060 #define BF_ANADIG_PLL_528_SS_STEP(v) \
1061 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) 1061 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
1062 1062
1063 #define BP_ANADIG_PLL_528_NUM_RSVD0 30 1063 #define BP_ANADIG_PLL_528_NUM_RSVD0 30
1064 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 1064 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
1065 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ 1065 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
1066 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) 1066 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
1067 #define BP_ANADIG_PLL_528_NUM_A 0 1067 #define BP_ANADIG_PLL_528_NUM_A 0
1068 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF 1068 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
1069 #define BF_ANADIG_PLL_528_NUM_A(v) \ 1069 #define BF_ANADIG_PLL_528_NUM_A(v) \
1070 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) 1070 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
1071 1071
1072 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30 1072 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30
1073 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 1073 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
1074 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ 1074 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
1075 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) 1075 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
1076 #define BP_ANADIG_PLL_528_DENOM_B 0 1076 #define BP_ANADIG_PLL_528_DENOM_B 0
1077 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF 1077 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
1078 #define BF_ANADIG_PLL_528_DENOM_B(v) \ 1078 #define BF_ANADIG_PLL_528_DENOM_B(v) \
1079 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) 1079 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
1080 1080
1081 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 1081 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
1082 #define BP_ANADIG_PLL_AUDIO_RSVD0 22 1082 #define BP_ANADIG_PLL_AUDIO_RSVD0 22
1083 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 1083 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
1084 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ 1084 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
1085 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) 1085 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
1086 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 1086 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
1087 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 1087 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
1088 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 1088 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
1089 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ 1089 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
1090 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) 1090 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
1091 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 1091 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
1092 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 1092 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
1093 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 1093 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
1094 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 1094 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
1095 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 1095 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
1096 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ 1096 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
1097 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) 1097 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
1098 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 1098 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
1099 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 1099 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
1100 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 1100 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
1101 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 1101 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
1102 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 1102 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
1103 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 1103 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
1104 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 1104 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
1105 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 1105 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
1106 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 1106 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
1107 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 1107 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
1108 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 1108 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
1109 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 1109 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
1110 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F 1110 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
1111 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ 1111 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
1112 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) 1112 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
1113 1113
1114 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 1114 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
1115 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 1115 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
1116 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ 1116 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
1117 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) 1117 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
1118 #define BP_ANADIG_PLL_AUDIO_NUM_A 0 1118 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
1119 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF 1119 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
1120 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ 1120 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
1121 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) 1121 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
1122 1122
1123 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 1123 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
1124 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 1124 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
1125 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ 1125 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
1126 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) 1126 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
1127 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0 1127 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
1128 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF 1128 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
1129 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ 1129 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
1130 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) 1130 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
1131 1131
1132 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 1132 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
1133 #define BP_ANADIG_PLL_VIDEO_RSVD0 22 1133 #define BP_ANADIG_PLL_VIDEO_RSVD0 22
1134 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 1134 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
1135 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ 1135 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
1136 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) 1136 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
1137 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 1137 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
1138 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19 1138 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
1139 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000 1139 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
1140 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \ 1140 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
1141 (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) 1141 (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
1142 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 1142 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
1143 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 1143 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
1144 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 1144 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
1145 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 1145 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
1146 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 1146 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
1147 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ 1147 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
1148 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) 1148 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
1149 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 1149 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
1150 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 1150 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
1151 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 1151 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
1152 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 1152 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
1153 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 1153 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
1154 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 1154 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
1155 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 1155 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
1156 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 1156 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
1157 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 1157 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
1158 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 1158 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
1159 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 1159 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
1160 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 1160 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
1161 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F 1161 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
1162 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ 1162 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
1163 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) 1163 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
1164 1164
1165 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 1165 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
1166 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 1166 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
1167 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ 1167 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
1168 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) 1168 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
1169 #define BP_ANADIG_PLL_VIDEO_NUM_A 0 1169 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
1170 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF 1170 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
1171 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ 1171 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
1172 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) 1172 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
1173 1173
1174 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 1174 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
1175 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 1175 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
1176 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ 1176 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
1177 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) 1177 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
1178 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0 1178 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
1179 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF 1179 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
1180 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ 1180 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
1181 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) 1181 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
1182 1182
1183 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000 1183 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000
1184 #define BP_ANADIG_PLL_ENET_RSVD1 21 1184 #define BP_ANADIG_PLL_ENET_RSVD1 21
1185 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 1185 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
1186 #define BF_ANADIG_PLL_ENET_RSVD1(v) \ 1186 #define BF_ANADIG_PLL_ENET_RSVD1(v) \
1187 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) 1187 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
1188 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000 1188 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
1189 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 1189 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
1190 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 1190 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
1191 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 1191 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
1192 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 1192 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
1193 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 1193 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
1194 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 1194 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
1195 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 1195 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
1196 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ 1196 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
1197 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) 1197 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1198 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 1198 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
1199 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 1199 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
1200 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 1200 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
1201 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 1201 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
1202 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 1202 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
1203 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 1203 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
1204 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 1204 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
1205 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 1205 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
1206 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 1206 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
1207 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 1207 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
1208 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 1208 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
1209 #define BP_ANADIG_PLL_ENET_RSVD0 2 1209 #define BP_ANADIG_PLL_ENET_RSVD0 2
1210 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C 1210 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
1211 #define BF_ANADIG_PLL_ENET_RSVD0(v) \ 1211 #define BF_ANADIG_PLL_ENET_RSVD0(v) \
1212 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) 1212 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
1213 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0 1213 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
1214 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 1214 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
1215 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ 1215 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
1216 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) 1216 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
1217 1217
1218 /* ENET2 for i.MX6SX/UL */ 1218 /* ENET2 for i.MX6SX/UL */
1219 #define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 1219 #define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
1220 #define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C 1220 #define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
1221 #define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ 1221 #define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \
1222 (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) 1222 (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
1223 1223
1224 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 1224 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
1225 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 1225 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
1226 #define BP_ANADIG_PFD_480_PFD3_FRAC 24 1226 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
1227 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 1227 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
1228 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ 1228 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
1229 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) 1229 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
1230 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 1230 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
1231 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 1231 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
1232 #define BP_ANADIG_PFD_480_PFD2_FRAC 16 1232 #define BP_ANADIG_PFD_480_PFD2_FRAC 16
1233 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 1233 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
1234 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ 1234 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
1235 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) 1235 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
1236 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 1236 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
1237 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 1237 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
1238 #define BP_ANADIG_PFD_480_PFD1_FRAC 8 1238 #define BP_ANADIG_PFD_480_PFD1_FRAC 8
1239 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 1239 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
1240 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ 1240 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
1241 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) 1241 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
1242 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 1242 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
1243 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 1243 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
1244 #define BP_ANADIG_PFD_480_PFD0_FRAC 0 1244 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
1245 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F 1245 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
1246 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ 1246 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
1247 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) 1247 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
1248 1248
1249 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 1249 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
1250 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 1250 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
1251 #define BP_ANADIG_PFD_528_PFD3_FRAC 24 1251 #define BP_ANADIG_PFD_528_PFD3_FRAC 24
1252 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 1252 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
1253 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ 1253 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
1254 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) 1254 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
1255 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 1255 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
1256 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 1256 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
1257 #define BP_ANADIG_PFD_528_PFD2_FRAC 16 1257 #define BP_ANADIG_PFD_528_PFD2_FRAC 16
1258 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 1258 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
1259 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ 1259 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
1260 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) 1260 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
1261 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 1261 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
1262 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 1262 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
1263 #define BP_ANADIG_PFD_528_PFD1_FRAC 8 1263 #define BP_ANADIG_PFD_528_PFD1_FRAC 8
1264 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 1264 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
1265 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ 1265 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
1266 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) 1266 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
1267 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 1267 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
1268 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 1268 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
1269 #define BP_ANADIG_PFD_528_PFD0_FRAC 0 1269 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
1270 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F 1270 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
1271 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ 1271 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
1272 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) 1272 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1273 1273
1274 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 1274 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
1275 1275
1276 #define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23) 1276 #define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
1277 #define BP_PMU_MISC2_AUDIO_DIV_MSB 23 1277 #define BP_PMU_MISC2_AUDIO_DIV_MSB 23
1278 1278
1279 #define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15) 1279 #define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15)
1280 #define BP_PMU_MISC2_AUDIO_DIV_LSB 15 1280 #define BP_PMU_MISC2_AUDIO_DIV_LSB 15
1281 1281
1282 #define PMU_MISC2_AUDIO_DIV(v) \ 1282 #define PMU_MISC2_AUDIO_DIV(v) \
1283 (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \ 1283 (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \
1284 (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \ 1284 (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \
1285 ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \ 1285 ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \
1286 BP_PMU_MISC2_AUDIO_DIV_LSB)) 1286 BP_PMU_MISC2_AUDIO_DIV_LSB))
1287 1287
1288 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ 1288 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
1289 1289
arch/arm/include/asm/arch-mx6/imx-regs.h
Diff comments   View file @ 05922b0
1 /* 1 /*
2 * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ 7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__ 8 #define __ASM_ARCH_MX6_IMX_REGS_H__
9 9
10 #define ARCH_MXC 10 #define ARCH_MXC
11 11
12 #ifdef CONFIG_MX6UL 12 #ifdef CONFIG_MX6UL
13 #define CONFIG_SYS_CACHELINE_SIZE 64 13 #define CONFIG_SYS_CACHELINE_SIZE 64
14 #else 14 #else
15 #define CONFIG_SYS_CACHELINE_SIZE 32 15 #define CONFIG_SYS_CACHELINE_SIZE 32
16 #endif 16 #endif
17 17
18 #define ROMCP_ARB_BASE_ADDR 0x00000000 18 #define ROMCP_ARB_BASE_ADDR 0x00000000
19 #define ROMCP_ARB_END_ADDR 0x000FFFFF 19 #define ROMCP_ARB_END_ADDR 0x000FFFFF
20 20
21 #ifdef CONFIG_MX6SL 21 #ifdef CONFIG_MX6SL
22 #define GPU_2D_ARB_BASE_ADDR 0x02200000 22 #define GPU_2D_ARB_BASE_ADDR 0x02200000
23 #define GPU_2D_ARB_END_ADDR 0x02203FFF 23 #define GPU_2D_ARB_END_ADDR 0x02203FFF
24 #define OPENVG_ARB_BASE_ADDR 0x02204000 24 #define OPENVG_ARB_BASE_ADDR 0x02204000
25 #define OPENVG_ARB_END_ADDR 0x02207FFF 25 #define OPENVG_ARB_END_ADDR 0x02207FFF
26 #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 26 #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
27 #define CAAM_ARB_BASE_ADDR 0x00100000 27 #define CAAM_ARB_BASE_ADDR 0x00100000
28 #define CAAM_ARB_END_ADDR 0x00107FFF 28 #define CAAM_ARB_END_ADDR 0x00107FFF
29 #define GPU_ARB_BASE_ADDR 0x01800000 29 #define GPU_ARB_BASE_ADDR 0x01800000
30 #define GPU_ARB_END_ADDR 0x01803FFF 30 #define GPU_ARB_END_ADDR 0x01803FFF
31 #define APBH_DMA_ARB_BASE_ADDR 0x01804000 31 #define APBH_DMA_ARB_BASE_ADDR 0x01804000
32 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF 32 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF
33 #define M4_BOOTROM_BASE_ADDR 0x007F8000 33 #define M4_BOOTROM_BASE_ADDR 0x007F8000
34 34
35 #else 35 #else
36 #define CAAM_ARB_BASE_ADDR 0x00100000 36 #define CAAM_ARB_BASE_ADDR 0x00100000
37 #define CAAM_ARB_END_ADDR 0x00103FFF 37 #define CAAM_ARB_END_ADDR 0x00103FFF
38 #define APBH_DMA_ARB_BASE_ADDR 0x00110000 38 #define APBH_DMA_ARB_BASE_ADDR 0x00110000
39 #define APBH_DMA_ARB_END_ADDR 0x00117FFF 39 #define APBH_DMA_ARB_END_ADDR 0x00117FFF
40 #define HDMI_ARB_BASE_ADDR 0x00120000 40 #define HDMI_ARB_BASE_ADDR 0x00120000
41 #define HDMI_ARB_END_ADDR 0x00128FFF 41 #define HDMI_ARB_END_ADDR 0x00128FFF
42 #define GPU_3D_ARB_BASE_ADDR 0x00130000 42 #define GPU_3D_ARB_BASE_ADDR 0x00130000
43 #define GPU_3D_ARB_END_ADDR 0x00133FFF 43 #define GPU_3D_ARB_END_ADDR 0x00133FFF
44 #define GPU_2D_ARB_BASE_ADDR 0x00134000 44 #define GPU_2D_ARB_BASE_ADDR 0x00134000
45 #define GPU_2D_ARB_END_ADDR 0x00137FFF 45 #define GPU_2D_ARB_END_ADDR 0x00137FFF
46 #define DTCP_ARB_BASE_ADDR 0x00138000 46 #define DTCP_ARB_BASE_ADDR 0x00138000
47 #define DTCP_ARB_END_ADDR 0x0013BFFF 47 #define DTCP_ARB_END_ADDR 0x0013BFFF
48 #endif /* CONFIG_MX6SL */ 48 #endif /* CONFIG_MX6SL */
49 49
50 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 50 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
51 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 51 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
52 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 52 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
53 53
54 /* GPV - PL301 configuration ports */ 54 /* GPV - PL301 configuration ports */
55 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 55 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
56 #define GPV2_BASE_ADDR 0x00D00000 56 #define GPV2_BASE_ADDR 0x00D00000
57 #else 57 #else
58 #define GPV2_BASE_ADDR 0x00200000 58 #define GPV2_BASE_ADDR 0x00200000
59 #endif 59 #endif
60 60
61 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 61 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
62 #define GPV3_BASE_ADDR 0x00E00000 62 #define GPV3_BASE_ADDR 0x00E00000
63 #define GPV4_BASE_ADDR 0x00F00000 63 #define GPV4_BASE_ADDR 0x00F00000
64 #define GPV5_BASE_ADDR 0x01000000 64 #define GPV5_BASE_ADDR 0x01000000
65 #define GPV6_BASE_ADDR 0x01100000 65 #define GPV6_BASE_ADDR 0x01100000
66 #define PCIE_ARB_BASE_ADDR 0x08000000 66 #define PCIE_ARB_BASE_ADDR 0x08000000
67 #define PCIE_ARB_END_ADDR 0x08FFFFFF 67 #define PCIE_ARB_END_ADDR 0x08FFFFFF
68 68
69 #else 69 #else
70 #define GPV3_BASE_ADDR 0x00300000 70 #define GPV3_BASE_ADDR 0x00300000
71 #define GPV4_BASE_ADDR 0x00800000 71 #define GPV4_BASE_ADDR 0x00800000
72 #define PCIE_ARB_BASE_ADDR 0x01000000 72 #define PCIE_ARB_BASE_ADDR 0x01000000
73 #define PCIE_ARB_END_ADDR 0x01FFFFFF 73 #define PCIE_ARB_END_ADDR 0x01FFFFFF
74 #endif 74 #endif
75 75
76 #define IRAM_BASE_ADDR 0x00900000 76 #define IRAM_BASE_ADDR 0x00900000
77 #define SCU_BASE_ADDR 0x00A00000 77 #define SCU_BASE_ADDR 0x00A00000
78 #define IC_INTERFACES_BASE_ADDR 0x00A00100 78 #define IC_INTERFACES_BASE_ADDR 0x00A00100
79 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 79 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
80 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 80 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
81 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 81 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
82 #define L2_PL310_BASE 0x00A02000 82 #define L2_PL310_BASE 0x00A02000
83 #define GPV0_BASE_ADDR 0x00B00000 83 #define GPV0_BASE_ADDR 0x00B00000
84 #define GPV1_BASE_ADDR 0x00C00000 84 #define GPV1_BASE_ADDR 0x00C00000
85 85
86 #define AIPS1_ARB_BASE_ADDR 0x02000000 86 #define AIPS1_ARB_BASE_ADDR 0x02000000
87 #define AIPS1_ARB_END_ADDR 0x020FFFFF 87 #define AIPS1_ARB_END_ADDR 0x020FFFFF
88 #define AIPS2_ARB_BASE_ADDR 0x02100000 88 #define AIPS2_ARB_BASE_ADDR 0x02100000
89 #define AIPS2_ARB_END_ADDR 0x021FFFFF 89 #define AIPS2_ARB_END_ADDR 0x021FFFFF
90 /* AIPS3 only on i.MX6SX */ 90 /* AIPS3 only on i.MX6SX */
91 #define AIPS3_ARB_BASE_ADDR 0x02200000 91 #define AIPS3_ARB_BASE_ADDR 0x02200000
92 #define AIPS3_ARB_END_ADDR 0x022FFFFF 92 #define AIPS3_ARB_END_ADDR 0x022FFFFF
93 #ifdef CONFIG_MX6SX 93 #ifdef CONFIG_MX6SX
94 #define WEIM_ARB_BASE_ADDR 0x50000000 94 #define WEIM_ARB_BASE_ADDR 0x50000000
95 #define WEIM_ARB_END_ADDR 0x57FFFFFF 95 #define WEIM_ARB_END_ADDR 0x57FFFFFF
96 #define QSPI0_AMBA_BASE 0x60000000 96 #define QSPI0_AMBA_BASE 0x60000000
97 #define QSPI0_AMBA_END 0x6FFFFFFF 97 #define QSPI0_AMBA_END 0x6FFFFFFF
98 #define QSPI1_AMBA_BASE 0x70000000 98 #define QSPI1_AMBA_BASE 0x70000000
99 #define QSPI1_AMBA_END 0x7FFFFFFF 99 #define QSPI1_AMBA_END 0x7FFFFFFF
100 #elif defined(CONFIG_MX6UL) 100 #elif defined(CONFIG_MX6UL)
101 #define WEIM_ARB_BASE_ADDR 0x50000000 101 #define WEIM_ARB_BASE_ADDR 0x50000000
102 #define WEIM_ARB_END_ADDR 0x57FFFFFF 102 #define WEIM_ARB_END_ADDR 0x57FFFFFF
103 #define QSPI0_AMBA_BASE 0x60000000 103 #define QSPI0_AMBA_BASE 0x60000000
104 #define QSPI0_AMBA_END 0x6FFFFFFF 104 #define QSPI0_AMBA_END 0x6FFFFFFF
105 #else 105 #else
106 #define SATA_ARB_BASE_ADDR 0x02200000 106 #define SATA_ARB_BASE_ADDR 0x02200000
107 #define SATA_ARB_END_ADDR 0x02203FFF 107 #define SATA_ARB_END_ADDR 0x02203FFF
108 #define OPENVG_ARB_BASE_ADDR 0x02204000 108 #define OPENVG_ARB_BASE_ADDR 0x02204000
109 #define OPENVG_ARB_END_ADDR 0x02207FFF 109 #define OPENVG_ARB_END_ADDR 0x02207FFF
110 #define HSI_ARB_BASE_ADDR 0x02208000 110 #define HSI_ARB_BASE_ADDR 0x02208000
111 #define HSI_ARB_END_ADDR 0x0220BFFF 111 #define HSI_ARB_END_ADDR 0x0220BFFF
112 #define IPU1_ARB_BASE_ADDR 0x02400000 112 #define IPU1_ARB_BASE_ADDR 0x02400000
113 #define IPU1_ARB_END_ADDR 0x027FFFFF 113 #define IPU1_ARB_END_ADDR 0x027FFFFF
114 #define IPU2_ARB_BASE_ADDR 0x02800000 114 #define IPU2_ARB_BASE_ADDR 0x02800000
115 #define IPU2_ARB_END_ADDR 0x02BFFFFF 115 #define IPU2_ARB_END_ADDR 0x02BFFFFF
116 #define WEIM_ARB_BASE_ADDR 0x08000000 116 #define WEIM_ARB_BASE_ADDR 0x08000000
117 #define WEIM_ARB_END_ADDR 0x0FFFFFFF 117 #define WEIM_ARB_END_ADDR 0x0FFFFFFF
118 #endif 118 #endif
119 119
120 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 120 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
121 #define MMDC0_ARB_BASE_ADDR 0x80000000 121 #define MMDC0_ARB_BASE_ADDR 0x80000000
122 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF 122 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
123 #define MMDC1_ARB_BASE_ADDR 0xC0000000 123 #define MMDC1_ARB_BASE_ADDR 0xC0000000
124 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 124 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
125 #else 125 #else
126 #define MMDC0_ARB_BASE_ADDR 0x10000000 126 #define MMDC0_ARB_BASE_ADDR 0x10000000
127 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF 127 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF
128 #define MMDC1_ARB_BASE_ADDR 0x80000000 128 #define MMDC1_ARB_BASE_ADDR 0x80000000
129 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 129 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
130 #endif 130 #endif
131 131
132 #define QSPI1_ARB_BASE_ADDR 0x60000000 132 #define QSPI1_ARB_BASE_ADDR 0x60000000
133 #define QSPI1_ARB_END_ADDR 0x6FFFFFFF 133 #define QSPI1_ARB_END_ADDR 0x6FFFFFFF
134 #define QSPI2_ARB_BASE_ADDR 0x70000000 134 #define QSPI2_ARB_BASE_ADDR 0x70000000
135 #define QSPI2_ARB_END_ADDR 0x7FFFFFFF 135 #define QSPI2_ARB_END_ADDR 0x7FFFFFFF
136 136
137 #if (!(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))) 137 #if (!(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)))
138 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR 138 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
139 #define IPU_SOC_OFFSET 0x00200000 139 #define IPU_SOC_OFFSET 0x00200000
140 #endif 140 #endif
141 141
142 /* Defines for Blocks connected via AIPS (SkyBlue) */ 142 /* Defines for Blocks connected via AIPS (SkyBlue) */
143 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 143 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
144 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 144 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
145 #define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR 145 #define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
146 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 146 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
147 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 147 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
148 #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR 148 #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
149 149
150 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) 150 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
151 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) 151 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
152 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) 152 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
153 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) 153 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
154 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) 154 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
155 #ifdef CONFIG_MX6SL 155 #ifdef CONFIG_MX6SL
156 #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 156 #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
157 #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) 157 #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
158 #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 158 #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
159 #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 159 #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
160 #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 160 #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
161 #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 161 #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
162 #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 162 #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
163 #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) 163 #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
164 #else 164 #else
165 165
166 #if defined(CONFIG_MX6UL) 166 #if defined(CONFIG_MX6UL)
167 #define UART7_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 167 #define UART7_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
168 #elif !defined(CONFIG_MX6SX) 168 #elif !defined(CONFIG_MX6SX)
169 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 169 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
170 #endif 170 #endif
171 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) 171 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
172 #if defined(CONFIG_MX6UL) 172 #if defined(CONFIG_MX6UL)
173 #if defined(CONFIG_MX6ULL) 173 #if defined(CONFIG_MX6ULL)
174 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 174 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
175 #else 175 #else
176 #define UART8_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 176 #define UART8_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
177 #endif 177 #endif
178 #define SAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 178 #define SAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
179 #define SAI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 179 #define SAI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
180 #define SAI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 180 #define SAI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
181 #else 181 #else
182 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 182 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
183 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 183 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
184 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 184 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
185 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 185 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
186 #endif 186 #endif
187 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 187 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
188 #endif 188 #endif
189 189
190 #if defined(CONFIG_MX6UL) 190 #if defined(CONFIG_MX6UL)
191 #define TOUCH_CTRL_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) 191 #define TOUCH_CTRL_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
192 #define BEE_BASE_ADDR (ATZ1_BASE_ADDR + 0x44000) 192 #define BEE_BASE_ADDR (ATZ1_BASE_ADDR + 0x44000)
193 #elif !defined(CONFIG_MX6SX) 193 #elif !defined(CONFIG_MX6SX)
194 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) 194 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
195 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) 195 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
196 #endif 196 #endif
197 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) 197 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
198 198
199 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) 199 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
200 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) 200 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
201 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) 201 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
202 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) 202 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
203 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) 203 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
204 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) 204 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
205 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) 205 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
206 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) 206 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
207 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) 207 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
208 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) 208 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
209 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) 209 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
210 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) 210 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
211 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) 211 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
212 #define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 212 #define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
213 #if defined(CONFIG_MX6UL) 213 #if defined(CONFIG_MX6UL)
214 #define SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 214 #define SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
215 #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 215 #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
216 #else 216 #else
217 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 217 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
218 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 218 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
219 #endif 219 #endif
220 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) 220 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
221 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) 221 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
222 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) 222 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
223 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) 223 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
224 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) 224 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
225 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) 225 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
226 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) 226 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
227 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) 227 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
228 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) 228 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
229 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) 229 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
230 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) 230 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
231 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) 231 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
232 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) 232 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
233 #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 233 #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
234 #ifdef CONFIG_MX6SL 234 #ifdef CONFIG_MX6SL
235 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 235 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
236 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 236 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
237 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 237 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
238 #define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) 238 #define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
239 #elif CONFIG_MX6SX 239 #elif CONFIG_MX6SX
240 #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 240 #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
241 #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 241 #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
242 #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) 242 #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
243 #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) 243 #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
244 #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) 244 #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
245 #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) 245 #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
246 246
247 #elif defined(CONFIG_MX6UL) 247 #elif defined(CONFIG_MX6UL)
248 #define GPT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 248 #define GPT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
249 #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 249 #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
250 #define PWM5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) 250 #define PWM5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
251 #define PWM6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) 251 #define PWM6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
252 #define PWM7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) 252 #define PWM7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
253 #define PWM8_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) 253 #define PWM8_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
254 #else 254 #else
255 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 255 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
256 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 256 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
257 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 257 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
258 #define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) 258 #define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
259 #endif 259 #endif
260 260
261 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) 261 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
262 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) 262 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
263 #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) 263 #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
264 #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) 264 #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
265 265
266 #if defined(CONFIG_MX6UL) 266 #if defined(CONFIG_MX6UL)
267 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 267 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
268 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR) 268 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR)
269 #else 269 #else
270 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) 270 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
271 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 271 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
272 #endif 272 #endif
273 273
274 #define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR 274 #define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR
275 #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000) 275 #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000)
276 276
277 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) 277 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
278 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) 278 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
279 279
280 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) 280 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
281 #ifdef CONFIG_MX6SL 281 #ifdef CONFIG_MX6SL
282 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 282 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
283 #elif defined(CONFIG_MX6UL) 283 #elif defined(CONFIG_MX6UL)
284 #define SIM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 284 #define SIM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
285 #else 285 #else
286 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 286 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
287 #endif 287 #endif
288 288
289 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) 289 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
290 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) 290 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
291 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) 291 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
292 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) 292 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
293 293
294 #define MX6UL_ADC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) 294 #define MX6UL_ADC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
295 #define MX6UL_ADC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) 295 #define MX6UL_ADC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
296 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) 296 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
297 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) 297 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
298 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) 298 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
299 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) 299 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
300 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) 300 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
301 /* i.MX6SL */ 301 /* i.MX6SL */
302 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 302 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
303 #ifdef CONFIG_MX6UL 303 #ifdef CONFIG_MX6UL
304 #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 304 #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
305 #else 305 #else
306 /* i.MX6SX */ 306 /* i.MX6SX */
307 #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 307 #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
308 #endif 308 #endif
309 /* i.MX6DQ/SDL */ 309 /* i.MX6DQ/SDL */
310 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 310 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
311 311
312 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) 312 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
313 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) 313 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
314 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) 314 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
315 #if defined(CONFIG_MX6UL) 315 #if defined(CONFIG_MX6UL)
316 #define CSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 316 #define CSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
317 #define PXP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 317 #define PXP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
318 #else 318 #else
319 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 319 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
320 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 320 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
321 #endif 321 #endif
322 #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 322 #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
323 #define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 323 #define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
324 #ifdef CONFIG_MX6SX 324 #ifdef CONFIG_MX6SX
325 #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 325 #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
326 #else 326 #else
327 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 327 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
328 #endif 328 #endif
329 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) 329 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
330 #ifdef CONFIG_MX6UL 330 #ifdef CONFIG_MX6UL
331 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 331 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
332 #define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 332 #define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
333 #define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) 333 #define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
334 #define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 334 #define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
335 #elif defined(CONFIG_MX6SX) 335 #elif defined(CONFIG_MX6SX)
336 #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 336 #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
337 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) 337 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
338 #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 338 #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
339 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 339 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
340 #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 340 #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
341 #else 341 #else
342 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 342 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
343 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 343 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
344 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 344 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
345 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 345 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
346 #endif 346 #endif
347 #define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 347 #define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
348 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) 348 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
349 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) 349 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
350 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) 350 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
351 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) 351 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
352 /* i.MX6SX/UL */ 352 /* i.MX6SX/UL */
353 #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 353 #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
354 /* i.MX6UL */ 354 /* i.MX6UL */
355 #define MX6UL_UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 355 #define MX6UL_UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
356 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 356 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
357 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 357 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
358 358
359 #define OTG_BASE_ADDR USB_BASE_ADDR 359 #define OTG_BASE_ADDR USB_BASE_ADDR
360 360
361 #if defined(CONFIG_MX6UL) 361 #if defined(CONFIG_MX6UL)
362 #define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR 362 #define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR
363 #endif 363 #endif
364 364
365 #ifdef CONFIG_MX6SX 365 #ifdef CONFIG_MX6SX
366 #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) 366 #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
367 #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) 367 #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
368 #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) 368 #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
369 #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) 369 #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
370 #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) 370 #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
371 #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) 371 #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
372 #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) 372 #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
373 #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) 373 #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
374 #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) 374 #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
375 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) 375 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
376 #define MX6SX_ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) 376 #define MX6SX_ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
377 #define MX6SX_ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) 377 #define MX6SX_ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
378 #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) 378 #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
379 #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) 379 #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
380 #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) 380 #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
381 #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) 381 #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
382 #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) 382 #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
383 #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) 383 #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
384 #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) 384 #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
385 #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) 385 #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
386 #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) 386 #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
387 #elif defined(CONFIG_MX6ULL) 387 #elif defined(CONFIG_MX6ULL)
388 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) 388 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
389 #define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) 389 #define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
390 #define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) 390 #define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
391 #define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) 391 #define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
392 #define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) 392 #define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
393 #define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) 393 #define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
394 #define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) 394 #define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
395 #endif 395 #endif
396 /* Only for i.MX6SX */ 396 /* Only for i.MX6SX */
397 #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) 397 #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
398 #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) 398 #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
399 #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) 399 #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
400 #define MX6SX_UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) 400 #define MX6SX_UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
401 401
402 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 402 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
403 #define IRAM_SIZE 0x00040000 403 #define IRAM_SIZE 0x00040000
404 #else 404 #else
405 #define IRAM_SIZE 0x00020000 405 #define IRAM_SIZE 0x00020000
406 #endif 406 #endif
407 #define FEC_QUIRK_ENET_MAC 407 #define FEC_QUIRK_ENET_MAC
408 #define SNVS_LPGPR 0x68 408 #define SNVS_LPGPR 0x68
409 409
410 #include <asm/imx-common/regs-lcdif.h> 410 #include <asm/imx-common/regs-lcdif.h>
411 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 411 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
412 #include <asm/types.h> 412 #include <asm/types.h>
413 413
414 /* only for i.MX6SX/UL */ 414 /* only for i.MX6SX/UL */
415 #define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \ 415 #define WDOG3_BASE_ADDR (((is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \
416 MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) 416 MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
417 #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \ 417 #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \
418 MX6UL_LCDIF1_BASE_ADDR : \ 418 MX6UL_LCDIF1_BASE_ADDR : \
419 ((is_cpu_type(MXC_CPU_MX6ULL)) ? \ 419 ((is_cpu_type(MXC_CPU_MX6ULL)) ? \
420 MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)) 420 MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))
421 #define UART6_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \ 421 #define UART6_BASE_ADDR (((is_cpu_type(MXC_CPU_MX6UL)) || is_cpu_type(MXC_CPU_MX6ULL)) ? \
422 MX6UL_UART6_BASE_ADDR : MX6SX_UART6_BASE_ADDR) 422 MX6UL_UART6_BASE_ADDR : MX6SX_UART6_BASE_ADDR)
423 423
424 #define MXS_LCDIF_BASE LCDIF1_BASE_ADDR 424 #define MXS_LCDIF_BASE LCDIF1_BASE_ADDR
425 425
426 426
427 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 427 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
428 428
429 #define SRC_SCR_CORE_1_RESET_OFFSET 14 429 #define SRC_SCR_CORE_1_RESET_OFFSET 14
430 #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET) 430 #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET)
431 #define SRC_SCR_CORE_2_RESET_OFFSET 15 431 #define SRC_SCR_CORE_2_RESET_OFFSET 15
432 #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET) 432 #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET)
433 #define SRC_SCR_CORE_3_RESET_OFFSET 16 433 #define SRC_SCR_CORE_3_RESET_OFFSET 16
434 #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET) 434 #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET)
435 #define SRC_SCR_CORE_1_ENABLE_OFFSET 22 435 #define SRC_SCR_CORE_1_ENABLE_OFFSET 22
436 #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET) 436 #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
437 #define SRC_SCR_CORE_2_ENABLE_OFFSET 23 437 #define SRC_SCR_CORE_2_ENABLE_OFFSET 23
438 #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET) 438 #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
439 #define SRC_SCR_CORE_3_ENABLE_OFFSET 24 439 #define SRC_SCR_CORE_3_ENABLE_OFFSET 24
440 #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET) 440 #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
441 441
442 struct rdc_regs { 442 struct rdc_regs {
443 u32 vir; /* Version information */ 443 u32 vir; /* Version information */
444 u32 reserved1[8]; 444 u32 reserved1[8];
445 u32 stat; /* Status */ 445 u32 stat; /* Status */
446 u32 intctrl; /* Interrupt and Control */ 446 u32 intctrl; /* Interrupt and Control */
447 u32 intstat; /* Interrupt Status */ 447 u32 intstat; /* Interrupt Status */
448 u32 reserved2[116]; 448 u32 reserved2[116];
449 u32 mda[32]; /* Master Domain Assignment */ 449 u32 mda[32]; /* Master Domain Assignment */
450 u32 reserved3[96]; 450 u32 reserved3[96];
451 u32 pdap[104]; /* Peripheral Domain Access Permissions */ 451 u32 pdap[104]; /* Peripheral Domain Access Permissions */
452 u32 reserved4[88]; 452 u32 reserved4[88];
453 struct { 453 struct {
454 u32 mrsa; /* Memory Region Start Address */ 454 u32 mrsa; /* Memory Region Start Address */
455 u32 mrea; /* Memory Region End Address */ 455 u32 mrea; /* Memory Region End Address */
456 u32 mrc; /* Memory Region Control */ 456 u32 mrc; /* Memory Region Control */
457 u32 mrvs; /* Memory Region Violation Status */ 457 u32 mrvs; /* Memory Region Violation Status */
458 } mem_region[55]; 458 } mem_region[55];
459 }; 459 };
460 460
461 struct rdc_sema_regs { 461 struct rdc_sema_regs {
462 u8 gate[64]; /* Gate */ 462 u8 gate[64]; /* Gate */
463 u16 rstgt; /* Reset Gate */ 463 u16 rstgt; /* Reset Gate */
464 }; 464 };
465 465
466 /* WEIM registers */ 466 /* WEIM registers */
467 struct weim { 467 struct weim {
468 u32 cs0gcr1; 468 u32 cs0gcr1;
469 u32 cs0gcr2; 469 u32 cs0gcr2;
470 u32 cs0rcr1; 470 u32 cs0rcr1;
471 u32 cs0rcr2; 471 u32 cs0rcr2;
472 u32 cs0wcr1; 472 u32 cs0wcr1;
473 u32 cs0wcr2; 473 u32 cs0wcr2;
474 474
475 u32 cs1gcr1; 475 u32 cs1gcr1;
476 u32 cs1gcr2; 476 u32 cs1gcr2;
477 u32 cs1rcr1; 477 u32 cs1rcr1;
478 u32 cs1rcr2; 478 u32 cs1rcr2;
479 u32 cs1wcr1; 479 u32 cs1wcr1;
480 u32 cs1wcr2; 480 u32 cs1wcr2;
481 481
482 u32 cs2gcr1; 482 u32 cs2gcr1;
483 u32 cs2gcr2; 483 u32 cs2gcr2;
484 u32 cs2rcr1; 484 u32 cs2rcr1;
485 u32 cs2rcr2; 485 u32 cs2rcr2;
486 u32 cs2wcr1; 486 u32 cs2wcr1;
487 u32 cs2wcr2; 487 u32 cs2wcr2;
488 488
489 u32 cs3gcr1; 489 u32 cs3gcr1;
490 u32 cs3gcr2; 490 u32 cs3gcr2;
491 u32 cs3rcr1; 491 u32 cs3rcr1;
492 u32 cs3rcr2; 492 u32 cs3rcr2;
493 u32 cs3wcr1; 493 u32 cs3wcr1;
494 u32 cs3wcr2; 494 u32 cs3wcr2;
495 495
496 u32 unused[12]; 496 u32 unused[12];
497 497
498 u32 wcr; 498 u32 wcr;
499 u32 wiar; 499 u32 wiar;
500 u32 ear; 500 u32 ear;
501 }; 501 };
502 502
503 /* System Reset Controller (SRC) */ 503 /* System Reset Controller (SRC) */
504 struct src { 504 struct src {
505 u32 scr; 505 u32 scr;
506 u32 sbmr1; 506 u32 sbmr1;
507 u32 srsr; 507 u32 srsr;
508 u32 reserved1[2]; 508 u32 reserved1[2];
509 u32 sisr; 509 u32 sisr;
510 u32 simr; 510 u32 simr;
511 u32 sbmr2; 511 u32 sbmr2;
512 u32 gpr1; 512 u32 gpr1;
513 u32 gpr2; 513 u32 gpr2;
514 u32 gpr3; 514 u32 gpr3;
515 u32 gpr4; 515 u32 gpr4;
516 u32 gpr5; 516 u32 gpr5;
517 u32 gpr6; 517 u32 gpr6;
518 u32 gpr7; 518 u32 gpr7;
519 u32 gpr8; 519 u32 gpr8;
520 u32 gpr9; 520 u32 gpr9;
521 u32 gpr10; 521 u32 gpr10;
522 }; 522 };
523 523
524 #define SRC_SCR_M4_ENABLE_OFFSET 22 524 #define SRC_SCR_M4_ENABLE_OFFSET 22
525 #define SRC_SCR_M4_ENABLE_MASK (1 << 22) 525 #define SRC_SCR_M4_ENABLE_MASK (1 << 22)
526 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4 526 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4
527 #define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4) 527 #define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4)
528 528
529 /* GPR1 bitfields */ 529 /* GPR1 bitfields */
530 #define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30) 530 #define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
531 #define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28) 531 #define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
532 #define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27) 532 #define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27)
533 #define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26) 533 #define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26)
534 #define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25) 534 #define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25)
535 #define IOMUXC_GPR1_DPI_OFF BIT(24) 535 #define IOMUXC_GPR1_DPI_OFF BIT(24)
536 #define IOMUXC_GPR1_EXC_MON_SLVE BIT(22) 536 #define IOMUXC_GPR1_EXC_MON_SLVE BIT(22)
537 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 537 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
538 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) 538 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
539 #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) 539 #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
540 #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) 540 #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
541 #define IOMUXC_GPR1_PCIE_TEST_PD BIT(18) 541 #define IOMUXC_GPR1_PCIE_TEST_PD BIT(18)
542 #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17) 542 #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
543 #define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16) 543 #define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16)
544 #define IOMUXC_GPR1_USB_EXP_MODE BIT(15) 544 #define IOMUXC_GPR1_USB_EXP_MODE BIT(15)
545 #define IOMUXC_GPR1_PCIE_INT BIT(14) 545 #define IOMUXC_GPR1_PCIE_INT BIT(14)
546 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 546 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
547 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET) 547 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
548 #define IOMUXC_GPR1_GINT BIT(12) 548 #define IOMUXC_GPR1_GINT BIT(12)
549 #define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10) 549 #define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10)
550 #define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10) 550 #define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10)
551 #define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10) 551 #define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10)
552 #define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10) 552 #define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10)
553 #define IOMUXC_GPR1_ACT_CS3 BIT(9) 553 #define IOMUXC_GPR1_ACT_CS3 BIT(9)
554 #define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7) 554 #define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7)
555 #define IOMUXC_GPR1_ACT_CS2 BIT(6) 555 #define IOMUXC_GPR1_ACT_CS2 BIT(6)
556 #define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4) 556 #define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4)
557 #define IOMUXC_GPR1_ACT_CS1 BIT(3) 557 #define IOMUXC_GPR1_ACT_CS1 BIT(3)
558 #define IOMUXC_GPR1_ADDRS0_OFFSET (1) 558 #define IOMUXC_GPR1_ADDRS0_OFFSET (1)
559 #define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1) 559 #define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1)
560 #define IOMUXC_GPR1_ACT_CS0 BIT(0) 560 #define IOMUXC_GPR1_ACT_CS0 BIT(0)
561 561
562 /* GPR3 bitfields */ 562 /* GPR3 bitfields */
563 #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 563 #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
564 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) 564 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
565 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 565 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
566 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) 566 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
567 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 567 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
568 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) 568 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
569 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 569 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
570 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) 570 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
571 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 571 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
572 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) 572 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
573 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 573 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
574 #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) 574 #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
575 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 575 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
576 #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) 576 #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
577 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 577 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
578 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) 578 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
579 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 579 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
580 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) 580 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
581 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 581 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
582 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) 582 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
583 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 583 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
584 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) 584 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
585 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 585 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
586 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) 586 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
587 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 587 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
588 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) 588 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
589 #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 589 #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
590 #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) 590 #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
591 591
592 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 592 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
593 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 593 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
594 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 594 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
595 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 595 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
596 596
597 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 597 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
598 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) 598 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
599 599
600 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 600 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
601 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) 601 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
602 602
603 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 603 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
604 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) 604 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
605 605
606 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 606 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
607 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) 607 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
608 608
609 /* gpr12 bitfields */ 609 /* gpr12 bitfields */
610 #define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27) 610 #define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27)
611 #define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26) 611 #define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26)
612 #define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25) 612 #define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25)
613 #define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24) 613 #define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24)
614 #define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12) 614 #define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12)
615 #define IOMUXC_GPR12_PCIE_CTL_2 BIT(10) 615 #define IOMUXC_GPR12_PCIE_CTL_2 BIT(10)
616 #define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4) 616 #define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
617 617
618 struct iomuxc { 618 struct iomuxc {
619 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 619 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
620 u8 reserved[0x4000]; 620 u8 reserved[0x4000];
621 #endif 621 #endif
622 622
623 #ifdef CONFIG_MX6UL 623 #ifdef CONFIG_MX6UL
624 u32 gpr[15]; 624 u32 gpr[15];
625 #else 625 #else
626 u32 gpr[14]; 626 u32 gpr[14];
627 #endif 627 #endif
628 }; 628 };
629 629
630 struct gpc { 630 struct gpc {
631 u32 cntr; 631 u32 cntr;
632 u32 pgr; 632 u32 pgr;
633 u32 imr1; 633 u32 imr1;
634 u32 imr2; 634 u32 imr2;
635 u32 imr3; 635 u32 imr3;
636 u32 imr4; 636 u32 imr4;
637 u32 isr1; 637 u32 isr1;
638 u32 isr2; 638 u32 isr2;
639 u32 isr3; 639 u32 isr3;
640 u32 isr4; 640 u32 isr4;
641 }; 641 };
642 642
643 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 643 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
644 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) 644 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
645 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 645 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
646 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) 646 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
647 647
648 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 648 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
649 #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 649 #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
650 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 650 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
651 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 651 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
652 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 652 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
653 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 653 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
654 654
655 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 655 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
656 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 656 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
657 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 657 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
658 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 658 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
659 659
660 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 660 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
661 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 661 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
662 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 662 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
663 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 663 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
664 664
665 #define IOMUXC_GPR2_BITMAP_SPWG 0 665 #define IOMUXC_GPR2_BITMAP_SPWG 0
666 #define IOMUXC_GPR2_BITMAP_JEIDA 1 666 #define IOMUXC_GPR2_BITMAP_JEIDA 1
667 667
668 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 668 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
669 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 669 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
670 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 670 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
671 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 671 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
672 672
673 #define IOMUXC_GPR2_DATA_WIDTH_18 0 673 #define IOMUXC_GPR2_DATA_WIDTH_18 0
674 #define IOMUXC_GPR2_DATA_WIDTH_24 1 674 #define IOMUXC_GPR2_DATA_WIDTH_24 1
675 675
676 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 676 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
677 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 677 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
678 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 678 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
679 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 679 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
680 680
681 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 681 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
682 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 682 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
683 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 683 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
684 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 684 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
685 685
686 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 686 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
687 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 687 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
688 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 688 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
689 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 689 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
690 690
691 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 691 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
692 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) 692 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
693 693
694 #define IOMUXC_GPR2_MODE_DISABLED 0 694 #define IOMUXC_GPR2_MODE_DISABLED 0
695 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1 695 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1
696 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3 696 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3
697 697
698 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 698 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
699 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 699 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
700 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 700 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
701 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 701 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
702 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 702 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
703 703
704 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 704 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
705 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 705 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
706 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 706 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
707 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 707 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
708 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 708 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
709 709
710 #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4) 710 #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4)
711 #define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4) 711 #define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4)
712 #define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD (0x1 << 4) 712 #define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD (0x1 << 4)
713 #define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI (0x2 << 4) 713 #define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI (0x2 << 4)
714 #define IMX6SX_GPR5_CSI1_MUX_CTRL_GND (0x3 << 4) 714 #define IMX6SX_GPR5_CSI1_MUX_CTRL_GND (0x3 << 4)
715 715
716 /* ECSPI registers */ 716 /* ECSPI registers */
717 struct cspi_regs { 717 struct cspi_regs {
718 u32 rxdata; 718 u32 rxdata;
719 u32 txdata; 719 u32 txdata;
720 u32 ctrl; 720 u32 ctrl;
721 u32 cfg; 721 u32 cfg;
722 u32 intr; 722 u32 intr;
723 u32 dma; 723 u32 dma;
724 u32 stat; 724 u32 stat;
725 u32 period; 725 u32 period;
726 }; 726 };
727 727
728 /* 728 /*
729 * CSPI register definitions 729 * CSPI register definitions
730 */ 730 */
731 #define MXC_ECSPI 731 #define MXC_ECSPI
732 #define MXC_CSPICTRL_EN (1 << 0) 732 #define MXC_CSPICTRL_EN (1 << 0)
733 #define MXC_CSPICTRL_MODE (1 << 1) 733 #define MXC_CSPICTRL_MODE (1 << 1)
734 #define MXC_CSPICTRL_XCH (1 << 2) 734 #define MXC_CSPICTRL_XCH (1 << 2)
735 #define MXC_CSPICTRL_MODE_MASK (0xf << 4) 735 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
736 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 736 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
737 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 737 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
738 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 738 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
739 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 739 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
740 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 740 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
741 #define MXC_CSPICTRL_MAXBITS 0xfff 741 #define MXC_CSPICTRL_MAXBITS 0xfff
742 #define MXC_CSPICTRL_TC (1 << 7) 742 #define MXC_CSPICTRL_TC (1 << 7)
743 #define MXC_CSPICTRL_RXOVF (1 << 6) 743 #define MXC_CSPICTRL_RXOVF (1 << 6)
744 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 744 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
745 #define MAX_SPI_BYTES 32 745 #define MAX_SPI_BYTES 32
746 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) 746 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
747 #define SPI_MAX_NUM 3 747 #define SPI_MAX_NUM 3
748 #else 748 #else
749 #define SPI_MAX_NUM 4 749 #define SPI_MAX_NUM 4
750 #endif 750 #endif
751 751
752 /* Bit position inside CTRL register to be associated with SS */ 752 /* Bit position inside CTRL register to be associated with SS */
753 #define MXC_CSPICTRL_CHAN 18 753 #define MXC_CSPICTRL_CHAN 18
754 754
755 /* Bit position inside CON register to be associated with SS */ 755 /* Bit position inside CON register to be associated with SS */
756 #define MXC_CSPICON_PHA 0 /* SCLK phase control */ 756 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
757 #define MXC_CSPICON_POL 4 /* SCLK polarity */ 757 #define MXC_CSPICON_POL 4 /* SCLK polarity */
758 #define MXC_CSPICON_SSPOL 12 /* SS polarity */ 758 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
759 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ 759 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
760 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) 760 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
761 #define MXC_SPI_BASE_ADDRESSES \ 761 #define MXC_SPI_BASE_ADDRESSES \
762 ECSPI1_BASE_ADDR, \ 762 ECSPI1_BASE_ADDR, \
763 ECSPI2_BASE_ADDR, \ 763 ECSPI2_BASE_ADDR, \
764 ECSPI3_BASE_ADDR, \ 764 ECSPI3_BASE_ADDR, \
765 ECSPI4_BASE_ADDR 765 ECSPI4_BASE_ADDR
766 #else 766 #else
767 #define MXC_SPI_BASE_ADDRESSES \ 767 #define MXC_SPI_BASE_ADDRESSES \
768 ECSPI1_BASE_ADDR, \ 768 ECSPI1_BASE_ADDR, \
769 ECSPI2_BASE_ADDR, \ 769 ECSPI2_BASE_ADDR, \
770 ECSPI3_BASE_ADDR, \ 770 ECSPI3_BASE_ADDR, \
771 ECSPI4_BASE_ADDR, \ 771 ECSPI4_BASE_ADDR, \
772 ECSPI5_BASE_ADDR 772 ECSPI5_BASE_ADDR
773 #endif 773 #endif
774 774
775 #define ANATOP_PLL_VIDEO 0xA0 775 #define ANATOP_PLL_VIDEO 0xA0
776 776
777 struct ocotp_regs { 777 struct ocotp_regs {
778 u32 ctrl; 778 u32 ctrl;
779 u32 ctrl_set; 779 u32 ctrl_set;
780 u32 ctrl_clr; 780 u32 ctrl_clr;
781 u32 ctrl_tog; 781 u32 ctrl_tog;
782 u32 timing; 782 u32 timing;
783 u32 rsvd0[3]; 783 u32 rsvd0[3];
784 u32 data; 784 u32 data;
785 u32 rsvd1[3]; 785 u32 rsvd1[3];
786 u32 read_ctrl; 786 u32 read_ctrl;
787 u32 rsvd2[3]; 787 u32 rsvd2[3];
788 u32 read_fuse_data; 788 u32 read_fuse_data;
789 u32 rsvd3[3]; 789 u32 rsvd3[3];
790 u32 sw_sticky; 790 u32 sw_sticky;
791 u32 rsvd4[3]; 791 u32 rsvd4[3];
792 u32 scs; 792 u32 scs;
793 u32 scs_set; 793 u32 scs_set;
794 u32 scs_clr; 794 u32 scs_clr;
795 u32 scs_tog; 795 u32 scs_tog;
796 u32 crc_addr; 796 u32 crc_addr;
797 u32 rsvd5[3]; 797 u32 rsvd5[3];
798 u32 crc_value; 798 u32 crc_value;
799 u32 rsvd6[3]; 799 u32 rsvd6[3];
800 u32 version; 800 u32 version;
801 u32 rsvd7[0xdb]; 801 u32 rsvd7[0xdb];
802 802
803 /* fuse banks */ 803 /* fuse banks */
804 struct fuse_bank { 804 struct fuse_bank {
805 u32 fuse_regs[0x20]; 805 u32 fuse_regs[0x20];
806 } bank[0]; 806 } bank[0];
807 }; 807 };
808 808
809 struct fuse_bank0_regs { 809 struct fuse_bank0_regs {
810 u32 lock; 810 u32 lock;
811 u32 rsvd0[3]; 811 u32 rsvd0[3];
812 u32 uid_low; 812 u32 uid_low;
813 u32 rsvd1[3]; 813 u32 rsvd1[3];
814 u32 uid_high; 814 u32 uid_high;
815 u32 rsvd2[3]; 815 u32 rsvd2[3];
816 u32 cfg2; 816 u32 cfg2;
817 u32 rsvd3[3]; 817 u32 rsvd3[3];
818 u32 cfg3; 818 u32 cfg3;
819 u32 rsvd4[3]; 819 u32 rsvd4[3];
820 u32 cfg4; 820 u32 cfg4;
821 u32 rsvd5[3]; 821 u32 rsvd5[3];
822 u32 cfg5; 822 u32 cfg5;
823 u32 rsvd6[3]; 823 u32 rsvd6[3];
824 u32 cfg6; 824 u32 cfg6;
825 u32 rsvd7[3]; 825 u32 rsvd7[3];
826 }; 826 };
827 827
828 struct fuse_bank1_regs { 828 struct fuse_bank1_regs {
829 u32 mem0; 829 u32 mem0;
830 u32 rsvd0[3]; 830 u32 rsvd0[3];
831 u32 mem1; 831 u32 mem1;
832 u32 rsvd1[3]; 832 u32 rsvd1[3];
833 u32 mem2; 833 u32 mem2;
834 u32 rsvd2[3]; 834 u32 rsvd2[3];
835 u32 mem3; 835 u32 mem3;
836 u32 rsvd3[3]; 836 u32 rsvd3[3];
837 u32 mem4; 837 u32 mem4;
838 u32 rsvd4[3]; 838 u32 rsvd4[3];
839 u32 ana0; 839 u32 ana0;
840 u32 rsvd5[3]; 840 u32 rsvd5[3];
841 u32 ana1; 841 u32 ana1;
842 u32 rsvd6[3]; 842 u32 rsvd6[3];
843 u32 ana2; 843 u32 ana2;
844 u32 rsvd7[3]; 844 u32 rsvd7[3];
845 }; 845 };
846 846
847 struct fuse_bank4_regs { 847 struct fuse_bank4_regs {
848 u32 sjc_resp_low; 848 u32 sjc_resp_low;
849 u32 rsvd0[3]; 849 u32 rsvd0[3];
850 u32 sjc_resp_high; 850 u32 sjc_resp_high;
851 u32 rsvd1[3]; 851 u32 rsvd1[3];
852 u32 mac_addr0; 852 u32 mac_addr0;
853 u32 rsvd2[3]; 853 u32 rsvd2[3];
854 u32 mac_addr1; 854 u32 mac_addr1;
855 u32 rsvd3[3]; 855 u32 rsvd3[3];
856 u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/ 856 u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
857 u32 rsvd4[7]; 857 u32 rsvd4[7];
858 u32 gp1; 858 u32 gp1;
859 u32 rsvd5[3]; 859 u32 rsvd5[3];
860 u32 gp2; 860 u32 gp2;
861 u32 rsvd6[3]; 861 u32 rsvd6[3];
862 }; 862 };
863 863
864 struct aipstz_regs { 864 struct aipstz_regs {
865 u32 mprot0; 865 u32 mprot0;
866 u32 mprot1; 866 u32 mprot1;
867 u32 rsvd[0xe]; 867 u32 rsvd[0xe];
868 u32 opacr0; 868 u32 opacr0;
869 u32 opacr1; 869 u32 opacr1;
870 u32 opacr2; 870 u32 opacr2;
871 u32 opacr3; 871 u32 opacr3;
872 u32 opacr4; 872 u32 opacr4;
873 }; 873 };
874 874
875 struct anatop_regs { 875 struct anatop_regs {
876 u32 pll_sys; /* 0x000 */ 876 u32 pll_sys; /* 0x000 */
877 u32 pll_sys_set; /* 0x004 */ 877 u32 pll_sys_set; /* 0x004 */
878 u32 pll_sys_clr; /* 0x008 */ 878 u32 pll_sys_clr; /* 0x008 */
879 u32 pll_sys_tog; /* 0x00c */ 879 u32 pll_sys_tog; /* 0x00c */
880 u32 usb1_pll_480_ctrl; /* 0x010 */ 880 u32 usb1_pll_480_ctrl; /* 0x010 */
881 u32 usb1_pll_480_ctrl_set; /* 0x014 */ 881 u32 usb1_pll_480_ctrl_set; /* 0x014 */
882 u32 usb1_pll_480_ctrl_clr; /* 0x018 */ 882 u32 usb1_pll_480_ctrl_clr; /* 0x018 */
883 u32 usb1_pll_480_ctrl_tog; /* 0x01c */ 883 u32 usb1_pll_480_ctrl_tog; /* 0x01c */
884 u32 usb2_pll_480_ctrl; /* 0x020 */ 884 u32 usb2_pll_480_ctrl; /* 0x020 */
885 u32 usb2_pll_480_ctrl_set; /* 0x024 */ 885 u32 usb2_pll_480_ctrl_set; /* 0x024 */
886 u32 usb2_pll_480_ctrl_clr; /* 0x028 */ 886 u32 usb2_pll_480_ctrl_clr; /* 0x028 */
887 u32 usb2_pll_480_ctrl_tog; /* 0x02c */ 887 u32 usb2_pll_480_ctrl_tog; /* 0x02c */
888 u32 pll_528; /* 0x030 */ 888 u32 pll_528; /* 0x030 */
889 u32 pll_528_set; /* 0x034 */ 889 u32 pll_528_set; /* 0x034 */
890 u32 pll_528_clr; /* 0x038 */ 890 u32 pll_528_clr; /* 0x038 */
891 u32 pll_528_tog; /* 0x03c */ 891 u32 pll_528_tog; /* 0x03c */
892 u32 pll_528_ss; /* 0x040 */ 892 u32 pll_528_ss; /* 0x040 */
893 u32 rsvd0[3]; 893 u32 rsvd0[3];
894 u32 pll_528_num; /* 0x050 */ 894 u32 pll_528_num; /* 0x050 */
895 u32 rsvd1[3]; 895 u32 rsvd1[3];
896 u32 pll_528_denom; /* 0x060 */ 896 u32 pll_528_denom; /* 0x060 */
897 u32 rsvd2[3]; 897 u32 rsvd2[3];
898 u32 pll_audio; /* 0x070 */ 898 u32 pll_audio; /* 0x070 */
899 u32 pll_audio_set; /* 0x074 */ 899 u32 pll_audio_set; /* 0x074 */
900 u32 pll_audio_clr; /* 0x078 */ 900 u32 pll_audio_clr; /* 0x078 */
901 u32 pll_audio_tog; /* 0x07c */ 901 u32 pll_audio_tog; /* 0x07c */
902 u32 pll_audio_num; /* 0x080 */ 902 u32 pll_audio_num; /* 0x080 */
903 u32 rsvd3[3]; 903 u32 rsvd3[3];
904 u32 pll_audio_denom; /* 0x090 */ 904 u32 pll_audio_denom; /* 0x090 */
905 u32 rsvd4[3]; 905 u32 rsvd4[3];
906 u32 pll_video; /* 0x0a0 */ 906 u32 pll_video; /* 0x0a0 */
907 u32 pll_video_set; /* 0x0a4 */ 907 u32 pll_video_set; /* 0x0a4 */
908 u32 pll_video_clr; /* 0x0a8 */ 908 u32 pll_video_clr; /* 0x0a8 */
909 u32 pll_video_tog; /* 0x0ac */ 909 u32 pll_video_tog; /* 0x0ac */
910 u32 pll_video_num; /* 0x0b0 */ 910 u32 pll_video_num; /* 0x0b0 */
911 u32 rsvd5[3]; 911 u32 rsvd5[3];
912 u32 pll_video_denom; /* 0x0c0 */ 912 u32 pll_video_denom; /* 0x0c0 */
913 u32 rsvd6[3]; 913 u32 rsvd6[3];
914 u32 pll_mlb; /* 0x0d0 */ 914 u32 pll_mlb; /* 0x0d0 */
915 u32 pll_mlb_set; /* 0x0d4 */ 915 u32 pll_mlb_set; /* 0x0d4 */
916 u32 pll_mlb_clr; /* 0x0d8 */ 916 u32 pll_mlb_clr; /* 0x0d8 */
917 u32 pll_mlb_tog; /* 0x0dc */ 917 u32 pll_mlb_tog; /* 0x0dc */
918 u32 pll_enet; /* 0x0e0 */ 918 u32 pll_enet; /* 0x0e0 */
919 u32 pll_enet_set; /* 0x0e4 */ 919 u32 pll_enet_set; /* 0x0e4 */
920 u32 pll_enet_clr; /* 0x0e8 */ 920 u32 pll_enet_clr; /* 0x0e8 */
921 u32 pll_enet_tog; /* 0x0ec */ 921 u32 pll_enet_tog; /* 0x0ec */
922 u32 pfd_480; /* 0x0f0 */ 922 u32 pfd_480; /* 0x0f0 */
923 u32 pfd_480_set; /* 0x0f4 */ 923 u32 pfd_480_set; /* 0x0f4 */
924 u32 pfd_480_clr; /* 0x0f8 */ 924 u32 pfd_480_clr; /* 0x0f8 */
925 u32 pfd_480_tog; /* 0x0fc */ 925 u32 pfd_480_tog; /* 0x0fc */
926 u32 pfd_528; /* 0x100 */ 926 u32 pfd_528; /* 0x100 */
927 u32 pfd_528_set; /* 0x104 */ 927 u32 pfd_528_set; /* 0x104 */
928 u32 pfd_528_clr; /* 0x108 */ 928 u32 pfd_528_clr; /* 0x108 */
929 u32 pfd_528_tog; /* 0x10c */ 929 u32 pfd_528_tog; /* 0x10c */
930 u32 reg_1p1; /* 0x110 */ 930 u32 reg_1p1; /* 0x110 */
931 u32 reg_1p1_set; /* 0x114 */ 931 u32 reg_1p1_set; /* 0x114 */
932 u32 reg_1p1_clr; /* 0x118 */ 932 u32 reg_1p1_clr; /* 0x118 */
933 u32 reg_1p1_tog; /* 0x11c */ 933 u32 reg_1p1_tog; /* 0x11c */
934 u32 reg_3p0; /* 0x120 */ 934 u32 reg_3p0; /* 0x120 */
935 u32 reg_3p0_set; /* 0x124 */ 935 u32 reg_3p0_set; /* 0x124 */
936 u32 reg_3p0_clr; /* 0x128 */ 936 u32 reg_3p0_clr; /* 0x128 */
937 u32 reg_3p0_tog; /* 0x12c */ 937 u32 reg_3p0_tog; /* 0x12c */
938 u32 reg_2p5; /* 0x130 */ 938 u32 reg_2p5; /* 0x130 */
939 u32 reg_2p5_set; /* 0x134 */ 939 u32 reg_2p5_set; /* 0x134 */
940 u32 reg_2p5_clr; /* 0x138 */ 940 u32 reg_2p5_clr; /* 0x138 */
941 u32 reg_2p5_tog; /* 0x13c */ 941 u32 reg_2p5_tog; /* 0x13c */
942 u32 reg_core; /* 0x140 */ 942 u32 reg_core; /* 0x140 */
943 u32 reg_core_set; /* 0x144 */ 943 u32 reg_core_set; /* 0x144 */
944 u32 reg_core_clr; /* 0x148 */ 944 u32 reg_core_clr; /* 0x148 */
945 u32 reg_core_tog; /* 0x14c */ 945 u32 reg_core_tog; /* 0x14c */
946 u32 ana_misc0; /* 0x150 */ 946 u32 ana_misc0; /* 0x150 */
947 u32 ana_misc0_set; /* 0x154 */ 947 u32 ana_misc0_set; /* 0x154 */
948 u32 ana_misc0_clr; /* 0x158 */ 948 u32 ana_misc0_clr; /* 0x158 */
949 u32 ana_misc0_tog; /* 0x15c */ 949 u32 ana_misc0_tog; /* 0x15c */
950 u32 ana_misc1; /* 0x160 */ 950 u32 ana_misc1; /* 0x160 */
951 u32 ana_misc1_set; /* 0x164 */ 951 u32 ana_misc1_set; /* 0x164 */
952 u32 ana_misc1_clr; /* 0x168 */ 952 u32 ana_misc1_clr; /* 0x168 */
953 u32 ana_misc1_tog; /* 0x16c */ 953 u32 ana_misc1_tog; /* 0x16c */
954 u32 ana_misc2; /* 0x170 */ 954 u32 ana_misc2; /* 0x170 */
955 u32 ana_misc2_set; /* 0x174 */ 955 u32 ana_misc2_set; /* 0x174 */
956 u32 ana_misc2_clr; /* 0x178 */ 956 u32 ana_misc2_clr; /* 0x178 */
957 u32 ana_misc2_tog; /* 0x17c */ 957 u32 ana_misc2_tog; /* 0x17c */
958 u32 tempsense0; /* 0x180 */ 958 u32 tempsense0; /* 0x180 */
959 u32 tempsense0_set; /* 0x184 */ 959 u32 tempsense0_set; /* 0x184 */
960 u32 tempsense0_clr; /* 0x188 */ 960 u32 tempsense0_clr; /* 0x188 */
961 u32 tempsense0_tog; /* 0x18c */ 961 u32 tempsense0_tog; /* 0x18c */
962 u32 tempsense1; /* 0x190 */ 962 u32 tempsense1; /* 0x190 */
963 u32 tempsense1_set; /* 0x194 */ 963 u32 tempsense1_set; /* 0x194 */
964 u32 tempsense1_clr; /* 0x198 */ 964 u32 tempsense1_clr; /* 0x198 */
965 u32 tempsense1_tog; /* 0x19c */ 965 u32 tempsense1_tog; /* 0x19c */
966 u32 usb1_vbus_detect; /* 0x1a0 */ 966 u32 usb1_vbus_detect; /* 0x1a0 */
967 u32 usb1_vbus_detect_set; /* 0x1a4 */ 967 u32 usb1_vbus_detect_set; /* 0x1a4 */
968 u32 usb1_vbus_detect_clr; /* 0x1a8 */ 968 u32 usb1_vbus_detect_clr; /* 0x1a8 */
969 u32 usb1_vbus_detect_tog; /* 0x1ac */ 969 u32 usb1_vbus_detect_tog; /* 0x1ac */
970 u32 usb1_chrg_detect; /* 0x1b0 */ 970 u32 usb1_chrg_detect; /* 0x1b0 */
971 u32 usb1_chrg_detect_set; /* 0x1b4 */ 971 u32 usb1_chrg_detect_set; /* 0x1b4 */
972 u32 usb1_chrg_detect_clr; /* 0x1b8 */ 972 u32 usb1_chrg_detect_clr; /* 0x1b8 */
973 u32 usb1_chrg_detect_tog; /* 0x1bc */ 973 u32 usb1_chrg_detect_tog; /* 0x1bc */
974 u32 usb1_vbus_det_stat; /* 0x1c0 */ 974 u32 usb1_vbus_det_stat; /* 0x1c0 */
975 u32 usb1_vbus_det_stat_set; /* 0x1c4 */ 975 u32 usb1_vbus_det_stat_set; /* 0x1c4 */
976 u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ 976 u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
977 u32 usb1_vbus_det_stat_tog; /* 0x1cc */ 977 u32 usb1_vbus_det_stat_tog; /* 0x1cc */
978 u32 usb1_chrg_det_stat; /* 0x1d0 */ 978 u32 usb1_chrg_det_stat; /* 0x1d0 */
979 u32 usb1_chrg_det_stat_set; /* 0x1d4 */ 979 u32 usb1_chrg_det_stat_set; /* 0x1d4 */
980 u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ 980 u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
981 u32 usb1_chrg_det_stat_tog; /* 0x1dc */ 981 u32 usb1_chrg_det_stat_tog; /* 0x1dc */
982 u32 usb1_loopback; /* 0x1e0 */ 982 u32 usb1_loopback; /* 0x1e0 */
983 u32 usb1_loopback_set; /* 0x1e4 */ 983 u32 usb1_loopback_set; /* 0x1e4 */
984 u32 usb1_loopback_clr; /* 0x1e8 */ 984 u32 usb1_loopback_clr; /* 0x1e8 */
985 u32 usb1_loopback_tog; /* 0x1ec */ 985 u32 usb1_loopback_tog; /* 0x1ec */
986 u32 usb1_misc; /* 0x1f0 */ 986 u32 usb1_misc; /* 0x1f0 */
987 u32 usb1_misc_set; /* 0x1f4 */ 987 u32 usb1_misc_set; /* 0x1f4 */
988 u32 usb1_misc_clr; /* 0x1f8 */ 988 u32 usb1_misc_clr; /* 0x1f8 */
989 u32 usb1_misc_tog; /* 0x1fc */ 989 u32 usb1_misc_tog; /* 0x1fc */
990 u32 usb2_vbus_detect; /* 0x200 */ 990 u32 usb2_vbus_detect; /* 0x200 */
991 u32 usb2_vbus_detect_set; /* 0x204 */ 991 u32 usb2_vbus_detect_set; /* 0x204 */
992 u32 usb2_vbus_detect_clr; /* 0x208 */ 992 u32 usb2_vbus_detect_clr; /* 0x208 */
993 u32 usb2_vbus_detect_tog; /* 0x20c */ 993 u32 usb2_vbus_detect_tog; /* 0x20c */
994 u32 usb2_chrg_detect; /* 0x210 */ 994 u32 usb2_chrg_detect; /* 0x210 */
995 u32 usb2_chrg_detect_set; /* 0x214 */ 995 u32 usb2_chrg_detect_set; /* 0x214 */
996 u32 usb2_chrg_detect_clr; /* 0x218 */ 996 u32 usb2_chrg_detect_clr; /* 0x218 */
997 u32 usb2_chrg_detect_tog; /* 0x21c */ 997 u32 usb2_chrg_detect_tog; /* 0x21c */
998 u32 usb2_vbus_det_stat; /* 0x220 */ 998 u32 usb2_vbus_det_stat; /* 0x220 */
999 u32 usb2_vbus_det_stat_set; /* 0x224 */ 999 u32 usb2_vbus_det_stat_set; /* 0x224 */
1000 u32 usb2_vbus_det_stat_clr; /* 0x228 */ 1000 u32 usb2_vbus_det_stat_clr; /* 0x228 */
1001 u32 usb2_vbus_det_stat_tog; /* 0x22c */ 1001 u32 usb2_vbus_det_stat_tog; /* 0x22c */
1002 u32 usb2_chrg_det_stat; /* 0x230 */ 1002 u32 usb2_chrg_det_stat; /* 0x230 */
1003 u32 usb2_chrg_det_stat_set; /* 0x234 */ 1003 u32 usb2_chrg_det_stat_set; /* 0x234 */
1004 u32 usb2_chrg_det_stat_clr; /* 0x238 */ 1004 u32 usb2_chrg_det_stat_clr; /* 0x238 */
1005 u32 usb2_chrg_det_stat_tog; /* 0x23c */ 1005 u32 usb2_chrg_det_stat_tog; /* 0x23c */
1006 u32 usb2_loopback; /* 0x240 */ 1006 u32 usb2_loopback; /* 0x240 */
1007 u32 usb2_loopback_set; /* 0x244 */ 1007 u32 usb2_loopback_set; /* 0x244 */
1008 u32 usb2_loopback_clr; /* 0x248 */ 1008 u32 usb2_loopback_clr; /* 0x248 */
1009 u32 usb2_loopback_tog; /* 0x24c */ 1009 u32 usb2_loopback_tog; /* 0x24c */
1010 u32 usb2_misc; /* 0x250 */ 1010 u32 usb2_misc; /* 0x250 */
1011 u32 usb2_misc_set; /* 0x254 */ 1011 u32 usb2_misc_set; /* 0x254 */
1012 u32 usb2_misc_clr; /* 0x258 */ 1012 u32 usb2_misc_clr; /* 0x258 */
1013 u32 usb2_misc_tog; /* 0x25c */ 1013 u32 usb2_misc_tog; /* 0x25c */
1014 u32 digprog; /* 0x260 */ 1014 u32 digprog; /* 0x260 */
1015 u32 reserved1[7]; 1015 u32 reserved1[7];
1016 u32 digprog_sololite; /* 0x280 */ 1016 u32 digprog_sololite; /* 0x280 */
1017 }; 1017 };
1018 1018
1019 #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8) 1019 #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
1020 #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n)) 1020 #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
1021 #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8)) 1021 #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
1022 #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n)) 1022 #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
1023 #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) 1023 #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
1024 #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n)) 1024 #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
1025 1025
1026 struct iomuxc_gpr_base_regs { 1026 struct iomuxc_gpr_base_regs {
1027 #if defined(CONFIG_MX6UL) 1027 #if defined(CONFIG_MX6UL)
1028 u32 gpr[15]; /* 0x000 */ 1028 u32 gpr[15]; /* 0x000 */
1029 #else 1029 #else
1030 u32 gpr[14]; /* 0x000 */ 1030 u32 gpr[14]; /* 0x000 */
1031 #endif 1031 #endif
1032 }; 1032 };
1033 1033
1034 struct iomuxc_base_regs { 1034 struct iomuxc_base_regs {
1035 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 1035 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
1036 u32 gpr[14]; /* 0x000 */ 1036 u32 gpr[14]; /* 0x000 */
1037 #endif 1037 #endif
1038 u32 obsrv[5]; /* 0x038 */ 1038 u32 obsrv[5]; /* 0x038 */
1039 u32 swmux_ctl[197]; /* 0x04c */ 1039 u32 swmux_ctl[197]; /* 0x04c */
1040 u32 swpad_ctl[250]; /* 0x360 */ 1040 u32 swpad_ctl[250]; /* 0x360 */
1041 u32 swgrp[26]; /* 0x748 */ 1041 u32 swgrp[26]; /* 0x748 */
1042 u32 daisy[104]; /* 0x7b0..94c */ 1042 u32 daisy[104]; /* 0x7b0..94c */
1043 }; 1043 };
1044 1044
1045 struct wdog_regs { 1045 struct wdog_regs {
1046 u16 wcr; /* Control */ 1046 u16 wcr; /* Control */
1047 u16 wsr; /* Service */ 1047 u16 wsr; /* Service */
1048 u16 wrsr; /* Reset Status */ 1048 u16 wrsr; /* Reset Status */
1049 u16 wicr; /* Interrupt Control */ 1049 u16 wicr; /* Interrupt Control */
1050 u16 wmcr; /* Miscellaneous Control */ 1050 u16 wmcr; /* Miscellaneous Control */
1051 }; 1051 };
1052 1052
1053 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) 1053 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
1054 #define PWMCR_DOZEEN (1 << 24) 1054 #define PWMCR_DOZEEN (1 << 24)
1055 #define PWMCR_WAITEN (1 << 23) 1055 #define PWMCR_WAITEN (1 << 23)
1056 #define PWMCR_DBGEN (1 << 22) 1056 #define PWMCR_DBGEN (1 << 22)
1057 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16) 1057 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
1058 #define PWMCR_CLKSRC_IPG (1 << 16) 1058 #define PWMCR_CLKSRC_IPG (1 << 16)
1059 #define PWMCR_EN (1 << 0) 1059 #define PWMCR_EN (1 << 0)
1060 1060
1061 struct pwm_regs { 1061 struct pwm_regs {
1062 u32 cr; 1062 u32 cr;
1063 u32 sr; 1063 u32 sr;
1064 u32 ir; 1064 u32 ir;
1065 u32 sar; 1065 u32 sar;
1066 u32 pr; 1066 u32 pr;
1067 u32 cnr; 1067 u32 cnr;
1068 }; 1068 };
1069 1069
1070 struct dbg_monitor_regs { 1070 struct dbg_monitor_regs {
1071 u32 ctrl[4]; /* Control */ 1071 u32 ctrl[4]; /* Control */
1072 u32 master_en[4]; /* Master enable */ 1072 u32 master_en[4]; /* Master enable */
1073 u32 irq[4]; /* IRQ */ 1073 u32 irq[4]; /* IRQ */
1074 u32 trap_addr_low[4]; /* Trap address low */ 1074 u32 trap_addr_low[4]; /* Trap address low */
1075 u32 trap_addr_high[4]; /* Trap address high */ 1075 u32 trap_addr_high[4]; /* Trap address high */
1076 u32 trap_id[4]; /* Trap ID */ 1076 u32 trap_id[4]; /* Trap ID */
1077 u32 snvs_addr[4]; /* SNVS address */ 1077 u32 snvs_addr[4]; /* SNVS address */
1078 u32 snvs_data[4]; /* SNVS data */ 1078 u32 snvs_data[4]; /* SNVS data */
1079 u32 snvs_info[4]; /* SNVS info */ 1079 u32 snvs_info[4]; /* SNVS info */
1080 u32 version[4]; /* Version */ 1080 u32 version[4]; /* Version */
1081 }; 1081 };
1082 1082
1083 /* 1083 /*
1084 * If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB 1084 * If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
1085 * If boot from the other mode, USB0_PWD will keep reset value 1085 * If boot from the other mode, USB0_PWD will keep reset value
1086 */ 1086 */
1087 #define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) 1087 #define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
1088 #define disconnect_from_pc(void) writel(0x0, OTG_BASE_ADDR + 0x140) 1088 #define disconnect_from_pc(void) writel(0x0, OTG_BASE_ADDR + 0x140)
1089 1089
1090 #endif /* __ASSEMBLER__*/ 1090 #endif /* __ASSEMBLER__*/
1091 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ 1091 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
1092 1092