MLK-12001 MMC:USDHC: Clear DLL_CTRL delay line settings at driver init

Clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. U-boot should re-init the USDHC not reply on the value set by boot from. On MX6DL, the ROM has set the default delay line(DLLCTRL) to 0x1000021, when eMMC works on DDR mode in kernel, it will possibly cause data CRC errors. Even u-boot always use eMMC in SDR mode, for safety sake, it is better to clear it too. Signed-off-by: Ye.Li <B37916@freescale.com>

MLK-12001 MMC:USDHC: Clear DLL_CTRL delay line settings at driver init
Clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. U-boot should re-init the USDHC not reply on the value set by boot from. On MX6DL, the ROM has set the default delay line(DLLCTRL) to 0x1000021, when eMMC works on DDR mode in kernel, it will possibly cause data CRC errors. Even u-boot always use eMMC in SDR mode, for safety sake, it is better to clear it too. Signed-off-by: Ye.Li <B37916@freescale.com>
Ye.Li · guoyin.chen
1 parent e4bbfbd519
Showing 1 changed file with 3 additions and 0 deletions Side-by-side Diff
drivers/mmc/fsl_esdhc.c
@@ -530,6 +530,9 @@
  
 	/* Put VEND_SPEC to default value */
 	esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
+
+	/* Disable DLL_CTRL delay line */
+	esdhc_write32(&regs->dllctrl, 0x0);
 #endif
  
 #ifndef ARCH_MXC
...	...	@@ -530,6 +530,9 @@
530	530
531	531	/* Put VEND_SPEC to default value */
532	532	esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
	533	+
	534	+ /* Disable DLL_CTRL delay line */
	535	+ esdhc_write32(&regs->dllctrl, 0x0);
533	536	#endif
534	537
535	538	#ifndef ARCH_MXC