Eric Lee / smarc-uboot

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Commit 05af9ac08052c92d011908726534e227db3143c4

Authored by Ye Li
1 parent 6df53e2727
Exists in smarc-8m-android-10.0.0_2.6.0 and in 1 other branch 8qm-imx_v2020.04_5.4.70_2.3.0

MLK-25003-1 iMX8MN: Add support for 11x11 UltraLite part number 

There are 3 part numbers for 11x11 i.MX8MNano with different core number
configuration: UltraLite Quad/Dual/Solo

Comparing with i.MX8MN Lite parts, they have MIPI DSI disabled. So
checking the MIPI DSI disable fuse to recognize these parts.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

Showing 4 changed files with 43 additions and 17 deletions Inline Diff

arch/arm/include/asm/arch-imx/cpu.h
Diff comments   View file @ 05af9ac
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * (C) Copyright 2014 Freescale Semiconductor, Inc. 3 * (C) Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2018-2020 NXP 4 * Copyright 2018-2020 NXP
5 */ 5 */
6 6
7 #define MXC_CPU_MX23 0x23 7 #define MXC_CPU_MX23 0x23
8 #define MXC_CPU_MX25 0x25 8 #define MXC_CPU_MX25 0x25
9 #define MXC_CPU_MX27 0x27 9 #define MXC_CPU_MX27 0x27
10 #define MXC_CPU_MX28 0x28 10 #define MXC_CPU_MX28 0x28
11 #define MXC_CPU_MX31 0x31 11 #define MXC_CPU_MX31 0x31
12 #define MXC_CPU_MX35 0x35 12 #define MXC_CPU_MX35 0x35
13 #define MXC_CPU_MX51 0x51 13 #define MXC_CPU_MX51 0x51
14 #define MXC_CPU_MX53 0x53 14 #define MXC_CPU_MX53 0x53
15 #define MXC_CPU_MX6SL 0x60 15 #define MXC_CPU_MX6SL 0x60
16 #define MXC_CPU_MX6DL 0x61 16 #define MXC_CPU_MX6DL 0x61
17 #define MXC_CPU_MX6SX 0x62 17 #define MXC_CPU_MX6SX 0x62
18 #define MXC_CPU_MX6Q 0x63 18 #define MXC_CPU_MX6Q 0x63
19 #define MXC_CPU_MX6UL 0x64 19 #define MXC_CPU_MX6UL 0x64
20 #define MXC_CPU_MX6ULL 0x65 20 #define MXC_CPU_MX6ULL 0x65
21 #define MXC_CPU_MX6ULZ 0x6B 21 #define MXC_CPU_MX6ULZ 0x6B
22 #define MXC_CPU_MX6SOLO 0x66 /* dummy */ 22 #define MXC_CPU_MX6SOLO 0x66 /* dummy */
23 #define MXC_CPU_MX6SLL 0x67 23 #define MXC_CPU_MX6SLL 0x67
24 #define MXC_CPU_MX6D 0x6A 24 #define MXC_CPU_MX6D 0x6A
25 #define MXC_CPU_MX6DP 0x68 25 #define MXC_CPU_MX6DP 0x68
26 #define MXC_CPU_MX6QP 0x69 26 #define MXC_CPU_MX6QP 0x69
27 #define MXC_CPU_MX7S 0x71 /* dummy ID */ 27 #define MXC_CPU_MX7S 0x71 /* dummy ID */
28 #define MXC_CPU_MX7D 0x72 28 #define MXC_CPU_MX7D 0x72
29 #define MXC_CPU_IMX8MQ 0x82 29 #define MXC_CPU_IMX8MQ 0x82
30 #define MXC_CPU_IMX8MD 0x83 /* dummy ID */ 30 #define MXC_CPU_IMX8MD 0x83 /* dummy ID */
31 #define MXC_CPU_IMX8MQL 0x84 /* dummy ID */ 31 #define MXC_CPU_IMX8MQL 0x84 /* dummy ID */
32 #define MXC_CPU_IMX8MM 0x85 /* dummy ID */ 32 #define MXC_CPU_IMX8MM 0x85 /* dummy ID */
33 #define MXC_CPU_IMX8MML 0x86 /* dummy ID */ 33 #define MXC_CPU_IMX8MML 0x86 /* dummy ID */
34 #define MXC_CPU_IMX8MMD 0x87 /* dummy ID */ 34 #define MXC_CPU_IMX8MMD 0x87 /* dummy ID */
35 #define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */ 35 #define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */
36 #define MXC_CPU_IMX8MMS 0x89 /* dummy ID */ 36 #define MXC_CPU_IMX8MMS 0x89 /* dummy ID */
37 #define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */ 37 #define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */
38 #define MXC_CPU_IMX8MN 0x8b /* dummy ID */ 38 #define MXC_CPU_IMX8MN 0x8b /* dummy ID */
39 #define MXC_CPU_IMX8MND 0x8c /* dummy ID */ 39 #define MXC_CPU_IMX8MND 0x8c /* dummy ID */
40 #define MXC_CPU_IMX8MNS 0x8d /* dummy ID */ 40 #define MXC_CPU_IMX8MNS 0x8d /* dummy ID */
41 #define MXC_CPU_IMX8MNL 0x8e /* dummy ID */ 41 #define MXC_CPU_IMX8MNL 0x8e /* dummy ID */
42 #define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */ 42 #define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */
43 #define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */ 43 #define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */
44 #define MXC_CPU_IMX8MP 0x182/* dummy ID */ 44 #define MXC_CPU_IMX8MNUQ 0x182 /* dummy ID */
45 #define MXC_CPU_IMX8MP6 0x184 /* dummy ID */ 45 #define MXC_CPU_IMX8MNUD 0x183 /* dummy ID */
46 #define MXC_CPU_IMX8MPL 0x186 /* dummy ID */ 46 #define MXC_CPU_IMX8MNUS 0x184 /* dummy ID */
47 #define MXC_CPU_IMX8MPD 0x187 /* dummy ID */ 47 #define MXC_CPU_IMX8MP 0x185/* dummy ID */
48 #define MXC_CPU_IMX8MP6 0x186 /* dummy ID */
49 #define MXC_CPU_IMX8MPL 0x187 /* dummy ID */
50 #define MXC_CPU_IMX8MPD 0x188 /* dummy ID */
48 #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ 51 #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
49 #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ 52 #define MXC_CPU_IMX8QM 0x91 /* dummy ID */
50 #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ 53 #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
51 #define MXC_CPU_IMX8DXL 0x9E /* dummy ID */ 54 #define MXC_CPU_IMX8DXL 0x9E /* dummy ID */
52 #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ 55 #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
53 #define MXC_CPU_VF610 0xF6 /* dummy ID */ 56 #define MXC_CPU_VF610 0xF6 /* dummy ID */
54 57
55 #define MXC_SOC_MX6 0x60 58 #define MXC_SOC_MX6 0x60
56 #define MXC_SOC_MX7 0x70 59 #define MXC_SOC_MX7 0x70
57 #define MXC_SOC_IMX8M 0x80 60 #define MXC_SOC_IMX8M 0x80
58 #define MXC_SOC_IMX8 0x90 /* dummy */ 61 #define MXC_SOC_IMX8 0x90 /* dummy */
59 #define MXC_SOC_MX7ULP 0xE0 /* dummy */ 62 #define MXC_SOC_MX7ULP 0xE0 /* dummy */
60 63
61 #define CHIP_REV_1_0 0x10 64 #define CHIP_REV_1_0 0x10
62 #define CHIP_REV_1_1 0x11 65 #define CHIP_REV_1_1 0x11
63 #define CHIP_REV_1_2 0x12 66 #define CHIP_REV_1_2 0x12
64 #define CHIP_REV_1_3 0x13 67 #define CHIP_REV_1_3 0x13
65 #define CHIP_REV_1_5 0x15 68 #define CHIP_REV_1_5 0x15
66 #define CHIP_REV_2_0 0x20 69 #define CHIP_REV_2_0 0x20
67 #define CHIP_REV_2_1 0x21 70 #define CHIP_REV_2_1 0x21
68 #define CHIP_REV_2_5 0x25 71 #define CHIP_REV_2_5 0x25
69 #define CHIP_REV_3_0 0x30 72 #define CHIP_REV_3_0 0x30
70 73
71 #define CHIP_REV_A 0x0 74 #define CHIP_REV_A 0x0
72 #define CHIP_REV_B 0x1 75 #define CHIP_REV_B 0x1
73 #define CHIP_REV_C 0x2 76 #define CHIP_REV_C 0x2
74 #define CHIP_REV_A1 0x11 77 #define CHIP_REV_A1 0x11
75 #define CHIP_REV_A2 0x12 78 #define CHIP_REV_A2 0x12
76 79
77 #define BOARD_REV_1_0 0x0 80 #define BOARD_REV_1_0 0x0
78 #define BOARD_REV_2_0 0x1 81 #define BOARD_REV_2_0 0x1
79 #define BOARD_VER_OFFSET 0x8 82 #define BOARD_VER_OFFSET 0x8
80 83
81 #define CS0_128 0 84 #define CS0_128 0
82 #define CS0_64M_CS1_64M 1 85 #define CS0_64M_CS1_64M 1
83 #define CS0_64M_CS1_32M_CS2_32M 2 86 #define CS0_64M_CS1_32M_CS2_32M 2
84 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 87 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
85 88
86 u32 get_imx_reset_cause(void); 89 u32 get_imx_reset_cause(void);
87 ulong get_systemPLLCLK(void); 90 ulong get_systemPLLCLK(void);
88 ulong get_FCLK(void); 91 ulong get_FCLK(void);
89 ulong get_HCLK(void); 92 ulong get_HCLK(void);
90 ulong get_BCLK(void); 93 ulong get_BCLK(void);
91 ulong get_PERCLK1(void); 94 ulong get_PERCLK1(void);
92 ulong get_PERCLK2(void); 95 ulong get_PERCLK2(void);
93 ulong get_PERCLK3(void); 96 ulong get_PERCLK3(void);
94 97
arch/arm/include/asm/mach-imx/sys_proto.h
Diff comments   View file @ 05af9ac
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * (C) Copyright 2009 3 * (C) Copyright 2009
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * Copyright 2018-2020 NXP 5 * Copyright 2018-2020 NXP
6 */ 6 */
7 7
8 #ifndef _SYS_PROTO_H_ 8 #ifndef _SYS_PROTO_H_
9 #define _SYS_PROTO_H_ 9 #define _SYS_PROTO_H_
10 10
11 #include <asm/io.h> 11 #include <asm/io.h>
12 #include <asm/mach-imx/regs-common.h> 12 #include <asm/mach-imx/regs-common.h>
13 #include <common.h> 13 #include <common.h>
14 #include "../arch-imx/cpu.h" 14 #include "../arch-imx/cpu.h"
15 15
16 #define soc_rev() (get_cpu_rev() & 0xFF) 16 #define soc_rev() (get_cpu_rev() & 0xFF)
17 #define is_soc_rev(rev) (soc_rev() == rev) 17 #define is_soc_rev(rev) (soc_rev() == rev)
18 18
19 /* returns MXC_CPU_ value */ 19 /* returns MXC_CPU_ value */
20 #define cpu_type(rev) (((rev) >> 12) & 0x1ff) 20 #define cpu_type(rev) (((rev) >> 12) & 0x1ff)
21 #define soc_type(rev) (((rev) >> 12) & 0xf0) 21 #define soc_type(rev) (((rev) >> 12) & 0xf0)
22 /* both macros return/take MXC_CPU_ constants */ 22 /* both macros return/take MXC_CPU_ constants */
23 #define get_cpu_type() (cpu_type(get_cpu_rev())) 23 #define get_cpu_type() (cpu_type(get_cpu_rev()))
24 #define get_soc_type() (soc_type(get_cpu_rev())) 24 #define get_soc_type() (soc_type(get_cpu_rev()))
25 #define is_cpu_type(cpu) (get_cpu_type() == cpu) 25 #define is_cpu_type(cpu) (get_cpu_type() == cpu)
26 #define is_soc_type(soc) (get_soc_type() == soc) 26 #define is_soc_type(soc) (get_soc_type() == soc)
27 27
28 #define is_mx6() (is_soc_type(MXC_SOC_MX6)) 28 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
29 #define is_mx7() (is_soc_type(MXC_SOC_MX7)) 29 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
30 #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) 30 #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
31 #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) 31 #define is_imx8() (is_soc_type(MXC_SOC_IMX8))
32 32
33 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) 33 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
34 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) 34 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
35 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL)) 35 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
36 #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL)) 36 #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
37 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX)) 37 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
38 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) 38 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
39 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) 39 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
40 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) 40 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
41 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ)) 41 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ))
42 #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ)) 42 #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
43 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) 43 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
44 44
45 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) 45 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
46 46
47 #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL)) 47 #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL))
48 #define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD)) 48 #define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD))
49 #define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL)) 49 #define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL))
50 #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) 50 #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM))
51 #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\ 51 #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\
52 is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \ 52 is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
53 is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL)) 53 is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL))
54 #define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML)) 54 #define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML))
55 #define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD)) 55 #define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD))
56 #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL)) 56 #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
57 #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS)) 57 #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
58 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) 58 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
59 #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \ 59 #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \
60 is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \ 60 is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \
61 is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL)) 61 is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \
62 is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ))
62 #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND)) 63 #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND))
63 #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS)) 64 #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS))
64 #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL)) 65 #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
65 #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL)) 66 #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
66 #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL)) 67 #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
68 #define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ))
69 #define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD))
70 #define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS))
67 #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \ 71 #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
68 is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6)) 72 is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6))
69 #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD)) 73 #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
70 #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL)) 74 #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
71 #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6)) 75 #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
72 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) 76 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
73 #define is_imx8dxl() (is_cpu_type(MXC_CPU_IMX8DXL)) 77 #define is_imx8dxl() (is_cpu_type(MXC_CPU_IMX8DXL))
74 78
75 /* gd->flags reserves high 16 bits for arch-specific flags */ 79 /* gd->flags reserves high 16 bits for arch-specific flags */
76 #define GD_FLG_ARCH_IMX_USB_BOOT 0x80000000 /* Only used for MX6/7, If set, the u-boot is booting from USB serial download */ 80 #define GD_FLG_ARCH_IMX_USB_BOOT 0x80000000 /* Only used for MX6/7, If set, the u-boot is booting from USB serial download */
77 81
78 #ifdef CONFIG_MX6 82 #ifdef CONFIG_MX6
79 #define IMX6_SRC_GPR10_BMODE BIT(28) 83 #define IMX6_SRC_GPR10_BMODE BIT(28)
80 84
81 #define IMX6_BMODE_MASK GENMASK(7, 0) 85 #define IMX6_BMODE_MASK GENMASK(7, 0)
82 #define IMX6_BMODE_SHIFT 4 86 #define IMX6_BMODE_SHIFT 4
83 #define IMX6_BMODE_EMI_MASK BIT(3) 87 #define IMX6_BMODE_EMI_MASK BIT(3)
84 #define IMX6_BMODE_EMI_SHIFT 3 88 #define IMX6_BMODE_EMI_SHIFT 3
85 #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24) 89 #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
86 #define IMX6_BMODE_SERIAL_ROM_SHIFT 24 90 #define IMX6_BMODE_SERIAL_ROM_SHIFT 24
87 91
88 enum imx6_bmode_serial_rom { 92 enum imx6_bmode_serial_rom {
89 IMX6_BMODE_ECSPI1, 93 IMX6_BMODE_ECSPI1,
90 IMX6_BMODE_ECSPI2, 94 IMX6_BMODE_ECSPI2,
91 IMX6_BMODE_ECSPI3, 95 IMX6_BMODE_ECSPI3,
92 IMX6_BMODE_ECSPI4, 96 IMX6_BMODE_ECSPI4,
93 IMX6_BMODE_ECSPI5, 97 IMX6_BMODE_ECSPI5,
94 IMX6_BMODE_I2C1, 98 IMX6_BMODE_I2C1,
95 IMX6_BMODE_I2C2, 99 IMX6_BMODE_I2C2,
96 IMX6_BMODE_I2C3, 100 IMX6_BMODE_I2C3,
97 }; 101 };
98 102
99 enum imx6_bmode_emi { 103 enum imx6_bmode_emi {
100 IMX6_BMODE_NOR, 104 IMX6_BMODE_NOR,
101 IMX6_BMODE_ONENAND, 105 IMX6_BMODE_ONENAND,
102 }; 106 };
103 107
104 enum imx6_bmode { 108 enum imx6_bmode {
105 IMX6_BMODE_EMI, 109 IMX6_BMODE_EMI,
106 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) 110 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
107 IMX6_BMODE_QSPI, 111 IMX6_BMODE_QSPI,
108 IMX6_BMODE_RESERVED, 112 IMX6_BMODE_RESERVED,
109 #else 113 #else
110 IMX6_BMODE_RESERVED, 114 IMX6_BMODE_RESERVED,
111 IMX6_BMODE_SATA, 115 IMX6_BMODE_SATA,
112 #endif 116 #endif
113 IMX6_BMODE_SERIAL_ROM, 117 IMX6_BMODE_SERIAL_ROM,
114 IMX6_BMODE_SD, 118 IMX6_BMODE_SD,
115 IMX6_BMODE_ESD, 119 IMX6_BMODE_ESD,
116 IMX6_BMODE_MMC, 120 IMX6_BMODE_MMC,
117 IMX6_BMODE_EMMC, 121 IMX6_BMODE_EMMC,
118 IMX6_BMODE_NAND_MIN, 122 IMX6_BMODE_NAND_MIN,
119 IMX6_BMODE_NAND_MAX = 0xf, 123 IMX6_BMODE_NAND_MAX = 0xf,
120 }; 124 };
121 125
122 u32 imx6_src_get_boot_mode(void); 126 u32 imx6_src_get_boot_mode(void);
123 void gpr_init(void); 127 void gpr_init(void);
124 128
125 #endif /* CONFIG_MX6 */ 129 #endif /* CONFIG_MX6 */
126 130
127 /* address translation table */ 131 /* address translation table */
128 struct rproc_att { 132 struct rproc_att {
129 u32 da; /* device address (From Cortex M4 view) */ 133 u32 da; /* device address (From Cortex M4 view) */
130 u32 sa; /* system bus address */ 134 u32 sa; /* system bus address */
131 u32 size; /* size of reg range */ 135 u32 size; /* size of reg range */
132 }; 136 };
133 137
134 #ifdef CONFIG_IMX8M 138 #ifdef CONFIG_IMX8M
135 struct rom_api { 139 struct rom_api {
136 u16 ver; 140 u16 ver;
137 u16 tag; 141 u16 tag;
138 u32 reserved1; 142 u32 reserved1;
139 u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor); 143 u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor);
140 u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor); 144 u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor);
141 }; 145 };
142 146
143 enum boot_dev_type_e { 147 enum boot_dev_type_e {
144 BT_DEV_TYPE_SD = 1, 148 BT_DEV_TYPE_SD = 1,
145 BT_DEV_TYPE_MMC = 2, 149 BT_DEV_TYPE_MMC = 2,
146 BT_DEV_TYPE_NAND = 3, 150 BT_DEV_TYPE_NAND = 3,
147 BT_DEV_TYPE_FLEXSPINOR = 4, 151 BT_DEV_TYPE_FLEXSPINOR = 4,
148 152
149 BT_DEV_TYPE_USB = 0xE, 153 BT_DEV_TYPE_USB = 0xE,
150 BT_DEV_TYPE_MEM_DEV = 0xF, 154 BT_DEV_TYPE_MEM_DEV = 0xF,
151 155
152 BT_DEV_TYPE_INVALID = 0xFF 156 BT_DEV_TYPE_INVALID = 0xFF
153 }; 157 };
154 158
155 #define QUERY_ROM_VER 1 159 #define QUERY_ROM_VER 1
156 #define QUERY_BT_DEV 2 160 #define QUERY_BT_DEV 2
157 #define QUERY_PAGE_SZ 3 161 #define QUERY_PAGE_SZ 3
158 #define QUERY_IVT_OFF 4 162 #define QUERY_IVT_OFF 4
159 #define QUERY_BT_STAGE 5 163 #define QUERY_BT_STAGE 5
160 #define QUERY_IMG_OFF 6 164 #define QUERY_IMG_OFF 6
161 165
162 #define ROM_API_OKAY 0xF0 166 #define ROM_API_OKAY 0xF0
163 167
164 extern struct rom_api *g_rom_api; 168 extern struct rom_api *g_rom_api;
165 #endif 169 #endif
166 170
167 u32 get_nr_cpus(void); 171 u32 get_nr_cpus(void);
168 u32 get_cpu_rev(void); 172 u32 get_cpu_rev(void);
169 u32 get_cpu_speed_grade_hz(void); 173 u32 get_cpu_speed_grade_hz(void);
170 u32 get_cpu_temp_grade(int *minc, int *maxc); 174 u32 get_cpu_temp_grade(int *minc, int *maxc);
171 const char *get_imx_type(u32 imxtype); 175 const char *get_imx_type(u32 imxtype);
172 u32 imx_ddr_size(void); 176 u32 imx_ddr_size(void);
173 void sdelay(unsigned long); 177 void sdelay(unsigned long);
174 void set_chipselect_size(int const); 178 void set_chipselect_size(int const);
175 179
176 void init_aips(void); 180 void init_aips(void);
177 void init_src(void); 181 void init_src(void);
178 void init_snvs(void); 182 void init_snvs(void);
179 void imx_wdog_disable_powerdown(void); 183 void imx_wdog_disable_powerdown(void);
180 184
181 int arch_auxiliary_core_check_up(u32 core_id); 185 int arch_auxiliary_core_check_up(u32 core_id);
182 186
183 int board_mmc_get_env_dev(int devno); 187 int board_mmc_get_env_dev(int devno);
184 188
185 int nxp_board_rev(void); 189 int nxp_board_rev(void);
186 char nxp_board_rev_string(void); 190 char nxp_board_rev_string(void);
187 191
188 /* 192 /*
189 * Initializes on-chip ethernet controllers. 193 * Initializes on-chip ethernet controllers.
190 * to override, implement board_eth_init() 194 * to override, implement board_eth_init()
191 */ 195 */
192 int fecmxc_initialize(bd_t *bis); 196 int fecmxc_initialize(bd_t *bis);
193 u32 get_ahb_clk(void); 197 u32 get_ahb_clk(void);
194 u32 get_periph_clk(void); 198 u32 get_periph_clk(void);
195 199
196 void lcdif_power_down(void); 200 void lcdif_power_down(void);
197 201
198 int mxs_reset_block(struct mxs_register_32 *reg); 202 int mxs_reset_block(struct mxs_register_32 *reg);
199 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); 203 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
200 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); 204 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
201 205
202 void board_late_mmc_env_init(void); 206 void board_late_mmc_env_init(void);
203 207
204 void vadc_power_up(void); 208 void vadc_power_up(void);
205 void vadc_power_down(void); 209 void vadc_power_down(void);
206 210
207 void pcie_power_up(void); 211 void pcie_power_up(void);
208 void pcie_power_off(void); 212 void pcie_power_off(void);
209 213
210 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data); 214 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data);
211 int arch_auxiliary_core_check_up(u32 core_id); 215 int arch_auxiliary_core_check_up(u32 core_id);
212 216
213 unsigned long call_imx_sip(unsigned long id, unsigned long reg0, 217 unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
214 unsigned long reg1, unsigned long reg2, 218 unsigned long reg1, unsigned long reg2,
215 unsigned long reg3); 219 unsigned long reg3);
216 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, 220 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
217 unsigned long *reg1, unsigned long reg2, 221 unsigned long *reg1, unsigned long reg2,
218 unsigned long reg3); 222 unsigned long reg3);
219 223
220 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 224 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
221 225
222 int add_res_mem_dt_node(void *fdt, const char *name, phys_addr_t pa, 226 int add_res_mem_dt_node(void *fdt, const char *name, phys_addr_t pa,
223 size_t size); 227 size_t size);
224 int add_dt_path_subnode(void *fdt, const char *path, const char *subnode); 228 int add_dt_path_subnode(void *fdt, const char *path, const char *subnode);
225 void configure_tzc380(void); 229 void configure_tzc380(void);
226 #endif 230 #endif
227 231
arch/arm/mach-imx/cpu.c
Diff comments   View file @ 05af9ac
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * (C) Copyright 2007 3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix 4 * Sascha Hauer, Pengutronix
5 * 5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc. 6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */ 7 */
8 8
9 #include <bootm.h> 9 #include <bootm.h>
10 #include <common.h> 10 #include <common.h>
11 #include <netdev.h> 11 #include <netdev.h>
12 #include <linux/errno.h> 12 #include <linux/errno.h>
13 #include <asm/io.h> 13 #include <asm/io.h>
14 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h> 15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h> 16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/crm_regs.h> 17 #include <asm/arch/crm_regs.h>
18 #include <asm/mach-imx/boot_mode.h> 18 #include <asm/mach-imx/boot_mode.h>
19 #include <imx_thermal.h> 19 #include <imx_thermal.h>
20 #include <ipu_pixfmt.h> 20 #include <ipu_pixfmt.h>
21 #include <thermal.h> 21 #include <thermal.h>
22 #include <sata.h> 22 #include <sata.h>
23 #include <dm/device-internal.h> 23 #include <dm/device-internal.h>
24 #include <dm/uclass-internal.h> 24 #include <dm/uclass-internal.h>
25 25
26 #ifdef CONFIG_VIDEO_GIS 26 #ifdef CONFIG_VIDEO_GIS
27 #include <gis.h> 27 #include <gis.h>
28 #endif 28 #endif
29 29
30 #ifdef CONFIG_FSL_ESDHC_IMX 30 #ifdef CONFIG_FSL_ESDHC_IMX
31 #include <fsl_esdhc_imx.h> 31 #include <fsl_esdhc_imx.h>
32 #endif 32 #endif
33 33
34 static u32 reset_cause = -1; 34 static u32 reset_cause = -1;
35 35
36 u32 get_imx_reset_cause(void) 36 u32 get_imx_reset_cause(void)
37 { 37 {
38 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 38 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
39 39
40 if (reset_cause == -1) { 40 if (reset_cause == -1) {
41 reset_cause = readl(&src_regs->srsr); 41 reset_cause = readl(&src_regs->srsr);
42 /* preserve the value for U-Boot proper */ 42 /* preserve the value for U-Boot proper */
43 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ANDROID_BOOT_IMAGE) 43 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ANDROID_BOOT_IMAGE)
44 /* We will read the ssrs states later for android so we don't 44 /* We will read the ssrs states later for android so we don't
45 * clear the states here. 45 * clear the states here.
46 */ 46 */
47 writel(reset_cause, &src_regs->srsr); 47 writel(reset_cause, &src_regs->srsr);
48 #endif 48 #endif
49 } 49 }
50 50
51 return reset_cause; 51 return reset_cause;
52 } 52 }
53 53
54 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) 54 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
55 static char *get_reset_cause(void) 55 static char *get_reset_cause(void)
56 { 56 {
57 switch (get_imx_reset_cause()) { 57 switch (get_imx_reset_cause()) {
58 case 0x00001: 58 case 0x00001:
59 case 0x00011: 59 case 0x00011:
60 return "POR"; 60 return "POR";
61 case 0x00004: 61 case 0x00004:
62 return "CSU"; 62 return "CSU";
63 case 0x00008: 63 case 0x00008:
64 return "IPP USER"; 64 return "IPP USER";
65 case 0x00010: 65 case 0x00010:
66 #ifdef CONFIG_MX7 66 #ifdef CONFIG_MX7
67 return "WDOG1"; 67 return "WDOG1";
68 #else 68 #else
69 return "WDOG"; 69 return "WDOG";
70 #endif 70 #endif
71 case 0x00020: 71 case 0x00020:
72 return "JTAG HIGH-Z"; 72 return "JTAG HIGH-Z";
73 case 0x00040: 73 case 0x00040:
74 return "JTAG SW"; 74 return "JTAG SW";
75 case 0x00080: 75 case 0x00080:
76 return "WDOG3"; 76 return "WDOG3";
77 #ifdef CONFIG_MX7 77 #ifdef CONFIG_MX7
78 case 0x00100: 78 case 0x00100:
79 return "WDOG4"; 79 return "WDOG4";
80 case 0x00200: 80 case 0x00200:
81 return "TEMPSENSE"; 81 return "TEMPSENSE";
82 #elif defined(CONFIG_IMX8M) 82 #elif defined(CONFIG_IMX8M)
83 case 0x00100: 83 case 0x00100:
84 return "WDOG2"; 84 return "WDOG2";
85 case 0x00200: 85 case 0x00200:
86 return "TEMPSENSE"; 86 return "TEMPSENSE";
87 #else 87 #else
88 case 0x00100: 88 case 0x00100:
89 return "TEMPSENSE"; 89 return "TEMPSENSE";
90 case 0x10000: 90 case 0x10000:
91 return "WARM BOOT"; 91 return "WARM BOOT";
92 #endif 92 #endif
93 default: 93 default:
94 return "unknown reset"; 94 return "unknown reset";
95 } 95 }
96 } 96 }
97 97
98 #ifdef CONFIG_ANDROID_BOOT_IMAGE 98 #ifdef CONFIG_ANDROID_BOOT_IMAGE
99 void get_reboot_reason(char *ret) 99 void get_reboot_reason(char *ret)
100 { 100 {
101 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 101 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
102 102
103 strcpy(ret, (const char *)get_reset_cause()); 103 strcpy(ret, (const char *)get_reset_cause());
104 /* clear the srsr here, its state has been recorded in reset_cause */ 104 /* clear the srsr here, its state has been recorded in reset_cause */
105 writel(reset_cause, &src_regs->srsr); 105 writel(reset_cause, &src_regs->srsr);
106 } 106 }
107 #endif 107 #endif
108 #endif 108 #endif
109 109
110 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) 110 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
111 111
112 const char *get_imx_type(u32 imxtype) 112 const char *get_imx_type(u32 imxtype)
113 { 113 {
114 switch (imxtype) { 114 switch (imxtype) {
115 case MXC_CPU_IMX8MP: 115 case MXC_CPU_IMX8MP:
116 return "8MP[8]"; /* Quad-core version of the imx8mp */ 116 return "8MP[8]"; /* Quad-core version of the imx8mp */
117 case MXC_CPU_IMX8MPD: 117 case MXC_CPU_IMX8MPD:
118 return "8MP Dual[3]"; /* Dual-core version of the imx8mp */ 118 return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
119 case MXC_CPU_IMX8MPL: 119 case MXC_CPU_IMX8MPL:
120 return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */ 120 return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
121 case MXC_CPU_IMX8MP6: 121 case MXC_CPU_IMX8MP6:
122 return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */ 122 return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
123 case MXC_CPU_IMX8MN: 123 case MXC_CPU_IMX8MN:
124 return "8MNano Quad";/* Quad-core version of the imx8mn */ 124 return "8MNano Quad";/* Quad-core version of the imx8mn */
125 case MXC_CPU_IMX8MND: 125 case MXC_CPU_IMX8MND:
126 return "8MNano Dual";/* Dual-core version of the imx8mn */ 126 return "8MNano Dual";/* Dual-core version of the imx8mn */
127 case MXC_CPU_IMX8MNS: 127 case MXC_CPU_IMX8MNS:
128 return "8MNano Solo";/* Single-core version of the imx8mn */ 128 return "8MNano Solo";/* Single-core version of the imx8mn */
129 case MXC_CPU_IMX8MNL: 129 case MXC_CPU_IMX8MNL:
130 return "8MNano QuadLite";/* Quad-core Lite version of the imx8mn */ 130 return "8MNano QuadLite";/* Quad-core Lite version of the imx8mn */
131 case MXC_CPU_IMX8MNDL: 131 case MXC_CPU_IMX8MNDL:
132 return "8MNano DualLite";/* Dual-core Lite version of the imx8mn */ 132 return "8MNano DualLite";/* Dual-core Lite version of the imx8mn */
133 case MXC_CPU_IMX8MNSL: 133 case MXC_CPU_IMX8MNSL:
134 return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */ 134 return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
135 case MXC_CPU_IMX8MNUQ:
136 return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
137 case MXC_CPU_IMX8MNUD:
138 return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
139 case MXC_CPU_IMX8MNUS:
140 return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
135 case MXC_CPU_IMX8MM: 141 case MXC_CPU_IMX8MM:
136 return "8MMQ"; /* Quad-core version of the imx8mm */ 142 return "8MMQ"; /* Quad-core version of the imx8mm */
137 case MXC_CPU_IMX8MML: 143 case MXC_CPU_IMX8MML:
138 return "8MMQL"; /* Quad-core Lite version of the imx8mm */ 144 return "8MMQL"; /* Quad-core Lite version of the imx8mm */
139 case MXC_CPU_IMX8MMD: 145 case MXC_CPU_IMX8MMD:
140 return "8MMD"; /* Dual-core version of the imx8mm */ 146 return "8MMD"; /* Dual-core version of the imx8mm */
141 case MXC_CPU_IMX8MMDL: 147 case MXC_CPU_IMX8MMDL:
142 return "8MMDL"; /* Dual-core Lite version of the imx8mm */ 148 return "8MMDL"; /* Dual-core Lite version of the imx8mm */
143 case MXC_CPU_IMX8MMS: 149 case MXC_CPU_IMX8MMS:
144 return "8MMS"; /* Single-core version of the imx8mm */ 150 return "8MMS"; /* Single-core version of the imx8mm */
145 case MXC_CPU_IMX8MMSL: 151 case MXC_CPU_IMX8MMSL:
146 return "8MMSL"; /* Single-core Lite version of the imx8mm */ 152 return "8MMSL"; /* Single-core Lite version of the imx8mm */
147 case MXC_CPU_IMX8MQ: 153 case MXC_CPU_IMX8MQ:
148 return "8MQ"; /* Quad-core version of the imx8mq */ 154 return "8MQ"; /* Quad-core version of the imx8mq */
149 case MXC_CPU_IMX8MQL: 155 case MXC_CPU_IMX8MQL:
150 return "8MQLite"; /* Quad-core Lite version of the imx8mq */ 156 return "8MQLite"; /* Quad-core Lite version of the imx8mq */
151 case MXC_CPU_IMX8MD: 157 case MXC_CPU_IMX8MD:
152 return "8MD"; /* Dual-core version of the imx8mq */ 158 return "8MD"; /* Dual-core version of the imx8mq */
153 case MXC_CPU_MX7S: 159 case MXC_CPU_MX7S:
154 return "7S"; /* Single-core version of the mx7 */ 160 return "7S"; /* Single-core version of the mx7 */
155 case MXC_CPU_MX7D: 161 case MXC_CPU_MX7D:
156 return "7D"; /* Dual-core version of the mx7 */ 162 return "7D"; /* Dual-core version of the mx7 */
157 case MXC_CPU_MX6QP: 163 case MXC_CPU_MX6QP:
158 return "6QP"; /* Quad-Plus version of the mx6 */ 164 return "6QP"; /* Quad-Plus version of the mx6 */
159 case MXC_CPU_MX6DP: 165 case MXC_CPU_MX6DP:
160 return "6DP"; /* Dual-Plus version of the mx6 */ 166 return "6DP"; /* Dual-Plus version of the mx6 */
161 case MXC_CPU_MX6Q: 167 case MXC_CPU_MX6Q:
162 return "6Q"; /* Quad-core version of the mx6 */ 168 return "6Q"; /* Quad-core version of the mx6 */
163 case MXC_CPU_MX6D: 169 case MXC_CPU_MX6D:
164 return "6D"; /* Dual-core version of the mx6 */ 170 return "6D"; /* Dual-core version of the mx6 */
165 case MXC_CPU_MX6DL: 171 case MXC_CPU_MX6DL:
166 return "6DL"; /* Dual Lite version of the mx6 */ 172 return "6DL"; /* Dual Lite version of the mx6 */
167 case MXC_CPU_MX6SOLO: 173 case MXC_CPU_MX6SOLO:
168 return "6SOLO"; /* Solo version of the mx6 */ 174 return "6SOLO"; /* Solo version of the mx6 */
169 case MXC_CPU_MX6SL: 175 case MXC_CPU_MX6SL:
170 return "6SL"; /* Solo-Lite version of the mx6 */ 176 return "6SL"; /* Solo-Lite version of the mx6 */
171 case MXC_CPU_MX6SLL: 177 case MXC_CPU_MX6SLL:
172 return "6SLL"; /* SLL version of the mx6 */ 178 return "6SLL"; /* SLL version of the mx6 */
173 case MXC_CPU_MX6SX: 179 case MXC_CPU_MX6SX:
174 return "6SX"; /* SoloX version of the mx6 */ 180 return "6SX"; /* SoloX version of the mx6 */
175 case MXC_CPU_MX6UL: 181 case MXC_CPU_MX6UL:
176 return "6UL"; /* Ultra-Lite version of the mx6 */ 182 return "6UL"; /* Ultra-Lite version of the mx6 */
177 case MXC_CPU_MX6ULL: 183 case MXC_CPU_MX6ULL:
178 return "6ULL"; /* ULL version of the mx6 */ 184 return "6ULL"; /* ULL version of the mx6 */
179 case MXC_CPU_MX6ULZ: 185 case MXC_CPU_MX6ULZ:
180 return "6ULZ"; /* ULZ version of the mx6 */ 186 return "6ULZ"; /* ULZ version of the mx6 */
181 case MXC_CPU_MX51: 187 case MXC_CPU_MX51:
182 return "51"; 188 return "51";
183 case MXC_CPU_MX53: 189 case MXC_CPU_MX53:
184 return "53"; 190 return "53";
185 default: 191 default:
186 return "??"; 192 return "??";
187 } 193 }
188 } 194 }
189 195
190 int print_cpuinfo(void) 196 int print_cpuinfo(void)
191 { 197 {
192 u32 cpurev; 198 u32 cpurev;
193 __maybe_unused u32 max_freq; 199 __maybe_unused u32 max_freq;
194 #if defined(CONFIG_DBG_MONITOR) 200 #if defined(CONFIG_DBG_MONITOR)
195 struct dbg_monitor_regs *dbg = 201 struct dbg_monitor_regs *dbg =
196 (struct dbg_monitor_regs *)DEBUG_MONITOR_BASE_ADDR; 202 (struct dbg_monitor_regs *)DEBUG_MONITOR_BASE_ADDR;
197 #endif 203 #endif
198 204
199 cpurev = get_cpu_rev(); 205 cpurev = get_cpu_rev();
200 206
201 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_NXP_TMU) 207 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_NXP_TMU)
202 struct udevice *thermal_dev; 208 struct udevice *thermal_dev;
203 int cpu_tmp, minc, maxc, ret; 209 int cpu_tmp, minc, maxc, ret;
204 210
205 printf("CPU: i.MX%s rev%d.%d", 211 printf("CPU: i.MX%s rev%d.%d",
206 get_imx_type((cpurev & 0x1FF000) >> 12), 212 get_imx_type((cpurev & 0x1FF000) >> 12),
207 (cpurev & 0x000F0) >> 4, 213 (cpurev & 0x000F0) >> 4,
208 (cpurev & 0x0000F) >> 0); 214 (cpurev & 0x0000F) >> 0);
209 max_freq = get_cpu_speed_grade_hz(); 215 max_freq = get_cpu_speed_grade_hz();
210 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) { 216 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
211 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); 217 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
212 } else { 218 } else {
213 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000, 219 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
214 mxc_get_clock(MXC_ARM_CLK) / 1000000); 220 mxc_get_clock(MXC_ARM_CLK) / 1000000);
215 } 221 }
216 #else 222 #else
217 printf("CPU: i.MX%s rev%d.%d at %d MHz\n", 223 printf("CPU: i.MX%s rev%d.%d at %d MHz\n",
218 get_imx_type((cpurev & 0x1FF000) >> 12), 224 get_imx_type((cpurev & 0x1FF000) >> 12),
219 (cpurev & 0x000F0) >> 4, 225 (cpurev & 0x000F0) >> 4,
220 (cpurev & 0x0000F) >> 0, 226 (cpurev & 0x0000F) >> 0,
221 mxc_get_clock(MXC_ARM_CLK) / 1000000); 227 mxc_get_clock(MXC_ARM_CLK) / 1000000);
222 #endif 228 #endif
223 229
224 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_NXP_TMU) 230 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_NXP_TMU)
225 puts("CPU: "); 231 puts("CPU: ");
226 switch (get_cpu_temp_grade(&minc, &maxc)) { 232 switch (get_cpu_temp_grade(&minc, &maxc)) {
227 case TEMP_AUTOMOTIVE: 233 case TEMP_AUTOMOTIVE:
228 puts("Automotive temperature grade "); 234 puts("Automotive temperature grade ");
229 break; 235 break;
230 case TEMP_INDUSTRIAL: 236 case TEMP_INDUSTRIAL:
231 puts("Industrial temperature grade "); 237 puts("Industrial temperature grade ");
232 break; 238 break;
233 case TEMP_EXTCOMMERCIAL: 239 case TEMP_EXTCOMMERCIAL:
234 puts("Extended Commercial temperature grade "); 240 puts("Extended Commercial temperature grade ");
235 break; 241 break;
236 default: 242 default:
237 puts("Commercial temperature grade "); 243 puts("Commercial temperature grade ");
238 break; 244 break;
239 } 245 }
240 printf("(%dC to %dC)", minc, maxc); 246 printf("(%dC to %dC)", minc, maxc);
241 #if defined(CONFIG_NXP_TMU) 247 #if defined(CONFIG_NXP_TMU)
242 ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal", &thermal_dev); 248 ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal", &thermal_dev);
243 #else 249 #else
244 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev); 250 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
245 #endif 251 #endif
246 if (!ret) { 252 if (!ret) {
247 ret = thermal_get_temp(thermal_dev, &cpu_tmp); 253 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
248 254
249 if (!ret) 255 if (!ret)
250 printf(" at %dC\n", cpu_tmp); 256 printf(" at %dC\n", cpu_tmp);
251 else 257 else
252 debug(" - invalid sensor data\n"); 258 debug(" - invalid sensor data\n");
253 } else { 259 } else {
254 debug(" - invalid sensor device\n"); 260 debug(" - invalid sensor device\n");
255 } 261 }
256 #endif 262 #endif
257 263
258 #if defined(CONFIG_DBG_MONITOR) 264 #if defined(CONFIG_DBG_MONITOR)
259 if (readl(&dbg->snvs_addr)) 265 if (readl(&dbg->snvs_addr))
260 printf("DBG snvs regs addr 0x%x, data 0x%x, info 0x%x\n", 266 printf("DBG snvs regs addr 0x%x, data 0x%x, info 0x%x\n",
261 readl(&dbg->snvs_addr), 267 readl(&dbg->snvs_addr),
262 readl(&dbg->snvs_data), 268 readl(&dbg->snvs_data),
263 readl(&dbg->snvs_info)); 269 readl(&dbg->snvs_info));
264 #endif 270 #endif
265 271
266 printf("Reset cause: %s\n", get_reset_cause()); 272 printf("Reset cause: %s\n", get_reset_cause());
267 return 0; 273 return 0;
268 } 274 }
269 #endif 275 #endif
270 276
271 int cpu_eth_init(bd_t *bis) 277 int cpu_eth_init(bd_t *bis)
272 { 278 {
273 int rc = -ENODEV; 279 int rc = -ENODEV;
274 280
275 #if defined(CONFIG_FEC_MXC) 281 #if defined(CONFIG_FEC_MXC)
276 rc = fecmxc_initialize(bis); 282 rc = fecmxc_initialize(bis);
277 #endif 283 #endif
278 284
279 return rc; 285 return rc;
280 } 286 }
281 287
282 #ifdef CONFIG_FSL_ESDHC_IMX 288 #ifdef CONFIG_FSL_ESDHC_IMX
283 /* 289 /*
284 * Initializes on-chip MMC controllers. 290 * Initializes on-chip MMC controllers.
285 * to override, implement board_mmc_init() 291 * to override, implement board_mmc_init()
286 */ 292 */
287 int cpu_mmc_init(bd_t *bis) 293 int cpu_mmc_init(bd_t *bis)
288 { 294 {
289 return fsl_esdhc_mmc_init(bis); 295 return fsl_esdhc_mmc_init(bis);
290 } 296 }
291 #endif 297 #endif
292 298
293 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) 299 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
294 u32 get_ahb_clk(void) 300 u32 get_ahb_clk(void)
295 { 301 {
296 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 302 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
297 u32 reg, ahb_podf; 303 u32 reg, ahb_podf;
298 304
299 reg = __raw_readl(&imx_ccm->cbcdr); 305 reg = __raw_readl(&imx_ccm->cbcdr);
300 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK; 306 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
301 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; 307 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
302 308
303 return get_periph_clk() / (ahb_podf + 1); 309 return get_periph_clk() / (ahb_podf + 1);
304 } 310 }
305 #endif 311 #endif
306 312
307 void arch_preboot_os(void) 313 void arch_preboot_os(void)
308 { 314 {
309 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI) 315 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
310 imx_pcie_remove(); 316 imx_pcie_remove();
311 #endif 317 #endif
312 318
313 #if defined(CONFIG_IMX_AHCI) 319 #if defined(CONFIG_IMX_AHCI)
314 struct udevice *dev; 320 struct udevice *dev;
315 int rc; 321 int rc;
316 322
317 rc = uclass_find_device(UCLASS_AHCI, 0, &dev); 323 rc = uclass_find_device(UCLASS_AHCI, 0, &dev);
318 if (!rc && dev) { 324 if (!rc && dev) {
319 rc = device_remove(dev, DM_REMOVE_NORMAL); 325 rc = device_remove(dev, DM_REMOVE_NORMAL);
320 if (rc) 326 if (rc)
321 printf("Cannot remove SATA device '%s' (err=%d)\n", 327 printf("Cannot remove SATA device '%s' (err=%d)\n",
322 dev->name, rc); 328 dev->name, rc);
323 } 329 }
324 #endif 330 #endif
325 331
326 #if defined(CONFIG_SATA) 332 #if defined(CONFIG_SATA)
327 if (!is_mx6sdl()) { 333 if (!is_mx6sdl()) {
328 sata_remove(0); 334 sata_remove(0);
329 #if defined(CONFIG_MX6) 335 #if defined(CONFIG_MX6)
330 disable_sata_clock(); 336 disable_sata_clock();
331 #endif 337 #endif
332 } 338 }
333 #endif 339 #endif
334 #if defined(CONFIG_LDO_BYPASS_CHECK) 340 #if defined(CONFIG_LDO_BYPASS_CHECK)
335 ldo_mode_set(check_ldo_bypass()); 341 ldo_mode_set(check_ldo_bypass());
336 #endif 342 #endif
337 #if defined(CONFIG_VIDEO_IPUV3) 343 #if defined(CONFIG_VIDEO_IPUV3)
338 /* disable video before launching O/S */ 344 /* disable video before launching O/S */
339 ipuv3_fb_shutdown(); 345 ipuv3_fb_shutdown();
340 #endif 346 #endif
341 #ifdef CONFIG_VIDEO_GIS 347 #ifdef CONFIG_VIDEO_GIS
342 /* Entry for GIS */ 348 /* Entry for GIS */
343 mxc_disable_gis(); 349 mxc_disable_gis();
344 #endif 350 #endif
345 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO) 351 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
346 lcdif_power_down(); 352 lcdif_power_down();
347 #endif 353 #endif
348 } 354 }
349 355
350 #ifndef CONFIG_IMX8M 356 #ifndef CONFIG_IMX8M
351 void set_chipselect_size(int const cs_size) 357 void set_chipselect_size(int const cs_size)
352 { 358 {
353 unsigned int reg; 359 unsigned int reg;
354 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 360 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
355 reg = readl(&iomuxc_regs->gpr[1]); 361 reg = readl(&iomuxc_regs->gpr[1]);
356 362
357 switch (cs_size) { 363 switch (cs_size) {
358 case CS0_128: 364 case CS0_128:
359 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */ 365 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
360 reg |= 0x5; 366 reg |= 0x5;
361 break; 367 break;
362 case CS0_64M_CS1_64M: 368 case CS0_64M_CS1_64M:
363 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */ 369 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
364 reg |= 0x1B; 370 reg |= 0x1B;
365 break; 371 break;
366 case CS0_64M_CS1_32M_CS2_32M: 372 case CS0_64M_CS1_32M_CS2_32M:
367 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */ 373 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
368 reg |= 0x4B; 374 reg |= 0x4B;
369 break; 375 break;
370 case CS0_32M_CS1_32M_CS2_32M_CS3_32M: 376 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
371 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */ 377 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
372 reg |= 0x249; 378 reg |= 0x249;
373 break; 379 break;
374 default: 380 default:
375 printf("Unknown chip select size: %d\n", cs_size); 381 printf("Unknown chip select size: %d\n", cs_size);
376 break; 382 break;
377 } 383 }
378 384
379 writel(reg, &iomuxc_regs->gpr[1]); 385 writel(reg, &iomuxc_regs->gpr[1]);
380 } 386 }
381 #endif 387 #endif
382 388
383 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) 389 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
384 /* 390 /*
385 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) 391 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
386 * defines a 2-bit SPEED_GRADING 392 * defines a 2-bit SPEED_GRADING
387 */ 393 */
388 #define OCOTP_TESTER3_SPEED_SHIFT 8 394 #define OCOTP_TESTER3_SPEED_SHIFT 8
389 enum cpu_speed { 395 enum cpu_speed {
390 OCOTP_TESTER3_SPEED_GRADE0, 396 OCOTP_TESTER3_SPEED_GRADE0,
391 OCOTP_TESTER3_SPEED_GRADE1, 397 OCOTP_TESTER3_SPEED_GRADE1,
392 OCOTP_TESTER3_SPEED_GRADE2, 398 OCOTP_TESTER3_SPEED_GRADE2,
393 OCOTP_TESTER3_SPEED_GRADE3, 399 OCOTP_TESTER3_SPEED_GRADE3,
394 OCOTP_TESTER3_SPEED_GRADE4, 400 OCOTP_TESTER3_SPEED_GRADE4,
395 }; 401 };
396 402
397 u32 get_cpu_speed_grade_hz(void) 403 u32 get_cpu_speed_grade_hz(void)
398 { 404 {
399 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 405 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
400 struct fuse_bank *bank = &ocotp->bank[1]; 406 struct fuse_bank *bank = &ocotp->bank[1];
401 struct fuse_bank1_regs *fuse = 407 struct fuse_bank1_regs *fuse =
402 (struct fuse_bank1_regs *)bank->fuse_regs; 408 (struct fuse_bank1_regs *)bank->fuse_regs;
403 uint32_t val; 409 uint32_t val;
404 410
405 val = readl(&fuse->tester3); 411 val = readl(&fuse->tester3);
406 val >>= OCOTP_TESTER3_SPEED_SHIFT; 412 val >>= OCOTP_TESTER3_SPEED_SHIFT;
407 413
408 if (is_imx8mn() || is_imx8mp()) { 414 if (is_imx8mn() || is_imx8mp()) {
409 val &= 0xf; 415 val &= 0xf;
410 return 2300000000 - val * 100000000; 416 return 2300000000 - val * 100000000;
411 } 417 }
412 418
413 if (is_imx8mm()) 419 if (is_imx8mm())
414 val &= 0x7; 420 val &= 0x7;
415 else 421 else
416 val &= 0x3; 422 val &= 0x3;
417 423
418 switch(val) { 424 switch(val) {
419 case OCOTP_TESTER3_SPEED_GRADE0: 425 case OCOTP_TESTER3_SPEED_GRADE0:
420 return 800000000; 426 return 800000000;
421 case OCOTP_TESTER3_SPEED_GRADE1: 427 case OCOTP_TESTER3_SPEED_GRADE1:
422 return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000)); 428 return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
423 case OCOTP_TESTER3_SPEED_GRADE2: 429 case OCOTP_TESTER3_SPEED_GRADE2:
424 return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000)); 430 return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
425 case OCOTP_TESTER3_SPEED_GRADE3: 431 case OCOTP_TESTER3_SPEED_GRADE3:
426 return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000)); 432 return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
427 case OCOTP_TESTER3_SPEED_GRADE4: 433 case OCOTP_TESTER3_SPEED_GRADE4:
428 return 2000000000; 434 return 2000000000;
429 } 435 }
430 436
431 return 0; 437 return 0;
432 } 438 }
433 439
434 /* 440 /*
435 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440) 441 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
436 * defines a 2-bit SPEED_GRADING 442 * defines a 2-bit SPEED_GRADING
437 */ 443 */
438 #define OCOTP_TESTER3_TEMP_SHIFT 6 444 #define OCOTP_TESTER3_TEMP_SHIFT 6
439 445
440 /* iMX8MP uses OCOTP_TESTER3[6:5] for Market segment */ 446 /* iMX8MP uses OCOTP_TESTER3[6:5] for Market segment */
441 #define IMX8MP_OCOTP_TESTER3_TEMP_SHIFT 5 447 #define IMX8MP_OCOTP_TESTER3_TEMP_SHIFT 5
442 448
443 u32 get_cpu_temp_grade(int *minc, int *maxc) 449 u32 get_cpu_temp_grade(int *minc, int *maxc)
444 { 450 {
445 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 451 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
446 struct fuse_bank *bank = &ocotp->bank[1]; 452 struct fuse_bank *bank = &ocotp->bank[1];
447 struct fuse_bank1_regs *fuse = 453 struct fuse_bank1_regs *fuse =
448 (struct fuse_bank1_regs *)bank->fuse_regs; 454 (struct fuse_bank1_regs *)bank->fuse_regs;
449 uint32_t val; 455 uint32_t val;
450 456
451 val = readl(&fuse->tester3); 457 val = readl(&fuse->tester3);
452 if (is_imx8mp()) 458 if (is_imx8mp())
453 val >>= IMX8MP_OCOTP_TESTER3_TEMP_SHIFT; 459 val >>= IMX8MP_OCOTP_TESTER3_TEMP_SHIFT;
454 else 460 else
455 val >>= OCOTP_TESTER3_TEMP_SHIFT; 461 val >>= OCOTP_TESTER3_TEMP_SHIFT;
456 val &= 0x3; 462 val &= 0x3;
457 463
458 if (minc && maxc) { 464 if (minc && maxc) {
459 if (val == TEMP_AUTOMOTIVE) { 465 if (val == TEMP_AUTOMOTIVE) {
460 *minc = -40; 466 *minc = -40;
461 *maxc = 125; 467 *maxc = 125;
462 } else if (val == TEMP_INDUSTRIAL) { 468 } else if (val == TEMP_INDUSTRIAL) {
463 *minc = -40; 469 *minc = -40;
464 *maxc = 105; 470 *maxc = 105;
465 } else if (val == TEMP_EXTCOMMERCIAL) { 471 } else if (val == TEMP_EXTCOMMERCIAL) {
466 *minc = -20; 472 *minc = -20;
467 *maxc = 105; 473 *maxc = 105;
468 } else { 474 } else {
469 *minc = 0; 475 *minc = 0;
470 *maxc = 95; 476 *maxc = 95;
471 } 477 }
472 } 478 }
473 return val; 479 return val;
474 } 480 }
475 #endif 481 #endif
476 482
477 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) 483 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
478 enum boot_device get_boot_device(void) 484 enum boot_device get_boot_device(void)
479 { 485 {
480 struct bootrom_sw_info **p = 486 struct bootrom_sw_info **p =
481 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR; 487 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
482 488
483 enum boot_device boot_dev = SD1_BOOT; 489 enum boot_device boot_dev = SD1_BOOT;
484 u8 boot_type = (*p)->boot_dev_type; 490 u8 boot_type = (*p)->boot_dev_type;
485 u8 boot_instance = (*p)->boot_dev_instance; 491 u8 boot_instance = (*p)->boot_dev_instance;
486 492
487 switch (boot_type) { 493 switch (boot_type) {
488 case BOOT_TYPE_SD: 494 case BOOT_TYPE_SD:
489 boot_dev = boot_instance + SD1_BOOT; 495 boot_dev = boot_instance + SD1_BOOT;
490 break; 496 break;
491 case BOOT_TYPE_MMC: 497 case BOOT_TYPE_MMC:
492 boot_dev = boot_instance + MMC1_BOOT; 498 boot_dev = boot_instance + MMC1_BOOT;
493 break; 499 break;
494 case BOOT_TYPE_NAND: 500 case BOOT_TYPE_NAND:
495 boot_dev = NAND_BOOT; 501 boot_dev = NAND_BOOT;
496 break; 502 break;
497 case BOOT_TYPE_QSPI: 503 case BOOT_TYPE_QSPI:
498 boot_dev = QSPI_BOOT; 504 boot_dev = QSPI_BOOT;
499 break; 505 break;
500 case BOOT_TYPE_WEIM: 506 case BOOT_TYPE_WEIM:
501 boot_dev = WEIM_NOR_BOOT; 507 boot_dev = WEIM_NOR_BOOT;
502 break; 508 break;
503 case BOOT_TYPE_SPINOR: 509 case BOOT_TYPE_SPINOR:
504 boot_dev = SPI_NOR_BOOT; 510 boot_dev = SPI_NOR_BOOT;
505 break; 511 break;
506 case BOOT_TYPE_USB: 512 case BOOT_TYPE_USB:
507 boot_dev = USB_BOOT; 513 boot_dev = USB_BOOT;
508 break; 514 break;
509 default: 515 default:
510 #ifdef CONFIG_IMX8M 516 #ifdef CONFIG_IMX8M
511 if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4) 517 if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4)
512 boot_dev = QSPI_BOOT; 518 boot_dev = QSPI_BOOT;
513 #endif 519 #endif
514 break; 520 break;
515 } 521 }
516 522
517 return boot_dev; 523 return boot_dev;
518 } 524 }
519 #endif 525 #endif
520 526
521 #ifdef CONFIG_NXP_BOARD_REVISION 527 #ifdef CONFIG_NXP_BOARD_REVISION
522 int nxp_board_rev(void) 528 int nxp_board_rev(void)
523 { 529 {
524 /* 530 /*
525 * Get Board ID information from OCOTP_GP1[15:8] 531 * Get Board ID information from OCOTP_GP1[15:8]
526 * RevA: 0x1 532 * RevA: 0x1
527 * RevB: 0x2 533 * RevB: 0x2
528 * RevC: 0x3 534 * RevC: 0x3
529 */ 535 */
530 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 536 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
531 struct fuse_bank *bank = &ocotp->bank[4]; 537 struct fuse_bank *bank = &ocotp->bank[4];
532 struct fuse_bank4_regs *fuse = 538 struct fuse_bank4_regs *fuse =
533 (struct fuse_bank4_regs *)bank->fuse_regs; 539 (struct fuse_bank4_regs *)bank->fuse_regs;
534 540
535 return (readl(&fuse->gp1) >> 8 & 0x0F); 541 return (readl(&fuse->gp1) >> 8 & 0x0F);
536 } 542 }
537 543
538 char nxp_board_rev_string(void) 544 char nxp_board_rev_string(void)
539 { 545 {
540 const char *rev = "A"; 546 const char *rev = "A";
541 547
542 return (*rev + nxp_board_rev() - 1); 548 return (*rev + nxp_board_rev() - 1);
543 } 549 }
544 #endif 550 #endif
545 551
arch/arm/mach-imx/imx8m/soc.c
Diff comments   View file @ 05af9ac
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2017-2019 NXP 3 * Copyright 2017-2019 NXP
4 * 4 *
5 * Peng Fan <peng.fan@nxp.com> 5 * Peng Fan <peng.fan@nxp.com>
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <cpu_func.h> 9 #include <cpu_func.h>
10 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/imx-regs.h>
11 #include <asm/io.h> 11 #include <asm/io.h>
12 #include <asm/arch/clock.h> 12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h> 13 #include <asm/arch/sys_proto.h>
14 #include <asm/mach-imx/hab.h> 14 #include <asm/mach-imx/hab.h>
15 #include <asm/mach-imx/boot_mode.h> 15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/mach-imx/optee.h> 16 #include <asm/mach-imx/optee.h>
17 #include <asm/mach-imx/syscounter.h> 17 #include <asm/mach-imx/syscounter.h>
18 #include <asm/armv8/mmu.h> 18 #include <asm/armv8/mmu.h>
19 #include <dm/uclass.h> 19 #include <dm/uclass.h>
20 #include <errno.h> 20 #include <errno.h>
21 #include <fdt_support.h> 21 #include <fdt_support.h>
22 #include <fdtdec.h> 22 #include <fdtdec.h>
23 #include <fsl_wdog.h> 23 #include <fsl_wdog.h>
24 #include <imx_sip.h> 24 #include <imx_sip.h>
25 #include <generated/version_autogenerated.h> 25 #include <generated/version_autogenerated.h>
26 #include <asm/setup.h> 26 #include <asm/setup.h>
27 #include <asm/bootm.h> 27 #include <asm/bootm.h>
28 #ifdef CONFIG_IMX_SEC_INIT 28 #ifdef CONFIG_IMX_SEC_INIT
29 #include <fsl_caam.h> 29 #include <fsl_caam.h>
30 #endif 30 #endif
31 #include <env.h> 31 #include <env.h>
32 #include <env_internal.h> 32 #include <env_internal.h>
33 #include <efi_loader.h> 33 #include <efi_loader.h>
34 34
35 DECLARE_GLOBAL_DATA_PTR; 35 DECLARE_GLOBAL_DATA_PTR;
36 36
37 #if defined(CONFIG_IMX_HAB) || defined(CONFIG_AVB_ATX) || defined(CONFIG_IMX_TRUSTY_OS) 37 #if defined(CONFIG_IMX_HAB) || defined(CONFIG_AVB_ATX) || defined(CONFIG_IMX_TRUSTY_OS)
38 struct imx_sec_config_fuse_t const imx_sec_config_fuse = { 38 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
39 .bank = 1, 39 .bank = 1,
40 .word = 3, 40 .word = 3,
41 }; 41 };
42 #endif 42 #endif
43 43
44 int timer_init(void) 44 int timer_init(void)
45 { 45 {
46 #ifdef CONFIG_SPL_BUILD 46 #ifdef CONFIG_SPL_BUILD
47 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; 47 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
48 unsigned long freq = readl(&sctr->cntfid0); 48 unsigned long freq = readl(&sctr->cntfid0);
49 49
50 /* Update with accurate clock frequency */ 50 /* Update with accurate clock frequency */
51 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory"); 51 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
52 52
53 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1, 53 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
54 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG); 54 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
55 #endif 55 #endif
56 56
57 gd->arch.tbl = 0; 57 gd->arch.tbl = 0;
58 gd->arch.tbu = 0; 58 gd->arch.tbu = 0;
59 59
60 return 0; 60 return 0;
61 } 61 }
62 62
63 void enable_tzc380(void) 63 void enable_tzc380(void)
64 { 64 {
65 struct iomuxc_gpr_base_regs *gpr = 65 struct iomuxc_gpr_base_regs *gpr =
66 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 66 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
67 67
68 /* Enable TZASC and lock setting */ 68 /* Enable TZASC and lock setting */
69 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN); 69 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
70 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); 70 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
71 if (is_imx8mm() || is_imx8mn() || is_imx8mp()) 71 if (is_imx8mm() || is_imx8mn() || is_imx8mp())
72 setbits_le32(&gpr->gpr[10], BIT(1)); 72 setbits_le32(&gpr->gpr[10], BIT(1));
73 /* 73 /*
74 * set Region 0 attribute to allow secure and non-secure 74 * set Region 0 attribute to allow secure and non-secure
75 * read/write permission. Found some masters like usb dwc3 75 * read/write permission. Found some masters like usb dwc3
76 * controllers can't work with secure memory. 76 * controllers can't work with secure memory.
77 */ 77 */
78 writel(0xf0000000, TZASC_BASE_ADDR + 0x108); 78 writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
79 } 79 }
80 80
81 void set_wdog_reset(struct wdog_regs *wdog) 81 void set_wdog_reset(struct wdog_regs *wdog)
82 { 82 {
83 /* 83 /*
84 * Output WDOG_B signal to reset external pmic or POR_B decided by 84 * Output WDOG_B signal to reset external pmic or POR_B decided by
85 * the board design. Without external reset, the peripherals/DDR/ 85 * the board design. Without external reset, the peripherals/DDR/
86 * PMIC are not reset, that may cause system working abnormal. 86 * PMIC are not reset, that may cause system working abnormal.
87 * WDZST bit is write-once only bit. Align this bit in kernel, 87 * WDZST bit is write-once only bit. Align this bit in kernel,
88 * otherwise kernel code will have no chance to set this bit. 88 * otherwise kernel code will have no chance to set this bit.
89 */ 89 */
90 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); 90 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
91 } 91 }
92 92
93 static struct mm_region imx8m_mem_map[] = { 93 static struct mm_region imx8m_mem_map[] = {
94 { 94 {
95 /* ROM */ 95 /* ROM */
96 .virt = 0x0UL, 96 .virt = 0x0UL,
97 .phys = 0x0UL, 97 .phys = 0x0UL,
98 .size = 0x100000UL, 98 .size = 0x100000UL,
99 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 99 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
100 PTE_BLOCK_OUTER_SHARE 100 PTE_BLOCK_OUTER_SHARE
101 }, { 101 }, {
102 /* CAAM */ 102 /* CAAM */
103 .virt = 0x100000UL, 103 .virt = 0x100000UL,
104 .phys = 0x100000UL, 104 .phys = 0x100000UL,
105 .size = 0x8000UL, 105 .size = 0x8000UL,
106 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 106 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
107 PTE_BLOCK_NON_SHARE | 107 PTE_BLOCK_NON_SHARE |
108 PTE_BLOCK_PXN | PTE_BLOCK_UXN 108 PTE_BLOCK_PXN | PTE_BLOCK_UXN
109 }, { 109 }, {
110 /* TCM */ 110 /* TCM */
111 .virt = 0x7C0000UL, 111 .virt = 0x7C0000UL,
112 .phys = 0x7C0000UL, 112 .phys = 0x7C0000UL,
113 .size = 0x80000UL, 113 .size = 0x80000UL,
114 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 114 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
115 PTE_BLOCK_NON_SHARE | 115 PTE_BLOCK_NON_SHARE |
116 PTE_BLOCK_PXN | PTE_BLOCK_UXN 116 PTE_BLOCK_PXN | PTE_BLOCK_UXN
117 }, { 117 }, {
118 /* OCRAM */ 118 /* OCRAM */
119 .virt = 0x900000UL, 119 .virt = 0x900000UL,
120 .phys = 0x900000UL, 120 .phys = 0x900000UL,
121 .size = 0x200000UL, 121 .size = 0x200000UL,
122 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 122 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
123 PTE_BLOCK_OUTER_SHARE 123 PTE_BLOCK_OUTER_SHARE
124 }, { 124 }, {
125 /* AIPS */ 125 /* AIPS */
126 .virt = 0xB00000UL, 126 .virt = 0xB00000UL,
127 .phys = 0xB00000UL, 127 .phys = 0xB00000UL,
128 .size = 0x3f500000UL, 128 .size = 0x3f500000UL,
129 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 129 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
130 PTE_BLOCK_NON_SHARE | 130 PTE_BLOCK_NON_SHARE |
131 PTE_BLOCK_PXN | PTE_BLOCK_UXN 131 PTE_BLOCK_PXN | PTE_BLOCK_UXN
132 }, { 132 }, {
133 /* DRAM1 */ 133 /* DRAM1 */
134 .virt = 0x40000000UL, 134 .virt = 0x40000000UL,
135 .phys = 0x40000000UL, 135 .phys = 0x40000000UL,
136 .size = PHYS_SDRAM_SIZE, 136 .size = PHYS_SDRAM_SIZE,
137 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 137 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
138 #ifdef CONFIG_IMX_TRUSTY_OS 138 #ifdef CONFIG_IMX_TRUSTY_OS
139 PTE_BLOCK_INNER_SHARE 139 PTE_BLOCK_INNER_SHARE
140 #else 140 #else
141 PTE_BLOCK_OUTER_SHARE 141 PTE_BLOCK_OUTER_SHARE
142 #endif 142 #endif
143 #ifdef PHYS_SDRAM_2_SIZE 143 #ifdef PHYS_SDRAM_2_SIZE
144 }, { 144 }, {
145 /* DRAM2 */ 145 /* DRAM2 */
146 .virt = 0x100000000UL, 146 .virt = 0x100000000UL,
147 .phys = 0x100000000UL, 147 .phys = 0x100000000UL,
148 .size = PHYS_SDRAM_2_SIZE, 148 .size = PHYS_SDRAM_2_SIZE,
149 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 149 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
150 #ifdef CONFIG_IMX_TRUSTY_OS 150 #ifdef CONFIG_IMX_TRUSTY_OS
151 PTE_BLOCK_INNER_SHARE 151 PTE_BLOCK_INNER_SHARE
152 #else 152 #else
153 PTE_BLOCK_OUTER_SHARE 153 PTE_BLOCK_OUTER_SHARE
154 #endif 154 #endif
155 #endif 155 #endif
156 }, { 156 }, {
157 /* empty entrie to split table entry 5 157 /* empty entrie to split table entry 5
158 * if needed when TEEs are used 158 * if needed when TEEs are used
159 */ 159 */
160 0, 160 0,
161 }, { 161 }, {
162 /* List terminator */ 162 /* List terminator */
163 0, 163 0,
164 } 164 }
165 }; 165 };
166 166
167 struct mm_region *mem_map = imx8m_mem_map; 167 struct mm_region *mem_map = imx8m_mem_map;
168 168
169 void enable_caches(void) 169 void enable_caches(void)
170 { 170 {
171 /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */ 171 /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
172 if (rom_pointer[1]) { 172 if (rom_pointer[1]) {
173 173
174 /* TEE are loaded, So the ddr bank structures 174 /* TEE are loaded, So the ddr bank structures
175 * have been modified update mmu table accordingly 175 * have been modified update mmu table accordingly
176 */ 176 */
177 int i = 0; 177 int i = 0;
178 /* please make sure that entry initial value matches 178 /* please make sure that entry initial value matches
179 * imx8m_mem_map for DRAM1 179 * imx8m_mem_map for DRAM1
180 */ 180 */
181 int entry = 5; 181 int entry = 5;
182 u64 attrs = imx8m_mem_map[entry].attrs; 182 u64 attrs = imx8m_mem_map[entry].attrs;
183 while (i < CONFIG_NR_DRAM_BANKS && entry < 8) { 183 while (i < CONFIG_NR_DRAM_BANKS && entry < 8) {
184 if (gd->bd->bi_dram[i].start == 0) 184 if (gd->bd->bi_dram[i].start == 0)
185 break; 185 break;
186 imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start; 186 imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
187 imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start; 187 imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
188 imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size; 188 imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
189 imx8m_mem_map[entry].attrs = attrs; 189 imx8m_mem_map[entry].attrs = attrs;
190 debug("Added memory mapping (%d): %llx %llx\n", entry, 190 debug("Added memory mapping (%d): %llx %llx\n", entry,
191 imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size); 191 imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
192 i++;entry++; 192 i++;entry++;
193 } 193 }
194 } 194 }
195 195
196 icache_enable(); 196 icache_enable();
197 dcache_enable(); 197 dcache_enable();
198 } 198 }
199 199
200 __weak int board_phys_sdram_size(phys_size_t *size) 200 __weak int board_phys_sdram_size(phys_size_t *size)
201 { 201 {
202 if (!size) 202 if (!size)
203 return -EINVAL; 203 return -EINVAL;
204 204
205 *size = PHYS_SDRAM_SIZE; 205 *size = PHYS_SDRAM_SIZE;
206 return 0; 206 return 0;
207 } 207 }
208 208
209 int dram_init(void) 209 int dram_init(void)
210 { 210 {
211 phys_size_t sdram_size; 211 phys_size_t sdram_size;
212 int ret; 212 int ret;
213 213
214 ret = board_phys_sdram_size(&sdram_size); 214 ret = board_phys_sdram_size(&sdram_size);
215 if (ret) 215 if (ret)
216 return ret; 216 return ret;
217 217
218 /* rom_pointer[1] contains the size of TEE occupies */ 218 /* rom_pointer[1] contains the size of TEE occupies */
219 if (rom_pointer[1]) 219 if (rom_pointer[1])
220 gd->ram_size = sdram_size - rom_pointer[1]; 220 gd->ram_size = sdram_size - rom_pointer[1];
221 else 221 else
222 gd->ram_size = sdram_size; 222 gd->ram_size = sdram_size;
223 223
224 #ifdef PHYS_SDRAM_2_SIZE 224 #ifdef PHYS_SDRAM_2_SIZE
225 gd->ram_size += PHYS_SDRAM_2_SIZE; 225 gd->ram_size += PHYS_SDRAM_2_SIZE;
226 #endif 226 #endif
227 227
228 return 0; 228 return 0;
229 } 229 }
230 230
231 int dram_init_banksize(void) 231 int dram_init_banksize(void)
232 { 232 {
233 int bank = 0; 233 int bank = 0;
234 int ret; 234 int ret;
235 phys_size_t sdram_size; 235 phys_size_t sdram_size;
236 236
237 ret = board_phys_sdram_size(&sdram_size); 237 ret = board_phys_sdram_size(&sdram_size);
238 if (ret) 238 if (ret)
239 return ret; 239 return ret;
240 240
241 gd->bd->bi_dram[bank].start = PHYS_SDRAM; 241 gd->bd->bi_dram[bank].start = PHYS_SDRAM;
242 if (rom_pointer[1]) { 242 if (rom_pointer[1]) {
243 phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; 243 phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
244 phys_size_t optee_size = (size_t)rom_pointer[1]; 244 phys_size_t optee_size = (size_t)rom_pointer[1];
245 245
246 gd->bd->bi_dram[bank].size = optee_start -gd->bd->bi_dram[bank].start; 246 gd->bd->bi_dram[bank].size = optee_start -gd->bd->bi_dram[bank].start;
247 if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) { 247 if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
248 if ( ++bank >= CONFIG_NR_DRAM_BANKS) { 248 if ( ++bank >= CONFIG_NR_DRAM_BANKS) {
249 puts("CONFIG_NR_DRAM_BANKS is not enough\n"); 249 puts("CONFIG_NR_DRAM_BANKS is not enough\n");
250 return -1; 250 return -1;
251 } 251 }
252 252
253 gd->bd->bi_dram[bank].start = optee_start + optee_size; 253 gd->bd->bi_dram[bank].start = optee_start + optee_size;
254 gd->bd->bi_dram[bank].size = PHYS_SDRAM + 254 gd->bd->bi_dram[bank].size = PHYS_SDRAM +
255 sdram_size - gd->bd->bi_dram[bank].start; 255 sdram_size - gd->bd->bi_dram[bank].start;
256 } 256 }
257 } else { 257 } else {
258 gd->bd->bi_dram[bank].size = sdram_size; 258 gd->bd->bi_dram[bank].size = sdram_size;
259 } 259 }
260 260
261 #ifdef PHYS_SDRAM_2_SIZE 261 #ifdef PHYS_SDRAM_2_SIZE
262 if ( ++bank >= CONFIG_NR_DRAM_BANKS) { 262 if ( ++bank >= CONFIG_NR_DRAM_BANKS) {
263 puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); 263 puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
264 return -1; 264 return -1;
265 } 265 }
266 gd->bd->bi_dram[bank].start = PHYS_SDRAM_2; 266 gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
267 gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE; 267 gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
268 #endif 268 #endif
269 269
270 return 0; 270 return 0;
271 } 271 }
272 272
273 phys_size_t get_effective_memsize(void) 273 phys_size_t get_effective_memsize(void)
274 { 274 {
275 /* return the first bank as effective memory */ 275 /* return the first bank as effective memory */
276 if (rom_pointer[1]) 276 if (rom_pointer[1])
277 return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM); 277 return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
278 278
279 #ifdef PHYS_SDRAM_2_SIZE 279 #ifdef PHYS_SDRAM_2_SIZE
280 return gd->ram_size - PHYS_SDRAM_2_SIZE; 280 return gd->ram_size - PHYS_SDRAM_2_SIZE;
281 #else 281 #else
282 return gd->ram_size; 282 return gd->ram_size;
283 #endif 283 #endif
284 } 284 }
285 285
286 static u32 get_cpu_variant_type(u32 type) 286 static u32 get_cpu_variant_type(u32 type)
287 { 287 {
288 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 288 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
289 struct fuse_bank *bank = &ocotp->bank[1]; 289 struct fuse_bank *bank = &ocotp->bank[1];
290 struct fuse_bank1_regs *fuse = 290 struct fuse_bank1_regs *fuse =
291 (struct fuse_bank1_regs *)bank->fuse_regs; 291 (struct fuse_bank1_regs *)bank->fuse_regs;
292 292
293 u32 value = readl(&fuse->tester4); 293 u32 value = readl(&fuse->tester4);
294 294
295 if (type == MXC_CPU_IMX8MQ) { 295 if (type == MXC_CPU_IMX8MQ) {
296 if ((value & 0x3) == 0x2) 296 if ((value & 0x3) == 0x2)
297 return MXC_CPU_IMX8MD; 297 return MXC_CPU_IMX8MD;
298 else if (value & 0x200000) 298 else if (value & 0x200000)
299 return MXC_CPU_IMX8MQL; 299 return MXC_CPU_IMX8MQL;
300 300
301 } else if (type == MXC_CPU_IMX8MM) { 301 } else if (type == MXC_CPU_IMX8MM) {
302 switch (value & 0x3) { 302 switch (value & 0x3) {
303 case 2: 303 case 2:
304 if (value & 0x1c0000) 304 if (value & 0x1c0000)
305 return MXC_CPU_IMX8MMDL; 305 return MXC_CPU_IMX8MMDL;
306 else 306 else
307 return MXC_CPU_IMX8MMD; 307 return MXC_CPU_IMX8MMD;
308 case 3: 308 case 3:
309 if (value & 0x1c0000) 309 if (value & 0x1c0000)
310 return MXC_CPU_IMX8MMSL; 310 return MXC_CPU_IMX8MMSL;
311 else 311 else
312 return MXC_CPU_IMX8MMS; 312 return MXC_CPU_IMX8MMS;
313 default: 313 default:
314 if (value & 0x1c0000) 314 if (value & 0x1c0000)
315 return MXC_CPU_IMX8MML; 315 return MXC_CPU_IMX8MML;
316 break; 316 break;
317 } 317 }
318 } else if (type == MXC_CPU_IMX8MN) { 318 } else if (type == MXC_CPU_IMX8MN) {
319 switch (value & 0x3) { 319 switch (value & 0x3) {
320 case 2: 320 case 2:
321 if (value & 0x1000000) 321 if (value & 0x1000000) {
322 return MXC_CPU_IMX8MNDL; 322 if (value & 0x10000000) /* MIPI DSI */
323 else 323 return MXC_CPU_IMX8MNUD;
324 else
325 return MXC_CPU_IMX8MNDL;
326 } else {
324 return MXC_CPU_IMX8MND; 327 return MXC_CPU_IMX8MND;
328 }
325 case 3: 329 case 3:
326 if (value & 0x1000000) 330 if (value & 0x1000000) {
327 return MXC_CPU_IMX8MNSL; 331 if (value & 0x10000000) /* MIPI DSI */
328 else 332 return MXC_CPU_IMX8MNUS;
333 else
334 return MXC_CPU_IMX8MNSL;
335 } else {
329 return MXC_CPU_IMX8MNS; 336 return MXC_CPU_IMX8MNS;
337 }
330 default: 338 default:
331 if (value & 0x1000000) 339 if (value & 0x1000000) {
332 return MXC_CPU_IMX8MNL; 340 if (value & 0x10000000) /* MIPI DSI */
341 return MXC_CPU_IMX8MNUQ;
342 else
343 return MXC_CPU_IMX8MNL;
344 }
333 break; 345 break;
334 } 346 }
335 } else if (type == MXC_CPU_IMX8MP) { 347 } else if (type == MXC_CPU_IMX8MP) {
336 u32 value0 = readl(&fuse->tester3); 348 u32 value0 = readl(&fuse->tester3);
337 u32 flag = 0; 349 u32 flag = 0;
338 350
339 if ((value0 & 0xc0000) == 0x80000) { 351 if ((value0 & 0xc0000) == 0x80000) {
340 return MXC_CPU_IMX8MPD; 352 return MXC_CPU_IMX8MPD;
341 } else { 353 } else {
342 /* vpu disabled */ 354 /* vpu disabled */
343 if ((value0 & 0x43000000) == 0x43000000) 355 if ((value0 & 0x43000000) == 0x43000000)
344 flag = 1; 356 flag = 1;
345 357
346 /* npu disabled*/ 358 /* npu disabled*/
347 if ((value & 0x8) == 0x8) 359 if ((value & 0x8) == 0x8)
348 flag |= (1 << 1); 360 flag |= (1 << 1);
349 361
350 /* isp disabled */ 362 /* isp disabled */
351 if ((value & 0x3) == 0x3) 363 if ((value & 0x3) == 0x3)
352 flag |= (1 << 2); 364 flag |= (1 << 2);
353 365
354 switch (flag) { 366 switch (flag) {
355 case 7: 367 case 7:
356 return MXC_CPU_IMX8MPL; 368 return MXC_CPU_IMX8MPL;
357 case 2: 369 case 2:
358 return MXC_CPU_IMX8MP6; 370 return MXC_CPU_IMX8MP6;
359 default: 371 default:
360 break; 372 break;
361 } 373 }
362 } 374 }
363 } 375 }
364 376
365 return type; 377 return type;
366 } 378 }
367 379
368 u32 get_cpu_rev(void) 380 u32 get_cpu_rev(void)
369 { 381 {
370 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; 382 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
371 u32 reg = readl(&ana_pll->digprog); 383 u32 reg = readl(&ana_pll->digprog);
372 u32 type = (reg >> 16) & 0xff; 384 u32 type = (reg >> 16) & 0xff;
373 u32 major_low = (reg >> 8) & 0xff; 385 u32 major_low = (reg >> 8) & 0xff;
374 u32 rom_version; 386 u32 rom_version;
375 387
376 reg &= 0xff; 388 reg &= 0xff;
377 389
378 /* iMX8MP */ 390 /* iMX8MP */
379 if (major_low == 0x43) { 391 if (major_low == 0x43) {
380 type = get_cpu_variant_type(MXC_CPU_IMX8MP); 392 type = get_cpu_variant_type(MXC_CPU_IMX8MP);
381 } else if (major_low == 0x42) { 393 } else if (major_low == 0x42) {
382 /* iMX8MN */ 394 /* iMX8MN */
383 type = get_cpu_variant_type(MXC_CPU_IMX8MN); 395 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
384 } else if (major_low == 0x41) { 396 } else if (major_low == 0x41) {
385 type = get_cpu_variant_type(MXC_CPU_IMX8MM); 397 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
386 } else { 398 } else {
387 if (reg == CHIP_REV_1_0) { 399 if (reg == CHIP_REV_1_0) {
388 /* 400 /*
389 * For B0 chip, the DIGPROG is not updated, 401 * For B0 chip, the DIGPROG is not updated,
390 * it is still TO1.0. we have to check ROM 402 * it is still TO1.0. we have to check ROM
391 * version or OCOTP_READ_FUSE_DATA. 403 * version or OCOTP_READ_FUSE_DATA.
392 * 0xff0055aa is magic number for B1. 404 * 0xff0055aa is magic number for B1.
393 */ 405 */
394 if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) { 406 if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
395 reg = CHIP_REV_2_1; 407 reg = CHIP_REV_2_1;
396 } else { 408 } else {
397 rom_version = 409 rom_version =
398 readl((void __iomem *)ROM_VERSION_A0); 410 readl((void __iomem *)ROM_VERSION_A0);
399 if (rom_version != CHIP_REV_1_0) { 411 if (rom_version != CHIP_REV_1_0) {
400 rom_version = readl((void __iomem *)ROM_VERSION_B0); 412 rom_version = readl((void __iomem *)ROM_VERSION_B0);
401 rom_version &= 0xff; 413 rom_version &= 0xff;
402 if (rom_version == CHIP_REV_2_0) 414 if (rom_version == CHIP_REV_2_0)
403 reg = CHIP_REV_2_0; 415 reg = CHIP_REV_2_0;
404 } 416 }
405 } 417 }
406 } 418 }
407 419
408 type = get_cpu_variant_type(type); 420 type = get_cpu_variant_type(type);
409 } 421 }
410 422
411 return (type << 12) | reg; 423 return (type << 12) | reg;
412 } 424 }
413 425
414 static void imx_set_wdog_powerdown(bool enable) 426 static void imx_set_wdog_powerdown(bool enable)
415 { 427 {
416 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; 428 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
417 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; 429 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
418 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; 430 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
419 431
420 /* Write to the PDE (Power Down Enable) bit */ 432 /* Write to the PDE (Power Down Enable) bit */
421 writew(enable, &wdog1->wmcr); 433 writew(enable, &wdog1->wmcr);
422 writew(enable, &wdog2->wmcr); 434 writew(enable, &wdog2->wmcr);
423 writew(enable, &wdog3->wmcr); 435 writew(enable, &wdog3->wmcr);
424 } 436 }
425 437
426 int arch_cpu_init_dm(void) 438 int arch_cpu_init_dm(void)
427 { 439 {
428 struct udevice *dev; 440 struct udevice *dev;
429 int ret; 441 int ret;
430 442
431 if (CONFIG_IS_ENABLED(CLK)) { 443 if (CONFIG_IS_ENABLED(CLK)) {
432 ret = uclass_get_device_by_name(UCLASS_CLK, 444 ret = uclass_get_device_by_name(UCLASS_CLK,
433 "clock-controller@30380000", 445 "clock-controller@30380000",
434 &dev); 446 &dev);
435 if (ret < 0) { 447 if (ret < 0) {
436 printf("Failed to find clock node. Check device tree\n"); 448 printf("Failed to find clock node. Check device tree\n");
437 return ret; 449 return ret;
438 } 450 }
439 } 451 }
440 452
441 return 0; 453 return 0;
442 } 454 }
443 455
444 #if defined(CONFIG_IMX_HAB) && defined(CONFIG_IMX8MQ) 456 #if defined(CONFIG_IMX_HAB) && defined(CONFIG_IMX8MQ)
445 static bool is_hdmi_fused(void) { 457 static bool is_hdmi_fused(void) {
446 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 458 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
447 struct fuse_bank *bank = &ocotp->bank[1]; 459 struct fuse_bank *bank = &ocotp->bank[1];
448 struct fuse_bank1_regs *fuse = 460 struct fuse_bank1_regs *fuse =
449 (struct fuse_bank1_regs *)bank->fuse_regs; 461 (struct fuse_bank1_regs *)bank->fuse_regs;
450 462
451 u32 value = readl(&fuse->tester4); 463 u32 value = readl(&fuse->tester4);
452 464
453 if (is_imx8mq()) { 465 if (is_imx8mq()) {
454 if (value & 0x02000000) 466 if (value & 0x02000000)
455 return true; 467 return true;
456 } 468 }
457 469
458 return false; 470 return false;
459 } 471 }
460 472
461 bool is_uid_matched(u64 uid) { 473 bool is_uid_matched(u64 uid) {
462 struct tag_serialnr nr; 474 struct tag_serialnr nr;
463 get_board_serial(&nr); 475 get_board_serial(&nr);
464 476
465 if (lower_32_bits(uid) == nr.low && 477 if (lower_32_bits(uid) == nr.low &&
466 upper_32_bits(uid) == nr.high) 478 upper_32_bits(uid) == nr.high)
467 return true; 479 return true;
468 480
469 return false; 481 return false;
470 } 482 }
471 483
472 static void secure_lockup(void) 484 static void secure_lockup(void)
473 { 485 {
474 if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1) && 486 if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1) &&
475 imx_hab_is_enabled() && !is_hdmi_fused()) { 487 imx_hab_is_enabled() && !is_hdmi_fused()) {
476 #ifdef CONFIG_SECURE_STICKY_BITS_LOCKUP 488 #ifdef CONFIG_SECURE_STICKY_BITS_LOCKUP
477 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 489 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
478 490
479 clock_enable(CCGR_OCOTP, 1); 491 clock_enable(CCGR_OCOTP, 1);
480 setbits_le32(&ocotp->sw_sticky, 0x6); /* Lock up field return and SRK revoke */ 492 setbits_le32(&ocotp->sw_sticky, 0x6); /* Lock up field return and SRK revoke */
481 writel(0x80000000, &ocotp->scs_set); /* Lock up SCS */ 493 writel(0x80000000, &ocotp->scs_set); /* Lock up SCS */
482 #else 494 #else
483 /* Check the Unique ID, if it is matched with UID config, then allow to leave sticky bits unlocked */ 495 /* Check the Unique ID, if it is matched with UID config, then allow to leave sticky bits unlocked */
484 if (!is_uid_matched(CONFIG_IMX_UNIQUE_ID)) 496 if (!is_uid_matched(CONFIG_IMX_UNIQUE_ID))
485 hang(); 497 hang();
486 #endif 498 #endif
487 } 499 }
488 } 500 }
489 #endif 501 #endif
490 502
491 int arch_cpu_init(void) 503 int arch_cpu_init(void)
492 { 504 {
493 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 505 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
494 /* 506 /*
495 * ROM might disable clock for SCTR, 507 * ROM might disable clock for SCTR,
496 * enable the clock before timer_init. 508 * enable the clock before timer_init.
497 */ 509 */
498 if (IS_ENABLED(CONFIG_SPL_BUILD)) 510 if (IS_ENABLED(CONFIG_SPL_BUILD))
499 clock_enable(CCGR_SCTR, 1); 511 clock_enable(CCGR_SCTR, 1);
500 /* 512 /*
501 * Init timer at very early state, because sscg pll setting 513 * Init timer at very early state, because sscg pll setting
502 * will use it 514 * will use it
503 */ 515 */
504 timer_init(); 516 timer_init();
505 517
506 if (IS_ENABLED(CONFIG_SPL_BUILD)) { 518 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
507 clock_init(); 519 clock_init();
508 imx_set_wdog_powerdown(false); 520 imx_set_wdog_powerdown(false);
509 521
510 #if defined(CONFIG_IMX_HAB) && defined(CONFIG_IMX8MQ) 522 #if defined(CONFIG_IMX_HAB) && defined(CONFIG_IMX8MQ)
511 secure_lockup(); 523 secure_lockup();
512 #endif 524 #endif
513 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() || is_imx8mmsl() || 525 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() || is_imx8mmsl() ||
514 is_imx8mnd() || is_imx8mndl() || is_imx8mns() || is_imx8mnsl() || is_imx8mpd()) { 526 is_imx8mnd() || is_imx8mndl() || is_imx8mns() || is_imx8mnsl() || is_imx8mpd() ||
527 is_imx8mnud() || is_imx8mnus()) {
515 /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */ 528 /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
516 struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840); 529 struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
517 struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880); 530 struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
518 struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0); 531 struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
519 struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR; 532 struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
520 533
521 writel(0x1, &pgc_core2->pgcr); 534 writel(0x1, &pgc_core2->pgcr);
522 writel(0x1, &pgc_core3->pgcr); 535 writel(0x1, &pgc_core3->pgcr);
523 if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl()) { 536 if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
524 writel(0x1, &pgc_core1->pgcr); 537 writel(0x1, &pgc_core1->pgcr);
525 writel(0xE, &gpc->cpu_pgc_dn_trg); 538 writel(0xE, &gpc->cpu_pgc_dn_trg);
526 } else { 539 } else {
527 writel(0xC, &gpc->cpu_pgc_dn_trg); 540 writel(0xC, &gpc->cpu_pgc_dn_trg);
528 } 541 }
529 } 542 }
530 } 543 }
531 544
532 #ifdef CONFIG_IMX_SEC_INIT 545 #ifdef CONFIG_IMX_SEC_INIT
533 /* Secure init function such RNG */ 546 /* Secure init function such RNG */
534 imx_sec_init(); 547 imx_sec_init();
535 #endif 548 #endif
536 #if defined(CONFIG_ANDROID_SUPPORT) 549 #if defined(CONFIG_ANDROID_SUPPORT)
537 /* Enable RTC */ 550 /* Enable RTC */
538 writel(0x21, 0x30370038); 551 writel(0x21, 0x30370038);
539 #endif 552 #endif
540 553
541 if (is_imx8mq()) { 554 if (is_imx8mq()) {
542 clock_enable(CCGR_OCOTP, 1); 555 clock_enable(CCGR_OCOTP, 1);
543 if (readl(&ocotp->ctrl) & 0x200) 556 if (readl(&ocotp->ctrl) & 0x200)
544 writel(0x200, &ocotp->ctrl_clr); 557 writel(0x200, &ocotp->ctrl_clr);
545 } 558 }
546 559
547 return 0; 560 return 0;
548 } 561 }
549 562
550 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) 563 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
551 struct rom_api *g_rom_api = (struct rom_api *)0x980; 564 struct rom_api *g_rom_api = (struct rom_api *)0x980;
552 565
553 enum boot_device get_boot_device(void) 566 enum boot_device get_boot_device(void)
554 { 567 {
555 volatile gd_t *pgd = gd; 568 volatile gd_t *pgd = gd;
556 int ret; 569 int ret;
557 u32 boot; 570 u32 boot;
558 u16 boot_type; 571 u16 boot_type;
559 u8 boot_instance; 572 u8 boot_instance;
560 enum boot_device boot_dev = SD1_BOOT; 573 enum boot_device boot_dev = SD1_BOOT;
561 574
562 ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot, 575 ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
563 ((uintptr_t)&boot) ^ QUERY_BT_DEV); 576 ((uintptr_t)&boot) ^ QUERY_BT_DEV);
564 gd = pgd; 577 gd = pgd;
565 578
566 if (ret != ROM_API_OKAY) { 579 if (ret != ROM_API_OKAY) {
567 puts("ROMAPI: failure at query_boot_info\n"); 580 puts("ROMAPI: failure at query_boot_info\n");
568 return -1; 581 return -1;
569 } 582 }
570 583
571 boot_type = boot >> 16; 584 boot_type = boot >> 16;
572 boot_instance = (boot >> 8) & 0xff; 585 boot_instance = (boot >> 8) & 0xff;
573 586
574 switch (boot_type) { 587 switch (boot_type) {
575 case BT_DEV_TYPE_SD: 588 case BT_DEV_TYPE_SD:
576 boot_dev = boot_instance + SD1_BOOT; 589 boot_dev = boot_instance + SD1_BOOT;
577 break; 590 break;
578 case BT_DEV_TYPE_MMC: 591 case BT_DEV_TYPE_MMC:
579 boot_dev = boot_instance + MMC1_BOOT; 592 boot_dev = boot_instance + MMC1_BOOT;
580 break; 593 break;
581 case BT_DEV_TYPE_NAND: 594 case BT_DEV_TYPE_NAND:
582 boot_dev = NAND_BOOT; 595 boot_dev = NAND_BOOT;
583 break; 596 break;
584 case BT_DEV_TYPE_FLEXSPINOR: 597 case BT_DEV_TYPE_FLEXSPINOR:
585 boot_dev = QSPI_BOOT; 598 boot_dev = QSPI_BOOT;
586 break; 599 break;
587 case BT_DEV_TYPE_USB: 600 case BT_DEV_TYPE_USB:
588 boot_dev = USB_BOOT; 601 boot_dev = USB_BOOT;
589 break; 602 break;
590 default: 603 default:
591 break; 604 break;
592 } 605 }
593 606
594 return boot_dev; 607 return boot_dev;
595 } 608 }
596 #endif 609 #endif
597 610
598 bool is_usb_boot(void) 611 bool is_usb_boot(void)
599 { 612 {
600 return get_boot_device() == USB_BOOT; 613 return get_boot_device() == USB_BOOT;
601 } 614 }
602 #ifdef CONFIG_SERIAL_TAG 615 #ifdef CONFIG_SERIAL_TAG
603 void get_board_serial(struct tag_serialnr *serialnr) 616 void get_board_serial(struct tag_serialnr *serialnr)
604 { 617 {
605 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 618 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
606 struct fuse_bank *bank = &ocotp->bank[0]; 619 struct fuse_bank *bank = &ocotp->bank[0];
607 struct fuse_bank0_regs *fuse = 620 struct fuse_bank0_regs *fuse =
608 (struct fuse_bank0_regs *)bank->fuse_regs; 621 (struct fuse_bank0_regs *)bank->fuse_regs;
609 622
610 serialnr->low = fuse->uid_low; 623 serialnr->low = fuse->uid_low;
611 serialnr->high = fuse->uid_high; 624 serialnr->high = fuse->uid_high;
612 } 625 }
613 #endif 626 #endif
614 627
615 #ifdef CONFIG_OF_SYSTEM_SETUP 628 #ifdef CONFIG_OF_SYSTEM_SETUP
616 bool check_fdt_new_path(void *blob) 629 bool check_fdt_new_path(void *blob)
617 { 630 {
618 const char *soc_path = "/soc@0"; 631 const char *soc_path = "/soc@0";
619 int nodeoff; 632 int nodeoff;
620 633
621 nodeoff = fdt_path_offset(blob, soc_path); 634 nodeoff = fdt_path_offset(blob, soc_path);
622 if (nodeoff < 0) { 635 if (nodeoff < 0) {
623 return false; 636 return false;
624 } 637 }
625 638
626 return true; 639 return true;
627 } 640 }
628 641
629 static int disable_fdt_nodes(void *blob, const char *nodes_path[], int size_array) 642 static int disable_fdt_nodes(void *blob, const char *nodes_path[], int size_array)
630 { 643 {
631 int i = 0; 644 int i = 0;
632 int rc; 645 int rc;
633 int nodeoff; 646 int nodeoff;
634 const char *status = "disabled"; 647 const char *status = "disabled";
635 648
636 for (i = 0; i < size_array; i++) { 649 for (i = 0; i < size_array; i++) {
637 nodeoff = fdt_path_offset(blob, nodes_path[i]); 650 nodeoff = fdt_path_offset(blob, nodes_path[i]);
638 if (nodeoff < 0) 651 if (nodeoff < 0)
639 continue; /* Not found, skip it */ 652 continue; /* Not found, skip it */
640 653
641 printf("Found %s node\n", nodes_path[i]); 654 printf("Found %s node\n", nodes_path[i]);
642 655
643 add_status: 656 add_status:
644 rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1); 657 rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
645 if (rc) { 658 if (rc) {
646 if (rc == -FDT_ERR_NOSPACE) { 659 if (rc == -FDT_ERR_NOSPACE) {
647 rc = fdt_increase_size(blob, 512); 660 rc = fdt_increase_size(blob, 512);
648 if (!rc) 661 if (!rc)
649 goto add_status; 662 goto add_status;
650 } 663 }
651 printf("Unable to update property %s:%s, err=%s\n", 664 printf("Unable to update property %s:%s, err=%s\n",
652 nodes_path[i], "status", fdt_strerror(rc)); 665 nodes_path[i], "status", fdt_strerror(rc));
653 } else { 666 } else {
654 printf("Modify %s:%s disabled\n", 667 printf("Modify %s:%s disabled\n",
655 nodes_path[i], "status"); 668 nodes_path[i], "status");
656 } 669 }
657 } 670 }
658 671
659 return 0; 672 return 0;
660 } 673 }
661 674
662 #ifdef CONFIG_IMX8MQ 675 #ifdef CONFIG_IMX8MQ
663 bool check_dcss_fused(void) 676 bool check_dcss_fused(void)
664 { 677 {
665 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 678 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
666 struct fuse_bank *bank = &ocotp->bank[1]; 679 struct fuse_bank *bank = &ocotp->bank[1];
667 struct fuse_bank1_regs *fuse = 680 struct fuse_bank1_regs *fuse =
668 (struct fuse_bank1_regs *)bank->fuse_regs; 681 (struct fuse_bank1_regs *)bank->fuse_regs;
669 682
670 u32 value = readl(&fuse->tester4); 683 u32 value = readl(&fuse->tester4);
671 if (value & 0x4000000) 684 if (value & 0x4000000)
672 return true; 685 return true;
673 686
674 return false; 687 return false;
675 } 688 }
676 689
677 static int disable_mipi_dsi_nodes(void *blob) 690 static int disable_mipi_dsi_nodes(void *blob)
678 { 691 {
679 const char *nodes_path[] = { 692 const char *nodes_path[] = {
680 "/mipi_dsi@30A00000", 693 "/mipi_dsi@30A00000",
681 "/mipi_dsi_bridge@30A00000", 694 "/mipi_dsi_bridge@30A00000",
682 "/dsi_phy@30A00300", 695 "/dsi_phy@30A00300",
683 "/soc@0/bus@30800000/mipi_dsi@30a00000", 696 "/soc@0/bus@30800000/mipi_dsi@30a00000",
684 "/soc@0/bus@30800000/dphy@30a00300" 697 "/soc@0/bus@30800000/dphy@30a00300"
685 "/soc@0/bus@30800000/mipi-dsi@30a00000", 698 "/soc@0/bus@30800000/mipi-dsi@30a00000",
686 }; 699 };
687 700
688 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path)); 701 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
689 } 702 }
690 703
691 static int disable_dcss_nodes(void *blob) 704 static int disable_dcss_nodes(void *blob)
692 { 705 {
693 const char *nodes_path[] = { 706 const char *nodes_path[] = {
694 "/dcss@0x32e00000", 707 "/dcss@0x32e00000",
695 "/dcss@32e00000", 708 "/dcss@32e00000",
696 "/hdmi@32c00000", 709 "/hdmi@32c00000",
697 "/hdmi_cec@32c33800", 710 "/hdmi_cec@32c33800",
698 "/hdmi_drm@32c00000", 711 "/hdmi_drm@32c00000",
699 "/display-subsystem", 712 "/display-subsystem",
700 "/sound-hdmi", 713 "/sound-hdmi",
701 "/sound-hdmi-arc", 714 "/sound-hdmi-arc",
702 "/soc@0/bus@32c00000/display-controller@32e00000", 715 "/soc@0/bus@32c00000/display-controller@32e00000",
703 "/soc@0/bus@32c00000/hdmi@32c00000", 716 "/soc@0/bus@32c00000/hdmi@32c00000",
704 }; 717 };
705 718
706 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path)); 719 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
707 } 720 }
708 721
709 static int check_mipi_dsi_nodes(void *blob) 722 static int check_mipi_dsi_nodes(void *blob)
710 { 723 {
711 const char *lcdif_path[] = { 724 const char *lcdif_path[] = {
712 "/lcdif@30320000", 725 "/lcdif@30320000",
713 "/soc@0/bus@30000000/lcdif@30320000", 726 "/soc@0/bus@30000000/lcdif@30320000",
714 "/soc@0/bus@30000000/lcd-controller@30320000" 727 "/soc@0/bus@30000000/lcd-controller@30320000"
715 }; 728 };
716 const char *mipi_dsi_path[] = { 729 const char *mipi_dsi_path[] = {
717 "/mipi_dsi@30A00000", 730 "/mipi_dsi@30A00000",
718 "/soc@0/bus@30800000/mipi_dsi@30a00000" 731 "/soc@0/bus@30800000/mipi_dsi@30a00000"
719 }; 732 };
720 const char *lcdif_ep_path[] = { 733 const char *lcdif_ep_path[] = {
721 "/lcdif@30320000/port@0/mipi-dsi-endpoint", 734 "/lcdif@30320000/port@0/mipi-dsi-endpoint",
722 "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint", 735 "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint",
723 "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint" 736 "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint"
724 }; 737 };
725 const char *mipi_dsi_ep_path[] = { 738 const char *mipi_dsi_ep_path[] = {
726 "/mipi_dsi@30A00000/port@1/endpoint", 739 "/mipi_dsi@30A00000/port@1/endpoint",
727 "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint", 740 "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint",
728 "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0" 741 "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0"
729 }; 742 };
730 743
731 int nodeoff; 744 int nodeoff;
732 bool new_path = check_fdt_new_path(blob); 745 bool new_path = check_fdt_new_path(blob);
733 int i = new_path? 1 : 0; 746 int i = new_path? 1 : 0;
734 747
735 nodeoff = fdt_path_offset(blob, lcdif_path[i]); 748 nodeoff = fdt_path_offset(blob, lcdif_path[i]);
736 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) { 749 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
737 /* If can't find lcdif node or lcdif node is disabled, then disable all mipi dsi, 750 /* If can't find lcdif node or lcdif node is disabled, then disable all mipi dsi,
738 since they only can input from DCSS */ 751 since they only can input from DCSS */
739 return disable_mipi_dsi_nodes(blob); 752 return disable_mipi_dsi_nodes(blob);
740 } 753 }
741 754
742 nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]); 755 nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
743 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) 756 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
744 return 0; 757 return 0;
745 758
746 nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]); 759 nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
747 if (nodeoff < 0) { 760 if (nodeoff < 0) {
748 /* If can't find lcdif endpoint, then disable all mipi dsi, 761 /* If can't find lcdif endpoint, then disable all mipi dsi,
749 since they only can input from DCSS */ 762 since they only can input from DCSS */
750 return disable_mipi_dsi_nodes(blob); 763 return disable_mipi_dsi_nodes(blob);
751 } else { 764 } else {
752 int lookup_node; 765 int lookup_node;
753 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint"); 766 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
754 nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]); 767 nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
755 768
756 if (nodeoff >0 && nodeoff == lookup_node) 769 if (nodeoff >0 && nodeoff == lookup_node)
757 return 0; 770 return 0;
758 771
759 return disable_mipi_dsi_nodes(blob); 772 return disable_mipi_dsi_nodes(blob);
760 } 773 }
761 774
762 } 775 }
763 #endif 776 #endif
764 777
765 void board_quiesce_devices(void) 778 void board_quiesce_devices(void)
766 { 779 {
767 #ifdef CONFIG_USB_DWC3 780 #ifdef CONFIG_USB_DWC3
768 if (is_usb_boot()) 781 if (is_usb_boot())
769 disconnect_from_pc(); 782 disconnect_from_pc();
770 #endif 783 #endif
771 } 784 }
772 785
773 int disable_vpu_nodes(void *blob) 786 int disable_vpu_nodes(void *blob)
774 { 787 {
775 const char *nodes_path_8mq[] = { 788 const char *nodes_path_8mq[] = {
776 "/vpu@38300000", 789 "/vpu@38300000",
777 "/soc@0/vpu@38300000" 790 "/soc@0/vpu@38300000"
778 }; 791 };
779 792
780 const char *nodes_path_8mm[] = { 793 const char *nodes_path_8mm[] = {
781 "/vpu_g1@38300000", 794 "/vpu_g1@38300000",
782 "/vpu_g2@38310000", 795 "/vpu_g2@38310000",
783 "/vpu_h1@38320000" 796 "/vpu_h1@38320000"
784 }; 797 };
785 798
786 const char *nodes_path_8mp[] = { 799 const char *nodes_path_8mp[] = {
787 "/vpu_g1@38300000", 800 "/vpu_g1@38300000",
788 "/vpu_g2@38310000", 801 "/vpu_g2@38310000",
789 "/vpu_vc8000e@38320000" 802 "/vpu_vc8000e@38320000"
790 }; 803 };
791 804
792 if (is_imx8mq()) 805 if (is_imx8mq())
793 return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq)); 806 return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
794 else if (is_imx8mm()) 807 else if (is_imx8mm())
795 return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm)); 808 return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
796 else if (is_imx8mp()) 809 else if (is_imx8mp())
797 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp)); 810 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
798 else 811 else
799 return -EPERM; 812 return -EPERM;
800 813
801 } 814 }
802 815
803 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE 816 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
804 static int low_drive_gpu_freq(void *blob) 817 static int low_drive_gpu_freq(void *blob)
805 { 818 {
806 const char *nodes_path_8mn[] = { 819 const char *nodes_path_8mn[] = {
807 "/gpu@38000000", 820 "/gpu@38000000",
808 "/soc@0/gpu@38000000" 821 "/soc@0/gpu@38000000"
809 }; 822 };
810 823
811 int nodeoff, cnt, i; 824 int nodeoff, cnt, i;
812 u32 assignedclks[7]; 825 u32 assignedclks[7];
813 826
814 nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]); 827 nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]);
815 if (nodeoff < 0) 828 if (nodeoff < 0)
816 return nodeoff; 829 return nodeoff;
817 830
818 cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7); 831 cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
819 if (cnt < 0) 832 if (cnt < 0)
820 return cnt; 833 return cnt;
821 834
822 if (cnt != 7) 835 if (cnt != 7)
823 printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt); 836 printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
824 837
825 assignedclks[cnt - 1] = 200000000; 838 assignedclks[cnt - 1] = 200000000;
826 assignedclks[cnt - 2] = 200000000; 839 assignedclks[cnt - 2] = 200000000;
827 840
828 for (i = 0; i < cnt; i++) { 841 for (i = 0; i < cnt; i++) {
829 debug("<%u>, ", assignedclks[i]); 842 debug("<%u>, ", assignedclks[i]);
830 assignedclks[i] = cpu_to_fdt32(assignedclks[i]); 843 assignedclks[i] = cpu_to_fdt32(assignedclks[i]);
831 } 844 }
832 debug("\n"); 845 debug("\n");
833 846
834 return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks)); 847 return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
835 } 848 }
836 #endif 849 #endif
837 850
838 int disable_gpu_nodes(void *blob) 851 int disable_gpu_nodes(void *blob)
839 { 852 {
840 const char *nodes_path_8mn[] = { 853 const char *nodes_path_8mn[] = {
841 "/gpu@38000000", 854 "/gpu@38000000",
842 "/soc@/gpu@38000000" 855 "/soc@/gpu@38000000"
843 }; 856 };
844 857
845 return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn)); 858 return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
846 } 859 }
847 860
848 int disable_npu_nodes(void *blob) 861 int disable_npu_nodes(void *blob)
849 { 862 {
850 const char *nodes_path_8mp[] = { 863 const char *nodes_path_8mp[] = {
851 "/vipsi@38500000" 864 "/vipsi@38500000"
852 }; 865 };
853 866
854 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp)); 867 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
855 } 868 }
856 869
857 int disable_isp_nodes(void *blob) 870 int disable_isp_nodes(void *blob)
858 { 871 {
859 const char *nodes_path_8mp[] = { 872 const char *nodes_path_8mp[] = {
860 "/soc@0/bus@32c00000/camera/isp@32e10000", 873 "/soc@0/bus@32c00000/camera/isp@32e10000",
861 "/soc@0/bus@32c00000/camera/isp@32e20000" 874 "/soc@0/bus@32c00000/camera/isp@32e20000"
862 }; 875 };
863 876
864 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp)); 877 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
865 } 878 }
866 879
867 int disable_dsp_nodes(void *blob) 880 int disable_dsp_nodes(void *blob)
868 { 881 {
869 const char *nodes_path_8mp[] = { 882 const char *nodes_path_8mp[] = {
870 "/dsp@3b6e8000" 883 "/dsp@3b6e8000"
871 }; 884 };
872 885
873 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp)); 886 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
874 } 887 }
875 888
876 static int disable_cpu_nodes(void *blob, u32 disabled_cores) 889 static int disable_cpu_nodes(void *blob, u32 disabled_cores)
877 { 890 {
878 const char *nodes_path[] = { 891 const char *nodes_path[] = {
879 "/cpus/cpu@1", 892 "/cpus/cpu@1",
880 "/cpus/cpu@2", 893 "/cpus/cpu@2",
881 "/cpus/cpu@3", 894 "/cpus/cpu@3",
882 }; 895 };
883 896
884 u32 i = 0; 897 u32 i = 0;
885 int rc; 898 int rc;
886 int nodeoff; 899 int nodeoff;
887 900
888 if (disabled_cores > 3) 901 if (disabled_cores > 3)
889 return -EINVAL; 902 return -EINVAL;
890 903
891 i = 3 - disabled_cores; 904 i = 3 - disabled_cores;
892 905
893 for (; i < 3; i++) { 906 for (; i < 3; i++) {
894 nodeoff = fdt_path_offset(blob, nodes_path[i]); 907 nodeoff = fdt_path_offset(blob, nodes_path[i]);
895 if (nodeoff < 0) 908 if (nodeoff < 0)
896 continue; /* Not found, skip it */ 909 continue; /* Not found, skip it */
897 910
898 printf("Found %s node\n", nodes_path[i]); 911 printf("Found %s node\n", nodes_path[i]);
899 912
900 rc = fdt_del_node(blob, nodeoff); 913 rc = fdt_del_node(blob, nodeoff);
901 if (rc < 0) { 914 if (rc < 0) {
902 printf("Unable to delete node %s, err=%s\n", 915 printf("Unable to delete node %s, err=%s\n",
903 nodes_path[i], fdt_strerror(rc)); 916 nodes_path[i], fdt_strerror(rc));
904 } else { 917 } else {
905 printf("Delete node %s\n", nodes_path[i]); 918 printf("Delete node %s\n", nodes_path[i]);
906 } 919 }
907 } 920 }
908 921
909 return 0; 922 return 0;
910 } 923 }
911 924
912 int ft_system_setup(void *blob, bd_t *bd) 925 int ft_system_setup(void *blob, bd_t *bd)
913 { 926 {
914 #ifdef CONFIG_IMX8MQ 927 #ifdef CONFIG_IMX8MQ
915 int i = 0; 928 int i = 0;
916 int rc; 929 int rc;
917 int nodeoff; 930 int nodeoff;
918 931
919 if (get_boot_device() == USB_BOOT) { 932 if (get_boot_device() == USB_BOOT) {
920 933
921 disable_dcss_nodes(blob); 934 disable_dcss_nodes(blob);
922 935
923 bool new_path = check_fdt_new_path(blob); 936 bool new_path = check_fdt_new_path(blob);
924 int v = new_path? 1 : 0; 937 int v = new_path? 1 : 0;
925 const char *usb_dwc3_path[] = { 938 const char *usb_dwc3_path[] = {
926 "/usb@38100000/dwc3", 939 "/usb@38100000/dwc3",
927 "/soc@0/usb@38100000" 940 "/soc@0/usb@38100000"
928 }; 941 };
929 942
930 nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]); 943 nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
931 if (nodeoff >= 0) { 944 if (nodeoff >= 0) {
932 const char *speed = "high-speed"; 945 const char *speed = "high-speed";
933 printf("Found %s node\n", usb_dwc3_path[v]); 946 printf("Found %s node\n", usb_dwc3_path[v]);
934 947
935 usb_modify_speed: 948 usb_modify_speed:
936 949
937 rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1); 950 rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
938 if (rc) { 951 if (rc) {
939 if (rc == -FDT_ERR_NOSPACE) { 952 if (rc == -FDT_ERR_NOSPACE) {
940 rc = fdt_increase_size(blob, 512); 953 rc = fdt_increase_size(blob, 512);
941 if (!rc) 954 if (!rc)
942 goto usb_modify_speed; 955 goto usb_modify_speed;
943 } 956 }
944 printf("Unable to set property %s:%s, err=%s\n", 957 printf("Unable to set property %s:%s, err=%s\n",
945 usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc)); 958 usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
946 } else { 959 } else {
947 printf("Modify %s:%s = %s\n", 960 printf("Modify %s:%s = %s\n",
948 usb_dwc3_path[v], "maximum-speed", speed); 961 usb_dwc3_path[v], "maximum-speed", speed);
949 } 962 }
950 }else { 963 }else {
951 printf("Can't found %s node\n", usb_dwc3_path[v]); 964 printf("Can't found %s node\n", usb_dwc3_path[v]);
952 } 965 }
953 } 966 }
954 967
955 /* Disable the CPU idle for A0 chip since the HW does not support it */ 968 /* Disable the CPU idle for A0 chip since the HW does not support it */
956 if (is_soc_rev(CHIP_REV_1_0)) { 969 if (is_soc_rev(CHIP_REV_1_0)) {
957 static const char * const nodes_path[] = { 970 static const char * const nodes_path[] = {
958 "/cpus/cpu@0", 971 "/cpus/cpu@0",
959 "/cpus/cpu@1", 972 "/cpus/cpu@1",
960 "/cpus/cpu@2", 973 "/cpus/cpu@2",
961 "/cpus/cpu@3", 974 "/cpus/cpu@3",
962 }; 975 };
963 976
964 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) { 977 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
965 nodeoff = fdt_path_offset(blob, nodes_path[i]); 978 nodeoff = fdt_path_offset(blob, nodes_path[i]);
966 if (nodeoff < 0) 979 if (nodeoff < 0)
967 continue; /* Not found, skip it */ 980 continue; /* Not found, skip it */
968 981
969 printf("Found %s node\n", nodes_path[i]); 982 printf("Found %s node\n", nodes_path[i]);
970 983
971 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states"); 984 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
972 if (rc) { 985 if (rc) {
973 printf("Unable to update property %s:%s, err=%s\n", 986 printf("Unable to update property %s:%s, err=%s\n",
974 nodes_path[i], "status", fdt_strerror(rc)); 987 nodes_path[i], "status", fdt_strerror(rc));
975 return rc; 988 return rc;
976 } 989 }
977 990
978 printf("Remove %s:%s\n", nodes_path[i], 991 printf("Remove %s:%s\n", nodes_path[i],
979 "cpu-idle-states"); 992 "cpu-idle-states");
980 } 993 }
981 } 994 }
982 995
983 if (is_imx8mql()) { 996 if (is_imx8mql()) {
984 disable_vpu_nodes(blob); 997 disable_vpu_nodes(blob);
985 if (check_dcss_fused()) { 998 if (check_dcss_fused()) {
986 printf("DCSS is fused\n"); 999 printf("DCSS is fused\n");
987 disable_dcss_nodes(blob); 1000 disable_dcss_nodes(blob);
988 check_mipi_dsi_nodes(blob); 1001 check_mipi_dsi_nodes(blob);
989 } 1002 }
990 } 1003 }
991 1004
992 if (is_imx8md()) 1005 if (is_imx8md())
993 disable_cpu_nodes(blob, 2); 1006 disable_cpu_nodes(blob, 2);
994 1007
995 #elif defined(CONFIG_IMX8MM) 1008 #elif defined(CONFIG_IMX8MM)
996 if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl()) 1009 if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl())
997 disable_vpu_nodes(blob); 1010 disable_vpu_nodes(blob);
998 1011
999 if (is_imx8mmd() || is_imx8mmdl()) 1012 if (is_imx8mmd() || is_imx8mmdl())
1000 disable_cpu_nodes(blob, 2); 1013 disable_cpu_nodes(blob, 2);
1001 else if (is_imx8mms() || is_imx8mmsl()) 1014 else if (is_imx8mms() || is_imx8mmsl())
1002 disable_cpu_nodes(blob, 3); 1015 disable_cpu_nodes(blob, 3);
1003 1016
1004 #elif defined(CONFIG_IMX8MN) 1017 #elif defined(CONFIG_IMX8MN)
1005 if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl()) 1018 if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
1006 disable_gpu_nodes(blob); 1019 disable_gpu_nodes(blob);
1007 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE 1020 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
1008 else { 1021 else {
1009 int ldm_gpu = low_drive_gpu_freq(blob); 1022 int ldm_gpu = low_drive_gpu_freq(blob);
1010 if (ldm_gpu < 0) 1023 if (ldm_gpu < 0)
1011 printf("Update GPU node assigned-clock-rates failed\n"); 1024 printf("Update GPU node assigned-clock-rates failed\n");
1012 else 1025 else
1013 printf("Update GPU node assigned-clock-rates ok\n"); 1026 printf("Update GPU node assigned-clock-rates ok\n");
1014 } 1027 }
1015 #endif 1028 #endif
1016 1029
1017 if (is_imx8mnd() || is_imx8mndl()) 1030 if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
1018 disable_cpu_nodes(blob, 2); 1031 disable_cpu_nodes(blob, 2);
1019 else if (is_imx8mns() || is_imx8mnsl()) 1032 else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
1020 disable_cpu_nodes(blob, 3); 1033 disable_cpu_nodes(blob, 3);
1021 1034
1022 #elif defined(CONFIG_IMX8MP) 1035 #elif defined(CONFIG_IMX8MP)
1023 if (is_imx8mpl()) 1036 if (is_imx8mpl())
1024 disable_vpu_nodes(blob); 1037 disable_vpu_nodes(blob);
1025 1038
1026 if (is_imx8mpl() || is_imx8mp6()) 1039 if (is_imx8mpl() || is_imx8mp6())
1027 disable_npu_nodes(blob); 1040 disable_npu_nodes(blob);
1028 1041
1029 if (is_imx8mpl()) 1042 if (is_imx8mpl())
1030 disable_isp_nodes(blob); 1043 disable_isp_nodes(blob);
1031 1044
1032 if (is_imx8mpl() || is_imx8mp6()) 1045 if (is_imx8mpl() || is_imx8mp6())
1033 disable_dsp_nodes(blob); 1046 disable_dsp_nodes(blob);
1034 1047
1035 if (is_imx8mpd()) 1048 if (is_imx8mpd())
1036 disable_cpu_nodes(blob, 2); 1049 disable_cpu_nodes(blob, 2);
1037 #endif 1050 #endif
1038 1051
1039 return ft_add_optee_node(blob, bd); 1052 return ft_add_optee_node(blob, bd);
1040 } 1053 }
1041 #endif 1054 #endif
1042 1055
1043 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET) 1056 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
1044 void reset_cpu(ulong addr) 1057 void reset_cpu(ulong addr)
1045 { 1058 {
1046 struct watchdog_regs *wdog = (struct watchdog_regs *)addr; 1059 struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
1047 1060
1048 if (!addr) 1061 if (!addr)
1049 wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 1062 wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
1050 1063
1051 /* Clear WDA to trigger WDOG_B immediately */ 1064 /* Clear WDA to trigger WDOG_B immediately */
1052 writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr); 1065 writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
1053 1066
1054 while (1) { 1067 while (1) {
1055 /* 1068 /*
1056 * spin for 1 second before timeout reset 1069 * spin for 1 second before timeout reset
1057 */ 1070 */
1058 } 1071 }
1059 } 1072 }
1060 #endif 1073 #endif
1061 1074
1062 #if defined(CONFIG_ARCH_MISC_INIT) 1075 #if defined(CONFIG_ARCH_MISC_INIT)
1063 #define FSL_SIP_BUILDINFO 0xC2000003 1076 #define FSL_SIP_BUILDINFO 0xC2000003
1064 #define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00 1077 #define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00
1065 static void acquire_buildinfo(void) 1078 static void acquire_buildinfo(void)
1066 { 1079 {
1067 uint64_t atf_commit = 0; 1080 uint64_t atf_commit = 0;
1068 1081
1069 /* Get ARM Trusted Firmware commit id */ 1082 /* Get ARM Trusted Firmware commit id */
1070 atf_commit = call_imx_sip(FSL_SIP_BUILDINFO, 1083 atf_commit = call_imx_sip(FSL_SIP_BUILDINFO,
1071 FSL_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0); 1084 FSL_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
1072 if (atf_commit == 0xffffffff) { 1085 if (atf_commit == 0xffffffff) {
1073 debug("ATF does not support build info\n"); 1086 debug("ATF does not support build info\n");
1074 atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */ 1087 atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
1075 } 1088 }
1076 1089
1077 printf("\n BuildInfo:\n - ATF %s\n - %s\n\n", (char *)&atf_commit, 1090 printf("\n BuildInfo:\n - ATF %s\n - %s\n\n", (char *)&atf_commit,
1078 U_BOOT_VERSION); 1091 U_BOOT_VERSION);
1079 } 1092 }
1080 1093
1081 int arch_misc_init(void) 1094 int arch_misc_init(void)
1082 { 1095 {
1083 acquire_buildinfo(); 1096 acquire_buildinfo();
1084 1097
1085 return 0; 1098 return 0;
1086 } 1099 }
1087 #endif 1100 #endif
1088 1101
1089 #define FSL_SIP_GPC 0xC2000000 1102 #define FSL_SIP_GPC 0xC2000000
1090 #define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03 1103 #define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03
1091 1104
1092 #ifdef CONFIG_SPL_BUILD 1105 #ifdef CONFIG_SPL_BUILD
1093 static uint32_t gpc_pu_m_core_offset[11] = { 1106 static uint32_t gpc_pu_m_core_offset[11] = {
1094 0xc00, 0xc40, 0xc80, 0xcc0, 1107 0xc00, 0xc40, 0xc80, 0xcc0,
1095 0xdc0, 0xe00, 0xe40, 0xe80, 1108 0xdc0, 0xe00, 0xe40, 0xe80,
1096 0xec0, 0xf00, 0xf40, 1109 0xec0, 0xf00, 0xf40,
1097 }; 1110 };
1098 1111
1099 #define PGC_PCR 0 1112 #define PGC_PCR 0
1100 1113
1101 void imx_gpc_set_m_core_pgc(unsigned int offset, bool pdn) 1114 void imx_gpc_set_m_core_pgc(unsigned int offset, bool pdn)
1102 { 1115 {
1103 uint32_t val; 1116 uint32_t val;
1104 uintptr_t reg = GPC_BASE_ADDR + offset; 1117 uintptr_t reg = GPC_BASE_ADDR + offset;
1105 1118
1106 val = readl(reg); 1119 val = readl(reg);
1107 val &= ~(0x1 << PGC_PCR); 1120 val &= ~(0x1 << PGC_PCR);
1108 1121
1109 if(pdn) 1122 if(pdn)
1110 val |= 0x1 << PGC_PCR; 1123 val |= 0x1 << PGC_PCR;
1111 writel(val, reg); 1124 writel(val, reg);
1112 } 1125 }
1113 1126
1114 void imx8m_usb_power_domain(uint32_t domain_id, bool on) 1127 void imx8m_usb_power_domain(uint32_t domain_id, bool on)
1115 { 1128 {
1116 uint32_t val; 1129 uint32_t val;
1117 uintptr_t reg; 1130 uintptr_t reg;
1118 1131
1119 imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], true); 1132 imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], true);
1120 1133
1121 reg = GPC_BASE_ADDR + (on ? 0xf8 : 0x104); 1134 reg = GPC_BASE_ADDR + (on ? 0xf8 : 0x104);
1122 val = 1 << (domain_id > 3 ? (domain_id + 3) : domain_id); 1135 val = 1 << (domain_id > 3 ? (domain_id + 3) : domain_id);
1123 writel(val, reg); 1136 writel(val, reg);
1124 while (readl(reg) & val) 1137 while (readl(reg) & val)
1125 ; 1138 ;
1126 imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], false); 1139 imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], false);
1127 } 1140 }
1128 #endif 1141 #endif
1129 1142
1130 int imx8m_usb_power(int usb_id, bool on) 1143 int imx8m_usb_power(int usb_id, bool on)
1131 { 1144 {
1132 if (usb_id > 1) 1145 if (usb_id > 1)
1133 return -EINVAL; 1146 return -EINVAL;
1134 1147
1135 #ifdef CONFIG_SPL_BUILD 1148 #ifdef CONFIG_SPL_BUILD
1136 imx8m_usb_power_domain(2 + usb_id, on); 1149 imx8m_usb_power_domain(2 + usb_id, on);
1137 #else 1150 #else
1138 unsigned long ret; 1151 unsigned long ret;
1139 ret = call_imx_sip(FSL_SIP_GPC, 1152 ret = call_imx_sip(FSL_SIP_GPC,
1140 FSL_SIP_CONFIG_GPC_PM_DOMAIN, 2 + usb_id, on, 0); 1153 FSL_SIP_CONFIG_GPC_PM_DOMAIN, 2 + usb_id, on, 0);
1141 if (ret) 1154 if (ret)
1142 return -EPERM; 1155 return -EPERM;
1143 #endif 1156 #endif
1144 1157
1145 return 0; 1158 return 0;
1146 } 1159 }
1147 1160
1148 void nxp_tmu_arch_init(void *reg_base) 1161 void nxp_tmu_arch_init(void *reg_base)
1149 { 1162 {
1150 if (is_imx8mm() || is_imx8mn()) { 1163 if (is_imx8mm() || is_imx8mn()) {
1151 /* Load TCALIV and TASR from fuses */ 1164 /* Load TCALIV and TASR from fuses */
1152 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 1165 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1153 struct fuse_bank *bank = &ocotp->bank[3]; 1166 struct fuse_bank *bank = &ocotp->bank[3];
1154 struct fuse_bank3_regs *fuse = 1167 struct fuse_bank3_regs *fuse =
1155 (struct fuse_bank3_regs *)bank->fuse_regs; 1168 (struct fuse_bank3_regs *)bank->fuse_regs;
1156 1169
1157 u32 tca_rt, tca_hr, tca_en; 1170 u32 tca_rt, tca_hr, tca_en;
1158 u32 buf_vref, buf_slope; 1171 u32 buf_vref, buf_slope;
1159 1172
1160 tca_rt = fuse->ana0 & 0xFF; 1173 tca_rt = fuse->ana0 & 0xFF;
1161 tca_hr = (fuse->ana0 & 0xFF00) >> 8; 1174 tca_hr = (fuse->ana0 & 0xFF00) >> 8;
1162 tca_en = (fuse->ana0 & 0x2000000) >> 25; 1175 tca_en = (fuse->ana0 & 0x2000000) >> 25;
1163 1176
1164 buf_vref = (fuse->ana0 & 0x1F00000) >> 20; 1177 buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
1165 buf_slope = (fuse->ana0 & 0xF0000) >> 16; 1178 buf_slope = (fuse->ana0 & 0xF0000) >> 16;
1166 1179
1167 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28); 1180 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
1168 writel((tca_en << 31) |(tca_hr <<16) | tca_rt, (ulong)reg_base + 0x30); 1181 writel((tca_en << 31) |(tca_hr <<16) | tca_rt, (ulong)reg_base + 0x30);
1169 } 1182 }
1170 #ifdef CONFIG_IMX8MP 1183 #ifdef CONFIG_IMX8MP
1171 /* Load TCALIV0/1/m40 and TRIM from fuses */ 1184 /* Load TCALIV0/1/m40 and TRIM from fuses */
1172 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 1185 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1173 struct fuse_bank *bank = &ocotp->bank[38]; 1186 struct fuse_bank *bank = &ocotp->bank[38];
1174 struct fuse_bank38_regs *fuse = 1187 struct fuse_bank38_regs *fuse =
1175 (struct fuse_bank38_regs *)bank->fuse_regs; 1188 (struct fuse_bank38_regs *)bank->fuse_regs;
1176 1189
1177 struct fuse_bank *bank2 = &ocotp->bank[39]; 1190 struct fuse_bank *bank2 = &ocotp->bank[39];
1178 struct fuse_bank39_regs *fuse2 = 1191 struct fuse_bank39_regs *fuse2 =
1179 (struct fuse_bank39_regs *)bank2->fuse_regs; 1192 (struct fuse_bank39_regs *)bank2->fuse_regs;
1180 1193
1181 u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr; 1194 u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
1182 u32 reg; 1195 u32 reg;
1183 u32 tca40[2], tca25[2], tca105[2]; 1196 u32 tca40[2], tca25[2], tca105[2];
1184 1197
1185 /* For blank sample */ 1198 /* For blank sample */
1186 if (!fuse->ana_trim2 && !fuse->ana_trim3 && 1199 if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
1187 !fuse->ana_trim4 && !fuse2->ana_trim5) { 1200 !fuse->ana_trim4 && !fuse2->ana_trim5) {
1188 /* Use a default 25C binary codes */ 1201 /* Use a default 25C binary codes */
1189 tca25[0] = 1596; 1202 tca25[0] = 1596;
1190 tca25[1] = 1596; 1203 tca25[1] = 1596;
1191 writel(tca25[0], (ulong)reg_base + 0x30); 1204 writel(tca25[0], (ulong)reg_base + 0x30);
1192 writel(tca25[1], (ulong)reg_base + 0x34); 1205 writel(tca25[1], (ulong)reg_base + 0x34);
1193 return; 1206 return;
1194 } 1207 }
1195 1208
1196 buf_vref = (fuse->ana_trim2 & 0xc0) >> 6; 1209 buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
1197 buf_slope = (fuse->ana_trim2 & 0xF00) >> 8; 1210 buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
1198 bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12; 1211 bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
1199 bgr = (fuse->ana_trim2 & 0xF0000) >> 16; 1212 bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
1200 vlsb = (fuse->ana_trim2 & 0xF00000) >> 20; 1213 vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
1201 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28); 1214 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
1202 1215
1203 reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | ( 1 << 7); 1216 reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | ( 1 << 7);
1204 writel(reg, (ulong)reg_base + 0x3c); 1217 writel(reg, (ulong)reg_base + 0x3c);
1205 1218
1206 tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16; 1219 tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
1207 tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28; 1220 tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
1208 tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4); 1221 tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
1209 tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8; 1222 tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
1210 tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20; 1223 tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
1211 tca25[1] = fuse2->ana_trim5 & 0xFFF; 1224 tca25[1] = fuse2->ana_trim5 & 0xFFF;
1212 tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12; 1225 tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
1213 1226
1214 /* use 25c for 1p calibration */ 1227 /* use 25c for 1p calibration */
1215 writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30); 1228 writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
1216 writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34); 1229 writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
1217 writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38); 1230 writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
1218 #endif 1231 #endif
1219 } 1232 }
1220 1233
1221 #if defined(CONFIG_SPL_BUILD) 1234 #if defined(CONFIG_SPL_BUILD)
1222 #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) 1235 #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
1223 bool serror_need_skip = true; 1236 bool serror_need_skip = true;
1224 void do_error(struct pt_regs *pt_regs, unsigned int esr) 1237 void do_error(struct pt_regs *pt_regs, unsigned int esr)
1225 { 1238 {
1226 /* If stack is still in ROM reserved OCRAM not switch to SPL, it is the ROM SError */ 1239 /* If stack is still in ROM reserved OCRAM not switch to SPL, it is the ROM SError */
1227 ulong sp; 1240 ulong sp;
1228 asm volatile("mov %0, sp" : "=r"(sp) : ); 1241 asm volatile("mov %0, sp" : "=r"(sp) : );
1229 1242
1230 if (serror_need_skip && 1243 if (serror_need_skip &&
1231 sp < 0x910000 && sp >= 0x900000) { 1244 sp < 0x910000 && sp >= 0x900000) {
1232 1245
1233 /* Check for ERR050342, imx8mq HDCP enabled parts */ 1246 /* Check for ERR050342, imx8mq HDCP enabled parts */
1234 if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) { 1247 if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
1235 serror_need_skip = false; 1248 serror_need_skip = false;
1236 return; /* Do nothing skip the SError in ROM */ 1249 return; /* Do nothing skip the SError in ROM */
1237 } 1250 }
1238 1251
1239 /* Check for ERR050350, field return mode for imx8mq, mm and mn */ 1252 /* Check for ERR050350, field return mode for imx8mq, mm and mn */
1240 if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) { 1253 if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
1241 serror_need_skip = false; 1254 serror_need_skip = false;
1242 return; /* Do nothing skip the SError in ROM */ 1255 return; /* Do nothing skip the SError in ROM */
1243 } 1256 }
1244 } 1257 }
1245 1258
1246 efi_restore_gd(); 1259 efi_restore_gd();
1247 printf("\"Error\" handler, esr 0x%08x\n", esr); 1260 printf("\"Error\" handler, esr 0x%08x\n", esr);
1248 show_regs(pt_regs); 1261 show_regs(pt_regs);
1249 panic("Resetting CPU ...\n"); 1262 panic("Resetting CPU ...\n");
1250 1263
1251 } 1264 }
1252 #endif 1265 #endif
1253 #endif 1266 #endif
1254 1267
1255 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) 1268 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
1256 enum env_location env_get_location(enum env_operation op, int prio) 1269 enum env_location env_get_location(enum env_operation op, int prio)
1257 { 1270 {
1258 enum boot_device dev = get_boot_device(); 1271 enum boot_device dev = get_boot_device();
1259 enum env_location env_loc = ENVL_UNKNOWN; 1272 enum env_location env_loc = ENVL_UNKNOWN;
1260 1273
1261 if (prio) 1274 if (prio)
1262 return env_loc; 1275 return env_loc;
1263 1276
1264 switch (dev) { 1277 switch (dev) {
1265 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH 1278 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1266 case QSPI_BOOT: 1279 case QSPI_BOOT:
1267 env_loc = ENVL_SPI_FLASH; 1280 env_loc = ENVL_SPI_FLASH;
1268 break; 1281 break;
1269 #endif 1282 #endif
1270 #ifdef CONFIG_ENV_IS_IN_NAND 1283 #ifdef CONFIG_ENV_IS_IN_NAND
1271 case NAND_BOOT: 1284 case NAND_BOOT:
1272 env_loc = ENVL_NAND; 1285 env_loc = ENVL_NAND;
1273 break; 1286 break;
1274 #endif 1287 #endif
1275 #ifdef CONFIG_ENV_IS_IN_MMC 1288 #ifdef CONFIG_ENV_IS_IN_MMC
1276 case SD1_BOOT: 1289 case SD1_BOOT:
1277 case SD2_BOOT: 1290 case SD2_BOOT:
1278 case SD3_BOOT: 1291 case SD3_BOOT:
1279 case MMC1_BOOT: 1292 case MMC1_BOOT:
1280 case MMC2_BOOT: 1293 case MMC2_BOOT:
1281 case MMC3_BOOT: 1294 case MMC3_BOOT:
1282 env_loc = ENVL_MMC; 1295 env_loc = ENVL_MMC;
1283 break; 1296 break;
1284 #endif 1297 #endif
1285 default: 1298 default:
1286 #if defined(CONFIG_ENV_IS_NOWHERE) 1299 #if defined(CONFIG_ENV_IS_NOWHERE)
1287 env_loc = ENVL_NOWHERE; 1300 env_loc = ENVL_NOWHERE;
1288 #endif 1301 #endif
1289 break; 1302 break;
1290 } 1303 }
1291 1304
1292 return env_loc; 1305 return env_loc;
1293 } 1306 }
1294 1307
1295 #ifndef ENV_IS_EMBEDDED 1308 #ifndef ENV_IS_EMBEDDED
1296 long long env_get_offset(long long defautl_offset) 1309 long long env_get_offset(long long defautl_offset)
1297 { 1310 {
1298 enum boot_device dev = get_boot_device(); 1311 enum boot_device dev = get_boot_device();
1299 1312
1300 switch (dev) { 1313 switch (dev) {
1301 case NAND_BOOT: 1314 case NAND_BOOT:
1302 return (60 << 20); /* 60MB offset for NAND */ 1315 return (60 << 20); /* 60MB offset for NAND */
1303 default: 1316 default:
1304 break; 1317 break;
1305 } 1318 }
1306 1319
1307 return defautl_offset; 1320 return defautl_offset;
1308 } 1321 }
1309 #endif 1322 #endif
1310 #endif 1323 #endif
1311 1324
1312 #ifdef CONFIG_IMX8MQ 1325 #ifdef CONFIG_IMX8MQ
1313 int imx8m_dcss_power_init(void) 1326 int imx8m_dcss_power_init(void)
1314 { 1327 {
1315 /* Enable the display CCGR before power on */ 1328 /* Enable the display CCGR before power on */
1316 clock_enable(CCGR_DISPLAY, 1); 1329 clock_enable(CCGR_DISPLAY, 1);
1317 1330
1318 writel(0x0000ffff, 0x303A00EC); /*PGC_CPU_MAPPING */ 1331 writel(0x0000ffff, 0x303A00EC); /*PGC_CPU_MAPPING */
1319 setbits_le32(0x303A00F8, 0x1 << 10); /*PU_PGC_SW_PUP_REQ : disp was 10 */ 1332 setbits_le32(0x303A00F8, 0x1 << 10); /*PU_PGC_SW_PUP_REQ : disp was 10 */
1320 1333
1321 return 0; 1334 return 0;
1322 } 1335 }
1323 #endif 1336 #endif
1324 1337