Eric Lee / smarc-uboot

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Commit 05af9ac08052c92d011908726534e227db3143c4

Authored by Ye Li
1 parent 6df53e2727
Exists in smarc-8m-android-10.0.0_2.6.0 and in 1 other branch 8qm-imx_v2020.04_5.4.70_2.3.0

MLK-25003-1 iMX8MN: Add support for 11x11 UltraLite part number 

There are 3 part numbers for 11x11 i.MX8MNano with different core number
configuration: UltraLite Quad/Dual/Solo

Comparing with i.MX8MN Lite parts, they have MIPI DSI disabled. So
checking the MIPI DSI disable fuse to recognize these parts.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

Showing 4 changed files with 43 additions and 17 deletions Side-by-side Diff

arch/arm/include/asm/arch-imx/cpu.h
Diff comments   View file @ 05af9ac
... ... @@ -41,10 +41,13 @@
41 41 #define MXC_CPU_IMX8MNL 0x8e /* dummy ID */
42 42 #define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */
43 43 #define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */
44   -#define MXC_CPU_IMX8MP 0x182/* dummy ID */
45   -#define MXC_CPU_IMX8MP6 0x184 /* dummy ID */
46   -#define MXC_CPU_IMX8MPL 0x186 /* dummy ID */
47   -#define MXC_CPU_IMX8MPD 0x187 /* dummy ID */
  44 +#define MXC_CPU_IMX8MNUQ 0x182 /* dummy ID */
  45 +#define MXC_CPU_IMX8MNUD 0x183 /* dummy ID */
  46 +#define MXC_CPU_IMX8MNUS 0x184 /* dummy ID */
  47 +#define MXC_CPU_IMX8MP 0x185/* dummy ID */
  48 +#define MXC_CPU_IMX8MP6 0x186 /* dummy ID */
  49 +#define MXC_CPU_IMX8MPL 0x187 /* dummy ID */
  50 +#define MXC_CPU_IMX8MPD 0x188 /* dummy ID */
48 51 #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
49 52 #define MXC_CPU_IMX8QM 0x91 /* dummy ID */
50 53 #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
arch/arm/include/asm/mach-imx/sys_proto.h
Diff comments   View file @ 05af9ac
... ... @@ -58,12 +58,16 @@
58 58 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
59 59 #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \
60 60 is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \
61   - is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL))
  61 + is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \
  62 + is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ))
62 63 #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND))
63 64 #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS))
64 65 #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
65 66 #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
66 67 #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
  68 +#define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ))
  69 +#define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD))
  70 +#define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS))
67 71 #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
68 72 is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6))
69 73 #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
arch/arm/mach-imx/cpu.c
Diff comments   View file @ 05af9ac
... ... @@ -132,6 +132,12 @@
132 132 return "8MNano DualLite";/* Dual-core Lite version of the imx8mn */
133 133 case MXC_CPU_IMX8MNSL:
134 134 return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
  135 + case MXC_CPU_IMX8MNUQ:
  136 + return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
  137 + case MXC_CPU_IMX8MNUD:
  138 + return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
  139 + case MXC_CPU_IMX8MNUS:
  140 + return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
135 141 case MXC_CPU_IMX8MM:
136 142 return "8MMQ"; /* Quad-core version of the imx8mm */
137 143 case MXC_CPU_IMX8MML:
arch/arm/mach-imx/imx8m/soc.c
Diff comments   View file @ 05af9ac
... ... @@ -318,18 +318,30 @@
318 318 } else if (type == MXC_CPU_IMX8MN) {
319 319 switch (value & 0x3) {
320 320 case 2:
321   - if (value & 0x1000000)
322   - return MXC_CPU_IMX8MNDL;
323   - else
  321 + if (value & 0x1000000) {
  322 + if (value & 0x10000000) /* MIPI DSI */
  323 + return MXC_CPU_IMX8MNUD;
  324 + else
  325 + return MXC_CPU_IMX8MNDL;
  326 + } else {
324 327 return MXC_CPU_IMX8MND;
  328 + }
325 329 case 3:
326   - if (value & 0x1000000)
327   - return MXC_CPU_IMX8MNSL;
328   - else
  330 + if (value & 0x1000000) {
  331 + if (value & 0x10000000) /* MIPI DSI */
  332 + return MXC_CPU_IMX8MNUS;
  333 + else
  334 + return MXC_CPU_IMX8MNSL;
  335 + } else {
329 336 return MXC_CPU_IMX8MNS;
  337 + }
330 338 default:
331   - if (value & 0x1000000)
332   - return MXC_CPU_IMX8MNL;
  339 + if (value & 0x1000000) {
  340 + if (value & 0x10000000) /* MIPI DSI */
  341 + return MXC_CPU_IMX8MNUQ;
  342 + else
  343 + return MXC_CPU_IMX8MNL;
  344 + }
333 345 break;
334 346 }
335 347 } else if (type == MXC_CPU_IMX8MP) {
... ... @@ -511,7 +523,8 @@
511 523 secure_lockup();
512 524 #endif
513 525 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() || is_imx8mmsl() ||
514   - is_imx8mnd() || is_imx8mndl() || is_imx8mns() || is_imx8mnsl() || is_imx8mpd()) {
  526 + is_imx8mnd() || is_imx8mndl() || is_imx8mns() || is_imx8mnsl() || is_imx8mpd() ||
  527 + is_imx8mnud() || is_imx8mnus()) {
515 528 /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
516 529 struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
517 530 struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
... ... @@ -520,7 +533,7 @@
520 533  
521 534 writel(0x1, &pgc_core2->pgcr);
522 535 writel(0x1, &pgc_core3->pgcr);
523   - if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl()) {
  536 + if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
524 537 writel(0x1, &pgc_core1->pgcr);
525 538 writel(0xE, &gpc->cpu_pgc_dn_trg);
526 539 } else {
527 540  
... ... @@ -1014,9 +1027,9 @@
1014 1027 }
1015 1028 #endif
1016 1029  
1017   - if (is_imx8mnd() || is_imx8mndl())
  1030 + if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
1018 1031 disable_cpu_nodes(blob, 2);
1019   - else if (is_imx8mns() || is_imx8mnsl())
  1032 + else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
1020 1033 disable_cpu_nodes(blob, 3);
1021 1034  
1022 1035 #elif defined(CONFIG_IMX8MP)