Eric Lee / smarc-uboot

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Commit 05d235a991cdd0c2a18ca1e3c52408c994ee160c

Authored by Ye Li
1 parent a31720a861
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

MLK-23811 imx8mp: Add fused parts support 

iMX8MP has 6 fused parts in each qualification tier, with core, VPU,
ISP, NPU or DSP fused respectively.

The configuration tables for enabled modules:
MIMX8ML8DVNLZAA          Quad Core, VPU, NPU, ISP, DSP
MIMX8ML7DVNLZAA          Quad Core, NPU, ISP
MIMX8ML6DVNLZAA          Quad Core, VPU, ISP
MIMX8ML5DVNLZAA          Quad Core, VPU
MIMX8ML4DVNLZAA          Quad Lite
MIMX8ML3DVNLZAA          Dual Core, VPU, NPU, ISP, DSP

Add the support in u-boot and update kernel DTS to disable nodes for
fused modules

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 9f8a807c5984b9d7859e6a70a2807843ab95b3f6)

Showing 4 changed files with 109 additions and 4 deletions Side-by-side Diff

arch/arm/include/asm/arch-imx/cpu.h
Diff comments   View file @ 05d235a
... ... @@ -42,6 +42,11 @@
42 42 #define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */
43 43 #define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */
44 44 #define MXC_CPU_IMX8MP 0x182/* dummy ID */
  45 +#define MXC_CPU_IMX8MP7 0x183 /* dummy ID */
  46 +#define MXC_CPU_IMX8MP6 0x184 /* dummy ID */
  47 +#define MXC_CPU_IMX8MP5 0x185 /* dummy ID */
  48 +#define MXC_CPU_IMX8MPL 0x186 /* dummy ID */
  49 +#define MXC_CPU_IMX8MPD 0x187 /* dummy ID */
45 50 #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
46 51 #define MXC_CPU_IMX8QM 0x91 /* dummy ID */
47 52 #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
arch/arm/include/asm/mach-imx/sys_proto.h
Diff comments   View file @ 05d235a
... ... @@ -64,7 +64,14 @@
64 64 #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
65 65 #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
66 66 #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
67   -#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP))
  67 +#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
  68 + is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP7) || \
  69 + is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MP5))
  70 +#define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
  71 +#define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
  72 +#define is_imx8mp7() (is_cpu_type(MXC_CPU_IMX8MP7))
  73 +#define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
  74 +#define is_imx8mp5() (is_cpu_type(MXC_CPU_IMX8MP5))
68 75 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
69 76 #define is_imx8dxl() (is_cpu_type(MXC_CPU_IMX8DXL))
70 77  
arch/arm/mach-imx/cpu.c
Diff comments   View file @ 05d235a
... ... @@ -113,7 +113,17 @@
113 113 {
114 114 switch (imxtype) {
115 115 case MXC_CPU_IMX8MP:
116   - return "8MP"; /* Quad-core version of the imx8mp */
  116 + return "8MP[8]"; /* Quad-core version of the imx8mp */
  117 + case MXC_CPU_IMX8MPD:
  118 + return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
  119 + case MXC_CPU_IMX8MPL:
  120 + return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
  121 + case MXC_CPU_IMX8MP7:
  122 + return "8MP[7]"; /* Quad-core version of the imx8mp, VPU fused */
  123 + case MXC_CPU_IMX8MP6:
  124 + return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
  125 + case MXC_CPU_IMX8MP5:
  126 + return "8MP[5]"; /* Quad-core version of the imx8mp, ISP fused */
117 127 case MXC_CPU_IMX8MN:
118 128 return "8MNano Quad";/* Quad-core version of the imx8mn */
119 129 case MXC_CPU_IMX8MND:
arch/arm/mach-imx/imx8m/soc.c
Diff comments   View file @ 05d235a
... ... @@ -332,6 +332,38 @@
332 332 return MXC_CPU_IMX8MNL;
333 333 break;
334 334 }
  335 + } else if (type == MXC_CPU_IMX8MP) {
  336 + u32 value0 = readl(&fuse->tester3);
  337 + u32 flag = 0;
  338 +
  339 + if ((value0 & 0xc0000) == 0x80000) {
  340 + return MXC_CPU_IMX8MPD;
  341 + } else {
  342 + /* vpu disabled */
  343 + if ((value0 & 0x43000000) == 0x43000000)
  344 + flag = 1;
  345 +
  346 + /* npu disabled*/
  347 + if ((value & 0x8) == 0x8)
  348 + flag |= (1 << 1);
  349 +
  350 + /* isp disabled */
  351 + if ((value & 0x3) == 0x3)
  352 + flag |= (1 << 2);
  353 +
  354 + switch (flag) {
  355 + case 7:
  356 + return MXC_CPU_IMX8MPL;
  357 + case 6:
  358 + return MXC_CPU_IMX8MP5;
  359 + case 2:
  360 + return MXC_CPU_IMX8MP6;
  361 + case 1:
  362 + return MXC_CPU_IMX8MP7;
  363 + default:
  364 + break;
  365 + }
  366 + }
335 367 }
336 368  
337 369 return type;
... ... @@ -349,7 +381,7 @@
349 381  
350 382 /* iMX8MP */
351 383 if (major_low == 0x43) {
352   - return (MXC_CPU_IMX8MP << 12) | reg;
  384 + type = get_cpu_variant_type(MXC_CPU_IMX8MP);
353 385 } else if (major_low == 0x42) {
354 386 /* iMX8MN */
355 387 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
... ... @@ -486,7 +518,7 @@
486 518 secure_lockup();
487 519 #endif
488 520 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() || is_imx8mmsl() ||
489   - is_imx8mnd() || is_imx8mndl() || is_imx8mns() || is_imx8mnsl()) {
  521 + is_imx8mnd() || is_imx8mndl() || is_imx8mns() || is_imx8mnsl() || is_imx8mpd()) {
490 522 /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
491 523 struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
492 524 struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
493 525  
... ... @@ -754,10 +786,18 @@
754 786 "/vpu_h1@38320000"
755 787 };
756 788  
  789 + const char *nodes_path_8mp[] = {
  790 + "/vpu_g1@38300000",
  791 + "/vpu_g2@38310000",
  792 + "/vpu_vc8000e@38320000"
  793 + };
  794 +
757 795 if (is_imx8mq())
758 796 return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
759 797 else if (is_imx8mm())
760 798 return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
  799 + else if (is_imx8mp())
  800 + return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
761 801 else
762 802 return -EPERM;
763 803  
... ... @@ -772,6 +812,34 @@
772 812 return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
773 813 }
774 814  
  815 +int disable_npu_nodes(void *blob)
  816 +{
  817 + const char *nodes_path_8mp[] = {
  818 + "/vipsi@38500000"
  819 + };
  820 +
  821 + return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  822 +}
  823 +
  824 +int disable_isp_nodes(void *blob)
  825 +{
  826 + const char *nodes_path_8mp[] = {
  827 + "/soc@0/bus@32c00000/camera/isp@32e10000",
  828 + "/soc@0/bus@32c00000/camera/isp@32e20000"
  829 + };
  830 +
  831 + return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  832 +}
  833 +
  834 +int disable_dsp_nodes(void *blob)
  835 +{
  836 + const char *nodes_path_8mp[] = {
  837 + "/dsp@3b6e8000"
  838 + };
  839 +
  840 + return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  841 +}
  842 +
775 843 static int disable_cpu_nodes(void *blob, u32 disabled_cores)
776 844 {
777 845 const char *nodes_path[] = {
... ... @@ -909,6 +977,21 @@
909 977 else if (is_imx8mns() || is_imx8mnsl())
910 978 disable_cpu_nodes(blob, 3);
911 979  
  980 +#elif defined(CONFIG_IMX8MP)
  981 + if (is_imx8mpl() || is_imx8mp7())
  982 + disable_vpu_nodes(blob);
  983 +
  984 + if (is_imx8mpl() || is_imx8mp6() || is_imx8mp5())
  985 + disable_npu_nodes(blob);
  986 +
  987 + if (is_imx8mpl() || is_imx8mp5())
  988 + disable_isp_nodes(blob);
  989 +
  990 + if (is_imx8mpl() || is_imx8mp7() || is_imx8mp6() || is_imx8mp5())
  991 + disable_dsp_nodes(blob);
  992 +
  993 + if (is_imx8mpd())
  994 + disable_cpu_nodes(blob, 2);
912 995 #endif
913 996  
914 997 return ft_add_optee_node(blob, bd);